2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd);
53 /* from radeon_legacy_encoder.c */
55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
56 uint32_t supported_device);
58 union atom_supported_devices {
59 struct _ATOM_SUPPORTED_DEVICES_INFO info;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
67 struct atom_context *ctx = rdev->mode_info.atom_context;
68 ATOM_GPIO_I2C_ASSIGMENT *gpio;
69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
75 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
78 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
83 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
84 gpio = &i2c_info->asGPIO_Info[i];
86 if (gpio->sucI2cId.ucAccess == id) {
87 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
88 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
89 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
90 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
91 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
92 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
93 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
94 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
95 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
96 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
97 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
98 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
99 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
100 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
101 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
102 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
104 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
105 i2c.hw_capable = true;
107 i2c.hw_capable = false;
109 if (gpio->sucI2cId.ucAccess == 0xa0)
114 i2c.i2c_id = gpio->sucI2cId.ucAccess;
123 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
126 struct atom_context *ctx = rdev->mode_info.atom_context;
127 struct radeon_gpio_rec gpio;
128 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
129 struct _ATOM_GPIO_PIN_LUT *gpio_info;
130 ATOM_GPIO_PIN_ASSIGNMENT *pin;
131 u16 data_offset, size;
134 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
137 atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset);
139 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
141 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
143 for (i = 0; i < num_indices; i++) {
144 pin = &gpio_info->asGPIO_Pin[i];
145 if (id == pin->ucGPIO_ID) {
146 gpio.id = pin->ucGPIO_ID;
147 gpio.reg = pin->usGpioPin_AIndex * 4;
148 gpio.mask = (1 << pin->ucGpioPinBitShift);
157 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
158 struct radeon_gpio_rec *gpio)
160 struct radeon_hpd hpd;
162 if (gpio->reg == AVIVO_DC_GPIO_HPD_A) {
165 hpd.hpd = RADEON_HPD_1;
168 hpd.hpd = RADEON_HPD_2;
171 hpd.hpd = RADEON_HPD_3;
174 hpd.hpd = RADEON_HPD_4;
177 hpd.hpd = RADEON_HPD_5;
180 hpd.hpd = RADEON_HPD_6;
183 hpd.hpd = RADEON_HPD_NONE;
187 hpd.hpd = RADEON_HPD_NONE;
191 static bool radeon_atom_apply_quirks(struct drm_device *dev,
192 uint32_t supported_device,
194 struct radeon_i2c_bus_rec *i2c_bus,
196 struct radeon_hpd *hpd)
199 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
200 if ((dev->pdev->device == 0x791e) &&
201 (dev->pdev->subsystem_vendor == 0x1043) &&
202 (dev->pdev->subsystem_device == 0x826d)) {
203 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
204 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
205 *connector_type = DRM_MODE_CONNECTOR_DVID;
208 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
209 if ((dev->pdev->device == 0x7941) &&
210 (dev->pdev->subsystem_vendor == 0x147b) &&
211 (dev->pdev->subsystem_device == 0x2412)) {
212 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
216 /* Falcon NW laptop lists vga ddc line for LVDS */
217 if ((dev->pdev->device == 0x5653) &&
218 (dev->pdev->subsystem_vendor == 0x1462) &&
219 (dev->pdev->subsystem_device == 0x0291)) {
220 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
221 i2c_bus->valid = false;
226 /* HIS X1300 is DVI+VGA, not DVI+DVI */
227 if ((dev->pdev->device == 0x7146) &&
228 (dev->pdev->subsystem_vendor == 0x17af) &&
229 (dev->pdev->subsystem_device == 0x2058)) {
230 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
234 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
235 if ((dev->pdev->device == 0x7142) &&
236 (dev->pdev->subsystem_vendor == 0x1458) &&
237 (dev->pdev->subsystem_device == 0x2134)) {
238 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
244 if ((dev->pdev->device == 0x71C5) &&
245 (dev->pdev->subsystem_vendor == 0x106b) &&
246 (dev->pdev->subsystem_device == 0x0080)) {
247 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
248 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
252 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
253 if ((dev->pdev->device == 0x9598) &&
254 (dev->pdev->subsystem_vendor == 0x1043) &&
255 (dev->pdev->subsystem_device == 0x01da)) {
256 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
257 *connector_type = DRM_MODE_CONNECTOR_DVII;
261 /* ASUS HD 3450 board lists the DVI port as HDMI */
262 if ((dev->pdev->device == 0x95C5) &&
263 (dev->pdev->subsystem_vendor == 0x1043) &&
264 (dev->pdev->subsystem_device == 0x01e2)) {
265 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
266 *connector_type = DRM_MODE_CONNECTOR_DVII;
270 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
271 * HDMI + VGA reporting as HDMI
273 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
274 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
275 *connector_type = DRM_MODE_CONNECTOR_VGA;
280 /* Acer laptop reports DVI-D as DVI-I */
281 if ((dev->pdev->device == 0x95c4) &&
282 (dev->pdev->subsystem_vendor == 0x1025) &&
283 (dev->pdev->subsystem_device == 0x013c)) {
284 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
285 (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
286 *connector_type = DRM_MODE_CONNECTOR_DVID;
292 const int supported_devices_connector_convert[] = {
293 DRM_MODE_CONNECTOR_Unknown,
294 DRM_MODE_CONNECTOR_VGA,
295 DRM_MODE_CONNECTOR_DVII,
296 DRM_MODE_CONNECTOR_DVID,
297 DRM_MODE_CONNECTOR_DVIA,
298 DRM_MODE_CONNECTOR_SVIDEO,
299 DRM_MODE_CONNECTOR_Composite,
300 DRM_MODE_CONNECTOR_LVDS,
301 DRM_MODE_CONNECTOR_Unknown,
302 DRM_MODE_CONNECTOR_Unknown,
303 DRM_MODE_CONNECTOR_HDMIA,
304 DRM_MODE_CONNECTOR_HDMIB,
305 DRM_MODE_CONNECTOR_Unknown,
306 DRM_MODE_CONNECTOR_Unknown,
307 DRM_MODE_CONNECTOR_9PinDIN,
308 DRM_MODE_CONNECTOR_DisplayPort
311 const uint16_t supported_devices_connector_object_id_convert[] = {
312 CONNECTOR_OBJECT_ID_NONE,
313 CONNECTOR_OBJECT_ID_VGA,
314 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
315 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
316 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
317 CONNECTOR_OBJECT_ID_COMPOSITE,
318 CONNECTOR_OBJECT_ID_SVIDEO,
319 CONNECTOR_OBJECT_ID_LVDS,
320 CONNECTOR_OBJECT_ID_9PIN_DIN,
321 CONNECTOR_OBJECT_ID_9PIN_DIN,
322 CONNECTOR_OBJECT_ID_DISPLAYPORT,
323 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
324 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
325 CONNECTOR_OBJECT_ID_SVIDEO
328 const int object_connector_convert[] = {
329 DRM_MODE_CONNECTOR_Unknown,
330 DRM_MODE_CONNECTOR_DVII,
331 DRM_MODE_CONNECTOR_DVII,
332 DRM_MODE_CONNECTOR_DVID,
333 DRM_MODE_CONNECTOR_DVID,
334 DRM_MODE_CONNECTOR_VGA,
335 DRM_MODE_CONNECTOR_Composite,
336 DRM_MODE_CONNECTOR_SVIDEO,
337 DRM_MODE_CONNECTOR_Unknown,
338 DRM_MODE_CONNECTOR_Unknown,
339 DRM_MODE_CONNECTOR_9PinDIN,
340 DRM_MODE_CONNECTOR_Unknown,
341 DRM_MODE_CONNECTOR_HDMIA,
342 DRM_MODE_CONNECTOR_HDMIB,
343 DRM_MODE_CONNECTOR_LVDS,
344 DRM_MODE_CONNECTOR_9PinDIN,
345 DRM_MODE_CONNECTOR_Unknown,
346 DRM_MODE_CONNECTOR_Unknown,
347 DRM_MODE_CONNECTOR_Unknown,
348 DRM_MODE_CONNECTOR_DisplayPort
351 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
353 struct radeon_device *rdev = dev->dev_private;
354 struct radeon_mode_info *mode_info = &rdev->mode_info;
355 struct atom_context *ctx = mode_info->atom_context;
356 int index = GetIndexIntoMasterTable(DATA, Object_Header);
357 u16 size, data_offset;
359 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
360 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
361 ATOM_OBJECT_HEADER *obj_header;
362 int i, j, path_size, device_support;
364 u16 igp_lane_info, conn_id, connector_object_id;
366 struct radeon_i2c_bus_rec ddc_bus;
367 struct radeon_gpio_rec gpio;
368 struct radeon_hpd hpd;
370 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
372 if (data_offset == 0)
378 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
379 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
380 (ctx->bios + data_offset +
381 le16_to_cpu(obj_header->usDisplayPathTableOffset));
382 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
383 (ctx->bios + data_offset +
384 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
385 device_support = le16_to_cpu(obj_header->usDeviceSupport);
388 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
389 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
390 ATOM_DISPLAY_OBJECT_PATH *path;
392 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
393 path_size += le16_to_cpu(path->usSize);
395 if (device_support & le16_to_cpu(path->usDeviceTag)) {
396 uint8_t con_obj_id, con_obj_num, con_obj_type;
399 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
402 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
405 (le16_to_cpu(path->usConnObjectId) &
406 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
408 /* TODO CV support */
409 if (le16_to_cpu(path->usDeviceTag) ==
410 ATOM_DEVICE_CV_SUPPORT)
414 if ((rdev->flags & RADEON_IS_IGP) &&
416 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
417 uint16_t igp_offset = 0;
418 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
421 GetIndexIntoMasterTable(DATA,
422 IntegratedSystemInfo);
424 atom_parse_data_header(ctx, index, &size, &frev,
429 (ATOM_INTEGRATED_SYSTEM_INFO_V2
430 *) (ctx->bios + igp_offset);
433 uint32_t slot_config, ct;
435 if (con_obj_num == 1)
444 ct = (slot_config >> 16) & 0xff;
446 object_connector_convert
448 connector_object_id = ct;
450 slot_config & 0xffff;
458 object_connector_convert[con_obj_id];
459 connector_object_id = con_obj_id;
462 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
465 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
467 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
470 (le16_to_cpu(path->usGraphicObjIds[j]) &
471 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
473 (le16_to_cpu(path->usGraphicObjIds[j]) &
474 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
476 (le16_to_cpu(path->usGraphicObjIds[j]) &
477 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
479 /* FIXME: add support for router objects */
480 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
481 if (enc_obj_num == 2)
486 radeon_add_atom_encoder(dev,
495 /* look up gpio for ddc, hpd */
496 if ((le16_to_cpu(path->usDeviceTag) &
497 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
498 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
499 if (le16_to_cpu(path->usConnObjectId) ==
500 le16_to_cpu(con_obj->asObjects[j].
502 ATOM_COMMON_RECORD_HEADER
504 (ATOM_COMMON_RECORD_HEADER
506 (ctx->bios + data_offset +
507 le16_to_cpu(con_obj->
510 ATOM_I2C_RECORD *i2c_record;
511 ATOM_HPD_INT_RECORD *hpd_record;
512 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
513 hpd.hpd = RADEON_HPD_NONE;
515 while (record->ucRecordType > 0
518 ATOM_MAX_OBJECT_RECORD_NUMBER) {
519 switch (record->ucRecordType) {
520 case ATOM_I2C_RECORD_TYPE:
525 (ATOM_I2C_ID_CONFIG_ACCESS *)
526 &i2c_record->sucI2cId;
527 ddc_bus = radeon_lookup_i2c_gpio(rdev,
531 case ATOM_HPD_INT_RECORD_TYPE:
533 (ATOM_HPD_INT_RECORD *)
535 gpio = radeon_lookup_gpio(rdev,
536 hpd_record->ucHPDIntGPIOID);
537 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
538 hpd.plugged_state = hpd_record->ucPlugged_PinState;
542 (ATOM_COMMON_RECORD_HEADER
552 hpd.hpd = RADEON_HPD_NONE;
553 ddc_bus.valid = false;
556 conn_id = le16_to_cpu(path->usConnObjectId);
558 if (!radeon_atom_apply_quirks
559 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
560 &ddc_bus, &conn_id, &hpd))
563 radeon_add_atom_connector(dev,
567 connector_type, &ddc_bus,
568 linkb, igp_lane_info,
575 radeon_link_encoder_connector(dev);
580 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
584 struct radeon_device *rdev = dev->dev_private;
586 if (rdev->flags & RADEON_IS_IGP) {
587 return supported_devices_connector_object_id_convert
589 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
590 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
591 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
592 struct radeon_mode_info *mode_info = &rdev->mode_info;
593 struct atom_context *ctx = mode_info->atom_context;
594 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
595 uint16_t size, data_offset;
597 ATOM_XTMDS_INFO *xtmds;
599 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
600 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
602 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
603 if (connector_type == DRM_MODE_CONNECTOR_DVII)
604 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
606 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
608 if (connector_type == DRM_MODE_CONNECTOR_DVII)
609 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
611 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
614 return supported_devices_connector_object_id_convert
619 struct bios_connector {
624 struct radeon_i2c_bus_rec ddc_bus;
625 struct radeon_hpd hpd;
628 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
632 struct radeon_device *rdev = dev->dev_private;
633 struct radeon_mode_info *mode_info = &rdev->mode_info;
634 struct atom_context *ctx = mode_info->atom_context;
635 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
636 uint16_t size, data_offset;
638 uint16_t device_support;
640 union atom_supported_devices *supported_devices;
641 int i, j, max_device;
642 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
644 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
647 (union atom_supported_devices *)(ctx->bios + data_offset);
649 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
652 max_device = ATOM_MAX_SUPPORTED_DEVICE;
654 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
656 for (i = 0; i < max_device; i++) {
657 ATOM_CONNECTOR_INFO_I2C ci =
658 supported_devices->info.asConnInfo[i];
660 bios_connectors[i].valid = false;
662 if (!(device_support & (1 << i))) {
666 if (i == ATOM_DEVICE_CV_INDEX) {
667 DRM_DEBUG("Skipping Component Video\n");
671 bios_connectors[i].connector_type =
672 supported_devices_connector_convert[ci.sucConnectorInfo.
676 if (bios_connectors[i].connector_type ==
677 DRM_MODE_CONNECTOR_Unknown)
680 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
682 bios_connectors[i].line_mux =
683 ci.sucI2cId.ucAccess;
685 /* give tv unique connector ids */
686 if (i == ATOM_DEVICE_TV1_INDEX) {
687 bios_connectors[i].ddc_bus.valid = false;
688 bios_connectors[i].line_mux = 50;
689 } else if (i == ATOM_DEVICE_TV2_INDEX) {
690 bios_connectors[i].ddc_bus.valid = false;
691 bios_connectors[i].line_mux = 51;
692 } else if (i == ATOM_DEVICE_CV_INDEX) {
693 bios_connectors[i].ddc_bus.valid = false;
694 bios_connectors[i].line_mux = 52;
696 bios_connectors[i].ddc_bus =
697 radeon_lookup_i2c_gpio(rdev,
698 bios_connectors[i].line_mux);
700 if ((crev > 1) && (frev > 1)) {
701 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
704 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
707 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
710 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
714 if (i == ATOM_DEVICE_DFP1_INDEX)
715 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
716 else if (i == ATOM_DEVICE_DFP2_INDEX)
717 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
719 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
722 /* Always set the connector type to VGA for CRT1/CRT2. if they are
723 * shared with a DVI port, we'll pick up the DVI connector when we
724 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
726 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
727 bios_connectors[i].connector_type =
728 DRM_MODE_CONNECTOR_VGA;
730 if (!radeon_atom_apply_quirks
731 (dev, (1 << i), &bios_connectors[i].connector_type,
732 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
733 &bios_connectors[i].hpd))
736 bios_connectors[i].valid = true;
737 bios_connectors[i].devices = (1 << i);
739 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
740 radeon_add_atom_encoder(dev,
741 radeon_get_encoder_id(dev,
746 radeon_add_legacy_encoder(dev,
747 radeon_get_encoder_id(dev,
754 /* combine shared connectors */
755 for (i = 0; i < max_device; i++) {
756 if (bios_connectors[i].valid) {
757 for (j = 0; j < max_device; j++) {
758 if (bios_connectors[j].valid && (i != j)) {
759 if (bios_connectors[i].line_mux ==
760 bios_connectors[j].line_mux) {
761 if (((bios_connectors[i].
763 (ATOM_DEVICE_DFP_SUPPORT))
764 && (bios_connectors[j].
766 (ATOM_DEVICE_CRT_SUPPORT)))
768 ((bios_connectors[j].
770 (ATOM_DEVICE_DFP_SUPPORT))
771 && (bios_connectors[i].
773 (ATOM_DEVICE_CRT_SUPPORT)))) {
780 DRM_MODE_CONNECTOR_DVII;
781 if (bios_connectors[j].devices &
782 (ATOM_DEVICE_DFP_SUPPORT))
783 bios_connectors[i].hpd =
784 bios_connectors[j].hpd;
794 /* add the connectors */
795 for (i = 0; i < max_device; i++) {
796 if (bios_connectors[i].valid) {
797 uint16_t connector_object_id =
798 atombios_get_connector_object_id(dev,
799 bios_connectors[i].connector_type,
800 bios_connectors[i].devices);
801 radeon_add_atom_connector(dev,
802 bios_connectors[i].line_mux,
803 bios_connectors[i].devices,
806 &bios_connectors[i].ddc_bus,
809 &bios_connectors[i].hpd);
813 radeon_link_encoder_connector(dev);
818 union firmware_info {
819 ATOM_FIRMWARE_INFO info;
820 ATOM_FIRMWARE_INFO_V1_2 info_12;
821 ATOM_FIRMWARE_INFO_V1_3 info_13;
822 ATOM_FIRMWARE_INFO_V1_4 info_14;
825 bool radeon_atom_get_clock_info(struct drm_device *dev)
827 struct radeon_device *rdev = dev->dev_private;
828 struct radeon_mode_info *mode_info = &rdev->mode_info;
829 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
830 union firmware_info *firmware_info;
832 struct radeon_pll *p1pll = &rdev->clock.p1pll;
833 struct radeon_pll *p2pll = &rdev->clock.p2pll;
834 struct radeon_pll *spll = &rdev->clock.spll;
835 struct radeon_pll *mpll = &rdev->clock.mpll;
836 uint16_t data_offset;
838 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
839 &crev, &data_offset);
842 (union firmware_info *)(mode_info->atom_context->bios +
847 p1pll->reference_freq =
848 le16_to_cpu(firmware_info->info.usReferenceClock);
849 p1pll->reference_div = 0;
853 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
856 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
858 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
860 if (p1pll->pll_out_min == 0) {
861 if (ASIC_IS_AVIVO(rdev))
862 p1pll->pll_out_min = 64800;
864 p1pll->pll_out_min = 20000;
865 } else if (p1pll->pll_out_min > 64800) {
866 /* Limiting the pll output range is a good thing generally as
867 * it limits the number of possible pll combinations for a given
868 * frequency presumably to the ones that work best on each card.
869 * However, certain duallink DVI monitors seem to like
870 * pll combinations that would be limited by this at least on
871 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
875 p1pll->pll_out_min = 64800;
879 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
881 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
886 spll->reference_freq =
887 le16_to_cpu(firmware_info->info.usReferenceClock);
888 spll->reference_div = 0;
891 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
893 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
896 if (spll->pll_out_min == 0) {
897 if (ASIC_IS_AVIVO(rdev))
898 spll->pll_out_min = 64800;
900 spll->pll_out_min = 20000;
904 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
906 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
909 mpll->reference_freq =
910 le16_to_cpu(firmware_info->info.usReferenceClock);
911 mpll->reference_div = 0;
914 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
916 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
919 if (mpll->pll_out_min == 0) {
920 if (ASIC_IS_AVIVO(rdev))
921 mpll->pll_out_min = 64800;
923 mpll->pll_out_min = 20000;
927 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
929 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
931 rdev->clock.default_sclk =
932 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
933 rdev->clock.default_mclk =
934 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
941 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
942 struct radeon_encoder_int_tmds *tmds)
944 struct drm_device *dev = encoder->base.dev;
945 struct radeon_device *rdev = dev->dev_private;
946 struct radeon_mode_info *mode_info = &rdev->mode_info;
947 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
948 uint16_t data_offset;
949 struct _ATOM_TMDS_INFO *tmds_info;
954 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
955 &crev, &data_offset);
958 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
962 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
963 for (i = 0; i < 4; i++) {
964 tmds->tmds_pll[i].freq =
965 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
966 tmds->tmds_pll[i].value =
967 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
968 tmds->tmds_pll[i].value |=
969 (tmds_info->asMiscInfo[i].
970 ucPLL_VCO_Gain & 0x3f) << 6;
971 tmds->tmds_pll[i].value |=
972 (tmds_info->asMiscInfo[i].
973 ucPLL_DutyCycle & 0xf) << 12;
974 tmds->tmds_pll[i].value |=
975 (tmds_info->asMiscInfo[i].
976 ucPLL_VoltageSwing & 0xf) << 16;
978 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
979 tmds->tmds_pll[i].freq,
980 tmds->tmds_pll[i].value);
982 if (maxfreq == tmds->tmds_pll[i].freq) {
983 tmds->tmds_pll[i].freq = 0xffffffff;
992 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
997 struct drm_device *dev = encoder->base.dev;
998 struct radeon_device *rdev = dev->dev_private;
999 struct radeon_mode_info *mode_info = &rdev->mode_info;
1000 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1001 uint16_t data_offset;
1002 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1004 struct radeon_atom_ss *ss = NULL;
1007 if (id > ATOM_MAX_SS_ENTRY)
1010 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1011 &crev, &data_offset);
1014 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1018 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1023 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1024 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1026 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1027 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1028 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1029 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1030 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1031 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1039 struct _ATOM_LVDS_INFO info;
1040 struct _ATOM_LVDS_INFO_V12 info_12;
1043 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1047 struct drm_device *dev = encoder->base.dev;
1048 struct radeon_device *rdev = dev->dev_private;
1049 struct radeon_mode_info *mode_info = &rdev->mode_info;
1050 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1051 uint16_t data_offset, misc;
1052 union lvds_info *lvds_info;
1054 struct radeon_encoder_atom_dig *lvds = NULL;
1056 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
1057 &crev, &data_offset);
1060 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1064 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1069 lvds->native_mode.clock =
1070 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1071 lvds->native_mode.hdisplay =
1072 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1073 lvds->native_mode.vdisplay =
1074 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1075 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1076 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1077 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1078 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1079 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1080 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1081 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1082 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1083 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1084 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1085 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1086 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1087 lvds->panel_pwr_delay =
1088 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1089 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1091 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1092 if (misc & ATOM_VSYNC_POLARITY)
1093 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1094 if (misc & ATOM_HSYNC_POLARITY)
1095 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1096 if (misc & ATOM_COMPOSITESYNC)
1097 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1098 if (misc & ATOM_INTERLACE)
1099 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1100 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1101 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1103 /* set crtc values */
1104 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1106 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1108 encoder->native_mode = lvds->native_mode;
1113 struct radeon_encoder_primary_dac *
1114 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1116 struct drm_device *dev = encoder->base.dev;
1117 struct radeon_device *rdev = dev->dev_private;
1118 struct radeon_mode_info *mode_info = &rdev->mode_info;
1119 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1120 uint16_t data_offset;
1121 struct _COMPASSIONATE_DATA *dac_info;
1124 struct radeon_encoder_primary_dac *p_dac = NULL;
1126 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1128 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1131 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1136 bg = dac_info->ucDAC1_BG_Adjustment;
1137 dac = dac_info->ucDAC1_DAC_Adjustment;
1138 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1144 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1145 struct drm_display_mode *mode)
1147 struct radeon_mode_info *mode_info = &rdev->mode_info;
1148 ATOM_ANALOG_TV_INFO *tv_info;
1149 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1150 ATOM_DTD_FORMAT *dtd_timings;
1151 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1153 u16 data_offset, misc;
1155 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
1159 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1160 if (index > MAX_SUPPORTED_TV_TIMING)
1163 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1164 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1165 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1166 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1167 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1169 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1170 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1171 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1172 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1173 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1176 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1177 if (misc & ATOM_VSYNC_POLARITY)
1178 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1179 if (misc & ATOM_HSYNC_POLARITY)
1180 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1181 if (misc & ATOM_COMPOSITESYNC)
1182 mode->flags |= DRM_MODE_FLAG_CSYNC;
1183 if (misc & ATOM_INTERLACE)
1184 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1185 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1186 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1188 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1191 /* PAL timings appear to have wrong values for totals */
1192 mode->crtc_htotal -= 1;
1193 mode->crtc_vtotal -= 1;
1197 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1198 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1201 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1202 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1203 le16_to_cpu(dtd_timings->usHBlanking_Time);
1204 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1205 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1206 le16_to_cpu(dtd_timings->usHSyncOffset);
1207 mode->crtc_hsync_end = mode->crtc_hsync_start +
1208 le16_to_cpu(dtd_timings->usHSyncWidth);
1210 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1211 le16_to_cpu(dtd_timings->usVBlanking_Time);
1212 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1213 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1214 le16_to_cpu(dtd_timings->usVSyncOffset);
1215 mode->crtc_vsync_end = mode->crtc_vsync_start +
1216 le16_to_cpu(dtd_timings->usVSyncWidth);
1219 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1220 if (misc & ATOM_VSYNC_POLARITY)
1221 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1222 if (misc & ATOM_HSYNC_POLARITY)
1223 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1224 if (misc & ATOM_COMPOSITESYNC)
1225 mode->flags |= DRM_MODE_FLAG_CSYNC;
1226 if (misc & ATOM_INTERLACE)
1227 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1228 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1229 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1231 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1237 struct radeon_encoder_tv_dac *
1238 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1240 struct drm_device *dev = encoder->base.dev;
1241 struct radeon_device *rdev = dev->dev_private;
1242 struct radeon_mode_info *mode_info = &rdev->mode_info;
1243 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1244 uint16_t data_offset;
1245 struct _COMPASSIONATE_DATA *dac_info;
1248 struct radeon_encoder_tv_dac *tv_dac = NULL;
1250 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1252 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1255 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1260 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1261 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1262 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1264 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1265 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1266 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1268 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1269 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1270 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1276 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1278 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1279 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1281 args.ucEnable = enable;
1283 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1286 void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
1288 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
1289 int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
1291 args.ucEnable = enable;
1293 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1296 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1298 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1299 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1301 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1302 return args.ulReturnEngineClock;
1305 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1307 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1308 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1310 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1311 return args.ulReturnMemoryClock;
1314 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1317 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1318 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1320 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1322 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1325 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1328 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1329 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1331 if (rdev->flags & RADEON_IS_IGP)
1334 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1336 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1339 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1341 struct radeon_device *rdev = dev->dev_private;
1342 uint32_t bios_2_scratch, bios_6_scratch;
1344 if (rdev->family >= CHIP_R600) {
1345 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1346 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1348 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1349 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1352 /* let the bios control the backlight */
1353 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1355 /* tell the bios not to handle mode switching */
1356 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1358 if (rdev->family >= CHIP_R600) {
1359 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1360 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1362 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1363 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1368 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1370 uint32_t scratch_reg;
1373 if (rdev->family >= CHIP_R600)
1374 scratch_reg = R600_BIOS_0_SCRATCH;
1376 scratch_reg = RADEON_BIOS_0_SCRATCH;
1378 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1379 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1382 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1384 uint32_t scratch_reg;
1387 if (rdev->family >= CHIP_R600)
1388 scratch_reg = R600_BIOS_0_SCRATCH;
1390 scratch_reg = RADEON_BIOS_0_SCRATCH;
1392 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1393 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1396 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1398 struct drm_device *dev = encoder->dev;
1399 struct radeon_device *rdev = dev->dev_private;
1400 uint32_t bios_6_scratch;
1402 if (rdev->family >= CHIP_R600)
1403 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1405 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1408 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1410 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1412 if (rdev->family >= CHIP_R600)
1413 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1415 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1418 /* at some point we may want to break this out into individual functions */
1420 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1421 struct drm_encoder *encoder,
1424 struct drm_device *dev = connector->dev;
1425 struct radeon_device *rdev = dev->dev_private;
1426 struct radeon_connector *radeon_connector =
1427 to_radeon_connector(connector);
1428 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1429 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1431 if (rdev->family >= CHIP_R600) {
1432 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1433 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1434 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1436 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1437 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1438 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1441 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1442 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1444 DRM_DEBUG("TV1 connected\n");
1445 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1446 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1448 DRM_DEBUG("TV1 disconnected\n");
1449 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1450 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1451 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1454 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1455 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1457 DRM_DEBUG("CV connected\n");
1458 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1459 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1461 DRM_DEBUG("CV disconnected\n");
1462 bios_0_scratch &= ~ATOM_S0_CV_MASK;
1463 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1464 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1467 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1468 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1470 DRM_DEBUG("LCD1 connected\n");
1471 bios_0_scratch |= ATOM_S0_LCD1;
1472 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1473 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1475 DRM_DEBUG("LCD1 disconnected\n");
1476 bios_0_scratch &= ~ATOM_S0_LCD1;
1477 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1478 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1481 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1482 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1484 DRM_DEBUG("CRT1 connected\n");
1485 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1486 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1487 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1489 DRM_DEBUG("CRT1 disconnected\n");
1490 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1491 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1492 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1495 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1496 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1498 DRM_DEBUG("CRT2 connected\n");
1499 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1500 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1501 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1503 DRM_DEBUG("CRT2 disconnected\n");
1504 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1505 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1506 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1509 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1510 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1512 DRM_DEBUG("DFP1 connected\n");
1513 bios_0_scratch |= ATOM_S0_DFP1;
1514 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1515 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1517 DRM_DEBUG("DFP1 disconnected\n");
1518 bios_0_scratch &= ~ATOM_S0_DFP1;
1519 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1520 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1523 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1524 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1526 DRM_DEBUG("DFP2 connected\n");
1527 bios_0_scratch |= ATOM_S0_DFP2;
1528 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1529 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1531 DRM_DEBUG("DFP2 disconnected\n");
1532 bios_0_scratch &= ~ATOM_S0_DFP2;
1533 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1534 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1537 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1538 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1540 DRM_DEBUG("DFP3 connected\n");
1541 bios_0_scratch |= ATOM_S0_DFP3;
1542 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1543 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1545 DRM_DEBUG("DFP3 disconnected\n");
1546 bios_0_scratch &= ~ATOM_S0_DFP3;
1547 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1548 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1551 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1552 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1554 DRM_DEBUG("DFP4 connected\n");
1555 bios_0_scratch |= ATOM_S0_DFP4;
1556 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1557 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1559 DRM_DEBUG("DFP4 disconnected\n");
1560 bios_0_scratch &= ~ATOM_S0_DFP4;
1561 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1562 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1565 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1566 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1568 DRM_DEBUG("DFP5 connected\n");
1569 bios_0_scratch |= ATOM_S0_DFP5;
1570 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1571 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1573 DRM_DEBUG("DFP5 disconnected\n");
1574 bios_0_scratch &= ~ATOM_S0_DFP5;
1575 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1576 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1580 if (rdev->family >= CHIP_R600) {
1581 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1582 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1583 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1585 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1586 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1587 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1592 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1594 struct drm_device *dev = encoder->dev;
1595 struct radeon_device *rdev = dev->dev_private;
1596 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1597 uint32_t bios_3_scratch;
1599 if (rdev->family >= CHIP_R600)
1600 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1602 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1604 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1605 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1606 bios_3_scratch |= (crtc << 18);
1608 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1609 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1610 bios_3_scratch |= (crtc << 24);
1612 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1613 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1614 bios_3_scratch |= (crtc << 16);
1616 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1617 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1618 bios_3_scratch |= (crtc << 20);
1620 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1621 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1622 bios_3_scratch |= (crtc << 17);
1624 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1625 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1626 bios_3_scratch |= (crtc << 19);
1628 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1629 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1630 bios_3_scratch |= (crtc << 23);
1632 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1633 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1634 bios_3_scratch |= (crtc << 25);
1637 if (rdev->family >= CHIP_R600)
1638 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1640 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1644 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1646 struct drm_device *dev = encoder->dev;
1647 struct radeon_device *rdev = dev->dev_private;
1648 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1649 uint32_t bios_2_scratch;
1651 if (rdev->family >= CHIP_R600)
1652 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1654 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1656 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1658 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1660 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1662 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1664 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1666 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1668 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1670 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1672 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1674 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1676 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1678 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1680 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1682 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1684 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1686 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1688 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1690 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1692 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1694 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1696 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1698 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1700 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1702 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1704 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1706 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1708 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1710 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1712 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1714 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1717 if (rdev->family >= CHIP_R600)
1718 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1720 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);