drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 /**
  44  * radeon_invalid_rreg - dummy reg read function
  45  *
  46  * @rdev: radeon device pointer
  47  * @reg: offset of register
  48  *
  49  * Dummy register read function.  Used for register blocks
  50  * that certain asics don't have (all asics).
  51  * Returns the value in the register.
  52  */
  53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  54 {
  55         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  56         BUG_ON(1);
  57         return 0;
  58 }
  59
  60 /**
  61  * radeon_invalid_wreg - dummy reg write function
  62  *
  63  * @rdev: radeon device pointer
  64  * @reg: offset of register
  65  * @v: value to write to the register
  66  *
  67  * Dummy register read function.  Used for register blocks
  68  * that certain asics don't have (all asics).
  69  */
  70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  71 {
  72         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  73                   reg, v);
  74         BUG_ON(1);
  75 }
  76
  77 /**
  78  * radeon_register_accessor_init - sets up the register accessor callbacks
  79  *
  80  * @rdev: radeon device pointer
  81  *
  82  * Sets up the register accessor callbacks for various register
  83  * apertures.  Not all asics have all apertures (all asics).
  84  */
  85 static void radeon_register_accessor_init(struct radeon_device *rdev)
  86 {
  87         rdev->mc_rreg = &radeon_invalid_rreg;
  88         rdev->mc_wreg = &radeon_invalid_wreg;
  89         rdev->pll_rreg = &radeon_invalid_rreg;
  90         rdev->pll_wreg = &radeon_invalid_wreg;
  91         rdev->pciep_rreg = &radeon_invalid_rreg;
  92         rdev->pciep_wreg = &radeon_invalid_wreg;
  93
  94         /* Don't change order as we are overridding accessor. */
  95         if (rdev->family < CHIP_RV515) {
  96                 rdev->pcie_reg_mask = 0xff;
  97         } else {
  98                 rdev->pcie_reg_mask = 0x7ff;
  99         }
 100         /* FIXME: not sure here */
 101         if (rdev->family <= CHIP_R580) {
 102                 rdev->pll_rreg = &r100_pll_rreg;
 103                 rdev->pll_wreg = &r100_pll_wreg;
 104         }
 105         if (rdev->family >= CHIP_R420) {
 106                 rdev->mc_rreg = &r420_mc_rreg;
 107                 rdev->mc_wreg = &r420_mc_wreg;
 108         }
 109         if (rdev->family >= CHIP_RV515) {
 110                 rdev->mc_rreg = &rv515_mc_rreg;
 111                 rdev->mc_wreg = &rv515_mc_wreg;
 112         }
 113         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 114                 rdev->mc_rreg = &rs400_mc_rreg;
 115                 rdev->mc_wreg = &rs400_mc_wreg;
 116         }
 117         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 118                 rdev->mc_rreg = &rs690_mc_rreg;
 119                 rdev->mc_wreg = &rs690_mc_wreg;
 120         }
 121         if (rdev->family == CHIP_RS600) {
 122                 rdev->mc_rreg = &rs600_mc_rreg;
 123                 rdev->mc_wreg = &rs600_mc_wreg;
 124         }
 125         if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
 126                 rdev->mc_rreg = &rs780_mc_rreg;
 127                 rdev->mc_wreg = &rs780_mc_wreg;
 128         }
 129
 130         if (rdev->family >= CHIP_BONAIRE) {
 131                 rdev->pciep_rreg = &cik_pciep_rreg;
 132                 rdev->pciep_wreg = &cik_pciep_wreg;
 133         } else if (rdev->family >= CHIP_R600) {
 134                 rdev->pciep_rreg = &r600_pciep_rreg;
 135                 rdev->pciep_wreg = &r600_pciep_wreg;
 136         }
 137 }
 138
 139
 140 /* helper to disable agp */
 141 /**
 142  * radeon_agp_disable - AGP disable helper function
 143  *
 144  * @rdev: radeon device pointer
 145  *
 146  * Removes AGP flags and changes the gart callbacks on AGP
 147  * cards when using the internal gart rather than AGP (all asics).
 148  */
 149 void radeon_agp_disable(struct radeon_device *rdev)
 150 {
 151         rdev->flags &= ~RADEON_IS_AGP;
 152         if (rdev->family >= CHIP_R600) {
 153                 DRM_INFO("Forcing AGP to PCIE mode\n");
 154                 rdev->flags |= RADEON_IS_PCIE;
 155         } else if (rdev->family >= CHIP_RV515 ||
 156                         rdev->family == CHIP_RV380 ||
 157                         rdev->family == CHIP_RV410 ||
 158                         rdev->family == CHIP_R423) {
 159                 DRM_INFO("Forcing AGP to PCIE mode\n");
 160                 rdev->flags |= RADEON_IS_PCIE;
 161                 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 162                 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 163         } else {
 164                 DRM_INFO("Forcing AGP to PCI mode\n");
 165                 rdev->flags |= RADEON_IS_PCI;
 166                 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 167                 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 168         }
 169         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 170 }
 171
 172 /*
 173  * ASIC
 174  */
 175
 176 static struct radeon_asic_ring r100_gfx_ring = {
 177         .ib_execute = &r100_ring_ib_execute,
 178         .emit_fence = &r100_fence_ring_emit,
 179         .emit_semaphore = &r100_semaphore_ring_emit,
 180         .cs_parse = &r100_cs_parse,
 181         .ring_start = &r100_ring_start,
 182         .ring_test = &r100_ring_test,
 183         .ib_test = &r100_ib_test,
 184         .is_lockup = &r100_gpu_is_lockup,
 185         .get_rptr = &r100_gfx_get_rptr,
 186         .get_wptr = &r100_gfx_get_wptr,
 187         .set_wptr = &r100_gfx_set_wptr,
 188 };
 189
 190 static struct radeon_asic r100_asic = {
 191         .init = &r100_init,
 192         .fini = &r100_fini,
 193         .suspend = &r100_suspend,
 194         .resume = &r100_resume,
 195         .vga_set_state = &r100_vga_set_state,
 196         .asic_reset = &r100_asic_reset,
 197         .mmio_hdp_flush = NULL,
 198         .gui_idle = &r100_gui_idle,
 199         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 200         .gart = {
 201                 .tlb_flush = &r100_pci_gart_tlb_flush,
 202                 .set_page = &r100_pci_gart_set_page,
 203         },
 204         .ring = {
 205                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
 206         },
 207         .irq = {
 208                 .set = &r100_irq_set,
 209                 .process = &r100_irq_process,
 210         },
 211         .display = {
 212                 .bandwidth_update = &r100_bandwidth_update,
 213                 .get_vblank_counter = &r100_get_vblank_counter,
 214                 .wait_for_vblank = &r100_wait_for_vblank,
 215                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 216                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 217         },
 218         .copy = {
 219                 .blit = &r100_copy_blit,
 220                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 221                 .dma = NULL,
 222                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 223                 .copy = &r100_copy_blit,
 224                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 225         },
 226         .surface = {
 227                 .set_reg = r100_set_surface_reg,
 228                 .clear_reg = r100_clear_surface_reg,
 229         },
 230         .hpd = {
 231                 .init = &r100_hpd_init,
 232                 .fini = &r100_hpd_fini,
 233                 .sense = &r100_hpd_sense,
 234                 .set_polarity = &r100_hpd_set_polarity,
 235         },
 236         .pm = {
 237                 .misc = &r100_pm_misc,
 238                 .prepare = &r100_pm_prepare,
 239                 .finish = &r100_pm_finish,
 240                 .init_profile = &r100_pm_init_profile,
 241                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 242                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 243                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 244                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 245                 .set_memory_clock = NULL,
 246                 .get_pcie_lanes = NULL,
 247                 .set_pcie_lanes = NULL,
 248                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 249         },
 250         .pflip = {
 251                 .page_flip = &r100_page_flip,
 252                 .page_flip_pending = &r100_page_flip_pending,
 253         },
 254 };
 255
 256 static struct radeon_asic r200_asic = {
 257         .init = &r100_init,
 258         .fini = &r100_fini,
 259         .suspend = &r100_suspend,
 260         .resume = &r100_resume,
 261         .vga_set_state = &r100_vga_set_state,
 262         .asic_reset = &r100_asic_reset,
 263         .mmio_hdp_flush = NULL,
 264         .gui_idle = &r100_gui_idle,
 265         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 266         .gart = {
 267                 .tlb_flush = &r100_pci_gart_tlb_flush,
 268                 .set_page = &r100_pci_gart_set_page,
 269         },
 270         .ring = {
 271                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
 272         },
 273         .irq = {
 274                 .set = &r100_irq_set,
 275                 .process = &r100_irq_process,
 276         },
 277         .display = {
 278                 .bandwidth_update = &r100_bandwidth_update,
 279                 .get_vblank_counter = &r100_get_vblank_counter,
 280                 .wait_for_vblank = &r100_wait_for_vblank,
 281                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 282                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 283         },
 284         .copy = {
 285                 .blit = &r100_copy_blit,
 286                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 287                 .dma = &r200_copy_dma,
 288                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 289                 .copy = &r100_copy_blit,
 290                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 291         },
 292         .surface = {
 293                 .set_reg = r100_set_surface_reg,
 294                 .clear_reg = r100_clear_surface_reg,
 295         },
 296         .hpd = {
 297                 .init = &r100_hpd_init,
 298                 .fini = &r100_hpd_fini,
 299                 .sense = &r100_hpd_sense,
 300                 .set_polarity = &r100_hpd_set_polarity,
 301         },
 302         .pm = {
 303                 .misc = &r100_pm_misc,
 304                 .prepare = &r100_pm_prepare,
 305                 .finish = &r100_pm_finish,
 306                 .init_profile = &r100_pm_init_profile,
 307                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 308                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 309                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 310                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 311                 .set_memory_clock = NULL,
 312                 .get_pcie_lanes = NULL,
 313                 .set_pcie_lanes = NULL,
 314                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 315         },
 316         .pflip = {
 317                 .page_flip = &r100_page_flip,
 318                 .page_flip_pending = &r100_page_flip_pending,
 319         },
 320 };
 321
 322 static struct radeon_asic_ring r300_gfx_ring = {
 323         .ib_execute = &r100_ring_ib_execute,
 324         .emit_fence = &r300_fence_ring_emit,
 325         .emit_semaphore = &r100_semaphore_ring_emit,
 326         .cs_parse = &r300_cs_parse,
 327         .ring_start = &r300_ring_start,
 328         .ring_test = &r100_ring_test,
 329         .ib_test = &r100_ib_test,
 330         .is_lockup = &r100_gpu_is_lockup,
 331         .get_rptr = &r100_gfx_get_rptr,
 332         .get_wptr = &r100_gfx_get_wptr,
 333         .set_wptr = &r100_gfx_set_wptr,
 334 };
 335
 336 static struct radeon_asic_ring rv515_gfx_ring = {
 337         .ib_execute = &r100_ring_ib_execute,
 338         .emit_fence = &r300_fence_ring_emit,
 339         .emit_semaphore = &r100_semaphore_ring_emit,
 340         .cs_parse = &r300_cs_parse,
 341         .ring_start = &rv515_ring_start,
 342         .ring_test = &r100_ring_test,
 343         .ib_test = &r100_ib_test,
 344         .is_lockup = &r100_gpu_is_lockup,
 345         .get_rptr = &r100_gfx_get_rptr,
 346         .get_wptr = &r100_gfx_get_wptr,
 347         .set_wptr = &r100_gfx_set_wptr,
 348 };
 349
 350 static struct radeon_asic r300_asic = {
 351         .init = &r300_init,
 352         .fini = &r300_fini,
 353         .suspend = &r300_suspend,
 354         .resume = &r300_resume,
 355         .vga_set_state = &r100_vga_set_state,
 356         .asic_reset = &r300_asic_reset,
 357         .mmio_hdp_flush = NULL,
 358         .gui_idle = &r100_gui_idle,
 359         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 360         .gart = {
 361                 .tlb_flush = &r100_pci_gart_tlb_flush,
 362                 .set_page = &r100_pci_gart_set_page,
 363         },
 364         .ring = {
 365                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 366         },
 367         .irq = {
 368                 .set = &r100_irq_set,
 369                 .process = &r100_irq_process,
 370         },
 371         .display = {
 372                 .bandwidth_update = &r100_bandwidth_update,
 373                 .get_vblank_counter = &r100_get_vblank_counter,
 374                 .wait_for_vblank = &r100_wait_for_vblank,
 375                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 376                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 377         },
 378         .copy = {
 379                 .blit = &r100_copy_blit,
 380                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 381                 .dma = &r200_copy_dma,
 382                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 383                 .copy = &r100_copy_blit,
 384                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 385         },
 386         .surface = {
 387                 .set_reg = r100_set_surface_reg,
 388                 .clear_reg = r100_clear_surface_reg,
 389         },
 390         .hpd = {
 391                 .init = &r100_hpd_init,
 392                 .fini = &r100_hpd_fini,
 393                 .sense = &r100_hpd_sense,
 394                 .set_polarity = &r100_hpd_set_polarity,
 395         },
 396         .pm = {
 397                 .misc = &r100_pm_misc,
 398                 .prepare = &r100_pm_prepare,
 399                 .finish = &r100_pm_finish,
 400                 .init_profile = &r100_pm_init_profile,
 401                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 402                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 403                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 404                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 405                 .set_memory_clock = NULL,
 406                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 407                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 408                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 409         },
 410         .pflip = {
 411                 .page_flip = &r100_page_flip,
 412                 .page_flip_pending = &r100_page_flip_pending,
 413         },
 414 };
 415
 416 static struct radeon_asic r300_asic_pcie = {
 417         .init = &r300_init,
 418         .fini = &r300_fini,
 419         .suspend = &r300_suspend,
 420         .resume = &r300_resume,
 421         .vga_set_state = &r100_vga_set_state,
 422         .asic_reset = &r300_asic_reset,
 423         .mmio_hdp_flush = NULL,
 424         .gui_idle = &r100_gui_idle,
 425         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 426         .gart = {
 427                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 428                 .set_page = &rv370_pcie_gart_set_page,
 429         },
 430         .ring = {
 431                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 432         },
 433         .irq = {
 434                 .set = &r100_irq_set,
 435                 .process = &r100_irq_process,
 436         },
 437         .display = {
 438                 .bandwidth_update = &r100_bandwidth_update,
 439                 .get_vblank_counter = &r100_get_vblank_counter,
 440                 .wait_for_vblank = &r100_wait_for_vblank,
 441                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 442                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 443         },
 444         .copy = {
 445                 .blit = &r100_copy_blit,
 446                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 447                 .dma = &r200_copy_dma,
 448                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 449                 .copy = &r100_copy_blit,
 450                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 451         },
 452         .surface = {
 453                 .set_reg = r100_set_surface_reg,
 454                 .clear_reg = r100_clear_surface_reg,
 455         },
 456         .hpd = {
 457                 .init = &r100_hpd_init,
 458                 .fini = &r100_hpd_fini,
 459                 .sense = &r100_hpd_sense,
 460                 .set_polarity = &r100_hpd_set_polarity,
 461         },
 462         .pm = {
 463                 .misc = &r100_pm_misc,
 464                 .prepare = &r100_pm_prepare,
 465                 .finish = &r100_pm_finish,
 466                 .init_profile = &r100_pm_init_profile,
 467                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 468                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 469                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 470                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 471                 .set_memory_clock = NULL,
 472                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 473                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 474                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 475         },
 476         .pflip = {
 477                 .page_flip = &r100_page_flip,
 478                 .page_flip_pending = &r100_page_flip_pending,
 479         },
 480 };
 481
 482 static struct radeon_asic r420_asic = {
 483         .init = &r420_init,
 484         .fini = &r420_fini,
 485         .suspend = &r420_suspend,
 486         .resume = &r420_resume,
 487         .vga_set_state = &r100_vga_set_state,
 488         .asic_reset = &r300_asic_reset,
 489         .mmio_hdp_flush = NULL,
 490         .gui_idle = &r100_gui_idle,
 491         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 492         .gart = {
 493                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 494                 .set_page = &rv370_pcie_gart_set_page,
 495         },
 496         .ring = {
 497                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 498         },
 499         .irq = {
 500                 .set = &r100_irq_set,
 501                 .process = &r100_irq_process,
 502         },
 503         .display = {
 504                 .bandwidth_update = &r100_bandwidth_update,
 505                 .get_vblank_counter = &r100_get_vblank_counter,
 506                 .wait_for_vblank = &r100_wait_for_vblank,
 507                 .set_backlight_level = &atombios_set_backlight_level,
 508                 .get_backlight_level = &atombios_get_backlight_level,
 509         },
 510         .copy = {
 511                 .blit = &r100_copy_blit,
 512                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 513                 .dma = &r200_copy_dma,
 514                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 515                 .copy = &r100_copy_blit,
 516                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 517         },
 518         .surface = {
 519                 .set_reg = r100_set_surface_reg,
 520                 .clear_reg = r100_clear_surface_reg,
 521         },
 522         .hpd = {
 523                 .init = &r100_hpd_init,
 524                 .fini = &r100_hpd_fini,
 525                 .sense = &r100_hpd_sense,
 526                 .set_polarity = &r100_hpd_set_polarity,
 527         },
 528         .pm = {
 529                 .misc = &r100_pm_misc,
 530                 .prepare = &r100_pm_prepare,
 531                 .finish = &r100_pm_finish,
 532                 .init_profile = &r420_pm_init_profile,
 533                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 534                 .get_engine_clock = &radeon_atom_get_engine_clock,
 535                 .set_engine_clock = &radeon_atom_set_engine_clock,
 536                 .get_memory_clock = &radeon_atom_get_memory_clock,
 537                 .set_memory_clock = &radeon_atom_set_memory_clock,
 538                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 539                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 540                 .set_clock_gating = &radeon_atom_set_clock_gating,
 541         },
 542         .pflip = {
 543                 .page_flip = &r100_page_flip,
 544                 .page_flip_pending = &r100_page_flip_pending,
 545         },
 546 };
 547
 548 static struct radeon_asic rs400_asic = {
 549         .init = &rs400_init,
 550         .fini = &rs400_fini,
 551         .suspend = &rs400_suspend,
 552         .resume = &rs400_resume,
 553         .vga_set_state = &r100_vga_set_state,
 554         .asic_reset = &r300_asic_reset,
 555         .mmio_hdp_flush = NULL,
 556         .gui_idle = &r100_gui_idle,
 557         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
 558         .gart = {
 559                 .tlb_flush = &rs400_gart_tlb_flush,
 560                 .set_page = &rs400_gart_set_page,
 561         },
 562         .ring = {
 563                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 564         },
 565         .irq = {
 566                 .set = &r100_irq_set,
 567                 .process = &r100_irq_process,
 568         },
 569         .display = {
 570                 .bandwidth_update = &r100_bandwidth_update,
 571                 .get_vblank_counter = &r100_get_vblank_counter,
 572                 .wait_for_vblank = &r100_wait_for_vblank,
 573                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 574                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 575         },
 576         .copy = {
 577                 .blit = &r100_copy_blit,
 578                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 579                 .dma = &r200_copy_dma,
 580                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 581                 .copy = &r100_copy_blit,
 582                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 583         },
 584         .surface = {
 585                 .set_reg = r100_set_surface_reg,
 586                 .clear_reg = r100_clear_surface_reg,
 587         },
 588         .hpd = {
 589                 .init = &r100_hpd_init,
 590                 .fini = &r100_hpd_fini,
 591                 .sense = &r100_hpd_sense,
 592                 .set_polarity = &r100_hpd_set_polarity,
 593         },
 594         .pm = {
 595                 .misc = &r100_pm_misc,
 596                 .prepare = &r100_pm_prepare,
 597                 .finish = &r100_pm_finish,
 598                 .init_profile = &r100_pm_init_profile,
 599                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 600                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 601                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 602                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 603                 .set_memory_clock = NULL,
 604                 .get_pcie_lanes = NULL,
 605                 .set_pcie_lanes = NULL,
 606                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 607         },
 608         .pflip = {
 609                 .page_flip = &r100_page_flip,
 610                 .page_flip_pending = &r100_page_flip_pending,
 611         },
 612 };
 613
 614 static struct radeon_asic rs600_asic = {
 615         .init = &rs600_init,
 616         .fini = &rs600_fini,
 617         .suspend = &rs600_suspend,
 618         .resume = &rs600_resume,
 619         .vga_set_state = &r100_vga_set_state,
 620         .asic_reset = &rs600_asic_reset,
 621         .mmio_hdp_flush = NULL,
 622         .gui_idle = &r100_gui_idle,
 623         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
 624         .gart = {
 625                 .tlb_flush = &rs600_gart_tlb_flush,
 626                 .set_page = &rs600_gart_set_page,
 627         },
 628         .ring = {
 629                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 630         },
 631         .irq = {
 632                 .set = &rs600_irq_set,
 633                 .process = &rs600_irq_process,
 634         },
 635         .display = {
 636                 .bandwidth_update = &rs600_bandwidth_update,
 637                 .get_vblank_counter = &rs600_get_vblank_counter,
 638                 .wait_for_vblank = &avivo_wait_for_vblank,
 639                 .set_backlight_level = &atombios_set_backlight_level,
 640                 .get_backlight_level = &atombios_get_backlight_level,
 641                 .hdmi_enable = &r600_hdmi_enable,
 642                 .hdmi_setmode = &r600_hdmi_setmode,
 643         },
 644         .copy = {
 645                 .blit = &r100_copy_blit,
 646                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 647                 .dma = &r200_copy_dma,
 648                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 649                 .copy = &r100_copy_blit,
 650                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 651         },
 652         .surface = {
 653                 .set_reg = r100_set_surface_reg,
 654                 .clear_reg = r100_clear_surface_reg,
 655         },
 656         .hpd = {
 657                 .init = &rs600_hpd_init,
 658                 .fini = &rs600_hpd_fini,
 659                 .sense = &rs600_hpd_sense,
 660                 .set_polarity = &rs600_hpd_set_polarity,
 661         },
 662         .pm = {
 663                 .misc = &rs600_pm_misc,
 664                 .prepare = &rs600_pm_prepare,
 665                 .finish = &rs600_pm_finish,
 666                 .init_profile = &r420_pm_init_profile,
 667                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 668                 .get_engine_clock = &radeon_atom_get_engine_clock,
 669                 .set_engine_clock = &radeon_atom_set_engine_clock,
 670                 .get_memory_clock = &radeon_atom_get_memory_clock,
 671                 .set_memory_clock = &radeon_atom_set_memory_clock,
 672                 .get_pcie_lanes = NULL,
 673                 .set_pcie_lanes = NULL,
 674                 .set_clock_gating = &radeon_atom_set_clock_gating,
 675         },
 676         .pflip = {
 677                 .page_flip = &rs600_page_flip,
 678                 .page_flip_pending = &rs600_page_flip_pending,
 679         },
 680 };
 681
 682 static struct radeon_asic rs690_asic = {
 683         .init = &rs690_init,
 684         .fini = &rs690_fini,
 685         .suspend = &rs690_suspend,
 686         .resume = &rs690_resume,
 687         .vga_set_state = &r100_vga_set_state,
 688         .asic_reset = &rs600_asic_reset,
 689         .mmio_hdp_flush = NULL,
 690         .gui_idle = &r100_gui_idle,
 691         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
 692         .gart = {
 693                 .tlb_flush = &rs400_gart_tlb_flush,
 694                 .set_page = &rs400_gart_set_page,
 695         },
 696         .ring = {
 697                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 698         },
 699         .irq = {
 700                 .set = &rs600_irq_set,
 701                 .process = &rs600_irq_process,
 702         },
 703         .display = {
 704                 .get_vblank_counter = &rs600_get_vblank_counter,
 705                 .bandwidth_update = &rs690_bandwidth_update,
 706                 .wait_for_vblank = &avivo_wait_for_vblank,
 707                 .set_backlight_level = &atombios_set_backlight_level,
 708                 .get_backlight_level = &atombios_get_backlight_level,
 709                 .hdmi_enable = &r600_hdmi_enable,
 710                 .hdmi_setmode = &r600_hdmi_setmode,
 711         },
 712         .copy = {
 713                 .blit = &r100_copy_blit,
 714                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 715                 .dma = &r200_copy_dma,
 716                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 717                 .copy = &r200_copy_dma,
 718                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 719         },
 720         .surface = {
 721                 .set_reg = r100_set_surface_reg,
 722                 .clear_reg = r100_clear_surface_reg,
 723         },
 724         .hpd = {
 725                 .init = &rs600_hpd_init,
 726                 .fini = &rs600_hpd_fini,
 727                 .sense = &rs600_hpd_sense,
 728                 .set_polarity = &rs600_hpd_set_polarity,
 729         },
 730         .pm = {
 731                 .misc = &rs600_pm_misc,
 732                 .prepare = &rs600_pm_prepare,
 733                 .finish = &rs600_pm_finish,
 734                 .init_profile = &r420_pm_init_profile,
 735                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 736                 .get_engine_clock = &radeon_atom_get_engine_clock,
 737                 .set_engine_clock = &radeon_atom_set_engine_clock,
 738                 .get_memory_clock = &radeon_atom_get_memory_clock,
 739                 .set_memory_clock = &radeon_atom_set_memory_clock,
 740                 .get_pcie_lanes = NULL,
 741                 .set_pcie_lanes = NULL,
 742                 .set_clock_gating = &radeon_atom_set_clock_gating,
 743         },
 744         .pflip = {
 745                 .page_flip = &rs600_page_flip,
 746                 .page_flip_pending = &rs600_page_flip_pending,
 747         },
 748 };
 749
 750 static struct radeon_asic rv515_asic = {
 751         .init = &rv515_init,
 752         .fini = &rv515_fini,
 753         .suspend = &rv515_suspend,
 754         .resume = &rv515_resume,
 755         .vga_set_state = &r100_vga_set_state,
 756         .asic_reset = &rs600_asic_reset,
 757         .mmio_hdp_flush = NULL,
 758         .gui_idle = &r100_gui_idle,
 759         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
 760         .gart = {
 761                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 762                 .set_page = &rv370_pcie_gart_set_page,
 763         },
 764         .ring = {
 765                 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
 766         },
 767         .irq = {
 768                 .set = &rs600_irq_set,
 769                 .process = &rs600_irq_process,
 770         },
 771         .display = {
 772                 .get_vblank_counter = &rs600_get_vblank_counter,
 773                 .bandwidth_update = &rv515_bandwidth_update,
 774                 .wait_for_vblank = &avivo_wait_for_vblank,
 775                 .set_backlight_level = &atombios_set_backlight_level,
 776                 .get_backlight_level = &atombios_get_backlight_level,
 777         },
 778         .copy = {
 779                 .blit = &r100_copy_blit,
 780                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 781                 .dma = &r200_copy_dma,
 782                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 783                 .copy = &r100_copy_blit,
 784                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 785         },
 786         .surface = {
 787                 .set_reg = r100_set_surface_reg,
 788                 .clear_reg = r100_clear_surface_reg,
 789         },
 790         .hpd = {
 791                 .init = &rs600_hpd_init,
 792                 .fini = &rs600_hpd_fini,
 793                 .sense = &rs600_hpd_sense,
 794                 .set_polarity = &rs600_hpd_set_polarity,
 795         },
 796         .pm = {
 797                 .misc = &rs600_pm_misc,
 798                 .prepare = &rs600_pm_prepare,
 799                 .finish = &rs600_pm_finish,
 800                 .init_profile = &r420_pm_init_profile,
 801                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 802                 .get_engine_clock = &radeon_atom_get_engine_clock,
 803                 .set_engine_clock = &radeon_atom_set_engine_clock,
 804                 .get_memory_clock = &radeon_atom_get_memory_clock,
 805                 .set_memory_clock = &radeon_atom_set_memory_clock,
 806                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 807                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 808                 .set_clock_gating = &radeon_atom_set_clock_gating,
 809         },
 810         .pflip = {
 811                 .page_flip = &rs600_page_flip,
 812                 .page_flip_pending = &rs600_page_flip_pending,
 813         },
 814 };
 815
 816 static struct radeon_asic r520_asic = {
 817         .init = &r520_init,
 818         .fini = &rv515_fini,
 819         .suspend = &rv515_suspend,
 820         .resume = &r520_resume,
 821         .vga_set_state = &r100_vga_set_state,
 822         .asic_reset = &rs600_asic_reset,
 823         .mmio_hdp_flush = NULL,
 824         .gui_idle = &r100_gui_idle,
 825         .mc_wait_for_idle = &r520_mc_wait_for_idle,
 826         .gart = {
 827                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 828                 .set_page = &rv370_pcie_gart_set_page,
 829         },
 830         .ring = {
 831                 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
 832         },
 833         .irq = {
 834                 .set = &rs600_irq_set,
 835                 .process = &rs600_irq_process,
 836         },
 837         .display = {
 838                 .bandwidth_update = &rv515_bandwidth_update,
 839                 .get_vblank_counter = &rs600_get_vblank_counter,
 840                 .wait_for_vblank = &avivo_wait_for_vblank,
 841                 .set_backlight_level = &atombios_set_backlight_level,
 842                 .get_backlight_level = &atombios_get_backlight_level,
 843         },
 844         .copy = {
 845                 .blit = &r100_copy_blit,
 846                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 847                 .dma = &r200_copy_dma,
 848                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 849                 .copy = &r100_copy_blit,
 850                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 851         },
 852         .surface = {
 853                 .set_reg = r100_set_surface_reg,
 854                 .clear_reg = r100_clear_surface_reg,
 855         },
 856         .hpd = {
 857                 .init = &rs600_hpd_init,
 858                 .fini = &rs600_hpd_fini,
 859                 .sense = &rs600_hpd_sense,
 860                 .set_polarity = &rs600_hpd_set_polarity,
 861         },
 862         .pm = {
 863                 .misc = &rs600_pm_misc,
 864                 .prepare = &rs600_pm_prepare,
 865                 .finish = &rs600_pm_finish,
 866                 .init_profile = &r420_pm_init_profile,
 867                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 868                 .get_engine_clock = &radeon_atom_get_engine_clock,
 869                 .set_engine_clock = &radeon_atom_set_engine_clock,
 870                 .get_memory_clock = &radeon_atom_get_memory_clock,
 871                 .set_memory_clock = &radeon_atom_set_memory_clock,
 872                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 873                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 874                 .set_clock_gating = &radeon_atom_set_clock_gating,
 875         },
 876         .pflip = {
 877                 .page_flip = &rs600_page_flip,
 878                 .page_flip_pending = &rs600_page_flip_pending,
 879         },
 880 };
 881
 882 static struct radeon_asic_ring r600_gfx_ring = {
 883         .ib_execute = &r600_ring_ib_execute,
 884         .emit_fence = &r600_fence_ring_emit,
 885         .emit_semaphore = &r600_semaphore_ring_emit,
 886         .cs_parse = &r600_cs_parse,
 887         .ring_test = &r600_ring_test,
 888         .ib_test = &r600_ib_test,
 889         .is_lockup = &r600_gfx_is_lockup,
 890         .get_rptr = &r600_gfx_get_rptr,
 891         .get_wptr = &r600_gfx_get_wptr,
 892         .set_wptr = &r600_gfx_set_wptr,
 893 };
 894
 895 static struct radeon_asic_ring r600_dma_ring = {
 896         .ib_execute = &r600_dma_ring_ib_execute,
 897         .emit_fence = &r600_dma_fence_ring_emit,
 898         .emit_semaphore = &r600_dma_semaphore_ring_emit,
 899         .cs_parse = &r600_dma_cs_parse,
 900         .ring_test = &r600_dma_ring_test,
 901         .ib_test = &r600_dma_ib_test,
 902         .is_lockup = &r600_dma_is_lockup,
 903         .get_rptr = &r600_dma_get_rptr,
 904         .get_wptr = &r600_dma_get_wptr,
 905         .set_wptr = &r600_dma_set_wptr,
 906 };
 907
 908 static struct radeon_asic r600_asic = {
 909         .init = &r600_init,
 910         .fini = &r600_fini,
 911         .suspend = &r600_suspend,
 912         .resume = &r600_resume,
 913         .vga_set_state = &r600_vga_set_state,
 914         .asic_reset = &r600_asic_reset,
 915         .mmio_hdp_flush = r600_mmio_hdp_flush,
 916         .gui_idle = &r600_gui_idle,
 917         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 918         .get_xclk = &r600_get_xclk,
 919         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 920         .gart = {
 921                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 922                 .set_page = &rs600_gart_set_page,
 923         },
 924         .ring = {
 925                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
 926                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
 927         },
 928         .irq = {
 929                 .set = &r600_irq_set,
 930                 .process = &r600_irq_process,
 931         },
 932         .display = {
 933                 .bandwidth_update = &rv515_bandwidth_update,
 934                 .get_vblank_counter = &rs600_get_vblank_counter,
 935                 .wait_for_vblank = &avivo_wait_for_vblank,
 936                 .set_backlight_level = &atombios_set_backlight_level,
 937                 .get_backlight_level = &atombios_get_backlight_level,
 938                 .hdmi_enable = &r600_hdmi_enable,
 939                 .hdmi_setmode = &r600_hdmi_setmode,
 940         },
 941         .copy = {
 942                 .blit = &r600_copy_cpdma,
 943                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 944                 .dma = &r600_copy_dma,
 945                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
 946                 .copy = &r600_copy_cpdma,
 947                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 948         },
 949         .surface = {
 950                 .set_reg = r600_set_surface_reg,
 951                 .clear_reg = r600_clear_surface_reg,
 952         },
 953         .hpd = {
 954                 .init = &r600_hpd_init,
 955                 .fini = &r600_hpd_fini,
 956                 .sense = &r600_hpd_sense,
 957                 .set_polarity = &r600_hpd_set_polarity,
 958         },
 959         .pm = {
 960                 .misc = &r600_pm_misc,
 961                 .prepare = &rs600_pm_prepare,
 962                 .finish = &rs600_pm_finish,
 963                 .init_profile = &r600_pm_init_profile,
 964                 .get_dynpm_state = &r600_pm_get_dynpm_state,
 965                 .get_engine_clock = &radeon_atom_get_engine_clock,
 966                 .set_engine_clock = &radeon_atom_set_engine_clock,
 967                 .get_memory_clock = &radeon_atom_get_memory_clock,
 968                 .set_memory_clock = &radeon_atom_set_memory_clock,
 969                 .get_pcie_lanes = &r600_get_pcie_lanes,
 970                 .set_pcie_lanes = &r600_set_pcie_lanes,
 971                 .set_clock_gating = NULL,
 972                 .get_temperature = &rv6xx_get_temp,
 973         },
 974         .pflip = {
 975                 .page_flip = &rs600_page_flip,
 976                 .page_flip_pending = &rs600_page_flip_pending,
 977         },
 978 };
 979
 980 static struct radeon_asic_ring rv6xx_uvd_ring = {
 981         .ib_execute = &uvd_v1_0_ib_execute,
 982         .emit_fence = &uvd_v1_0_fence_emit,
 983         .emit_semaphore = &uvd_v1_0_semaphore_emit,
 984         .cs_parse = &radeon_uvd_cs_parse,
 985         .ring_test = &uvd_v1_0_ring_test,
 986         .ib_test = &uvd_v1_0_ib_test,
 987         .is_lockup = &radeon_ring_test_lockup,
 988         .get_rptr = &uvd_v1_0_get_rptr,
 989         .get_wptr = &uvd_v1_0_get_wptr,
 990         .set_wptr = &uvd_v1_0_set_wptr,
 991 };
 992
 993 static struct radeon_asic rv6xx_asic = {
 994         .init = &r600_init,
 995         .fini = &r600_fini,
 996         .suspend = &r600_suspend,
 997         .resume = &r600_resume,
 998         .vga_set_state = &r600_vga_set_state,
 999         .asic_reset = &r600_asic_reset,
1000         .mmio_hdp_flush = r600_mmio_hdp_flush,
1001         .gui_idle = &r600_gui_idle,
1002         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1003         .get_xclk = &r600_get_xclk,
1004         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1005         .gart = {
1006                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1007                 .set_page = &rs600_gart_set_page,
1008         },
1009         .ring = {
1010                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1011                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1012                 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1013         },
1014         .irq = {
1015                 .set = &r600_irq_set,
1016                 .process = &r600_irq_process,
1017         },
1018         .display = {
1019                 .bandwidth_update = &rv515_bandwidth_update,
1020                 .get_vblank_counter = &rs600_get_vblank_counter,
1021                 .wait_for_vblank = &avivo_wait_for_vblank,
1022                 .set_backlight_level = &atombios_set_backlight_level,
1023                 .get_backlight_level = &atombios_get_backlight_level,
1024                 .hdmi_enable = &r600_hdmi_enable,
1025                 .hdmi_setmode = &r600_hdmi_setmode,
1026         },
1027         .copy = {
1028                 .blit = &r600_copy_cpdma,
1029                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1030                 .dma = &r600_copy_dma,
1031                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1032                 .copy = &r600_copy_cpdma,
1033                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1034         },
1035         .surface = {
1036                 .set_reg = r600_set_surface_reg,
1037                 .clear_reg = r600_clear_surface_reg,
1038         },
1039         .hpd = {
1040                 .init = &r600_hpd_init,
1041                 .fini = &r600_hpd_fini,
1042                 .sense = &r600_hpd_sense,
1043                 .set_polarity = &r600_hpd_set_polarity,
1044         },
1045         .pm = {
1046                 .misc = &r600_pm_misc,
1047                 .prepare = &rs600_pm_prepare,
1048                 .finish = &rs600_pm_finish,
1049                 .init_profile = &r600_pm_init_profile,
1050                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1051                 .get_engine_clock = &radeon_atom_get_engine_clock,
1052                 .set_engine_clock = &radeon_atom_set_engine_clock,
1053                 .get_memory_clock = &radeon_atom_get_memory_clock,
1054                 .set_memory_clock = &radeon_atom_set_memory_clock,
1055                 .get_pcie_lanes = &r600_get_pcie_lanes,
1056                 .set_pcie_lanes = &r600_set_pcie_lanes,
1057                 .set_clock_gating = NULL,
1058                 .get_temperature = &rv6xx_get_temp,
1059                 .set_uvd_clocks = &r600_set_uvd_clocks,
1060         },
1061         .dpm = {
1062                 .init = &rv6xx_dpm_init,
1063                 .setup_asic = &rv6xx_setup_asic,
1064                 .enable = &rv6xx_dpm_enable,
1065                 .late_enable = &r600_dpm_late_enable,
1066                 .disable = &rv6xx_dpm_disable,
1067                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1068                 .set_power_state = &rv6xx_dpm_set_power_state,
1069                 .post_set_power_state = &r600_dpm_post_set_power_state,
1070                 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1071                 .fini = &rv6xx_dpm_fini,
1072                 .get_sclk = &rv6xx_dpm_get_sclk,
1073                 .get_mclk = &rv6xx_dpm_get_mclk,
1074                 .print_power_state = &rv6xx_dpm_print_power_state,
1075                 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1076                 .force_performance_level = &rv6xx_dpm_force_performance_level,
1077         },
1078         .pflip = {
1079                 .page_flip = &rs600_page_flip,
1080                 .page_flip_pending = &rs600_page_flip_pending,
1081         },
1082 };
1083
1084 static struct radeon_asic rs780_asic = {
1085         .init = &r600_init,
1086         .fini = &r600_fini,
1087         .suspend = &r600_suspend,
1088         .resume = &r600_resume,
1089         .vga_set_state = &r600_vga_set_state,
1090         .asic_reset = &r600_asic_reset,
1091         .mmio_hdp_flush = r600_mmio_hdp_flush,
1092         .gui_idle = &r600_gui_idle,
1093         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1094         .get_xclk = &r600_get_xclk,
1095         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1096         .gart = {
1097                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1098                 .set_page = &rs600_gart_set_page,
1099         },
1100         .ring = {
1101                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1102                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1103                 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1104         },
1105         .irq = {
1106                 .set = &r600_irq_set,
1107                 .process = &r600_irq_process,
1108         },
1109         .display = {
1110                 .bandwidth_update = &rs690_bandwidth_update,
1111                 .get_vblank_counter = &rs600_get_vblank_counter,
1112                 .wait_for_vblank = &avivo_wait_for_vblank,
1113                 .set_backlight_level = &atombios_set_backlight_level,
1114                 .get_backlight_level = &atombios_get_backlight_level,
1115                 .hdmi_enable = &r600_hdmi_enable,
1116                 .hdmi_setmode = &r600_hdmi_setmode,
1117         },
1118         .copy = {
1119                 .blit = &r600_copy_cpdma,
1120                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1121                 .dma = &r600_copy_dma,
1122                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1123                 .copy = &r600_copy_cpdma,
1124                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1125         },
1126         .surface = {
1127                 .set_reg = r600_set_surface_reg,
1128                 .clear_reg = r600_clear_surface_reg,
1129         },
1130         .hpd = {
1131                 .init = &r600_hpd_init,
1132                 .fini = &r600_hpd_fini,
1133                 .sense = &r600_hpd_sense,
1134                 .set_polarity = &r600_hpd_set_polarity,
1135         },
1136         .pm = {
1137                 .misc = &r600_pm_misc,
1138                 .prepare = &rs600_pm_prepare,
1139                 .finish = &rs600_pm_finish,
1140                 .init_profile = &rs780_pm_init_profile,
1141                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1142                 .get_engine_clock = &radeon_atom_get_engine_clock,
1143                 .set_engine_clock = &radeon_atom_set_engine_clock,
1144                 .get_memory_clock = NULL,
1145                 .set_memory_clock = NULL,
1146                 .get_pcie_lanes = NULL,
1147                 .set_pcie_lanes = NULL,
1148                 .set_clock_gating = NULL,
1149                 .get_temperature = &rv6xx_get_temp,
1150                 .set_uvd_clocks = &r600_set_uvd_clocks,
1151         },
1152         .dpm = {
1153                 .init = &rs780_dpm_init,
1154                 .setup_asic = &rs780_dpm_setup_asic,
1155                 .enable = &rs780_dpm_enable,
1156                 .late_enable = &r600_dpm_late_enable,
1157                 .disable = &rs780_dpm_disable,
1158                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1159                 .set_power_state = &rs780_dpm_set_power_state,
1160                 .post_set_power_state = &r600_dpm_post_set_power_state,
1161                 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1162                 .fini = &rs780_dpm_fini,
1163                 .get_sclk = &rs780_dpm_get_sclk,
1164                 .get_mclk = &rs780_dpm_get_mclk,
1165                 .print_power_state = &rs780_dpm_print_power_state,
1166                 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1167                 .force_performance_level = &rs780_dpm_force_performance_level,
1168         },
1169         .pflip = {
1170                 .page_flip = &rs600_page_flip,
1171                 .page_flip_pending = &rs600_page_flip_pending,
1172         },
1173 };
1174
1175 static struct radeon_asic_ring rv770_uvd_ring = {
1176         .ib_execute = &uvd_v1_0_ib_execute,
1177         .emit_fence = &uvd_v2_2_fence_emit,
1178         .emit_semaphore = &uvd_v1_0_semaphore_emit,
1179         .cs_parse = &radeon_uvd_cs_parse,
1180         .ring_test = &uvd_v1_0_ring_test,
1181         .ib_test = &uvd_v1_0_ib_test,
1182         .is_lockup = &radeon_ring_test_lockup,
1183         .get_rptr = &uvd_v1_0_get_rptr,
1184         .get_wptr = &uvd_v1_0_get_wptr,
1185         .set_wptr = &uvd_v1_0_set_wptr,
1186 };
1187
1188 static struct radeon_asic rv770_asic = {
1189         .init = &rv770_init,
1190         .fini = &rv770_fini,
1191         .suspend = &rv770_suspend,
1192         .resume = &rv770_resume,
1193         .asic_reset = &r600_asic_reset,
1194         .vga_set_state = &r600_vga_set_state,
1195         .mmio_hdp_flush = r600_mmio_hdp_flush,
1196         .gui_idle = &r600_gui_idle,
1197         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1198         .get_xclk = &rv770_get_xclk,
1199         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1200         .gart = {
1201                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1202                 .set_page = &rs600_gart_set_page,
1203         },
1204         .ring = {
1205                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1206                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1207                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1208         },
1209         .irq = {
1210                 .set = &r600_irq_set,
1211                 .process = &r600_irq_process,
1212         },
1213         .display = {
1214                 .bandwidth_update = &rv515_bandwidth_update,
1215                 .get_vblank_counter = &rs600_get_vblank_counter,
1216                 .wait_for_vblank = &avivo_wait_for_vblank,
1217                 .set_backlight_level = &atombios_set_backlight_level,
1218                 .get_backlight_level = &atombios_get_backlight_level,
1219                 .hdmi_enable = &r600_hdmi_enable,
1220                 .hdmi_setmode = &dce3_1_hdmi_setmode,
1221         },
1222         .copy = {
1223                 .blit = &r600_copy_cpdma,
1224                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1225                 .dma = &rv770_copy_dma,
1226                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1227                 .copy = &rv770_copy_dma,
1228                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1229         },
1230         .surface = {
1231                 .set_reg = r600_set_surface_reg,
1232                 .clear_reg = r600_clear_surface_reg,
1233         },
1234         .hpd = {
1235                 .init = &r600_hpd_init,
1236                 .fini = &r600_hpd_fini,
1237                 .sense = &r600_hpd_sense,
1238                 .set_polarity = &r600_hpd_set_polarity,
1239         },
1240         .pm = {
1241                 .misc = &rv770_pm_misc,
1242                 .prepare = &rs600_pm_prepare,
1243                 .finish = &rs600_pm_finish,
1244                 .init_profile = &r600_pm_init_profile,
1245                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1246                 .get_engine_clock = &radeon_atom_get_engine_clock,
1247                 .set_engine_clock = &radeon_atom_set_engine_clock,
1248                 .get_memory_clock = &radeon_atom_get_memory_clock,
1249                 .set_memory_clock = &radeon_atom_set_memory_clock,
1250                 .get_pcie_lanes = &r600_get_pcie_lanes,
1251                 .set_pcie_lanes = &r600_set_pcie_lanes,
1252                 .set_clock_gating = &radeon_atom_set_clock_gating,
1253                 .set_uvd_clocks = &rv770_set_uvd_clocks,
1254                 .get_temperature = &rv770_get_temp,
1255         },
1256         .dpm = {
1257                 .init = &rv770_dpm_init,
1258                 .setup_asic = &rv770_dpm_setup_asic,
1259                 .enable = &rv770_dpm_enable,
1260                 .late_enable = &rv770_dpm_late_enable,
1261                 .disable = &rv770_dpm_disable,
1262                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1263                 .set_power_state = &rv770_dpm_set_power_state,
1264                 .post_set_power_state = &r600_dpm_post_set_power_state,
1265                 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1266                 .fini = &rv770_dpm_fini,
1267                 .get_sclk = &rv770_dpm_get_sclk,
1268                 .get_mclk = &rv770_dpm_get_mclk,
1269                 .print_power_state = &rv770_dpm_print_power_state,
1270                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1271                 .force_performance_level = &rv770_dpm_force_performance_level,
1272                 .vblank_too_short = &rv770_dpm_vblank_too_short,
1273         },
1274         .pflip = {
1275                 .page_flip = &rv770_page_flip,
1276                 .page_flip_pending = &rv770_page_flip_pending,
1277         },
1278 };
1279
1280 static struct radeon_asic_ring evergreen_gfx_ring = {
1281         .ib_execute = &evergreen_ring_ib_execute,
1282         .emit_fence = &r600_fence_ring_emit,
1283         .emit_semaphore = &r600_semaphore_ring_emit,
1284         .cs_parse = &evergreen_cs_parse,
1285         .ring_test = &r600_ring_test,
1286         .ib_test = &r600_ib_test,
1287         .is_lockup = &evergreen_gfx_is_lockup,
1288         .get_rptr = &r600_gfx_get_rptr,
1289         .get_wptr = &r600_gfx_get_wptr,
1290         .set_wptr = &r600_gfx_set_wptr,
1291 };
1292
1293 static struct radeon_asic_ring evergreen_dma_ring = {
1294         .ib_execute = &evergreen_dma_ring_ib_execute,
1295         .emit_fence = &evergreen_dma_fence_ring_emit,
1296         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1297         .cs_parse = &evergreen_dma_cs_parse,
1298         .ring_test = &r600_dma_ring_test,
1299         .ib_test = &r600_dma_ib_test,
1300         .is_lockup = &evergreen_dma_is_lockup,
1301         .get_rptr = &r600_dma_get_rptr,
1302         .get_wptr = &r600_dma_get_wptr,
1303         .set_wptr = &r600_dma_set_wptr,
1304 };
1305
1306 static struct radeon_asic evergreen_asic = {
1307         .init = &evergreen_init,
1308         .fini = &evergreen_fini,
1309         .suspend = &evergreen_suspend,
1310         .resume = &evergreen_resume,
1311         .asic_reset = &evergreen_asic_reset,
1312         .vga_set_state = &r600_vga_set_state,
1313         .mmio_hdp_flush = r600_mmio_hdp_flush,
1314         .gui_idle = &r600_gui_idle,
1315         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1316         .get_xclk = &rv770_get_xclk,
1317         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1318         .gart = {
1319                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1320                 .set_page = &rs600_gart_set_page,
1321         },
1322         .ring = {
1323                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1324                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1325                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1326         },
1327         .irq = {
1328                 .set = &evergreen_irq_set,
1329                 .process = &evergreen_irq_process,
1330         },
1331         .display = {
1332                 .bandwidth_update = &evergreen_bandwidth_update,
1333                 .get_vblank_counter = &evergreen_get_vblank_counter,
1334                 .wait_for_vblank = &dce4_wait_for_vblank,
1335                 .set_backlight_level = &atombios_set_backlight_level,
1336                 .get_backlight_level = &atombios_get_backlight_level,
1337                 .hdmi_enable = &evergreen_hdmi_enable,
1338                 .hdmi_setmode = &evergreen_hdmi_setmode,
1339         },
1340         .copy = {
1341                 .blit = &r600_copy_cpdma,
1342                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1343                 .dma = &evergreen_copy_dma,
1344                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1345                 .copy = &evergreen_copy_dma,
1346                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1347         },
1348         .surface = {
1349                 .set_reg = r600_set_surface_reg,
1350                 .clear_reg = r600_clear_surface_reg,
1351         },
1352         .hpd = {
1353                 .init = &evergreen_hpd_init,
1354                 .fini = &evergreen_hpd_fini,
1355                 .sense = &evergreen_hpd_sense,
1356                 .set_polarity = &evergreen_hpd_set_polarity,
1357         },
1358         .pm = {
1359                 .misc = &evergreen_pm_misc,
1360                 .prepare = &evergreen_pm_prepare,
1361                 .finish = &evergreen_pm_finish,
1362                 .init_profile = &r600_pm_init_profile,
1363                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1364                 .get_engine_clock = &radeon_atom_get_engine_clock,
1365                 .set_engine_clock = &radeon_atom_set_engine_clock,
1366                 .get_memory_clock = &radeon_atom_get_memory_clock,
1367                 .set_memory_clock = &radeon_atom_set_memory_clock,
1368                 .get_pcie_lanes = &r600_get_pcie_lanes,
1369                 .set_pcie_lanes = &r600_set_pcie_lanes,
1370                 .set_clock_gating = NULL,
1371                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1372                 .get_temperature = &evergreen_get_temp,
1373         },
1374         .dpm = {
1375                 .init = &cypress_dpm_init,
1376                 .setup_asic = &cypress_dpm_setup_asic,
1377                 .enable = &cypress_dpm_enable,
1378                 .late_enable = &rv770_dpm_late_enable,
1379                 .disable = &cypress_dpm_disable,
1380                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1381                 .set_power_state = &cypress_dpm_set_power_state,
1382                 .post_set_power_state = &r600_dpm_post_set_power_state,
1383                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1384                 .fini = &cypress_dpm_fini,
1385                 .get_sclk = &rv770_dpm_get_sclk,
1386                 .get_mclk = &rv770_dpm_get_mclk,
1387                 .print_power_state = &rv770_dpm_print_power_state,
1388                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1389                 .force_performance_level = &rv770_dpm_force_performance_level,
1390                 .vblank_too_short = &cypress_dpm_vblank_too_short,
1391         },
1392         .pflip = {
1393                 .page_flip = &evergreen_page_flip,
1394                 .page_flip_pending = &evergreen_page_flip_pending,
1395         },
1396 };
1397
1398 static struct radeon_asic sumo_asic = {
1399         .init = &evergreen_init,
1400         .fini = &evergreen_fini,
1401         .suspend = &evergreen_suspend,
1402         .resume = &evergreen_resume,
1403         .asic_reset = &evergreen_asic_reset,
1404         .vga_set_state = &r600_vga_set_state,
1405         .mmio_hdp_flush = r600_mmio_hdp_flush,
1406         .gui_idle = &r600_gui_idle,
1407         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1408         .get_xclk = &r600_get_xclk,
1409         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1410         .gart = {
1411                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1412                 .set_page = &rs600_gart_set_page,
1413         },
1414         .ring = {
1415                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1416                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1417                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1418         },
1419         .irq = {
1420                 .set = &evergreen_irq_set,
1421                 .process = &evergreen_irq_process,
1422         },
1423         .display = {
1424                 .bandwidth_update = &evergreen_bandwidth_update,
1425                 .get_vblank_counter = &evergreen_get_vblank_counter,
1426                 .wait_for_vblank = &dce4_wait_for_vblank,
1427                 .set_backlight_level = &atombios_set_backlight_level,
1428                 .get_backlight_level = &atombios_get_backlight_level,
1429                 .hdmi_enable = &evergreen_hdmi_enable,
1430                 .hdmi_setmode = &evergreen_hdmi_setmode,
1431         },
1432         .copy = {
1433                 .blit = &r600_copy_cpdma,
1434                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1435                 .dma = &evergreen_copy_dma,
1436                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1437                 .copy = &evergreen_copy_dma,
1438                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1439         },
1440         .surface = {
1441                 .set_reg = r600_set_surface_reg,
1442                 .clear_reg = r600_clear_surface_reg,
1443         },
1444         .hpd = {
1445                 .init = &evergreen_hpd_init,
1446                 .fini = &evergreen_hpd_fini,
1447                 .sense = &evergreen_hpd_sense,
1448                 .set_polarity = &evergreen_hpd_set_polarity,
1449         },
1450         .pm = {
1451                 .misc = &evergreen_pm_misc,
1452                 .prepare = &evergreen_pm_prepare,
1453                 .finish = &evergreen_pm_finish,
1454                 .init_profile = &sumo_pm_init_profile,
1455                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1456                 .get_engine_clock = &radeon_atom_get_engine_clock,
1457                 .set_engine_clock = &radeon_atom_set_engine_clock,
1458                 .get_memory_clock = NULL,
1459                 .set_memory_clock = NULL,
1460                 .get_pcie_lanes = NULL,
1461                 .set_pcie_lanes = NULL,
1462                 .set_clock_gating = NULL,
1463                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1464                 .get_temperature = &sumo_get_temp,
1465         },
1466         .dpm = {
1467                 .init = &sumo_dpm_init,
1468                 .setup_asic = &sumo_dpm_setup_asic,
1469                 .enable = &sumo_dpm_enable,
1470                 .late_enable = &sumo_dpm_late_enable,
1471                 .disable = &sumo_dpm_disable,
1472                 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1473                 .set_power_state = &sumo_dpm_set_power_state,
1474                 .post_set_power_state = &sumo_dpm_post_set_power_state,
1475                 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1476                 .fini = &sumo_dpm_fini,
1477                 .get_sclk = &sumo_dpm_get_sclk,
1478                 .get_mclk = &sumo_dpm_get_mclk,
1479                 .print_power_state = &sumo_dpm_print_power_state,
1480                 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1481                 .force_performance_level = &sumo_dpm_force_performance_level,
1482         },
1483         .pflip = {
1484                 .page_flip = &evergreen_page_flip,
1485                 .page_flip_pending = &evergreen_page_flip_pending,
1486         },
1487 };
1488
1489 static struct radeon_asic btc_asic = {
1490         .init = &evergreen_init,
1491         .fini = &evergreen_fini,
1492         .suspend = &evergreen_suspend,
1493         .resume = &evergreen_resume,
1494         .asic_reset = &evergreen_asic_reset,
1495         .vga_set_state = &r600_vga_set_state,
1496         .mmio_hdp_flush = r600_mmio_hdp_flush,
1497         .gui_idle = &r600_gui_idle,
1498         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1499         .get_xclk = &rv770_get_xclk,
1500         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1501         .gart = {
1502                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1503                 .set_page = &rs600_gart_set_page,
1504         },
1505         .ring = {
1506                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1507                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1508                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1509         },
1510         .irq = {
1511                 .set = &evergreen_irq_set,
1512                 .process = &evergreen_irq_process,
1513         },
1514         .display = {
1515                 .bandwidth_update = &evergreen_bandwidth_update,
1516                 .get_vblank_counter = &evergreen_get_vblank_counter,
1517                 .wait_for_vblank = &dce4_wait_for_vblank,
1518                 .set_backlight_level = &atombios_set_backlight_level,
1519                 .get_backlight_level = &atombios_get_backlight_level,
1520                 .hdmi_enable = &evergreen_hdmi_enable,
1521                 .hdmi_setmode = &evergreen_hdmi_setmode,
1522         },
1523         .copy = {
1524                 .blit = &r600_copy_cpdma,
1525                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1526                 .dma = &evergreen_copy_dma,
1527                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1528                 .copy = &evergreen_copy_dma,
1529                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1530         },
1531         .surface = {
1532                 .set_reg = r600_set_surface_reg,
1533                 .clear_reg = r600_clear_surface_reg,
1534         },
1535         .hpd = {
1536                 .init = &evergreen_hpd_init,
1537                 .fini = &evergreen_hpd_fini,
1538                 .sense = &evergreen_hpd_sense,
1539                 .set_polarity = &evergreen_hpd_set_polarity,
1540         },
1541         .pm = {
1542                 .misc = &evergreen_pm_misc,
1543                 .prepare = &evergreen_pm_prepare,
1544                 .finish = &evergreen_pm_finish,
1545                 .init_profile = &btc_pm_init_profile,
1546                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1547                 .get_engine_clock = &radeon_atom_get_engine_clock,
1548                 .set_engine_clock = &radeon_atom_set_engine_clock,
1549                 .get_memory_clock = &radeon_atom_get_memory_clock,
1550                 .set_memory_clock = &radeon_atom_set_memory_clock,
1551                 .get_pcie_lanes = &r600_get_pcie_lanes,
1552                 .set_pcie_lanes = &r600_set_pcie_lanes,
1553                 .set_clock_gating = NULL,
1554                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1555                 .get_temperature = &evergreen_get_temp,
1556         },
1557         .dpm = {
1558                 .init = &btc_dpm_init,
1559                 .setup_asic = &btc_dpm_setup_asic,
1560                 .enable = &btc_dpm_enable,
1561                 .late_enable = &rv770_dpm_late_enable,
1562                 .disable = &btc_dpm_disable,
1563                 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1564                 .set_power_state = &btc_dpm_set_power_state,
1565                 .post_set_power_state = &btc_dpm_post_set_power_state,
1566                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1567                 .fini = &btc_dpm_fini,
1568                 .get_sclk = &btc_dpm_get_sclk,
1569                 .get_mclk = &btc_dpm_get_mclk,
1570                 .print_power_state = &rv770_dpm_print_power_state,
1571                 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
1572                 .force_performance_level = &rv770_dpm_force_performance_level,
1573                 .vblank_too_short = &btc_dpm_vblank_too_short,
1574         },
1575         .pflip = {
1576                 .page_flip = &evergreen_page_flip,
1577                 .page_flip_pending = &evergreen_page_flip_pending,
1578         },
1579 };
1580
1581 static struct radeon_asic_ring cayman_gfx_ring = {
1582         .ib_execute = &cayman_ring_ib_execute,
1583         .ib_parse = &evergreen_ib_parse,
1584         .emit_fence = &cayman_fence_ring_emit,
1585         .emit_semaphore = &r600_semaphore_ring_emit,
1586         .cs_parse = &evergreen_cs_parse,
1587         .ring_test = &r600_ring_test,
1588         .ib_test = &r600_ib_test,
1589         .is_lockup = &cayman_gfx_is_lockup,
1590         .vm_flush = &cayman_vm_flush,
1591         .get_rptr = &cayman_gfx_get_rptr,
1592         .get_wptr = &cayman_gfx_get_wptr,
1593         .set_wptr = &cayman_gfx_set_wptr,
1594 };
1595
1596 static struct radeon_asic_ring cayman_dma_ring = {
1597         .ib_execute = &cayman_dma_ring_ib_execute,
1598         .ib_parse = &evergreen_dma_ib_parse,
1599         .emit_fence = &evergreen_dma_fence_ring_emit,
1600         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1601         .cs_parse = &evergreen_dma_cs_parse,
1602         .ring_test = &r600_dma_ring_test,
1603         .ib_test = &r600_dma_ib_test,
1604         .is_lockup = &cayman_dma_is_lockup,
1605         .vm_flush = &cayman_dma_vm_flush,
1606         .get_rptr = &cayman_dma_get_rptr,
1607         .get_wptr = &cayman_dma_get_wptr,
1608         .set_wptr = &cayman_dma_set_wptr
1609 };
1610
1611 static struct radeon_asic_ring cayman_uvd_ring = {
1612         .ib_execute = &uvd_v1_0_ib_execute,
1613         .emit_fence = &uvd_v2_2_fence_emit,
1614         .emit_semaphore = &uvd_v3_1_semaphore_emit,
1615         .cs_parse = &radeon_uvd_cs_parse,
1616         .ring_test = &uvd_v1_0_ring_test,
1617         .ib_test = &uvd_v1_0_ib_test,
1618         .is_lockup = &radeon_ring_test_lockup,
1619         .get_rptr = &uvd_v1_0_get_rptr,
1620         .get_wptr = &uvd_v1_0_get_wptr,
1621         .set_wptr = &uvd_v1_0_set_wptr,
1622 };
1623
1624 static struct radeon_asic cayman_asic = {
1625         .init = &cayman_init,
1626         .fini = &cayman_fini,
1627         .suspend = &cayman_suspend,
1628         .resume = &cayman_resume,
1629         .asic_reset = &cayman_asic_reset,
1630         .vga_set_state = &r600_vga_set_state,
1631         .mmio_hdp_flush = r600_mmio_hdp_flush,
1632         .gui_idle = &r600_gui_idle,
1633         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1634         .get_xclk = &rv770_get_xclk,
1635         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1636         .gart = {
1637                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1638                 .set_page = &rs600_gart_set_page,
1639         },
1640         .vm = {
1641                 .init = &cayman_vm_init,
1642                 .fini = &cayman_vm_fini,
1643                 .copy_pages = &cayman_dma_vm_copy_pages,
1644                 .write_pages = &cayman_dma_vm_write_pages,
1645                 .set_pages = &cayman_dma_vm_set_pages,
1646                 .pad_ib = &cayman_dma_vm_pad_ib,
1647         },
1648         .ring = {
1649                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1650                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1651                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1652                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1653                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1654                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1655         },
1656         .irq = {
1657                 .set = &evergreen_irq_set,
1658                 .process = &evergreen_irq_process,
1659         },
1660         .display = {
1661                 .bandwidth_update = &evergreen_bandwidth_update,
1662                 .get_vblank_counter = &evergreen_get_vblank_counter,
1663                 .wait_for_vblank = &dce4_wait_for_vblank,
1664                 .set_backlight_level = &atombios_set_backlight_level,
1665                 .get_backlight_level = &atombios_get_backlight_level,
1666                 .hdmi_enable = &evergreen_hdmi_enable,
1667                 .hdmi_setmode = &evergreen_hdmi_setmode,
1668         },
1669         .copy = {
1670                 .blit = &r600_copy_cpdma,
1671                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1672                 .dma = &evergreen_copy_dma,
1673                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1674                 .copy = &evergreen_copy_dma,
1675                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1676         },
1677         .surface = {
1678                 .set_reg = r600_set_surface_reg,
1679                 .clear_reg = r600_clear_surface_reg,
1680         },
1681         .hpd = {
1682                 .init = &evergreen_hpd_init,
1683                 .fini = &evergreen_hpd_fini,
1684                 .sense = &evergreen_hpd_sense,
1685                 .set_polarity = &evergreen_hpd_set_polarity,
1686         },
1687         .pm = {
1688                 .misc = &evergreen_pm_misc,
1689                 .prepare = &evergreen_pm_prepare,
1690                 .finish = &evergreen_pm_finish,
1691                 .init_profile = &btc_pm_init_profile,
1692                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1693                 .get_engine_clock = &radeon_atom_get_engine_clock,
1694                 .set_engine_clock = &radeon_atom_set_engine_clock,
1695                 .get_memory_clock = &radeon_atom_get_memory_clock,
1696                 .set_memory_clock = &radeon_atom_set_memory_clock,
1697                 .get_pcie_lanes = &r600_get_pcie_lanes,
1698                 .set_pcie_lanes = &r600_set_pcie_lanes,
1699                 .set_clock_gating = NULL,
1700                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1701                 .get_temperature = &evergreen_get_temp,
1702         },
1703         .dpm = {
1704                 .init = &ni_dpm_init,
1705                 .setup_asic = &ni_dpm_setup_asic,
1706                 .enable = &ni_dpm_enable,
1707                 .late_enable = &rv770_dpm_late_enable,
1708                 .disable = &ni_dpm_disable,
1709                 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1710                 .set_power_state = &ni_dpm_set_power_state,
1711                 .post_set_power_state = &ni_dpm_post_set_power_state,
1712                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1713                 .fini = &ni_dpm_fini,
1714                 .get_sclk = &ni_dpm_get_sclk,
1715                 .get_mclk = &ni_dpm_get_mclk,
1716                 .print_power_state = &ni_dpm_print_power_state,
1717                 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1718                 .force_performance_level = &ni_dpm_force_performance_level,
1719                 .vblank_too_short = &ni_dpm_vblank_too_short,
1720         },
1721         .pflip = {
1722                 .page_flip = &evergreen_page_flip,
1723                 .page_flip_pending = &evergreen_page_flip_pending,
1724         },
1725 };
1726
1727 static struct radeon_asic trinity_asic = {
1728         .init = &cayman_init,
1729         .fini = &cayman_fini,
1730         .suspend = &cayman_suspend,
1731         .resume = &cayman_resume,
1732         .asic_reset = &cayman_asic_reset,
1733         .vga_set_state = &r600_vga_set_state,
1734         .mmio_hdp_flush = r600_mmio_hdp_flush,
1735         .gui_idle = &r600_gui_idle,
1736         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1737         .get_xclk = &r600_get_xclk,
1738         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1739         .gart = {
1740                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1741                 .set_page = &rs600_gart_set_page,
1742         },
1743         .vm = {
1744                 .init = &cayman_vm_init,
1745                 .fini = &cayman_vm_fini,
1746                 .copy_pages = &cayman_dma_vm_copy_pages,
1747                 .write_pages = &cayman_dma_vm_write_pages,
1748                 .set_pages = &cayman_dma_vm_set_pages,
1749                 .pad_ib = &cayman_dma_vm_pad_ib,
1750         },
1751         .ring = {
1752                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1753                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1754                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1755                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1756                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1757                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1758         },
1759         .irq = {
1760                 .set = &evergreen_irq_set,
1761                 .process = &evergreen_irq_process,
1762         },
1763         .display = {
1764                 .bandwidth_update = &dce6_bandwidth_update,
1765                 .get_vblank_counter = &evergreen_get_vblank_counter,
1766                 .wait_for_vblank = &dce4_wait_for_vblank,
1767                 .set_backlight_level = &atombios_set_backlight_level,
1768                 .get_backlight_level = &atombios_get_backlight_level,
1769                 .hdmi_enable = &evergreen_hdmi_enable,
1770                 .hdmi_setmode = &evergreen_hdmi_setmode,
1771         },
1772         .copy = {
1773                 .blit = &r600_copy_cpdma,
1774                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1775                 .dma = &evergreen_copy_dma,
1776                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1777                 .copy = &evergreen_copy_dma,
1778                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1779         },
1780         .surface = {
1781                 .set_reg = r600_set_surface_reg,
1782                 .clear_reg = r600_clear_surface_reg,
1783         },
1784         .hpd = {
1785                 .init = &evergreen_hpd_init,
1786                 .fini = &evergreen_hpd_fini,
1787                 .sense = &evergreen_hpd_sense,
1788                 .set_polarity = &evergreen_hpd_set_polarity,
1789         },
1790         .pm = {
1791                 .misc = &evergreen_pm_misc,
1792                 .prepare = &evergreen_pm_prepare,
1793                 .finish = &evergreen_pm_finish,
1794                 .init_profile = &sumo_pm_init_profile,
1795                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1796                 .get_engine_clock = &radeon_atom_get_engine_clock,
1797                 .set_engine_clock = &radeon_atom_set_engine_clock,
1798                 .get_memory_clock = NULL,
1799                 .set_memory_clock = NULL,
1800                 .get_pcie_lanes = NULL,
1801                 .set_pcie_lanes = NULL,
1802                 .set_clock_gating = NULL,
1803                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1804                 .get_temperature = &tn_get_temp,
1805         },
1806         .dpm = {
1807                 .init = &trinity_dpm_init,
1808                 .setup_asic = &trinity_dpm_setup_asic,
1809                 .enable = &trinity_dpm_enable,
1810                 .late_enable = &trinity_dpm_late_enable,
1811                 .disable = &trinity_dpm_disable,
1812                 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
1813                 .set_power_state = &trinity_dpm_set_power_state,
1814                 .post_set_power_state = &trinity_dpm_post_set_power_state,
1815                 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1816                 .fini = &trinity_dpm_fini,
1817                 .get_sclk = &trinity_dpm_get_sclk,
1818                 .get_mclk = &trinity_dpm_get_mclk,
1819                 .print_power_state = &trinity_dpm_print_power_state,
1820                 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1821                 .force_performance_level = &trinity_dpm_force_performance_level,
1822                 .enable_bapm = &trinity_dpm_enable_bapm,
1823         },
1824         .pflip = {
1825                 .page_flip = &evergreen_page_flip,
1826                 .page_flip_pending = &evergreen_page_flip_pending,
1827         },
1828 };
1829
1830 static struct radeon_asic_ring si_gfx_ring = {
1831         .ib_execute = &si_ring_ib_execute,
1832         .ib_parse = &si_ib_parse,
1833         .emit_fence = &si_fence_ring_emit,
1834         .emit_semaphore = &r600_semaphore_ring_emit,
1835         .cs_parse = NULL,
1836         .ring_test = &r600_ring_test,
1837         .ib_test = &r600_ib_test,
1838         .is_lockup = &si_gfx_is_lockup,
1839         .vm_flush = &si_vm_flush,
1840         .get_rptr = &cayman_gfx_get_rptr,
1841         .get_wptr = &cayman_gfx_get_wptr,
1842         .set_wptr = &cayman_gfx_set_wptr,
1843 };
1844
1845 static struct radeon_asic_ring si_dma_ring = {
1846         .ib_execute = &cayman_dma_ring_ib_execute,
1847         .ib_parse = &evergreen_dma_ib_parse,
1848         .emit_fence = &evergreen_dma_fence_ring_emit,
1849         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1850         .cs_parse = NULL,
1851         .ring_test = &r600_dma_ring_test,
1852         .ib_test = &r600_dma_ib_test,
1853         .is_lockup = &si_dma_is_lockup,
1854         .vm_flush = &si_dma_vm_flush,
1855         .get_rptr = &cayman_dma_get_rptr,
1856         .get_wptr = &cayman_dma_get_wptr,
1857         .set_wptr = &cayman_dma_set_wptr,
1858 };
1859
1860 static struct radeon_asic si_asic = {
1861         .init = &si_init,
1862         .fini = &si_fini,
1863         .suspend = &si_suspend,
1864         .resume = &si_resume,
1865         .asic_reset = &si_asic_reset,
1866         .vga_set_state = &r600_vga_set_state,
1867         .mmio_hdp_flush = r600_mmio_hdp_flush,
1868         .gui_idle = &r600_gui_idle,
1869         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1870         .get_xclk = &si_get_xclk,
1871         .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1872         .gart = {
1873                 .tlb_flush = &si_pcie_gart_tlb_flush,
1874                 .set_page = &rs600_gart_set_page,
1875         },
1876         .vm = {
1877                 .init = &si_vm_init,
1878                 .fini = &si_vm_fini,
1879                 .copy_pages = &si_dma_vm_copy_pages,
1880                 .write_pages = &si_dma_vm_write_pages,
1881                 .set_pages = &si_dma_vm_set_pages,
1882                 .pad_ib = &cayman_dma_vm_pad_ib,
1883         },
1884         .ring = {
1885                 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1886                 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1887                 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1888                 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1889                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1890                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1891         },
1892         .irq = {
1893                 .set = &si_irq_set,
1894                 .process = &si_irq_process,
1895         },
1896         .display = {
1897                 .bandwidth_update = &dce6_bandwidth_update,
1898                 .get_vblank_counter = &evergreen_get_vblank_counter,
1899                 .wait_for_vblank = &dce4_wait_for_vblank,
1900                 .set_backlight_level = &atombios_set_backlight_level,
1901                 .get_backlight_level = &atombios_get_backlight_level,
1902                 .hdmi_enable = &evergreen_hdmi_enable,
1903                 .hdmi_setmode = &evergreen_hdmi_setmode,
1904         },
1905         .copy = {
1906                 .blit = &r600_copy_cpdma,
1907                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1908                 .dma = &si_copy_dma,
1909                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1910                 .copy = &si_copy_dma,
1911                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1912         },
1913         .surface = {
1914                 .set_reg = r600_set_surface_reg,
1915                 .clear_reg = r600_clear_surface_reg,
1916         },
1917         .hpd = {
1918                 .init = &evergreen_hpd_init,
1919                 .fini = &evergreen_hpd_fini,
1920                 .sense = &evergreen_hpd_sense,
1921                 .set_polarity = &evergreen_hpd_set_polarity,
1922         },
1923         .pm = {
1924                 .misc = &evergreen_pm_misc,
1925                 .prepare = &evergreen_pm_prepare,
1926                 .finish = &evergreen_pm_finish,
1927                 .init_profile = &sumo_pm_init_profile,
1928                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1929                 .get_engine_clock = &radeon_atom_get_engine_clock,
1930                 .set_engine_clock = &radeon_atom_set_engine_clock,
1931                 .get_memory_clock = &radeon_atom_get_memory_clock,
1932                 .set_memory_clock = &radeon_atom_set_memory_clock,
1933                 .get_pcie_lanes = &r600_get_pcie_lanes,
1934                 .set_pcie_lanes = &r600_set_pcie_lanes,
1935                 .set_clock_gating = NULL,
1936                 .set_uvd_clocks = &si_set_uvd_clocks,
1937                 .get_temperature = &si_get_temp,
1938         },
1939         .dpm = {
1940                 .init = &si_dpm_init,
1941                 .setup_asic = &si_dpm_setup_asic,
1942                 .enable = &si_dpm_enable,
1943                 .late_enable = &si_dpm_late_enable,
1944                 .disable = &si_dpm_disable,
1945                 .pre_set_power_state = &si_dpm_pre_set_power_state,
1946                 .set_power_state = &si_dpm_set_power_state,
1947                 .post_set_power_state = &si_dpm_post_set_power_state,
1948                 .display_configuration_changed = &si_dpm_display_configuration_changed,
1949                 .fini = &si_dpm_fini,
1950                 .get_sclk = &ni_dpm_get_sclk,
1951                 .get_mclk = &ni_dpm_get_mclk,
1952                 .print_power_state = &ni_dpm_print_power_state,
1953                 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
1954                 .force_performance_level = &si_dpm_force_performance_level,
1955                 .vblank_too_short = &ni_dpm_vblank_too_short,
1956         },
1957         .pflip = {
1958                 .page_flip = &evergreen_page_flip,
1959                 .page_flip_pending = &evergreen_page_flip_pending,
1960         },
1961 };
1962
1963 static struct radeon_asic_ring ci_gfx_ring = {
1964         .ib_execute = &cik_ring_ib_execute,
1965         .ib_parse = &cik_ib_parse,
1966         .emit_fence = &cik_fence_gfx_ring_emit,
1967         .emit_semaphore = &cik_semaphore_ring_emit,
1968         .cs_parse = NULL,
1969         .ring_test = &cik_ring_test,
1970         .ib_test = &cik_ib_test,
1971         .is_lockup = &cik_gfx_is_lockup,
1972         .vm_flush = &cik_vm_flush,
1973         .get_rptr = &cik_gfx_get_rptr,
1974         .get_wptr = &cik_gfx_get_wptr,
1975         .set_wptr = &cik_gfx_set_wptr,
1976 };
1977
1978 static struct radeon_asic_ring ci_cp_ring = {
1979         .ib_execute = &cik_ring_ib_execute,
1980         .ib_parse = &cik_ib_parse,
1981         .emit_fence = &cik_fence_compute_ring_emit,
1982         .emit_semaphore = &cik_semaphore_ring_emit,
1983         .cs_parse = NULL,
1984         .ring_test = &cik_ring_test,
1985         .ib_test = &cik_ib_test,
1986         .is_lockup = &cik_gfx_is_lockup,
1987         .vm_flush = &cik_vm_flush,
1988         .get_rptr = &cik_compute_get_rptr,
1989         .get_wptr = &cik_compute_get_wptr,
1990         .set_wptr = &cik_compute_set_wptr,
1991 };
1992
1993 static struct radeon_asic_ring ci_dma_ring = {
1994         .ib_execute = &cik_sdma_ring_ib_execute,
1995         .ib_parse = &cik_ib_parse,
1996         .emit_fence = &cik_sdma_fence_ring_emit,
1997         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
1998         .cs_parse = NULL,
1999         .ring_test = &cik_sdma_ring_test,
2000         .ib_test = &cik_sdma_ib_test,
2001         .is_lockup = &cik_sdma_is_lockup,
2002         .vm_flush = &cik_dma_vm_flush,
2003         .get_rptr = &cik_sdma_get_rptr,
2004         .get_wptr = &cik_sdma_get_wptr,
2005         .set_wptr = &cik_sdma_set_wptr,
2006 };
2007
2008 static struct radeon_asic_ring ci_vce_ring = {
2009         .ib_execute = &radeon_vce_ib_execute,
2010         .emit_fence = &radeon_vce_fence_emit,
2011         .emit_semaphore = &radeon_vce_semaphore_emit,
2012         .cs_parse = &radeon_vce_cs_parse,
2013         .ring_test = &radeon_vce_ring_test,
2014         .ib_test = &radeon_vce_ib_test,
2015         .is_lockup = &radeon_ring_test_lockup,
2016         .get_rptr = &vce_v1_0_get_rptr,
2017         .get_wptr = &vce_v1_0_get_wptr,
2018         .set_wptr = &vce_v1_0_set_wptr,
2019 };
2020
2021 static struct radeon_asic ci_asic = {
2022         .init = &cik_init,
2023         .fini = &cik_fini,
2024         .suspend = &cik_suspend,
2025         .resume = &cik_resume,
2026         .asic_reset = &cik_asic_reset,
2027         .vga_set_state = &r600_vga_set_state,
2028         .mmio_hdp_flush = &r600_mmio_hdp_flush,
2029         .gui_idle = &r600_gui_idle,
2030         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2031         .get_xclk = &cik_get_xclk,
2032         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2033         .gart = {
2034                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2035                 .set_page = &rs600_gart_set_page,
2036         },
2037         .vm = {
2038                 .init = &cik_vm_init,
2039                 .fini = &cik_vm_fini,
2040                 .copy_pages = &cik_sdma_vm_copy_pages,
2041                 .write_pages = &cik_sdma_vm_write_pages,
2042                 .set_pages = &cik_sdma_vm_set_pages,
2043                 .pad_ib = &cik_sdma_vm_pad_ib,
2044         },
2045         .ring = {
2046                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2047                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2048                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2049                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2050                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2051                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2052                 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2053                 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2054         },
2055         .irq = {
2056                 .set = &cik_irq_set,
2057                 .process = &cik_irq_process,
2058         },
2059         .display = {
2060                 .bandwidth_update = &dce8_bandwidth_update,
2061                 .get_vblank_counter = &evergreen_get_vblank_counter,
2062                 .wait_for_vblank = &dce4_wait_for_vblank,
2063                 .set_backlight_level = &atombios_set_backlight_level,
2064                 .get_backlight_level = &atombios_get_backlight_level,
2065                 .hdmi_enable = &evergreen_hdmi_enable,
2066                 .hdmi_setmode = &evergreen_hdmi_setmode,
2067         },
2068         .copy = {
2069                 .blit = &cik_copy_cpdma,
2070                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2071                 .dma = &cik_copy_dma,
2072                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2073                 .copy = &cik_copy_dma,
2074                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2075         },
2076         .surface = {
2077                 .set_reg = r600_set_surface_reg,
2078                 .clear_reg = r600_clear_surface_reg,
2079         },
2080         .hpd = {
2081                 .init = &evergreen_hpd_init,
2082                 .fini = &evergreen_hpd_fini,
2083                 .sense = &evergreen_hpd_sense,
2084                 .set_polarity = &evergreen_hpd_set_polarity,
2085         },
2086         .pm = {
2087                 .misc = &evergreen_pm_misc,
2088                 .prepare = &evergreen_pm_prepare,
2089                 .finish = &evergreen_pm_finish,
2090                 .init_profile = &sumo_pm_init_profile,
2091                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2092                 .get_engine_clock = &radeon_atom_get_engine_clock,
2093                 .set_engine_clock = &radeon_atom_set_engine_clock,
2094                 .get_memory_clock = &radeon_atom_get_memory_clock,
2095                 .set_memory_clock = &radeon_atom_set_memory_clock,
2096                 .get_pcie_lanes = NULL,
2097                 .set_pcie_lanes = NULL,
2098                 .set_clock_gating = NULL,
2099                 .set_uvd_clocks = &cik_set_uvd_clocks,
2100                 .set_vce_clocks = &cik_set_vce_clocks,
2101                 .get_temperature = &ci_get_temp,
2102         },
2103         .dpm = {
2104                 .init = &ci_dpm_init,
2105                 .setup_asic = &ci_dpm_setup_asic,
2106                 .enable = &ci_dpm_enable,
2107                 .late_enable = &ci_dpm_late_enable,
2108                 .disable = &ci_dpm_disable,
2109                 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2110                 .set_power_state = &ci_dpm_set_power_state,
2111                 .post_set_power_state = &ci_dpm_post_set_power_state,
2112                 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2113                 .fini = &ci_dpm_fini,
2114                 .get_sclk = &ci_dpm_get_sclk,
2115                 .get_mclk = &ci_dpm_get_mclk,
2116                 .print_power_state = &ci_dpm_print_power_state,
2117                 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2118                 .force_performance_level = &ci_dpm_force_performance_level,
2119                 .vblank_too_short = &ci_dpm_vblank_too_short,
2120                 .powergate_uvd = &ci_dpm_powergate_uvd,
2121         },
2122         .pflip = {
2123                 .page_flip = &evergreen_page_flip,
2124                 .page_flip_pending = &evergreen_page_flip_pending,
2125         },
2126 };
2127
2128 static struct radeon_asic kv_asic = {
2129         .init = &cik_init,
2130         .fini = &cik_fini,
2131         .suspend = &cik_suspend,
2132         .resume = &cik_resume,
2133         .asic_reset = &cik_asic_reset,
2134         .vga_set_state = &r600_vga_set_state,
2135         .mmio_hdp_flush = &r600_mmio_hdp_flush,
2136         .gui_idle = &r600_gui_idle,
2137         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2138         .get_xclk = &cik_get_xclk,
2139         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2140         .gart = {
2141                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2142                 .set_page = &rs600_gart_set_page,
2143         },
2144         .vm = {
2145                 .init = &cik_vm_init,
2146                 .fini = &cik_vm_fini,
2147                 .copy_pages = &cik_sdma_vm_copy_pages,
2148                 .write_pages = &cik_sdma_vm_write_pages,
2149                 .set_pages = &cik_sdma_vm_set_pages,
2150                 .pad_ib = &cik_sdma_vm_pad_ib,
2151         },
2152         .ring = {
2153                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2154                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2155                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2156                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2157                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2158                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2159                 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2160                 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2161         },
2162         .irq = {
2163                 .set = &cik_irq_set,
2164                 .process = &cik_irq_process,
2165         },
2166         .display = {
2167                 .bandwidth_update = &dce8_bandwidth_update,
2168                 .get_vblank_counter = &evergreen_get_vblank_counter,
2169                 .wait_for_vblank = &dce4_wait_for_vblank,
2170                 .set_backlight_level = &atombios_set_backlight_level,
2171                 .get_backlight_level = &atombios_get_backlight_level,
2172                 .hdmi_enable = &evergreen_hdmi_enable,
2173                 .hdmi_setmode = &evergreen_hdmi_setmode,
2174         },
2175         .copy = {
2176                 .blit = &cik_copy_cpdma,
2177                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2178                 .dma = &cik_copy_dma,
2179                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2180                 .copy = &cik_copy_dma,
2181                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2182         },
2183         .surface = {
2184                 .set_reg = r600_set_surface_reg,
2185                 .clear_reg = r600_clear_surface_reg,
2186         },
2187         .hpd = {
2188                 .init = &evergreen_hpd_init,
2189                 .fini = &evergreen_hpd_fini,
2190                 .sense = &evergreen_hpd_sense,
2191                 .set_polarity = &evergreen_hpd_set_polarity,
2192         },
2193         .pm = {
2194                 .misc = &evergreen_pm_misc,
2195                 .prepare = &evergreen_pm_prepare,
2196                 .finish = &evergreen_pm_finish,
2197                 .init_profile = &sumo_pm_init_profile,
2198                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2199                 .get_engine_clock = &radeon_atom_get_engine_clock,
2200                 .set_engine_clock = &radeon_atom_set_engine_clock,
2201                 .get_memory_clock = &radeon_atom_get_memory_clock,
2202                 .set_memory_clock = &radeon_atom_set_memory_clock,
2203                 .get_pcie_lanes = NULL,
2204                 .set_pcie_lanes = NULL,
2205                 .set_clock_gating = NULL,
2206                 .set_uvd_clocks = &cik_set_uvd_clocks,
2207                 .set_vce_clocks = &cik_set_vce_clocks,
2208                 .get_temperature = &kv_get_temp,
2209         },
2210         .dpm = {
2211                 .init = &kv_dpm_init,
2212                 .setup_asic = &kv_dpm_setup_asic,
2213                 .enable = &kv_dpm_enable,
2214                 .late_enable = &kv_dpm_late_enable,
2215                 .disable = &kv_dpm_disable,
2216                 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2217                 .set_power_state = &kv_dpm_set_power_state,
2218                 .post_set_power_state = &kv_dpm_post_set_power_state,
2219                 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2220                 .fini = &kv_dpm_fini,
2221                 .get_sclk = &kv_dpm_get_sclk,
2222                 .get_mclk = &kv_dpm_get_mclk,
2223                 .print_power_state = &kv_dpm_print_power_state,
2224                 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2225                 .force_performance_level = &kv_dpm_force_performance_level,
2226                 .powergate_uvd = &kv_dpm_powergate_uvd,
2227                 .enable_bapm = &kv_dpm_enable_bapm,
2228         },
2229         .pflip = {
2230                 .page_flip = &evergreen_page_flip,
2231                 .page_flip_pending = &evergreen_page_flip_pending,
2232         },
2233 };
2234
2235 /**
2236  * radeon_asic_init - register asic specific callbacks
2237  *
2238  * @rdev: radeon device pointer
2239  *
2240  * Registers the appropriate asic specific callbacks for each
2241  * chip family.  Also sets other asics specific info like the number
2242  * of crtcs and the register aperture accessors (all asics).
2243  * Returns 0 for success.
2244  */
2245 int radeon_asic_init(struct radeon_device *rdev)
2246 {
2247         radeon_register_accessor_init(rdev);
2248
2249         /* set the number of crtcs */
2250         if (rdev->flags & RADEON_SINGLE_CRTC)
2251                 rdev->num_crtc = 1;
2252         else
2253                 rdev->num_crtc = 2;
2254
2255         rdev->has_uvd = false;
2256
2257         switch (rdev->family) {
2258         case CHIP_R100:
2259         case CHIP_RV100:
2260         case CHIP_RS100:
2261         case CHIP_RV200:
2262         case CHIP_RS200:
2263                 rdev->asic = &r100_asic;
2264                 break;
2265         case CHIP_R200:
2266         case CHIP_RV250:
2267         case CHIP_RS300:
2268         case CHIP_RV280:
2269                 rdev->asic = &r200_asic;
2270                 break;
2271         case CHIP_R300:
2272         case CHIP_R350:
2273         case CHIP_RV350:
2274         case CHIP_RV380:
2275                 if (rdev->flags & RADEON_IS_PCIE)
2276                         rdev->asic = &r300_asic_pcie;
2277                 else
2278                         rdev->asic = &r300_asic;
2279                 break;
2280         case CHIP_R420:
2281         case CHIP_R423:
2282         case CHIP_RV410:
2283                 rdev->asic = &r420_asic;
2284                 /* handle macs */
2285                 if (rdev->bios == NULL) {
2286                         rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2287                         rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2288                         rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2289                         rdev->asic->pm.set_memory_clock = NULL;
2290                         rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2291                 }
2292                 break;
2293         case CHIP_RS400:
2294         case CHIP_RS480:
2295                 rdev->asic = &rs400_asic;
2296                 break;
2297         case CHIP_RS600:
2298                 rdev->asic = &rs600_asic;
2299                 break;
2300         case CHIP_RS690:
2301         case CHIP_RS740:
2302                 rdev->asic = &rs690_asic;
2303                 break;
2304         case CHIP_RV515:
2305                 rdev->asic = &rv515_asic;
2306                 break;
2307         case CHIP_R520:
2308         case CHIP_RV530:
2309         case CHIP_RV560:
2310         case CHIP_RV570:
2311         case CHIP_R580:
2312                 rdev->asic = &r520_asic;
2313                 break;
2314         case CHIP_R600:
2315                 rdev->asic = &r600_asic;
2316                 break;
2317         case CHIP_RV610:
2318         case CHIP_RV630:
2319         case CHIP_RV620:
2320         case CHIP_RV635:
2321         case CHIP_RV670:
2322                 rdev->asic = &rv6xx_asic;
2323                 rdev->has_uvd = true;
2324                 break;
2325         case CHIP_RS780:
2326         case CHIP_RS880:
2327                 rdev->asic = &rs780_asic;
2328                 /* 760G/780V/880V don't have UVD */
2329                 if ((rdev->pdev->device == 0x9616)||
2330                     (rdev->pdev->device == 0x9611)||
2331                     (rdev->pdev->device == 0x9613)||
2332                     (rdev->pdev->device == 0x9711)||
2333                     (rdev->pdev->device == 0x9713))
2334                         rdev->has_uvd = false;
2335                 else
2336                         rdev->has_uvd = true;
2337                 break;
2338         case CHIP_RV770:
2339         case CHIP_RV730:
2340         case CHIP_RV710:
2341         case CHIP_RV740:
2342                 rdev->asic = &rv770_asic;
2343                 rdev->has_uvd = true;
2344                 break;
2345         case CHIP_CEDAR:
2346         case CHIP_REDWOOD:
2347         case CHIP_JUNIPER:
2348         case CHIP_CYPRESS:
2349         case CHIP_HEMLOCK:
2350                 /* set num crtcs */
2351                 if (rdev->family == CHIP_CEDAR)
2352                         rdev->num_crtc = 4;
2353                 else
2354                         rdev->num_crtc = 6;
2355                 rdev->asic = &evergreen_asic;
2356                 rdev->has_uvd = true;
2357                 break;
2358         case CHIP_PALM:
2359         case CHIP_SUMO:
2360         case CHIP_SUMO2:
2361                 rdev->asic = &sumo_asic;
2362                 rdev->has_uvd = true;
2363                 break;
2364         case CHIP_BARTS:
2365         case CHIP_TURKS:
2366         case CHIP_CAICOS:
2367                 /* set num crtcs */
2368                 if (rdev->family == CHIP_CAICOS)
2369                         rdev->num_crtc = 4;
2370                 else
2371                         rdev->num_crtc = 6;
2372                 rdev->asic = &btc_asic;
2373                 rdev->has_uvd = true;
2374                 break;
2375         case CHIP_CAYMAN:
2376                 rdev->asic = &cayman_asic;
2377                 /* set num crtcs */
2378                 rdev->num_crtc = 6;
2379                 rdev->has_uvd = true;
2380                 break;
2381         case CHIP_ARUBA:
2382                 rdev->asic = &trinity_asic;
2383                 /* set num crtcs */
2384                 rdev->num_crtc = 4;
2385                 rdev->has_uvd = true;
2386                 break;
2387         case CHIP_TAHITI:
2388         case CHIP_PITCAIRN:
2389         case CHIP_VERDE:
2390         case CHIP_OLAND:
2391         case CHIP_HAINAN:
2392                 rdev->asic = &si_asic;
2393                 /* set num crtcs */
2394                 if (rdev->family == CHIP_HAINAN)
2395                         rdev->num_crtc = 0;
2396                 else if (rdev->family == CHIP_OLAND)
2397                         rdev->num_crtc = 2;
2398                 else
2399                         rdev->num_crtc = 6;
2400                 if (rdev->family == CHIP_HAINAN)
2401                         rdev->has_uvd = false;
2402                 else
2403                         rdev->has_uvd = true;
2404                 switch (rdev->family) {
2405                 case CHIP_TAHITI:
2406                         rdev->cg_flags =
2407                                 RADEON_CG_SUPPORT_GFX_MGCG |
2408                                 RADEON_CG_SUPPORT_GFX_MGLS |
2409                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2410                                 RADEON_CG_SUPPORT_GFX_CGLS |
2411                                 RADEON_CG_SUPPORT_GFX_CGTS |
2412                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2413                                 RADEON_CG_SUPPORT_MC_MGCG |
2414                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2415                                 RADEON_CG_SUPPORT_BIF_LS |
2416                                 RADEON_CG_SUPPORT_VCE_MGCG |
2417                                 RADEON_CG_SUPPORT_UVD_MGCG |
2418                                 RADEON_CG_SUPPORT_HDP_LS |
2419                                 RADEON_CG_SUPPORT_HDP_MGCG;
2420                         rdev->pg_flags = 0;
2421                         break;
2422                 case CHIP_PITCAIRN:
2423                         rdev->cg_flags =
2424                                 RADEON_CG_SUPPORT_GFX_MGCG |
2425                                 RADEON_CG_SUPPORT_GFX_MGLS |
2426                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2427                                 RADEON_CG_SUPPORT_GFX_CGLS |
2428                                 RADEON_CG_SUPPORT_GFX_CGTS |
2429                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2430                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2431                                 RADEON_CG_SUPPORT_MC_LS |
2432                                 RADEON_CG_SUPPORT_MC_MGCG |
2433                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2434                                 RADEON_CG_SUPPORT_BIF_LS |
2435                                 RADEON_CG_SUPPORT_VCE_MGCG |
2436                                 RADEON_CG_SUPPORT_UVD_MGCG |
2437                                 RADEON_CG_SUPPORT_HDP_LS |
2438                                 RADEON_CG_SUPPORT_HDP_MGCG;
2439                         rdev->pg_flags = 0;
2440                         break;
2441                 case CHIP_VERDE:
2442                         rdev->cg_flags =
2443                                 RADEON_CG_SUPPORT_GFX_MGCG |
2444                                 RADEON_CG_SUPPORT_GFX_MGLS |
2445                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2446                                 RADEON_CG_SUPPORT_GFX_CGLS |
2447                                 RADEON_CG_SUPPORT_GFX_CGTS |
2448                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2449                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2450                                 RADEON_CG_SUPPORT_MC_LS |
2451                                 RADEON_CG_SUPPORT_MC_MGCG |
2452                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2453                                 RADEON_CG_SUPPORT_BIF_LS |
2454                                 RADEON_CG_SUPPORT_VCE_MGCG |
2455                                 RADEON_CG_SUPPORT_UVD_MGCG |
2456                                 RADEON_CG_SUPPORT_HDP_LS |
2457                                 RADEON_CG_SUPPORT_HDP_MGCG;
2458                         rdev->pg_flags = 0 |
2459                                 /*RADEON_PG_SUPPORT_GFX_PG | */
2460                                 RADEON_PG_SUPPORT_SDMA;
2461                         break;
2462                 case CHIP_OLAND:
2463                         rdev->cg_flags =
2464                                 RADEON_CG_SUPPORT_GFX_MGCG |
2465                                 RADEON_CG_SUPPORT_GFX_MGLS |
2466                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2467                                 RADEON_CG_SUPPORT_GFX_CGLS |
2468                                 RADEON_CG_SUPPORT_GFX_CGTS |
2469                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2470                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2471                                 RADEON_CG_SUPPORT_MC_LS |
2472                                 RADEON_CG_SUPPORT_MC_MGCG |
2473                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2474                                 RADEON_CG_SUPPORT_BIF_LS |
2475                                 RADEON_CG_SUPPORT_UVD_MGCG |
2476                                 RADEON_CG_SUPPORT_HDP_LS |
2477                                 RADEON_CG_SUPPORT_HDP_MGCG;
2478                         rdev->pg_flags = 0;
2479                         break;
2480                 case CHIP_HAINAN:
2481                         rdev->cg_flags =
2482                                 RADEON_CG_SUPPORT_GFX_MGCG |
2483                                 RADEON_CG_SUPPORT_GFX_MGLS |
2484                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2485                                 RADEON_CG_SUPPORT_GFX_CGLS |
2486                                 RADEON_CG_SUPPORT_GFX_CGTS |
2487                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2488                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2489                                 RADEON_CG_SUPPORT_MC_LS |
2490                                 RADEON_CG_SUPPORT_MC_MGCG |
2491                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2492                                 RADEON_CG_SUPPORT_BIF_LS |
2493                                 RADEON_CG_SUPPORT_HDP_LS |
2494                                 RADEON_CG_SUPPORT_HDP_MGCG;
2495                         rdev->pg_flags = 0;
2496                         break;
2497                 default:
2498                         rdev->cg_flags = 0;
2499                         rdev->pg_flags = 0;
2500                         break;
2501                 }
2502                 break;
2503         case CHIP_BONAIRE:
2504         case CHIP_HAWAII:
2505                 rdev->asic = &ci_asic;
2506                 rdev->num_crtc = 6;
2507                 rdev->has_uvd = true;
2508                 if (rdev->family == CHIP_BONAIRE) {
2509                         rdev->cg_flags =
2510                                 RADEON_CG_SUPPORT_GFX_MGCG |
2511                                 RADEON_CG_SUPPORT_GFX_MGLS |
2512                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2513                                 RADEON_CG_SUPPORT_GFX_CGLS |
2514                                 RADEON_CG_SUPPORT_GFX_CGTS |
2515                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2516                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2517                                 RADEON_CG_SUPPORT_MC_LS |
2518                                 RADEON_CG_SUPPORT_MC_MGCG |
2519                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2520                                 RADEON_CG_SUPPORT_SDMA_LS |
2521                                 RADEON_CG_SUPPORT_BIF_LS |
2522                                 RADEON_CG_SUPPORT_VCE_MGCG |
2523                                 RADEON_CG_SUPPORT_UVD_MGCG |
2524                                 RADEON_CG_SUPPORT_HDP_LS |
2525                                 RADEON_CG_SUPPORT_HDP_MGCG;
2526                         rdev->pg_flags = 0;
2527                 } else {
2528                         rdev->cg_flags =
2529                                 RADEON_CG_SUPPORT_GFX_MGCG |
2530                                 RADEON_CG_SUPPORT_GFX_MGLS |
2531                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2532                                 RADEON_CG_SUPPORT_GFX_CGLS |
2533                                 RADEON_CG_SUPPORT_GFX_CGTS |
2534                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2535                                 RADEON_CG_SUPPORT_MC_LS |
2536                                 RADEON_CG_SUPPORT_MC_MGCG |
2537                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2538                                 RADEON_CG_SUPPORT_SDMA_LS |
2539                                 RADEON_CG_SUPPORT_BIF_LS |
2540                                 RADEON_CG_SUPPORT_VCE_MGCG |
2541                                 RADEON_CG_SUPPORT_UVD_MGCG |
2542                                 RADEON_CG_SUPPORT_HDP_LS |
2543                                 RADEON_CG_SUPPORT_HDP_MGCG;
2544                         rdev->pg_flags = 0;
2545                 }
2546                 break;
2547         case CHIP_KAVERI:
2548         case CHIP_KABINI:
2549         case CHIP_MULLINS:
2550                 rdev->asic = &kv_asic;
2551                 /* set num crtcs */
2552                 if (rdev->family == CHIP_KAVERI) {
2553                         rdev->num_crtc = 4;
2554                         rdev->cg_flags =
2555                                 RADEON_CG_SUPPORT_GFX_MGCG |
2556                                 RADEON_CG_SUPPORT_GFX_MGLS |
2557                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2558                                 RADEON_CG_SUPPORT_GFX_CGLS |
2559                                 RADEON_CG_SUPPORT_GFX_CGTS |
2560                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2561                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2562                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2563                                 RADEON_CG_SUPPORT_SDMA_LS |
2564                                 RADEON_CG_SUPPORT_BIF_LS |
2565                                 RADEON_CG_SUPPORT_VCE_MGCG |
2566                                 RADEON_CG_SUPPORT_UVD_MGCG |
2567                                 RADEON_CG_SUPPORT_HDP_LS |
2568                                 RADEON_CG_SUPPORT_HDP_MGCG;
2569                         rdev->pg_flags = 0;
2570                                 /*RADEON_PG_SUPPORT_GFX_PG |
2571                                 RADEON_PG_SUPPORT_GFX_SMG |
2572                                 RADEON_PG_SUPPORT_GFX_DMG |
2573                                 RADEON_PG_SUPPORT_UVD |
2574                                 RADEON_PG_SUPPORT_VCE |
2575                                 RADEON_PG_SUPPORT_CP |
2576                                 RADEON_PG_SUPPORT_GDS |
2577                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2578                                 RADEON_PG_SUPPORT_ACP |
2579                                 RADEON_PG_SUPPORT_SAMU;*/
2580                 } else {
2581                         rdev->num_crtc = 2;
2582                         rdev->cg_flags =
2583                                 RADEON_CG_SUPPORT_GFX_MGCG |
2584                                 RADEON_CG_SUPPORT_GFX_MGLS |
2585                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2586                                 RADEON_CG_SUPPORT_GFX_CGLS |
2587                                 RADEON_CG_SUPPORT_GFX_CGTS |
2588                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2589                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2590                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2591                                 RADEON_CG_SUPPORT_SDMA_LS |
2592                                 RADEON_CG_SUPPORT_BIF_LS |
2593                                 RADEON_CG_SUPPORT_VCE_MGCG |
2594                                 RADEON_CG_SUPPORT_UVD_MGCG |
2595                                 RADEON_CG_SUPPORT_HDP_LS |
2596                                 RADEON_CG_SUPPORT_HDP_MGCG;
2597                         rdev->pg_flags = 0;
2598                                 /*RADEON_PG_SUPPORT_GFX_PG |
2599                                 RADEON_PG_SUPPORT_GFX_SMG |
2600                                 RADEON_PG_SUPPORT_UVD |
2601                                 RADEON_PG_SUPPORT_VCE |
2602                                 RADEON_PG_SUPPORT_CP |
2603                                 RADEON_PG_SUPPORT_GDS |
2604                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2605                                 RADEON_PG_SUPPORT_SAMU;*/
2606                 }
2607                 rdev->has_uvd = true;
2608                 break;
2609         default:
2610                 /* FIXME: not supported yet */
2611                 return -EINVAL;
2612         }
2613
2614         if (rdev->flags & RADEON_IS_IGP) {
2615                 rdev->asic->pm.get_memory_clock = NULL;
2616                 rdev->asic->pm.set_memory_clock = NULL;
2617         }
2618
2619         return 0;
2620 }
2621