2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/console.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
37 #include "radeon_asic.h"
41 * Registers accessors functions.
44 * radeon_invalid_rreg - dummy reg read function
46 * @rdev: radeon device pointer
47 * @reg: offset of register
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
61 * radeon_invalid_wreg - dummy reg write function
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
78 * radeon_register_accessor_init - sets up the register accessor callbacks
80 * @rdev: radeon device pointer
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
85 static void radeon_register_accessor_init(struct radeon_device *rdev)
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
98 rdev->pcie_reg_mask = 0x7ff;
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
140 /* helper to disable agp */
142 * radeon_agp_disable - AGP disable helper function
144 * @rdev: radeon device pointer
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
149 void radeon_agp_disable(struct radeon_device *rdev)
151 rdev->flags &= ~RADEON_IS_AGP;
152 if (rdev->family >= CHIP_R600) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev->flags |= RADEON_IS_PCIE;
155 } else if (rdev->family >= CHIP_RV515 ||
156 rdev->family == CHIP_RV380 ||
157 rdev->family == CHIP_RV410 ||
158 rdev->family == CHIP_R423) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev->flags |= RADEON_IS_PCIE;
161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev->flags |= RADEON_IS_PCI;
166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
167 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
176 static struct radeon_asic_ring r100_gfx_ring = {
177 .ib_execute = &r100_ring_ib_execute,
178 .emit_fence = &r100_fence_ring_emit,
179 .emit_semaphore = &r100_semaphore_ring_emit,
180 .cs_parse = &r100_cs_parse,
181 .ring_start = &r100_ring_start,
182 .ring_test = &r100_ring_test,
183 .ib_test = &r100_ib_test,
184 .is_lockup = &r100_gpu_is_lockup,
185 .get_rptr = &r100_gfx_get_rptr,
186 .get_wptr = &r100_gfx_get_wptr,
187 .set_wptr = &r100_gfx_set_wptr,
190 static struct radeon_asic r100_asic = {
193 .suspend = &r100_suspend,
194 .resume = &r100_resume,
195 .vga_set_state = &r100_vga_set_state,
196 .asic_reset = &r100_asic_reset,
197 .mmio_hdp_flush = NULL,
198 .gui_idle = &r100_gui_idle,
199 .mc_wait_for_idle = &r100_mc_wait_for_idle,
201 .tlb_flush = &r100_pci_gart_tlb_flush,
202 .set_page = &r100_pci_gart_set_page,
205 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
208 .set = &r100_irq_set,
209 .process = &r100_irq_process,
212 .bandwidth_update = &r100_bandwidth_update,
213 .get_vblank_counter = &r100_get_vblank_counter,
214 .wait_for_vblank = &r100_wait_for_vblank,
215 .set_backlight_level = &radeon_legacy_set_backlight_level,
216 .get_backlight_level = &radeon_legacy_get_backlight_level,
219 .blit = &r100_copy_blit,
220 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
222 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
223 .copy = &r100_copy_blit,
224 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
227 .set_reg = r100_set_surface_reg,
228 .clear_reg = r100_clear_surface_reg,
231 .init = &r100_hpd_init,
232 .fini = &r100_hpd_fini,
233 .sense = &r100_hpd_sense,
234 .set_polarity = &r100_hpd_set_polarity,
237 .misc = &r100_pm_misc,
238 .prepare = &r100_pm_prepare,
239 .finish = &r100_pm_finish,
240 .init_profile = &r100_pm_init_profile,
241 .get_dynpm_state = &r100_pm_get_dynpm_state,
242 .get_engine_clock = &radeon_legacy_get_engine_clock,
243 .set_engine_clock = &radeon_legacy_set_engine_clock,
244 .get_memory_clock = &radeon_legacy_get_memory_clock,
245 .set_memory_clock = NULL,
246 .get_pcie_lanes = NULL,
247 .set_pcie_lanes = NULL,
248 .set_clock_gating = &radeon_legacy_set_clock_gating,
251 .page_flip = &r100_page_flip,
252 .page_flip_pending = &r100_page_flip_pending,
256 static struct radeon_asic r200_asic = {
259 .suspend = &r100_suspend,
260 .resume = &r100_resume,
261 .vga_set_state = &r100_vga_set_state,
262 .asic_reset = &r100_asic_reset,
263 .mmio_hdp_flush = NULL,
264 .gui_idle = &r100_gui_idle,
265 .mc_wait_for_idle = &r100_mc_wait_for_idle,
267 .tlb_flush = &r100_pci_gart_tlb_flush,
268 .set_page = &r100_pci_gart_set_page,
271 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
274 .set = &r100_irq_set,
275 .process = &r100_irq_process,
278 .bandwidth_update = &r100_bandwidth_update,
279 .get_vblank_counter = &r100_get_vblank_counter,
280 .wait_for_vblank = &r100_wait_for_vblank,
281 .set_backlight_level = &radeon_legacy_set_backlight_level,
282 .get_backlight_level = &radeon_legacy_get_backlight_level,
285 .blit = &r100_copy_blit,
286 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
287 .dma = &r200_copy_dma,
288 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
289 .copy = &r100_copy_blit,
290 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
293 .set_reg = r100_set_surface_reg,
294 .clear_reg = r100_clear_surface_reg,
297 .init = &r100_hpd_init,
298 .fini = &r100_hpd_fini,
299 .sense = &r100_hpd_sense,
300 .set_polarity = &r100_hpd_set_polarity,
303 .misc = &r100_pm_misc,
304 .prepare = &r100_pm_prepare,
305 .finish = &r100_pm_finish,
306 .init_profile = &r100_pm_init_profile,
307 .get_dynpm_state = &r100_pm_get_dynpm_state,
308 .get_engine_clock = &radeon_legacy_get_engine_clock,
309 .set_engine_clock = &radeon_legacy_set_engine_clock,
310 .get_memory_clock = &radeon_legacy_get_memory_clock,
311 .set_memory_clock = NULL,
312 .get_pcie_lanes = NULL,
313 .set_pcie_lanes = NULL,
314 .set_clock_gating = &radeon_legacy_set_clock_gating,
317 .page_flip = &r100_page_flip,
318 .page_flip_pending = &r100_page_flip_pending,
322 static struct radeon_asic_ring r300_gfx_ring = {
323 .ib_execute = &r100_ring_ib_execute,
324 .emit_fence = &r300_fence_ring_emit,
325 .emit_semaphore = &r100_semaphore_ring_emit,
326 .cs_parse = &r300_cs_parse,
327 .ring_start = &r300_ring_start,
328 .ring_test = &r100_ring_test,
329 .ib_test = &r100_ib_test,
330 .is_lockup = &r100_gpu_is_lockup,
331 .get_rptr = &r100_gfx_get_rptr,
332 .get_wptr = &r100_gfx_get_wptr,
333 .set_wptr = &r100_gfx_set_wptr,
336 static struct radeon_asic r300_asic = {
339 .suspend = &r300_suspend,
340 .resume = &r300_resume,
341 .vga_set_state = &r100_vga_set_state,
342 .asic_reset = &r300_asic_reset,
343 .mmio_hdp_flush = NULL,
344 .gui_idle = &r100_gui_idle,
345 .mc_wait_for_idle = &r300_mc_wait_for_idle,
347 .tlb_flush = &r100_pci_gart_tlb_flush,
348 .set_page = &r100_pci_gart_set_page,
351 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
354 .set = &r100_irq_set,
355 .process = &r100_irq_process,
358 .bandwidth_update = &r100_bandwidth_update,
359 .get_vblank_counter = &r100_get_vblank_counter,
360 .wait_for_vblank = &r100_wait_for_vblank,
361 .set_backlight_level = &radeon_legacy_set_backlight_level,
362 .get_backlight_level = &radeon_legacy_get_backlight_level,
365 .blit = &r100_copy_blit,
366 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
367 .dma = &r200_copy_dma,
368 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
369 .copy = &r100_copy_blit,
370 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
373 .set_reg = r100_set_surface_reg,
374 .clear_reg = r100_clear_surface_reg,
377 .init = &r100_hpd_init,
378 .fini = &r100_hpd_fini,
379 .sense = &r100_hpd_sense,
380 .set_polarity = &r100_hpd_set_polarity,
383 .misc = &r100_pm_misc,
384 .prepare = &r100_pm_prepare,
385 .finish = &r100_pm_finish,
386 .init_profile = &r100_pm_init_profile,
387 .get_dynpm_state = &r100_pm_get_dynpm_state,
388 .get_engine_clock = &radeon_legacy_get_engine_clock,
389 .set_engine_clock = &radeon_legacy_set_engine_clock,
390 .get_memory_clock = &radeon_legacy_get_memory_clock,
391 .set_memory_clock = NULL,
392 .get_pcie_lanes = &rv370_get_pcie_lanes,
393 .set_pcie_lanes = &rv370_set_pcie_lanes,
394 .set_clock_gating = &radeon_legacy_set_clock_gating,
397 .page_flip = &r100_page_flip,
398 .page_flip_pending = &r100_page_flip_pending,
402 static struct radeon_asic r300_asic_pcie = {
405 .suspend = &r300_suspend,
406 .resume = &r300_resume,
407 .vga_set_state = &r100_vga_set_state,
408 .asic_reset = &r300_asic_reset,
409 .mmio_hdp_flush = NULL,
410 .gui_idle = &r100_gui_idle,
411 .mc_wait_for_idle = &r300_mc_wait_for_idle,
413 .tlb_flush = &rv370_pcie_gart_tlb_flush,
414 .set_page = &rv370_pcie_gart_set_page,
417 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
420 .set = &r100_irq_set,
421 .process = &r100_irq_process,
424 .bandwidth_update = &r100_bandwidth_update,
425 .get_vblank_counter = &r100_get_vblank_counter,
426 .wait_for_vblank = &r100_wait_for_vblank,
427 .set_backlight_level = &radeon_legacy_set_backlight_level,
428 .get_backlight_level = &radeon_legacy_get_backlight_level,
431 .blit = &r100_copy_blit,
432 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
433 .dma = &r200_copy_dma,
434 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
435 .copy = &r100_copy_blit,
436 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
439 .set_reg = r100_set_surface_reg,
440 .clear_reg = r100_clear_surface_reg,
443 .init = &r100_hpd_init,
444 .fini = &r100_hpd_fini,
445 .sense = &r100_hpd_sense,
446 .set_polarity = &r100_hpd_set_polarity,
449 .misc = &r100_pm_misc,
450 .prepare = &r100_pm_prepare,
451 .finish = &r100_pm_finish,
452 .init_profile = &r100_pm_init_profile,
453 .get_dynpm_state = &r100_pm_get_dynpm_state,
454 .get_engine_clock = &radeon_legacy_get_engine_clock,
455 .set_engine_clock = &radeon_legacy_set_engine_clock,
456 .get_memory_clock = &radeon_legacy_get_memory_clock,
457 .set_memory_clock = NULL,
458 .get_pcie_lanes = &rv370_get_pcie_lanes,
459 .set_pcie_lanes = &rv370_set_pcie_lanes,
460 .set_clock_gating = &radeon_legacy_set_clock_gating,
463 .page_flip = &r100_page_flip,
464 .page_flip_pending = &r100_page_flip_pending,
468 static struct radeon_asic r420_asic = {
471 .suspend = &r420_suspend,
472 .resume = &r420_resume,
473 .vga_set_state = &r100_vga_set_state,
474 .asic_reset = &r300_asic_reset,
475 .mmio_hdp_flush = NULL,
476 .gui_idle = &r100_gui_idle,
477 .mc_wait_for_idle = &r300_mc_wait_for_idle,
479 .tlb_flush = &rv370_pcie_gart_tlb_flush,
480 .set_page = &rv370_pcie_gart_set_page,
483 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
486 .set = &r100_irq_set,
487 .process = &r100_irq_process,
490 .bandwidth_update = &r100_bandwidth_update,
491 .get_vblank_counter = &r100_get_vblank_counter,
492 .wait_for_vblank = &r100_wait_for_vblank,
493 .set_backlight_level = &atombios_set_backlight_level,
494 .get_backlight_level = &atombios_get_backlight_level,
497 .blit = &r100_copy_blit,
498 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
499 .dma = &r200_copy_dma,
500 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
501 .copy = &r100_copy_blit,
502 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
505 .set_reg = r100_set_surface_reg,
506 .clear_reg = r100_clear_surface_reg,
509 .init = &r100_hpd_init,
510 .fini = &r100_hpd_fini,
511 .sense = &r100_hpd_sense,
512 .set_polarity = &r100_hpd_set_polarity,
515 .misc = &r100_pm_misc,
516 .prepare = &r100_pm_prepare,
517 .finish = &r100_pm_finish,
518 .init_profile = &r420_pm_init_profile,
519 .get_dynpm_state = &r100_pm_get_dynpm_state,
520 .get_engine_clock = &radeon_atom_get_engine_clock,
521 .set_engine_clock = &radeon_atom_set_engine_clock,
522 .get_memory_clock = &radeon_atom_get_memory_clock,
523 .set_memory_clock = &radeon_atom_set_memory_clock,
524 .get_pcie_lanes = &rv370_get_pcie_lanes,
525 .set_pcie_lanes = &rv370_set_pcie_lanes,
526 .set_clock_gating = &radeon_atom_set_clock_gating,
529 .page_flip = &r100_page_flip,
530 .page_flip_pending = &r100_page_flip_pending,
534 static struct radeon_asic rs400_asic = {
537 .suspend = &rs400_suspend,
538 .resume = &rs400_resume,
539 .vga_set_state = &r100_vga_set_state,
540 .asic_reset = &r300_asic_reset,
541 .mmio_hdp_flush = NULL,
542 .gui_idle = &r100_gui_idle,
543 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
545 .tlb_flush = &rs400_gart_tlb_flush,
546 .set_page = &rs400_gart_set_page,
549 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
552 .set = &r100_irq_set,
553 .process = &r100_irq_process,
556 .bandwidth_update = &r100_bandwidth_update,
557 .get_vblank_counter = &r100_get_vblank_counter,
558 .wait_for_vblank = &r100_wait_for_vblank,
559 .set_backlight_level = &radeon_legacy_set_backlight_level,
560 .get_backlight_level = &radeon_legacy_get_backlight_level,
563 .blit = &r100_copy_blit,
564 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
565 .dma = &r200_copy_dma,
566 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
567 .copy = &r100_copy_blit,
568 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
571 .set_reg = r100_set_surface_reg,
572 .clear_reg = r100_clear_surface_reg,
575 .init = &r100_hpd_init,
576 .fini = &r100_hpd_fini,
577 .sense = &r100_hpd_sense,
578 .set_polarity = &r100_hpd_set_polarity,
581 .misc = &r100_pm_misc,
582 .prepare = &r100_pm_prepare,
583 .finish = &r100_pm_finish,
584 .init_profile = &r100_pm_init_profile,
585 .get_dynpm_state = &r100_pm_get_dynpm_state,
586 .get_engine_clock = &radeon_legacy_get_engine_clock,
587 .set_engine_clock = &radeon_legacy_set_engine_clock,
588 .get_memory_clock = &radeon_legacy_get_memory_clock,
589 .set_memory_clock = NULL,
590 .get_pcie_lanes = NULL,
591 .set_pcie_lanes = NULL,
592 .set_clock_gating = &radeon_legacy_set_clock_gating,
595 .page_flip = &r100_page_flip,
596 .page_flip_pending = &r100_page_flip_pending,
600 static struct radeon_asic rs600_asic = {
603 .suspend = &rs600_suspend,
604 .resume = &rs600_resume,
605 .vga_set_state = &r100_vga_set_state,
606 .asic_reset = &rs600_asic_reset,
607 .mmio_hdp_flush = NULL,
608 .gui_idle = &r100_gui_idle,
609 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
611 .tlb_flush = &rs600_gart_tlb_flush,
612 .set_page = &rs600_gart_set_page,
615 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
618 .set = &rs600_irq_set,
619 .process = &rs600_irq_process,
622 .bandwidth_update = &rs600_bandwidth_update,
623 .get_vblank_counter = &rs600_get_vblank_counter,
624 .wait_for_vblank = &avivo_wait_for_vblank,
625 .set_backlight_level = &atombios_set_backlight_level,
626 .get_backlight_level = &atombios_get_backlight_level,
627 .hdmi_enable = &r600_hdmi_enable,
628 .hdmi_setmode = &r600_hdmi_setmode,
631 .blit = &r100_copy_blit,
632 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
633 .dma = &r200_copy_dma,
634 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
635 .copy = &r100_copy_blit,
636 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
639 .set_reg = r100_set_surface_reg,
640 .clear_reg = r100_clear_surface_reg,
643 .init = &rs600_hpd_init,
644 .fini = &rs600_hpd_fini,
645 .sense = &rs600_hpd_sense,
646 .set_polarity = &rs600_hpd_set_polarity,
649 .misc = &rs600_pm_misc,
650 .prepare = &rs600_pm_prepare,
651 .finish = &rs600_pm_finish,
652 .init_profile = &r420_pm_init_profile,
653 .get_dynpm_state = &r100_pm_get_dynpm_state,
654 .get_engine_clock = &radeon_atom_get_engine_clock,
655 .set_engine_clock = &radeon_atom_set_engine_clock,
656 .get_memory_clock = &radeon_atom_get_memory_clock,
657 .set_memory_clock = &radeon_atom_set_memory_clock,
658 .get_pcie_lanes = NULL,
659 .set_pcie_lanes = NULL,
660 .set_clock_gating = &radeon_atom_set_clock_gating,
663 .page_flip = &rs600_page_flip,
664 .page_flip_pending = &rs600_page_flip_pending,
668 static struct radeon_asic rs690_asic = {
671 .suspend = &rs690_suspend,
672 .resume = &rs690_resume,
673 .vga_set_state = &r100_vga_set_state,
674 .asic_reset = &rs600_asic_reset,
675 .mmio_hdp_flush = NULL,
676 .gui_idle = &r100_gui_idle,
677 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
679 .tlb_flush = &rs400_gart_tlb_flush,
680 .set_page = &rs400_gart_set_page,
683 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
686 .set = &rs600_irq_set,
687 .process = &rs600_irq_process,
690 .get_vblank_counter = &rs600_get_vblank_counter,
691 .bandwidth_update = &rs690_bandwidth_update,
692 .wait_for_vblank = &avivo_wait_for_vblank,
693 .set_backlight_level = &atombios_set_backlight_level,
694 .get_backlight_level = &atombios_get_backlight_level,
695 .hdmi_enable = &r600_hdmi_enable,
696 .hdmi_setmode = &r600_hdmi_setmode,
699 .blit = &r100_copy_blit,
700 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
701 .dma = &r200_copy_dma,
702 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
703 .copy = &r200_copy_dma,
704 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
707 .set_reg = r100_set_surface_reg,
708 .clear_reg = r100_clear_surface_reg,
711 .init = &rs600_hpd_init,
712 .fini = &rs600_hpd_fini,
713 .sense = &rs600_hpd_sense,
714 .set_polarity = &rs600_hpd_set_polarity,
717 .misc = &rs600_pm_misc,
718 .prepare = &rs600_pm_prepare,
719 .finish = &rs600_pm_finish,
720 .init_profile = &r420_pm_init_profile,
721 .get_dynpm_state = &r100_pm_get_dynpm_state,
722 .get_engine_clock = &radeon_atom_get_engine_clock,
723 .set_engine_clock = &radeon_atom_set_engine_clock,
724 .get_memory_clock = &radeon_atom_get_memory_clock,
725 .set_memory_clock = &radeon_atom_set_memory_clock,
726 .get_pcie_lanes = NULL,
727 .set_pcie_lanes = NULL,
728 .set_clock_gating = &radeon_atom_set_clock_gating,
731 .page_flip = &rs600_page_flip,
732 .page_flip_pending = &rs600_page_flip_pending,
736 static struct radeon_asic rv515_asic = {
739 .suspend = &rv515_suspend,
740 .resume = &rv515_resume,
741 .vga_set_state = &r100_vga_set_state,
742 .asic_reset = &rs600_asic_reset,
743 .mmio_hdp_flush = NULL,
744 .gui_idle = &r100_gui_idle,
745 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
747 .tlb_flush = &rv370_pcie_gart_tlb_flush,
748 .set_page = &rv370_pcie_gart_set_page,
751 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
754 .set = &rs600_irq_set,
755 .process = &rs600_irq_process,
758 .get_vblank_counter = &rs600_get_vblank_counter,
759 .bandwidth_update = &rv515_bandwidth_update,
760 .wait_for_vblank = &avivo_wait_for_vblank,
761 .set_backlight_level = &atombios_set_backlight_level,
762 .get_backlight_level = &atombios_get_backlight_level,
765 .blit = &r100_copy_blit,
766 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
767 .dma = &r200_copy_dma,
768 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
769 .copy = &r100_copy_blit,
770 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
773 .set_reg = r100_set_surface_reg,
774 .clear_reg = r100_clear_surface_reg,
777 .init = &rs600_hpd_init,
778 .fini = &rs600_hpd_fini,
779 .sense = &rs600_hpd_sense,
780 .set_polarity = &rs600_hpd_set_polarity,
783 .misc = &rs600_pm_misc,
784 .prepare = &rs600_pm_prepare,
785 .finish = &rs600_pm_finish,
786 .init_profile = &r420_pm_init_profile,
787 .get_dynpm_state = &r100_pm_get_dynpm_state,
788 .get_engine_clock = &radeon_atom_get_engine_clock,
789 .set_engine_clock = &radeon_atom_set_engine_clock,
790 .get_memory_clock = &radeon_atom_get_memory_clock,
791 .set_memory_clock = &radeon_atom_set_memory_clock,
792 .get_pcie_lanes = &rv370_get_pcie_lanes,
793 .set_pcie_lanes = &rv370_set_pcie_lanes,
794 .set_clock_gating = &radeon_atom_set_clock_gating,
797 .page_flip = &rs600_page_flip,
798 .page_flip_pending = &rs600_page_flip_pending,
802 static struct radeon_asic r520_asic = {
805 .suspend = &rv515_suspend,
806 .resume = &r520_resume,
807 .vga_set_state = &r100_vga_set_state,
808 .asic_reset = &rs600_asic_reset,
809 .mmio_hdp_flush = NULL,
810 .gui_idle = &r100_gui_idle,
811 .mc_wait_for_idle = &r520_mc_wait_for_idle,
813 .tlb_flush = &rv370_pcie_gart_tlb_flush,
814 .set_page = &rv370_pcie_gart_set_page,
817 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
820 .set = &rs600_irq_set,
821 .process = &rs600_irq_process,
824 .bandwidth_update = &rv515_bandwidth_update,
825 .get_vblank_counter = &rs600_get_vblank_counter,
826 .wait_for_vblank = &avivo_wait_for_vblank,
827 .set_backlight_level = &atombios_set_backlight_level,
828 .get_backlight_level = &atombios_get_backlight_level,
831 .blit = &r100_copy_blit,
832 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
833 .dma = &r200_copy_dma,
834 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
835 .copy = &r100_copy_blit,
836 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
839 .set_reg = r100_set_surface_reg,
840 .clear_reg = r100_clear_surface_reg,
843 .init = &rs600_hpd_init,
844 .fini = &rs600_hpd_fini,
845 .sense = &rs600_hpd_sense,
846 .set_polarity = &rs600_hpd_set_polarity,
849 .misc = &rs600_pm_misc,
850 .prepare = &rs600_pm_prepare,
851 .finish = &rs600_pm_finish,
852 .init_profile = &r420_pm_init_profile,
853 .get_dynpm_state = &r100_pm_get_dynpm_state,
854 .get_engine_clock = &radeon_atom_get_engine_clock,
855 .set_engine_clock = &radeon_atom_set_engine_clock,
856 .get_memory_clock = &radeon_atom_get_memory_clock,
857 .set_memory_clock = &radeon_atom_set_memory_clock,
858 .get_pcie_lanes = &rv370_get_pcie_lanes,
859 .set_pcie_lanes = &rv370_set_pcie_lanes,
860 .set_clock_gating = &radeon_atom_set_clock_gating,
863 .page_flip = &rs600_page_flip,
864 .page_flip_pending = &rs600_page_flip_pending,
868 static struct radeon_asic_ring r600_gfx_ring = {
869 .ib_execute = &r600_ring_ib_execute,
870 .emit_fence = &r600_fence_ring_emit,
871 .emit_semaphore = &r600_semaphore_ring_emit,
872 .cs_parse = &r600_cs_parse,
873 .ring_test = &r600_ring_test,
874 .ib_test = &r600_ib_test,
875 .is_lockup = &r600_gfx_is_lockup,
876 .get_rptr = &r600_gfx_get_rptr,
877 .get_wptr = &r600_gfx_get_wptr,
878 .set_wptr = &r600_gfx_set_wptr,
881 static struct radeon_asic_ring r600_dma_ring = {
882 .ib_execute = &r600_dma_ring_ib_execute,
883 .emit_fence = &r600_dma_fence_ring_emit,
884 .emit_semaphore = &r600_dma_semaphore_ring_emit,
885 .cs_parse = &r600_dma_cs_parse,
886 .ring_test = &r600_dma_ring_test,
887 .ib_test = &r600_dma_ib_test,
888 .is_lockup = &r600_dma_is_lockup,
889 .get_rptr = &r600_dma_get_rptr,
890 .get_wptr = &r600_dma_get_wptr,
891 .set_wptr = &r600_dma_set_wptr,
894 static struct radeon_asic r600_asic = {
897 .suspend = &r600_suspend,
898 .resume = &r600_resume,
899 .vga_set_state = &r600_vga_set_state,
900 .asic_reset = &r600_asic_reset,
901 .mmio_hdp_flush = r600_mmio_hdp_flush,
902 .gui_idle = &r600_gui_idle,
903 .mc_wait_for_idle = &r600_mc_wait_for_idle,
904 .get_xclk = &r600_get_xclk,
905 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
907 .tlb_flush = &r600_pcie_gart_tlb_flush,
908 .set_page = &rs600_gart_set_page,
911 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
912 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
915 .set = &r600_irq_set,
916 .process = &r600_irq_process,
919 .bandwidth_update = &rv515_bandwidth_update,
920 .get_vblank_counter = &rs600_get_vblank_counter,
921 .wait_for_vblank = &avivo_wait_for_vblank,
922 .set_backlight_level = &atombios_set_backlight_level,
923 .get_backlight_level = &atombios_get_backlight_level,
924 .hdmi_enable = &r600_hdmi_enable,
925 .hdmi_setmode = &r600_hdmi_setmode,
928 .blit = &r600_copy_cpdma,
929 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
930 .dma = &r600_copy_dma,
931 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
932 .copy = &r600_copy_cpdma,
933 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
936 .set_reg = r600_set_surface_reg,
937 .clear_reg = r600_clear_surface_reg,
940 .init = &r600_hpd_init,
941 .fini = &r600_hpd_fini,
942 .sense = &r600_hpd_sense,
943 .set_polarity = &r600_hpd_set_polarity,
946 .misc = &r600_pm_misc,
947 .prepare = &rs600_pm_prepare,
948 .finish = &rs600_pm_finish,
949 .init_profile = &r600_pm_init_profile,
950 .get_dynpm_state = &r600_pm_get_dynpm_state,
951 .get_engine_clock = &radeon_atom_get_engine_clock,
952 .set_engine_clock = &radeon_atom_set_engine_clock,
953 .get_memory_clock = &radeon_atom_get_memory_clock,
954 .set_memory_clock = &radeon_atom_set_memory_clock,
955 .get_pcie_lanes = &r600_get_pcie_lanes,
956 .set_pcie_lanes = &r600_set_pcie_lanes,
957 .set_clock_gating = NULL,
958 .get_temperature = &rv6xx_get_temp,
961 .page_flip = &rs600_page_flip,
962 .page_flip_pending = &rs600_page_flip_pending,
966 static struct radeon_asic_ring rv6xx_uvd_ring = {
967 .ib_execute = &uvd_v1_0_ib_execute,
968 .emit_fence = &uvd_v1_0_fence_emit,
969 .emit_semaphore = &uvd_v1_0_semaphore_emit,
970 .cs_parse = &radeon_uvd_cs_parse,
971 .ring_test = &uvd_v1_0_ring_test,
972 .ib_test = &uvd_v1_0_ib_test,
973 .is_lockup = &radeon_ring_test_lockup,
974 .get_rptr = &uvd_v1_0_get_rptr,
975 .get_wptr = &uvd_v1_0_get_wptr,
976 .set_wptr = &uvd_v1_0_set_wptr,
979 static struct radeon_asic rv6xx_asic = {
982 .suspend = &r600_suspend,
983 .resume = &r600_resume,
984 .vga_set_state = &r600_vga_set_state,
985 .asic_reset = &r600_asic_reset,
986 .mmio_hdp_flush = r600_mmio_hdp_flush,
987 .gui_idle = &r600_gui_idle,
988 .mc_wait_for_idle = &r600_mc_wait_for_idle,
989 .get_xclk = &r600_get_xclk,
990 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
992 .tlb_flush = &r600_pcie_gart_tlb_flush,
993 .set_page = &rs600_gart_set_page,
996 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
997 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
998 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1001 .set = &r600_irq_set,
1002 .process = &r600_irq_process,
1005 .bandwidth_update = &rv515_bandwidth_update,
1006 .get_vblank_counter = &rs600_get_vblank_counter,
1007 .wait_for_vblank = &avivo_wait_for_vblank,
1008 .set_backlight_level = &atombios_set_backlight_level,
1009 .get_backlight_level = &atombios_get_backlight_level,
1010 .hdmi_enable = &r600_hdmi_enable,
1011 .hdmi_setmode = &r600_hdmi_setmode,
1014 .blit = &r600_copy_cpdma,
1015 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1016 .dma = &r600_copy_dma,
1017 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1018 .copy = &r600_copy_cpdma,
1019 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1022 .set_reg = r600_set_surface_reg,
1023 .clear_reg = r600_clear_surface_reg,
1026 .init = &r600_hpd_init,
1027 .fini = &r600_hpd_fini,
1028 .sense = &r600_hpd_sense,
1029 .set_polarity = &r600_hpd_set_polarity,
1032 .misc = &r600_pm_misc,
1033 .prepare = &rs600_pm_prepare,
1034 .finish = &rs600_pm_finish,
1035 .init_profile = &r600_pm_init_profile,
1036 .get_dynpm_state = &r600_pm_get_dynpm_state,
1037 .get_engine_clock = &radeon_atom_get_engine_clock,
1038 .set_engine_clock = &radeon_atom_set_engine_clock,
1039 .get_memory_clock = &radeon_atom_get_memory_clock,
1040 .set_memory_clock = &radeon_atom_set_memory_clock,
1041 .get_pcie_lanes = &r600_get_pcie_lanes,
1042 .set_pcie_lanes = &r600_set_pcie_lanes,
1043 .set_clock_gating = NULL,
1044 .get_temperature = &rv6xx_get_temp,
1045 .set_uvd_clocks = &r600_set_uvd_clocks,
1048 .init = &rv6xx_dpm_init,
1049 .setup_asic = &rv6xx_setup_asic,
1050 .enable = &rv6xx_dpm_enable,
1051 .late_enable = &r600_dpm_late_enable,
1052 .disable = &rv6xx_dpm_disable,
1053 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1054 .set_power_state = &rv6xx_dpm_set_power_state,
1055 .post_set_power_state = &r600_dpm_post_set_power_state,
1056 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1057 .fini = &rv6xx_dpm_fini,
1058 .get_sclk = &rv6xx_dpm_get_sclk,
1059 .get_mclk = &rv6xx_dpm_get_mclk,
1060 .print_power_state = &rv6xx_dpm_print_power_state,
1061 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1062 .force_performance_level = &rv6xx_dpm_force_performance_level,
1065 .page_flip = &rs600_page_flip,
1066 .page_flip_pending = &rs600_page_flip_pending,
1070 static struct radeon_asic rs780_asic = {
1073 .suspend = &r600_suspend,
1074 .resume = &r600_resume,
1075 .vga_set_state = &r600_vga_set_state,
1076 .asic_reset = &r600_asic_reset,
1077 .mmio_hdp_flush = r600_mmio_hdp_flush,
1078 .gui_idle = &r600_gui_idle,
1079 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1080 .get_xclk = &r600_get_xclk,
1081 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1083 .tlb_flush = &r600_pcie_gart_tlb_flush,
1084 .set_page = &rs600_gart_set_page,
1087 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1088 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1089 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1092 .set = &r600_irq_set,
1093 .process = &r600_irq_process,
1096 .bandwidth_update = &rs690_bandwidth_update,
1097 .get_vblank_counter = &rs600_get_vblank_counter,
1098 .wait_for_vblank = &avivo_wait_for_vblank,
1099 .set_backlight_level = &atombios_set_backlight_level,
1100 .get_backlight_level = &atombios_get_backlight_level,
1101 .hdmi_enable = &r600_hdmi_enable,
1102 .hdmi_setmode = &r600_hdmi_setmode,
1105 .blit = &r600_copy_cpdma,
1106 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1107 .dma = &r600_copy_dma,
1108 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1109 .copy = &r600_copy_cpdma,
1110 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1113 .set_reg = r600_set_surface_reg,
1114 .clear_reg = r600_clear_surface_reg,
1117 .init = &r600_hpd_init,
1118 .fini = &r600_hpd_fini,
1119 .sense = &r600_hpd_sense,
1120 .set_polarity = &r600_hpd_set_polarity,
1123 .misc = &r600_pm_misc,
1124 .prepare = &rs600_pm_prepare,
1125 .finish = &rs600_pm_finish,
1126 .init_profile = &rs780_pm_init_profile,
1127 .get_dynpm_state = &r600_pm_get_dynpm_state,
1128 .get_engine_clock = &radeon_atom_get_engine_clock,
1129 .set_engine_clock = &radeon_atom_set_engine_clock,
1130 .get_memory_clock = NULL,
1131 .set_memory_clock = NULL,
1132 .get_pcie_lanes = NULL,
1133 .set_pcie_lanes = NULL,
1134 .set_clock_gating = NULL,
1135 .get_temperature = &rv6xx_get_temp,
1136 .set_uvd_clocks = &r600_set_uvd_clocks,
1139 .init = &rs780_dpm_init,
1140 .setup_asic = &rs780_dpm_setup_asic,
1141 .enable = &rs780_dpm_enable,
1142 .late_enable = &r600_dpm_late_enable,
1143 .disable = &rs780_dpm_disable,
1144 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1145 .set_power_state = &rs780_dpm_set_power_state,
1146 .post_set_power_state = &r600_dpm_post_set_power_state,
1147 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1148 .fini = &rs780_dpm_fini,
1149 .get_sclk = &rs780_dpm_get_sclk,
1150 .get_mclk = &rs780_dpm_get_mclk,
1151 .print_power_state = &rs780_dpm_print_power_state,
1152 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1153 .force_performance_level = &rs780_dpm_force_performance_level,
1156 .page_flip = &rs600_page_flip,
1157 .page_flip_pending = &rs600_page_flip_pending,
1161 static struct radeon_asic_ring rv770_uvd_ring = {
1162 .ib_execute = &uvd_v1_0_ib_execute,
1163 .emit_fence = &uvd_v2_2_fence_emit,
1164 .emit_semaphore = &uvd_v1_0_semaphore_emit,
1165 .cs_parse = &radeon_uvd_cs_parse,
1166 .ring_test = &uvd_v1_0_ring_test,
1167 .ib_test = &uvd_v1_0_ib_test,
1168 .is_lockup = &radeon_ring_test_lockup,
1169 .get_rptr = &uvd_v1_0_get_rptr,
1170 .get_wptr = &uvd_v1_0_get_wptr,
1171 .set_wptr = &uvd_v1_0_set_wptr,
1174 static struct radeon_asic rv770_asic = {
1175 .init = &rv770_init,
1176 .fini = &rv770_fini,
1177 .suspend = &rv770_suspend,
1178 .resume = &rv770_resume,
1179 .asic_reset = &r600_asic_reset,
1180 .vga_set_state = &r600_vga_set_state,
1181 .mmio_hdp_flush = r600_mmio_hdp_flush,
1182 .gui_idle = &r600_gui_idle,
1183 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1184 .get_xclk = &rv770_get_xclk,
1185 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1187 .tlb_flush = &r600_pcie_gart_tlb_flush,
1188 .set_page = &rs600_gart_set_page,
1191 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1192 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1193 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1196 .set = &r600_irq_set,
1197 .process = &r600_irq_process,
1200 .bandwidth_update = &rv515_bandwidth_update,
1201 .get_vblank_counter = &rs600_get_vblank_counter,
1202 .wait_for_vblank = &avivo_wait_for_vblank,
1203 .set_backlight_level = &atombios_set_backlight_level,
1204 .get_backlight_level = &atombios_get_backlight_level,
1205 .hdmi_enable = &r600_hdmi_enable,
1206 .hdmi_setmode = &dce3_1_hdmi_setmode,
1209 .blit = &r600_copy_cpdma,
1210 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1211 .dma = &rv770_copy_dma,
1212 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1213 .copy = &rv770_copy_dma,
1214 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1217 .set_reg = r600_set_surface_reg,
1218 .clear_reg = r600_clear_surface_reg,
1221 .init = &r600_hpd_init,
1222 .fini = &r600_hpd_fini,
1223 .sense = &r600_hpd_sense,
1224 .set_polarity = &r600_hpd_set_polarity,
1227 .misc = &rv770_pm_misc,
1228 .prepare = &rs600_pm_prepare,
1229 .finish = &rs600_pm_finish,
1230 .init_profile = &r600_pm_init_profile,
1231 .get_dynpm_state = &r600_pm_get_dynpm_state,
1232 .get_engine_clock = &radeon_atom_get_engine_clock,
1233 .set_engine_clock = &radeon_atom_set_engine_clock,
1234 .get_memory_clock = &radeon_atom_get_memory_clock,
1235 .set_memory_clock = &radeon_atom_set_memory_clock,
1236 .get_pcie_lanes = &r600_get_pcie_lanes,
1237 .set_pcie_lanes = &r600_set_pcie_lanes,
1238 .set_clock_gating = &radeon_atom_set_clock_gating,
1239 .set_uvd_clocks = &rv770_set_uvd_clocks,
1240 .get_temperature = &rv770_get_temp,
1243 .init = &rv770_dpm_init,
1244 .setup_asic = &rv770_dpm_setup_asic,
1245 .enable = &rv770_dpm_enable,
1246 .late_enable = &rv770_dpm_late_enable,
1247 .disable = &rv770_dpm_disable,
1248 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1249 .set_power_state = &rv770_dpm_set_power_state,
1250 .post_set_power_state = &r600_dpm_post_set_power_state,
1251 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1252 .fini = &rv770_dpm_fini,
1253 .get_sclk = &rv770_dpm_get_sclk,
1254 .get_mclk = &rv770_dpm_get_mclk,
1255 .print_power_state = &rv770_dpm_print_power_state,
1256 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1257 .force_performance_level = &rv770_dpm_force_performance_level,
1258 .vblank_too_short = &rv770_dpm_vblank_too_short,
1261 .page_flip = &rv770_page_flip,
1262 .page_flip_pending = &rv770_page_flip_pending,
1266 static struct radeon_asic_ring evergreen_gfx_ring = {
1267 .ib_execute = &evergreen_ring_ib_execute,
1268 .emit_fence = &r600_fence_ring_emit,
1269 .emit_semaphore = &r600_semaphore_ring_emit,
1270 .cs_parse = &evergreen_cs_parse,
1271 .ring_test = &r600_ring_test,
1272 .ib_test = &r600_ib_test,
1273 .is_lockup = &evergreen_gfx_is_lockup,
1274 .get_rptr = &r600_gfx_get_rptr,
1275 .get_wptr = &r600_gfx_get_wptr,
1276 .set_wptr = &r600_gfx_set_wptr,
1279 static struct radeon_asic_ring evergreen_dma_ring = {
1280 .ib_execute = &evergreen_dma_ring_ib_execute,
1281 .emit_fence = &evergreen_dma_fence_ring_emit,
1282 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1283 .cs_parse = &evergreen_dma_cs_parse,
1284 .ring_test = &r600_dma_ring_test,
1285 .ib_test = &r600_dma_ib_test,
1286 .is_lockup = &evergreen_dma_is_lockup,
1287 .get_rptr = &r600_dma_get_rptr,
1288 .get_wptr = &r600_dma_get_wptr,
1289 .set_wptr = &r600_dma_set_wptr,
1292 static struct radeon_asic evergreen_asic = {
1293 .init = &evergreen_init,
1294 .fini = &evergreen_fini,
1295 .suspend = &evergreen_suspend,
1296 .resume = &evergreen_resume,
1297 .asic_reset = &evergreen_asic_reset,
1298 .vga_set_state = &r600_vga_set_state,
1299 .mmio_hdp_flush = r600_mmio_hdp_flush,
1300 .gui_idle = &r600_gui_idle,
1301 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1302 .get_xclk = &rv770_get_xclk,
1303 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1305 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1306 .set_page = &rs600_gart_set_page,
1309 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1310 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1311 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1314 .set = &evergreen_irq_set,
1315 .process = &evergreen_irq_process,
1318 .bandwidth_update = &evergreen_bandwidth_update,
1319 .get_vblank_counter = &evergreen_get_vblank_counter,
1320 .wait_for_vblank = &dce4_wait_for_vblank,
1321 .set_backlight_level = &atombios_set_backlight_level,
1322 .get_backlight_level = &atombios_get_backlight_level,
1323 .hdmi_enable = &evergreen_hdmi_enable,
1324 .hdmi_setmode = &evergreen_hdmi_setmode,
1327 .blit = &r600_copy_cpdma,
1328 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1329 .dma = &evergreen_copy_dma,
1330 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1331 .copy = &evergreen_copy_dma,
1332 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1335 .set_reg = r600_set_surface_reg,
1336 .clear_reg = r600_clear_surface_reg,
1339 .init = &evergreen_hpd_init,
1340 .fini = &evergreen_hpd_fini,
1341 .sense = &evergreen_hpd_sense,
1342 .set_polarity = &evergreen_hpd_set_polarity,
1345 .misc = &evergreen_pm_misc,
1346 .prepare = &evergreen_pm_prepare,
1347 .finish = &evergreen_pm_finish,
1348 .init_profile = &r600_pm_init_profile,
1349 .get_dynpm_state = &r600_pm_get_dynpm_state,
1350 .get_engine_clock = &radeon_atom_get_engine_clock,
1351 .set_engine_clock = &radeon_atom_set_engine_clock,
1352 .get_memory_clock = &radeon_atom_get_memory_clock,
1353 .set_memory_clock = &radeon_atom_set_memory_clock,
1354 .get_pcie_lanes = &r600_get_pcie_lanes,
1355 .set_pcie_lanes = &r600_set_pcie_lanes,
1356 .set_clock_gating = NULL,
1357 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1358 .get_temperature = &evergreen_get_temp,
1361 .init = &cypress_dpm_init,
1362 .setup_asic = &cypress_dpm_setup_asic,
1363 .enable = &cypress_dpm_enable,
1364 .late_enable = &rv770_dpm_late_enable,
1365 .disable = &cypress_dpm_disable,
1366 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1367 .set_power_state = &cypress_dpm_set_power_state,
1368 .post_set_power_state = &r600_dpm_post_set_power_state,
1369 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1370 .fini = &cypress_dpm_fini,
1371 .get_sclk = &rv770_dpm_get_sclk,
1372 .get_mclk = &rv770_dpm_get_mclk,
1373 .print_power_state = &rv770_dpm_print_power_state,
1374 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1375 .force_performance_level = &rv770_dpm_force_performance_level,
1376 .vblank_too_short = &cypress_dpm_vblank_too_short,
1379 .page_flip = &evergreen_page_flip,
1380 .page_flip_pending = &evergreen_page_flip_pending,
1384 static struct radeon_asic sumo_asic = {
1385 .init = &evergreen_init,
1386 .fini = &evergreen_fini,
1387 .suspend = &evergreen_suspend,
1388 .resume = &evergreen_resume,
1389 .asic_reset = &evergreen_asic_reset,
1390 .vga_set_state = &r600_vga_set_state,
1391 .mmio_hdp_flush = r600_mmio_hdp_flush,
1392 .gui_idle = &r600_gui_idle,
1393 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1394 .get_xclk = &r600_get_xclk,
1395 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1397 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1398 .set_page = &rs600_gart_set_page,
1401 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1402 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1403 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1406 .set = &evergreen_irq_set,
1407 .process = &evergreen_irq_process,
1410 .bandwidth_update = &evergreen_bandwidth_update,
1411 .get_vblank_counter = &evergreen_get_vblank_counter,
1412 .wait_for_vblank = &dce4_wait_for_vblank,
1413 .set_backlight_level = &atombios_set_backlight_level,
1414 .get_backlight_level = &atombios_get_backlight_level,
1415 .hdmi_enable = &evergreen_hdmi_enable,
1416 .hdmi_setmode = &evergreen_hdmi_setmode,
1419 .blit = &r600_copy_cpdma,
1420 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1421 .dma = &evergreen_copy_dma,
1422 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1423 .copy = &evergreen_copy_dma,
1424 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1427 .set_reg = r600_set_surface_reg,
1428 .clear_reg = r600_clear_surface_reg,
1431 .init = &evergreen_hpd_init,
1432 .fini = &evergreen_hpd_fini,
1433 .sense = &evergreen_hpd_sense,
1434 .set_polarity = &evergreen_hpd_set_polarity,
1437 .misc = &evergreen_pm_misc,
1438 .prepare = &evergreen_pm_prepare,
1439 .finish = &evergreen_pm_finish,
1440 .init_profile = &sumo_pm_init_profile,
1441 .get_dynpm_state = &r600_pm_get_dynpm_state,
1442 .get_engine_clock = &radeon_atom_get_engine_clock,
1443 .set_engine_clock = &radeon_atom_set_engine_clock,
1444 .get_memory_clock = NULL,
1445 .set_memory_clock = NULL,
1446 .get_pcie_lanes = NULL,
1447 .set_pcie_lanes = NULL,
1448 .set_clock_gating = NULL,
1449 .set_uvd_clocks = &sumo_set_uvd_clocks,
1450 .get_temperature = &sumo_get_temp,
1453 .init = &sumo_dpm_init,
1454 .setup_asic = &sumo_dpm_setup_asic,
1455 .enable = &sumo_dpm_enable,
1456 .late_enable = &sumo_dpm_late_enable,
1457 .disable = &sumo_dpm_disable,
1458 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1459 .set_power_state = &sumo_dpm_set_power_state,
1460 .post_set_power_state = &sumo_dpm_post_set_power_state,
1461 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1462 .fini = &sumo_dpm_fini,
1463 .get_sclk = &sumo_dpm_get_sclk,
1464 .get_mclk = &sumo_dpm_get_mclk,
1465 .print_power_state = &sumo_dpm_print_power_state,
1466 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1467 .force_performance_level = &sumo_dpm_force_performance_level,
1470 .page_flip = &evergreen_page_flip,
1471 .page_flip_pending = &evergreen_page_flip_pending,
1475 static struct radeon_asic btc_asic = {
1476 .init = &evergreen_init,
1477 .fini = &evergreen_fini,
1478 .suspend = &evergreen_suspend,
1479 .resume = &evergreen_resume,
1480 .asic_reset = &evergreen_asic_reset,
1481 .vga_set_state = &r600_vga_set_state,
1482 .mmio_hdp_flush = r600_mmio_hdp_flush,
1483 .gui_idle = &r600_gui_idle,
1484 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1485 .get_xclk = &rv770_get_xclk,
1486 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1488 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1489 .set_page = &rs600_gart_set_page,
1492 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1493 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1494 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1497 .set = &evergreen_irq_set,
1498 .process = &evergreen_irq_process,
1501 .bandwidth_update = &evergreen_bandwidth_update,
1502 .get_vblank_counter = &evergreen_get_vblank_counter,
1503 .wait_for_vblank = &dce4_wait_for_vblank,
1504 .set_backlight_level = &atombios_set_backlight_level,
1505 .get_backlight_level = &atombios_get_backlight_level,
1506 .hdmi_enable = &evergreen_hdmi_enable,
1507 .hdmi_setmode = &evergreen_hdmi_setmode,
1510 .blit = &r600_copy_cpdma,
1511 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1512 .dma = &evergreen_copy_dma,
1513 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1514 .copy = &evergreen_copy_dma,
1515 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1518 .set_reg = r600_set_surface_reg,
1519 .clear_reg = r600_clear_surface_reg,
1522 .init = &evergreen_hpd_init,
1523 .fini = &evergreen_hpd_fini,
1524 .sense = &evergreen_hpd_sense,
1525 .set_polarity = &evergreen_hpd_set_polarity,
1528 .misc = &evergreen_pm_misc,
1529 .prepare = &evergreen_pm_prepare,
1530 .finish = &evergreen_pm_finish,
1531 .init_profile = &btc_pm_init_profile,
1532 .get_dynpm_state = &r600_pm_get_dynpm_state,
1533 .get_engine_clock = &radeon_atom_get_engine_clock,
1534 .set_engine_clock = &radeon_atom_set_engine_clock,
1535 .get_memory_clock = &radeon_atom_get_memory_clock,
1536 .set_memory_clock = &radeon_atom_set_memory_clock,
1537 .get_pcie_lanes = &r600_get_pcie_lanes,
1538 .set_pcie_lanes = &r600_set_pcie_lanes,
1539 .set_clock_gating = NULL,
1540 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1541 .get_temperature = &evergreen_get_temp,
1544 .init = &btc_dpm_init,
1545 .setup_asic = &btc_dpm_setup_asic,
1546 .enable = &btc_dpm_enable,
1547 .late_enable = &rv770_dpm_late_enable,
1548 .disable = &btc_dpm_disable,
1549 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1550 .set_power_state = &btc_dpm_set_power_state,
1551 .post_set_power_state = &btc_dpm_post_set_power_state,
1552 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1553 .fini = &btc_dpm_fini,
1554 .get_sclk = &btc_dpm_get_sclk,
1555 .get_mclk = &btc_dpm_get_mclk,
1556 .print_power_state = &rv770_dpm_print_power_state,
1557 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
1558 .force_performance_level = &rv770_dpm_force_performance_level,
1559 .vblank_too_short = &btc_dpm_vblank_too_short,
1562 .page_flip = &evergreen_page_flip,
1563 .page_flip_pending = &evergreen_page_flip_pending,
1567 static struct radeon_asic_ring cayman_gfx_ring = {
1568 .ib_execute = &cayman_ring_ib_execute,
1569 .ib_parse = &evergreen_ib_parse,
1570 .emit_fence = &cayman_fence_ring_emit,
1571 .emit_semaphore = &r600_semaphore_ring_emit,
1572 .cs_parse = &evergreen_cs_parse,
1573 .ring_test = &r600_ring_test,
1574 .ib_test = &r600_ib_test,
1575 .is_lockup = &cayman_gfx_is_lockup,
1576 .vm_flush = &cayman_vm_flush,
1577 .get_rptr = &cayman_gfx_get_rptr,
1578 .get_wptr = &cayman_gfx_get_wptr,
1579 .set_wptr = &cayman_gfx_set_wptr,
1582 static struct radeon_asic_ring cayman_dma_ring = {
1583 .ib_execute = &cayman_dma_ring_ib_execute,
1584 .ib_parse = &evergreen_dma_ib_parse,
1585 .emit_fence = &evergreen_dma_fence_ring_emit,
1586 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1587 .cs_parse = &evergreen_dma_cs_parse,
1588 .ring_test = &r600_dma_ring_test,
1589 .ib_test = &r600_dma_ib_test,
1590 .is_lockup = &cayman_dma_is_lockup,
1591 .vm_flush = &cayman_dma_vm_flush,
1592 .get_rptr = &cayman_dma_get_rptr,
1593 .get_wptr = &cayman_dma_get_wptr,
1594 .set_wptr = &cayman_dma_set_wptr
1597 static struct radeon_asic_ring cayman_uvd_ring = {
1598 .ib_execute = &uvd_v1_0_ib_execute,
1599 .emit_fence = &uvd_v2_2_fence_emit,
1600 .emit_semaphore = &uvd_v3_1_semaphore_emit,
1601 .cs_parse = &radeon_uvd_cs_parse,
1602 .ring_test = &uvd_v1_0_ring_test,
1603 .ib_test = &uvd_v1_0_ib_test,
1604 .is_lockup = &radeon_ring_test_lockup,
1605 .get_rptr = &uvd_v1_0_get_rptr,
1606 .get_wptr = &uvd_v1_0_get_wptr,
1607 .set_wptr = &uvd_v1_0_set_wptr,
1610 static struct radeon_asic cayman_asic = {
1611 .init = &cayman_init,
1612 .fini = &cayman_fini,
1613 .suspend = &cayman_suspend,
1614 .resume = &cayman_resume,
1615 .asic_reset = &cayman_asic_reset,
1616 .vga_set_state = &r600_vga_set_state,
1617 .mmio_hdp_flush = r600_mmio_hdp_flush,
1618 .gui_idle = &r600_gui_idle,
1619 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1620 .get_xclk = &rv770_get_xclk,
1621 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1623 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1624 .set_page = &rs600_gart_set_page,
1627 .init = &cayman_vm_init,
1628 .fini = &cayman_vm_fini,
1629 .copy_pages = &cayman_dma_vm_copy_pages,
1630 .write_pages = &cayman_dma_vm_write_pages,
1631 .set_pages = &cayman_dma_vm_set_pages,
1632 .pad_ib = &cayman_dma_vm_pad_ib,
1635 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1636 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1637 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1638 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1639 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1640 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1643 .set = &evergreen_irq_set,
1644 .process = &evergreen_irq_process,
1647 .bandwidth_update = &evergreen_bandwidth_update,
1648 .get_vblank_counter = &evergreen_get_vblank_counter,
1649 .wait_for_vblank = &dce4_wait_for_vblank,
1650 .set_backlight_level = &atombios_set_backlight_level,
1651 .get_backlight_level = &atombios_get_backlight_level,
1652 .hdmi_enable = &evergreen_hdmi_enable,
1653 .hdmi_setmode = &evergreen_hdmi_setmode,
1656 .blit = &r600_copy_cpdma,
1657 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1658 .dma = &evergreen_copy_dma,
1659 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1660 .copy = &evergreen_copy_dma,
1661 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1664 .set_reg = r600_set_surface_reg,
1665 .clear_reg = r600_clear_surface_reg,
1668 .init = &evergreen_hpd_init,
1669 .fini = &evergreen_hpd_fini,
1670 .sense = &evergreen_hpd_sense,
1671 .set_polarity = &evergreen_hpd_set_polarity,
1674 .misc = &evergreen_pm_misc,
1675 .prepare = &evergreen_pm_prepare,
1676 .finish = &evergreen_pm_finish,
1677 .init_profile = &btc_pm_init_profile,
1678 .get_dynpm_state = &r600_pm_get_dynpm_state,
1679 .get_engine_clock = &radeon_atom_get_engine_clock,
1680 .set_engine_clock = &radeon_atom_set_engine_clock,
1681 .get_memory_clock = &radeon_atom_get_memory_clock,
1682 .set_memory_clock = &radeon_atom_set_memory_clock,
1683 .get_pcie_lanes = &r600_get_pcie_lanes,
1684 .set_pcie_lanes = &r600_set_pcie_lanes,
1685 .set_clock_gating = NULL,
1686 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1687 .get_temperature = &evergreen_get_temp,
1690 .init = &ni_dpm_init,
1691 .setup_asic = &ni_dpm_setup_asic,
1692 .enable = &ni_dpm_enable,
1693 .late_enable = &rv770_dpm_late_enable,
1694 .disable = &ni_dpm_disable,
1695 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1696 .set_power_state = &ni_dpm_set_power_state,
1697 .post_set_power_state = &ni_dpm_post_set_power_state,
1698 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1699 .fini = &ni_dpm_fini,
1700 .get_sclk = &ni_dpm_get_sclk,
1701 .get_mclk = &ni_dpm_get_mclk,
1702 .print_power_state = &ni_dpm_print_power_state,
1703 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1704 .force_performance_level = &ni_dpm_force_performance_level,
1705 .vblank_too_short = &ni_dpm_vblank_too_short,
1708 .page_flip = &evergreen_page_flip,
1709 .page_flip_pending = &evergreen_page_flip_pending,
1713 static struct radeon_asic trinity_asic = {
1714 .init = &cayman_init,
1715 .fini = &cayman_fini,
1716 .suspend = &cayman_suspend,
1717 .resume = &cayman_resume,
1718 .asic_reset = &cayman_asic_reset,
1719 .vga_set_state = &r600_vga_set_state,
1720 .mmio_hdp_flush = r600_mmio_hdp_flush,
1721 .gui_idle = &r600_gui_idle,
1722 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1723 .get_xclk = &r600_get_xclk,
1724 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1726 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1727 .set_page = &rs600_gart_set_page,
1730 .init = &cayman_vm_init,
1731 .fini = &cayman_vm_fini,
1732 .copy_pages = &cayman_dma_vm_copy_pages,
1733 .write_pages = &cayman_dma_vm_write_pages,
1734 .set_pages = &cayman_dma_vm_set_pages,
1735 .pad_ib = &cayman_dma_vm_pad_ib,
1738 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1739 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1740 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1741 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1742 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1743 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1746 .set = &evergreen_irq_set,
1747 .process = &evergreen_irq_process,
1750 .bandwidth_update = &dce6_bandwidth_update,
1751 .get_vblank_counter = &evergreen_get_vblank_counter,
1752 .wait_for_vblank = &dce4_wait_for_vblank,
1753 .set_backlight_level = &atombios_set_backlight_level,
1754 .get_backlight_level = &atombios_get_backlight_level,
1755 .hdmi_enable = &evergreen_hdmi_enable,
1756 .hdmi_setmode = &evergreen_hdmi_setmode,
1759 .blit = &r600_copy_cpdma,
1760 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1761 .dma = &evergreen_copy_dma,
1762 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1763 .copy = &evergreen_copy_dma,
1764 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1767 .set_reg = r600_set_surface_reg,
1768 .clear_reg = r600_clear_surface_reg,
1771 .init = &evergreen_hpd_init,
1772 .fini = &evergreen_hpd_fini,
1773 .sense = &evergreen_hpd_sense,
1774 .set_polarity = &evergreen_hpd_set_polarity,
1777 .misc = &evergreen_pm_misc,
1778 .prepare = &evergreen_pm_prepare,
1779 .finish = &evergreen_pm_finish,
1780 .init_profile = &sumo_pm_init_profile,
1781 .get_dynpm_state = &r600_pm_get_dynpm_state,
1782 .get_engine_clock = &radeon_atom_get_engine_clock,
1783 .set_engine_clock = &radeon_atom_set_engine_clock,
1784 .get_memory_clock = NULL,
1785 .set_memory_clock = NULL,
1786 .get_pcie_lanes = NULL,
1787 .set_pcie_lanes = NULL,
1788 .set_clock_gating = NULL,
1789 .set_uvd_clocks = &sumo_set_uvd_clocks,
1790 .get_temperature = &tn_get_temp,
1793 .init = &trinity_dpm_init,
1794 .setup_asic = &trinity_dpm_setup_asic,
1795 .enable = &trinity_dpm_enable,
1796 .late_enable = &trinity_dpm_late_enable,
1797 .disable = &trinity_dpm_disable,
1798 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
1799 .set_power_state = &trinity_dpm_set_power_state,
1800 .post_set_power_state = &trinity_dpm_post_set_power_state,
1801 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1802 .fini = &trinity_dpm_fini,
1803 .get_sclk = &trinity_dpm_get_sclk,
1804 .get_mclk = &trinity_dpm_get_mclk,
1805 .print_power_state = &trinity_dpm_print_power_state,
1806 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1807 .force_performance_level = &trinity_dpm_force_performance_level,
1808 .enable_bapm = &trinity_dpm_enable_bapm,
1811 .page_flip = &evergreen_page_flip,
1812 .page_flip_pending = &evergreen_page_flip_pending,
1816 static struct radeon_asic_ring si_gfx_ring = {
1817 .ib_execute = &si_ring_ib_execute,
1818 .ib_parse = &si_ib_parse,
1819 .emit_fence = &si_fence_ring_emit,
1820 .emit_semaphore = &r600_semaphore_ring_emit,
1822 .ring_test = &r600_ring_test,
1823 .ib_test = &r600_ib_test,
1824 .is_lockup = &si_gfx_is_lockup,
1825 .vm_flush = &si_vm_flush,
1826 .get_rptr = &cayman_gfx_get_rptr,
1827 .get_wptr = &cayman_gfx_get_wptr,
1828 .set_wptr = &cayman_gfx_set_wptr,
1831 static struct radeon_asic_ring si_dma_ring = {
1832 .ib_execute = &cayman_dma_ring_ib_execute,
1833 .ib_parse = &evergreen_dma_ib_parse,
1834 .emit_fence = &evergreen_dma_fence_ring_emit,
1835 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1837 .ring_test = &r600_dma_ring_test,
1838 .ib_test = &r600_dma_ib_test,
1839 .is_lockup = &si_dma_is_lockup,
1840 .vm_flush = &si_dma_vm_flush,
1841 .get_rptr = &cayman_dma_get_rptr,
1842 .get_wptr = &cayman_dma_get_wptr,
1843 .set_wptr = &cayman_dma_set_wptr,
1846 static struct radeon_asic si_asic = {
1849 .suspend = &si_suspend,
1850 .resume = &si_resume,
1851 .asic_reset = &si_asic_reset,
1852 .vga_set_state = &r600_vga_set_state,
1853 .mmio_hdp_flush = r600_mmio_hdp_flush,
1854 .gui_idle = &r600_gui_idle,
1855 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1856 .get_xclk = &si_get_xclk,
1857 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1859 .tlb_flush = &si_pcie_gart_tlb_flush,
1860 .set_page = &rs600_gart_set_page,
1863 .init = &si_vm_init,
1864 .fini = &si_vm_fini,
1865 .copy_pages = &si_dma_vm_copy_pages,
1866 .write_pages = &si_dma_vm_write_pages,
1867 .set_pages = &si_dma_vm_set_pages,
1868 .pad_ib = &cayman_dma_vm_pad_ib,
1871 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1872 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1873 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1874 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1875 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1876 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1880 .process = &si_irq_process,
1883 .bandwidth_update = &dce6_bandwidth_update,
1884 .get_vblank_counter = &evergreen_get_vblank_counter,
1885 .wait_for_vblank = &dce4_wait_for_vblank,
1886 .set_backlight_level = &atombios_set_backlight_level,
1887 .get_backlight_level = &atombios_get_backlight_level,
1888 .hdmi_enable = &evergreen_hdmi_enable,
1889 .hdmi_setmode = &evergreen_hdmi_setmode,
1892 .blit = &r600_copy_cpdma,
1893 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1894 .dma = &si_copy_dma,
1895 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1896 .copy = &si_copy_dma,
1897 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1900 .set_reg = r600_set_surface_reg,
1901 .clear_reg = r600_clear_surface_reg,
1904 .init = &evergreen_hpd_init,
1905 .fini = &evergreen_hpd_fini,
1906 .sense = &evergreen_hpd_sense,
1907 .set_polarity = &evergreen_hpd_set_polarity,
1910 .misc = &evergreen_pm_misc,
1911 .prepare = &evergreen_pm_prepare,
1912 .finish = &evergreen_pm_finish,
1913 .init_profile = &sumo_pm_init_profile,
1914 .get_dynpm_state = &r600_pm_get_dynpm_state,
1915 .get_engine_clock = &radeon_atom_get_engine_clock,
1916 .set_engine_clock = &radeon_atom_set_engine_clock,
1917 .get_memory_clock = &radeon_atom_get_memory_clock,
1918 .set_memory_clock = &radeon_atom_set_memory_clock,
1919 .get_pcie_lanes = &r600_get_pcie_lanes,
1920 .set_pcie_lanes = &r600_set_pcie_lanes,
1921 .set_clock_gating = NULL,
1922 .set_uvd_clocks = &si_set_uvd_clocks,
1923 .get_temperature = &si_get_temp,
1926 .init = &si_dpm_init,
1927 .setup_asic = &si_dpm_setup_asic,
1928 .enable = &si_dpm_enable,
1929 .late_enable = &si_dpm_late_enable,
1930 .disable = &si_dpm_disable,
1931 .pre_set_power_state = &si_dpm_pre_set_power_state,
1932 .set_power_state = &si_dpm_set_power_state,
1933 .post_set_power_state = &si_dpm_post_set_power_state,
1934 .display_configuration_changed = &si_dpm_display_configuration_changed,
1935 .fini = &si_dpm_fini,
1936 .get_sclk = &ni_dpm_get_sclk,
1937 .get_mclk = &ni_dpm_get_mclk,
1938 .print_power_state = &ni_dpm_print_power_state,
1939 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
1940 .force_performance_level = &si_dpm_force_performance_level,
1941 .vblank_too_short = &ni_dpm_vblank_too_short,
1944 .page_flip = &evergreen_page_flip,
1945 .page_flip_pending = &evergreen_page_flip_pending,
1949 static struct radeon_asic_ring ci_gfx_ring = {
1950 .ib_execute = &cik_ring_ib_execute,
1951 .ib_parse = &cik_ib_parse,
1952 .emit_fence = &cik_fence_gfx_ring_emit,
1953 .emit_semaphore = &cik_semaphore_ring_emit,
1955 .ring_test = &cik_ring_test,
1956 .ib_test = &cik_ib_test,
1957 .is_lockup = &cik_gfx_is_lockup,
1958 .vm_flush = &cik_vm_flush,
1959 .get_rptr = &cik_gfx_get_rptr,
1960 .get_wptr = &cik_gfx_get_wptr,
1961 .set_wptr = &cik_gfx_set_wptr,
1964 static struct radeon_asic_ring ci_cp_ring = {
1965 .ib_execute = &cik_ring_ib_execute,
1966 .ib_parse = &cik_ib_parse,
1967 .emit_fence = &cik_fence_compute_ring_emit,
1968 .emit_semaphore = &cik_semaphore_ring_emit,
1970 .ring_test = &cik_ring_test,
1971 .ib_test = &cik_ib_test,
1972 .is_lockup = &cik_gfx_is_lockup,
1973 .vm_flush = &cik_vm_flush,
1974 .get_rptr = &cik_compute_get_rptr,
1975 .get_wptr = &cik_compute_get_wptr,
1976 .set_wptr = &cik_compute_set_wptr,
1979 static struct radeon_asic_ring ci_dma_ring = {
1980 .ib_execute = &cik_sdma_ring_ib_execute,
1981 .ib_parse = &cik_ib_parse,
1982 .emit_fence = &cik_sdma_fence_ring_emit,
1983 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
1985 .ring_test = &cik_sdma_ring_test,
1986 .ib_test = &cik_sdma_ib_test,
1987 .is_lockup = &cik_sdma_is_lockup,
1988 .vm_flush = &cik_dma_vm_flush,
1989 .get_rptr = &cik_sdma_get_rptr,
1990 .get_wptr = &cik_sdma_get_wptr,
1991 .set_wptr = &cik_sdma_set_wptr,
1994 static struct radeon_asic_ring ci_vce_ring = {
1995 .ib_execute = &radeon_vce_ib_execute,
1996 .emit_fence = &radeon_vce_fence_emit,
1997 .emit_semaphore = &radeon_vce_semaphore_emit,
1998 .cs_parse = &radeon_vce_cs_parse,
1999 .ring_test = &radeon_vce_ring_test,
2000 .ib_test = &radeon_vce_ib_test,
2001 .is_lockup = &radeon_ring_test_lockup,
2002 .get_rptr = &vce_v1_0_get_rptr,
2003 .get_wptr = &vce_v1_0_get_wptr,
2004 .set_wptr = &vce_v1_0_set_wptr,
2007 static struct radeon_asic ci_asic = {
2010 .suspend = &cik_suspend,
2011 .resume = &cik_resume,
2012 .asic_reset = &cik_asic_reset,
2013 .vga_set_state = &r600_vga_set_state,
2014 .mmio_hdp_flush = &r600_mmio_hdp_flush,
2015 .gui_idle = &r600_gui_idle,
2016 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2017 .get_xclk = &cik_get_xclk,
2018 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2020 .tlb_flush = &cik_pcie_gart_tlb_flush,
2021 .set_page = &rs600_gart_set_page,
2024 .init = &cik_vm_init,
2025 .fini = &cik_vm_fini,
2026 .copy_pages = &cik_sdma_vm_copy_pages,
2027 .write_pages = &cik_sdma_vm_write_pages,
2028 .set_pages = &cik_sdma_vm_set_pages,
2029 .pad_ib = &cik_sdma_vm_pad_ib,
2032 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2033 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2034 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2035 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2036 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2037 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2038 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2039 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2042 .set = &cik_irq_set,
2043 .process = &cik_irq_process,
2046 .bandwidth_update = &dce8_bandwidth_update,
2047 .get_vblank_counter = &evergreen_get_vblank_counter,
2048 .wait_for_vblank = &dce4_wait_for_vblank,
2049 .set_backlight_level = &atombios_set_backlight_level,
2050 .get_backlight_level = &atombios_get_backlight_level,
2051 .hdmi_enable = &evergreen_hdmi_enable,
2052 .hdmi_setmode = &evergreen_hdmi_setmode,
2055 .blit = &cik_copy_cpdma,
2056 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2057 .dma = &cik_copy_dma,
2058 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2059 .copy = &cik_copy_dma,
2060 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2063 .set_reg = r600_set_surface_reg,
2064 .clear_reg = r600_clear_surface_reg,
2067 .init = &evergreen_hpd_init,
2068 .fini = &evergreen_hpd_fini,
2069 .sense = &evergreen_hpd_sense,
2070 .set_polarity = &evergreen_hpd_set_polarity,
2073 .misc = &evergreen_pm_misc,
2074 .prepare = &evergreen_pm_prepare,
2075 .finish = &evergreen_pm_finish,
2076 .init_profile = &sumo_pm_init_profile,
2077 .get_dynpm_state = &r600_pm_get_dynpm_state,
2078 .get_engine_clock = &radeon_atom_get_engine_clock,
2079 .set_engine_clock = &radeon_atom_set_engine_clock,
2080 .get_memory_clock = &radeon_atom_get_memory_clock,
2081 .set_memory_clock = &radeon_atom_set_memory_clock,
2082 .get_pcie_lanes = NULL,
2083 .set_pcie_lanes = NULL,
2084 .set_clock_gating = NULL,
2085 .set_uvd_clocks = &cik_set_uvd_clocks,
2086 .set_vce_clocks = &cik_set_vce_clocks,
2087 .get_temperature = &ci_get_temp,
2090 .init = &ci_dpm_init,
2091 .setup_asic = &ci_dpm_setup_asic,
2092 .enable = &ci_dpm_enable,
2093 .late_enable = &ci_dpm_late_enable,
2094 .disable = &ci_dpm_disable,
2095 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2096 .set_power_state = &ci_dpm_set_power_state,
2097 .post_set_power_state = &ci_dpm_post_set_power_state,
2098 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2099 .fini = &ci_dpm_fini,
2100 .get_sclk = &ci_dpm_get_sclk,
2101 .get_mclk = &ci_dpm_get_mclk,
2102 .print_power_state = &ci_dpm_print_power_state,
2103 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2104 .force_performance_level = &ci_dpm_force_performance_level,
2105 .vblank_too_short = &ci_dpm_vblank_too_short,
2106 .powergate_uvd = &ci_dpm_powergate_uvd,
2109 .page_flip = &evergreen_page_flip,
2110 .page_flip_pending = &evergreen_page_flip_pending,
2114 static struct radeon_asic kv_asic = {
2117 .suspend = &cik_suspend,
2118 .resume = &cik_resume,
2119 .asic_reset = &cik_asic_reset,
2120 .vga_set_state = &r600_vga_set_state,
2121 .mmio_hdp_flush = &r600_mmio_hdp_flush,
2122 .gui_idle = &r600_gui_idle,
2123 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2124 .get_xclk = &cik_get_xclk,
2125 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2127 .tlb_flush = &cik_pcie_gart_tlb_flush,
2128 .set_page = &rs600_gart_set_page,
2131 .init = &cik_vm_init,
2132 .fini = &cik_vm_fini,
2133 .copy_pages = &cik_sdma_vm_copy_pages,
2134 .write_pages = &cik_sdma_vm_write_pages,
2135 .set_pages = &cik_sdma_vm_set_pages,
2136 .pad_ib = &cik_sdma_vm_pad_ib,
2139 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2140 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2141 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2142 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2143 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2144 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2145 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2146 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2149 .set = &cik_irq_set,
2150 .process = &cik_irq_process,
2153 .bandwidth_update = &dce8_bandwidth_update,
2154 .get_vblank_counter = &evergreen_get_vblank_counter,
2155 .wait_for_vblank = &dce4_wait_for_vblank,
2156 .set_backlight_level = &atombios_set_backlight_level,
2157 .get_backlight_level = &atombios_get_backlight_level,
2158 .hdmi_enable = &evergreen_hdmi_enable,
2159 .hdmi_setmode = &evergreen_hdmi_setmode,
2162 .blit = &cik_copy_cpdma,
2163 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2164 .dma = &cik_copy_dma,
2165 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2166 .copy = &cik_copy_dma,
2167 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2170 .set_reg = r600_set_surface_reg,
2171 .clear_reg = r600_clear_surface_reg,
2174 .init = &evergreen_hpd_init,
2175 .fini = &evergreen_hpd_fini,
2176 .sense = &evergreen_hpd_sense,
2177 .set_polarity = &evergreen_hpd_set_polarity,
2180 .misc = &evergreen_pm_misc,
2181 .prepare = &evergreen_pm_prepare,
2182 .finish = &evergreen_pm_finish,
2183 .init_profile = &sumo_pm_init_profile,
2184 .get_dynpm_state = &r600_pm_get_dynpm_state,
2185 .get_engine_clock = &radeon_atom_get_engine_clock,
2186 .set_engine_clock = &radeon_atom_set_engine_clock,
2187 .get_memory_clock = &radeon_atom_get_memory_clock,
2188 .set_memory_clock = &radeon_atom_set_memory_clock,
2189 .get_pcie_lanes = NULL,
2190 .set_pcie_lanes = NULL,
2191 .set_clock_gating = NULL,
2192 .set_uvd_clocks = &cik_set_uvd_clocks,
2193 .set_vce_clocks = &cik_set_vce_clocks,
2194 .get_temperature = &kv_get_temp,
2197 .init = &kv_dpm_init,
2198 .setup_asic = &kv_dpm_setup_asic,
2199 .enable = &kv_dpm_enable,
2200 .late_enable = &kv_dpm_late_enable,
2201 .disable = &kv_dpm_disable,
2202 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2203 .set_power_state = &kv_dpm_set_power_state,
2204 .post_set_power_state = &kv_dpm_post_set_power_state,
2205 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2206 .fini = &kv_dpm_fini,
2207 .get_sclk = &kv_dpm_get_sclk,
2208 .get_mclk = &kv_dpm_get_mclk,
2209 .print_power_state = &kv_dpm_print_power_state,
2210 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2211 .force_performance_level = &kv_dpm_force_performance_level,
2212 .powergate_uvd = &kv_dpm_powergate_uvd,
2213 .enable_bapm = &kv_dpm_enable_bapm,
2216 .page_flip = &evergreen_page_flip,
2217 .page_flip_pending = &evergreen_page_flip_pending,
2222 * radeon_asic_init - register asic specific callbacks
2224 * @rdev: radeon device pointer
2226 * Registers the appropriate asic specific callbacks for each
2227 * chip family. Also sets other asics specific info like the number
2228 * of crtcs and the register aperture accessors (all asics).
2229 * Returns 0 for success.
2231 int radeon_asic_init(struct radeon_device *rdev)
2233 radeon_register_accessor_init(rdev);
2235 /* set the number of crtcs */
2236 if (rdev->flags & RADEON_SINGLE_CRTC)
2241 rdev->has_uvd = false;
2243 switch (rdev->family) {
2249 rdev->asic = &r100_asic;
2255 rdev->asic = &r200_asic;
2261 if (rdev->flags & RADEON_IS_PCIE)
2262 rdev->asic = &r300_asic_pcie;
2264 rdev->asic = &r300_asic;
2269 rdev->asic = &r420_asic;
2271 if (rdev->bios == NULL) {
2272 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2273 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2274 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2275 rdev->asic->pm.set_memory_clock = NULL;
2276 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2281 rdev->asic = &rs400_asic;
2284 rdev->asic = &rs600_asic;
2288 rdev->asic = &rs690_asic;
2291 rdev->asic = &rv515_asic;
2298 rdev->asic = &r520_asic;
2301 rdev->asic = &r600_asic;
2308 rdev->asic = &rv6xx_asic;
2309 rdev->has_uvd = true;
2313 rdev->asic = &rs780_asic;
2314 /* 760G/780V/880V don't have UVD */
2315 if ((rdev->pdev->device == 0x9616)||
2316 (rdev->pdev->device == 0x9611)||
2317 (rdev->pdev->device == 0x9613)||
2318 (rdev->pdev->device == 0x9711)||
2319 (rdev->pdev->device == 0x9713))
2320 rdev->has_uvd = false;
2322 rdev->has_uvd = true;
2328 rdev->asic = &rv770_asic;
2329 rdev->has_uvd = true;
2337 if (rdev->family == CHIP_CEDAR)
2341 rdev->asic = &evergreen_asic;
2342 rdev->has_uvd = true;
2347 rdev->asic = &sumo_asic;
2348 rdev->has_uvd = true;
2354 if (rdev->family == CHIP_CAICOS)
2358 rdev->asic = &btc_asic;
2359 rdev->has_uvd = true;
2362 rdev->asic = &cayman_asic;
2365 rdev->has_uvd = true;
2368 rdev->asic = &trinity_asic;
2371 rdev->has_uvd = true;
2378 rdev->asic = &si_asic;
2380 if (rdev->family == CHIP_HAINAN)
2382 else if (rdev->family == CHIP_OLAND)
2386 if (rdev->family == CHIP_HAINAN)
2387 rdev->has_uvd = false;
2389 rdev->has_uvd = true;
2390 switch (rdev->family) {
2393 RADEON_CG_SUPPORT_GFX_MGCG |
2394 RADEON_CG_SUPPORT_GFX_MGLS |
2395 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2396 RADEON_CG_SUPPORT_GFX_CGLS |
2397 RADEON_CG_SUPPORT_GFX_CGTS |
2398 RADEON_CG_SUPPORT_GFX_CP_LS |
2399 RADEON_CG_SUPPORT_MC_MGCG |
2400 RADEON_CG_SUPPORT_SDMA_MGCG |
2401 RADEON_CG_SUPPORT_BIF_LS |
2402 RADEON_CG_SUPPORT_VCE_MGCG |
2403 RADEON_CG_SUPPORT_UVD_MGCG |
2404 RADEON_CG_SUPPORT_HDP_LS |
2405 RADEON_CG_SUPPORT_HDP_MGCG;
2410 RADEON_CG_SUPPORT_GFX_MGCG |
2411 RADEON_CG_SUPPORT_GFX_MGLS |
2412 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2413 RADEON_CG_SUPPORT_GFX_CGLS |
2414 RADEON_CG_SUPPORT_GFX_CGTS |
2415 RADEON_CG_SUPPORT_GFX_CP_LS |
2416 RADEON_CG_SUPPORT_GFX_RLC_LS |
2417 RADEON_CG_SUPPORT_MC_LS |
2418 RADEON_CG_SUPPORT_MC_MGCG |
2419 RADEON_CG_SUPPORT_SDMA_MGCG |
2420 RADEON_CG_SUPPORT_BIF_LS |
2421 RADEON_CG_SUPPORT_VCE_MGCG |
2422 RADEON_CG_SUPPORT_UVD_MGCG |
2423 RADEON_CG_SUPPORT_HDP_LS |
2424 RADEON_CG_SUPPORT_HDP_MGCG;
2429 RADEON_CG_SUPPORT_GFX_MGCG |
2430 RADEON_CG_SUPPORT_GFX_MGLS |
2431 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2432 RADEON_CG_SUPPORT_GFX_CGLS |
2433 RADEON_CG_SUPPORT_GFX_CGTS |
2434 RADEON_CG_SUPPORT_GFX_CP_LS |
2435 RADEON_CG_SUPPORT_GFX_RLC_LS |
2436 RADEON_CG_SUPPORT_MC_LS |
2437 RADEON_CG_SUPPORT_MC_MGCG |
2438 RADEON_CG_SUPPORT_SDMA_MGCG |
2439 RADEON_CG_SUPPORT_BIF_LS |
2440 RADEON_CG_SUPPORT_VCE_MGCG |
2441 RADEON_CG_SUPPORT_UVD_MGCG |
2442 RADEON_CG_SUPPORT_HDP_LS |
2443 RADEON_CG_SUPPORT_HDP_MGCG;
2444 rdev->pg_flags = 0 |
2445 /*RADEON_PG_SUPPORT_GFX_PG | */
2446 RADEON_PG_SUPPORT_SDMA;
2450 RADEON_CG_SUPPORT_GFX_MGCG |
2451 RADEON_CG_SUPPORT_GFX_MGLS |
2452 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2453 RADEON_CG_SUPPORT_GFX_CGLS |
2454 RADEON_CG_SUPPORT_GFX_CGTS |
2455 RADEON_CG_SUPPORT_GFX_CP_LS |
2456 RADEON_CG_SUPPORT_GFX_RLC_LS |
2457 RADEON_CG_SUPPORT_MC_LS |
2458 RADEON_CG_SUPPORT_MC_MGCG |
2459 RADEON_CG_SUPPORT_SDMA_MGCG |
2460 RADEON_CG_SUPPORT_BIF_LS |
2461 RADEON_CG_SUPPORT_UVD_MGCG |
2462 RADEON_CG_SUPPORT_HDP_LS |
2463 RADEON_CG_SUPPORT_HDP_MGCG;
2468 RADEON_CG_SUPPORT_GFX_MGCG |
2469 RADEON_CG_SUPPORT_GFX_MGLS |
2470 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2471 RADEON_CG_SUPPORT_GFX_CGLS |
2472 RADEON_CG_SUPPORT_GFX_CGTS |
2473 RADEON_CG_SUPPORT_GFX_CP_LS |
2474 RADEON_CG_SUPPORT_GFX_RLC_LS |
2475 RADEON_CG_SUPPORT_MC_LS |
2476 RADEON_CG_SUPPORT_MC_MGCG |
2477 RADEON_CG_SUPPORT_SDMA_MGCG |
2478 RADEON_CG_SUPPORT_BIF_LS |
2479 RADEON_CG_SUPPORT_HDP_LS |
2480 RADEON_CG_SUPPORT_HDP_MGCG;
2491 rdev->asic = &ci_asic;
2493 rdev->has_uvd = true;
2494 if (rdev->family == CHIP_BONAIRE) {
2496 RADEON_CG_SUPPORT_GFX_MGCG |
2497 RADEON_CG_SUPPORT_GFX_MGLS |
2498 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2499 RADEON_CG_SUPPORT_GFX_CGLS |
2500 RADEON_CG_SUPPORT_GFX_CGTS |
2501 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2502 RADEON_CG_SUPPORT_GFX_CP_LS |
2503 RADEON_CG_SUPPORT_MC_LS |
2504 RADEON_CG_SUPPORT_MC_MGCG |
2505 RADEON_CG_SUPPORT_SDMA_MGCG |
2506 RADEON_CG_SUPPORT_SDMA_LS |
2507 RADEON_CG_SUPPORT_BIF_LS |
2508 RADEON_CG_SUPPORT_VCE_MGCG |
2509 RADEON_CG_SUPPORT_UVD_MGCG |
2510 RADEON_CG_SUPPORT_HDP_LS |
2511 RADEON_CG_SUPPORT_HDP_MGCG;
2515 RADEON_CG_SUPPORT_GFX_MGCG |
2516 RADEON_CG_SUPPORT_GFX_MGLS |
2517 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2518 RADEON_CG_SUPPORT_GFX_CGLS |
2519 RADEON_CG_SUPPORT_GFX_CGTS |
2520 RADEON_CG_SUPPORT_GFX_CP_LS |
2521 RADEON_CG_SUPPORT_MC_LS |
2522 RADEON_CG_SUPPORT_MC_MGCG |
2523 RADEON_CG_SUPPORT_SDMA_MGCG |
2524 RADEON_CG_SUPPORT_SDMA_LS |
2525 RADEON_CG_SUPPORT_BIF_LS |
2526 RADEON_CG_SUPPORT_VCE_MGCG |
2527 RADEON_CG_SUPPORT_UVD_MGCG |
2528 RADEON_CG_SUPPORT_HDP_LS |
2529 RADEON_CG_SUPPORT_HDP_MGCG;
2536 rdev->asic = &kv_asic;
2538 if (rdev->family == CHIP_KAVERI) {
2541 RADEON_CG_SUPPORT_GFX_MGCG |
2542 RADEON_CG_SUPPORT_GFX_MGLS |
2543 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2544 RADEON_CG_SUPPORT_GFX_CGLS |
2545 RADEON_CG_SUPPORT_GFX_CGTS |
2546 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2547 RADEON_CG_SUPPORT_GFX_CP_LS |
2548 RADEON_CG_SUPPORT_SDMA_MGCG |
2549 RADEON_CG_SUPPORT_SDMA_LS |
2550 RADEON_CG_SUPPORT_BIF_LS |
2551 RADEON_CG_SUPPORT_VCE_MGCG |
2552 RADEON_CG_SUPPORT_UVD_MGCG |
2553 RADEON_CG_SUPPORT_HDP_LS |
2554 RADEON_CG_SUPPORT_HDP_MGCG;
2556 /*RADEON_PG_SUPPORT_GFX_PG |
2557 RADEON_PG_SUPPORT_GFX_SMG |
2558 RADEON_PG_SUPPORT_GFX_DMG |
2559 RADEON_PG_SUPPORT_UVD |
2560 RADEON_PG_SUPPORT_VCE |
2561 RADEON_PG_SUPPORT_CP |
2562 RADEON_PG_SUPPORT_GDS |
2563 RADEON_PG_SUPPORT_RLC_SMU_HS |
2564 RADEON_PG_SUPPORT_ACP |
2565 RADEON_PG_SUPPORT_SAMU;*/
2569 RADEON_CG_SUPPORT_GFX_MGCG |
2570 RADEON_CG_SUPPORT_GFX_MGLS |
2571 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2572 RADEON_CG_SUPPORT_GFX_CGLS |
2573 RADEON_CG_SUPPORT_GFX_CGTS |
2574 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2575 RADEON_CG_SUPPORT_GFX_CP_LS |
2576 RADEON_CG_SUPPORT_SDMA_MGCG |
2577 RADEON_CG_SUPPORT_SDMA_LS |
2578 RADEON_CG_SUPPORT_BIF_LS |
2579 RADEON_CG_SUPPORT_VCE_MGCG |
2580 RADEON_CG_SUPPORT_UVD_MGCG |
2581 RADEON_CG_SUPPORT_HDP_LS |
2582 RADEON_CG_SUPPORT_HDP_MGCG;
2584 /*RADEON_PG_SUPPORT_GFX_PG |
2585 RADEON_PG_SUPPORT_GFX_SMG |
2586 RADEON_PG_SUPPORT_UVD |
2587 RADEON_PG_SUPPORT_VCE |
2588 RADEON_PG_SUPPORT_CP |
2589 RADEON_PG_SUPPORT_GDS |
2590 RADEON_PG_SUPPORT_RLC_SMU_HS |
2591 RADEON_PG_SUPPORT_SAMU;*/
2593 rdev->has_uvd = true;
2596 /* FIXME: not supported yet */
2600 if (rdev->flags & RADEON_IS_IGP) {
2601 rdev->asic->pm.get_memory_clock = NULL;
2602 rdev->asic->pm.set_memory_clock = NULL;