2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/console.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
37 #include "radeon_asic.h"
41 * Registers accessors functions.
44 * radeon_invalid_rreg - dummy reg read function
46 * @rdev: radeon device pointer
47 * @reg: offset of register
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
61 * radeon_invalid_wreg - dummy reg write function
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
78 * radeon_register_accessor_init - sets up the register accessor callbacks
80 * @rdev: radeon device pointer
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
85 static void radeon_register_accessor_init(struct radeon_device *rdev)
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
98 rdev->pcie_reg_mask = 0x7ff;
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
140 /* helper to disable agp */
142 * radeon_agp_disable - AGP disable helper function
144 * @rdev: radeon device pointer
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
149 void radeon_agp_disable(struct radeon_device *rdev)
151 rdev->flags &= ~RADEON_IS_AGP;
152 if (rdev->family >= CHIP_R600) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev->flags |= RADEON_IS_PCIE;
155 } else if (rdev->family >= CHIP_RV515 ||
156 rdev->family == CHIP_RV380 ||
157 rdev->family == CHIP_RV410 ||
158 rdev->family == CHIP_R423) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev->flags |= RADEON_IS_PCIE;
161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev->flags |= RADEON_IS_PCI;
166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
167 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
176 static struct radeon_asic_ring r100_gfx_ring = {
177 .ib_execute = &r100_ring_ib_execute,
178 .emit_fence = &r100_fence_ring_emit,
179 .emit_semaphore = &r100_semaphore_ring_emit,
180 .cs_parse = &r100_cs_parse,
181 .ring_start = &r100_ring_start,
182 .ring_test = &r100_ring_test,
183 .ib_test = &r100_ib_test,
184 .is_lockup = &r100_gpu_is_lockup,
185 .get_rptr = &radeon_ring_generic_get_rptr,
186 .get_wptr = &radeon_ring_generic_get_wptr,
187 .set_wptr = &radeon_ring_generic_set_wptr,
190 static struct radeon_asic r100_asic = {
193 .suspend = &r100_suspend,
194 .resume = &r100_resume,
195 .vga_set_state = &r100_vga_set_state,
196 .asic_reset = &r100_asic_reset,
197 .ioctl_wait_idle = NULL,
198 .gui_idle = &r100_gui_idle,
199 .mc_wait_for_idle = &r100_mc_wait_for_idle,
201 .tlb_flush = &r100_pci_gart_tlb_flush,
202 .set_page = &r100_pci_gart_set_page,
205 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
208 .set = &r100_irq_set,
209 .process = &r100_irq_process,
212 .bandwidth_update = &r100_bandwidth_update,
213 .get_vblank_counter = &r100_get_vblank_counter,
214 .wait_for_vblank = &r100_wait_for_vblank,
215 .set_backlight_level = &radeon_legacy_set_backlight_level,
216 .get_backlight_level = &radeon_legacy_get_backlight_level,
219 .blit = &r100_copy_blit,
220 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
222 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
223 .copy = &r100_copy_blit,
224 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
227 .set_reg = r100_set_surface_reg,
228 .clear_reg = r100_clear_surface_reg,
231 .init = &r100_hpd_init,
232 .fini = &r100_hpd_fini,
233 .sense = &r100_hpd_sense,
234 .set_polarity = &r100_hpd_set_polarity,
237 .misc = &r100_pm_misc,
238 .prepare = &r100_pm_prepare,
239 .finish = &r100_pm_finish,
240 .init_profile = &r100_pm_init_profile,
241 .get_dynpm_state = &r100_pm_get_dynpm_state,
242 .get_engine_clock = &radeon_legacy_get_engine_clock,
243 .set_engine_clock = &radeon_legacy_set_engine_clock,
244 .get_memory_clock = &radeon_legacy_get_memory_clock,
245 .set_memory_clock = NULL,
246 .get_pcie_lanes = NULL,
247 .set_pcie_lanes = NULL,
248 .set_clock_gating = &radeon_legacy_set_clock_gating,
251 .pre_page_flip = &r100_pre_page_flip,
252 .page_flip = &r100_page_flip,
253 .post_page_flip = &r100_post_page_flip,
257 static struct radeon_asic r200_asic = {
260 .suspend = &r100_suspend,
261 .resume = &r100_resume,
262 .vga_set_state = &r100_vga_set_state,
263 .asic_reset = &r100_asic_reset,
264 .ioctl_wait_idle = NULL,
265 .gui_idle = &r100_gui_idle,
266 .mc_wait_for_idle = &r100_mc_wait_for_idle,
268 .tlb_flush = &r100_pci_gart_tlb_flush,
269 .set_page = &r100_pci_gart_set_page,
272 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
275 .set = &r100_irq_set,
276 .process = &r100_irq_process,
279 .bandwidth_update = &r100_bandwidth_update,
280 .get_vblank_counter = &r100_get_vblank_counter,
281 .wait_for_vblank = &r100_wait_for_vblank,
282 .set_backlight_level = &radeon_legacy_set_backlight_level,
283 .get_backlight_level = &radeon_legacy_get_backlight_level,
286 .blit = &r100_copy_blit,
287 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
288 .dma = &r200_copy_dma,
289 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
290 .copy = &r100_copy_blit,
291 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
294 .set_reg = r100_set_surface_reg,
295 .clear_reg = r100_clear_surface_reg,
298 .init = &r100_hpd_init,
299 .fini = &r100_hpd_fini,
300 .sense = &r100_hpd_sense,
301 .set_polarity = &r100_hpd_set_polarity,
304 .misc = &r100_pm_misc,
305 .prepare = &r100_pm_prepare,
306 .finish = &r100_pm_finish,
307 .init_profile = &r100_pm_init_profile,
308 .get_dynpm_state = &r100_pm_get_dynpm_state,
309 .get_engine_clock = &radeon_legacy_get_engine_clock,
310 .set_engine_clock = &radeon_legacy_set_engine_clock,
311 .get_memory_clock = &radeon_legacy_get_memory_clock,
312 .set_memory_clock = NULL,
313 .get_pcie_lanes = NULL,
314 .set_pcie_lanes = NULL,
315 .set_clock_gating = &radeon_legacy_set_clock_gating,
318 .pre_page_flip = &r100_pre_page_flip,
319 .page_flip = &r100_page_flip,
320 .post_page_flip = &r100_post_page_flip,
324 static struct radeon_asic_ring r300_gfx_ring = {
325 .ib_execute = &r100_ring_ib_execute,
326 .emit_fence = &r300_fence_ring_emit,
327 .emit_semaphore = &r100_semaphore_ring_emit,
328 .cs_parse = &r300_cs_parse,
329 .ring_start = &r300_ring_start,
330 .ring_test = &r100_ring_test,
331 .ib_test = &r100_ib_test,
332 .is_lockup = &r100_gpu_is_lockup,
333 .get_rptr = &radeon_ring_generic_get_rptr,
334 .get_wptr = &radeon_ring_generic_get_wptr,
335 .set_wptr = &radeon_ring_generic_set_wptr,
338 static struct radeon_asic r300_asic = {
341 .suspend = &r300_suspend,
342 .resume = &r300_resume,
343 .vga_set_state = &r100_vga_set_state,
344 .asic_reset = &r300_asic_reset,
345 .ioctl_wait_idle = NULL,
346 .gui_idle = &r100_gui_idle,
347 .mc_wait_for_idle = &r300_mc_wait_for_idle,
349 .tlb_flush = &r100_pci_gart_tlb_flush,
350 .set_page = &r100_pci_gart_set_page,
353 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
356 .set = &r100_irq_set,
357 .process = &r100_irq_process,
360 .bandwidth_update = &r100_bandwidth_update,
361 .get_vblank_counter = &r100_get_vblank_counter,
362 .wait_for_vblank = &r100_wait_for_vblank,
363 .set_backlight_level = &radeon_legacy_set_backlight_level,
364 .get_backlight_level = &radeon_legacy_get_backlight_level,
367 .blit = &r100_copy_blit,
368 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
369 .dma = &r200_copy_dma,
370 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
371 .copy = &r100_copy_blit,
372 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
375 .set_reg = r100_set_surface_reg,
376 .clear_reg = r100_clear_surface_reg,
379 .init = &r100_hpd_init,
380 .fini = &r100_hpd_fini,
381 .sense = &r100_hpd_sense,
382 .set_polarity = &r100_hpd_set_polarity,
385 .misc = &r100_pm_misc,
386 .prepare = &r100_pm_prepare,
387 .finish = &r100_pm_finish,
388 .init_profile = &r100_pm_init_profile,
389 .get_dynpm_state = &r100_pm_get_dynpm_state,
390 .get_engine_clock = &radeon_legacy_get_engine_clock,
391 .set_engine_clock = &radeon_legacy_set_engine_clock,
392 .get_memory_clock = &radeon_legacy_get_memory_clock,
393 .set_memory_clock = NULL,
394 .get_pcie_lanes = &rv370_get_pcie_lanes,
395 .set_pcie_lanes = &rv370_set_pcie_lanes,
396 .set_clock_gating = &radeon_legacy_set_clock_gating,
399 .pre_page_flip = &r100_pre_page_flip,
400 .page_flip = &r100_page_flip,
401 .post_page_flip = &r100_post_page_flip,
405 static struct radeon_asic r300_asic_pcie = {
408 .suspend = &r300_suspend,
409 .resume = &r300_resume,
410 .vga_set_state = &r100_vga_set_state,
411 .asic_reset = &r300_asic_reset,
412 .ioctl_wait_idle = NULL,
413 .gui_idle = &r100_gui_idle,
414 .mc_wait_for_idle = &r300_mc_wait_for_idle,
416 .tlb_flush = &rv370_pcie_gart_tlb_flush,
417 .set_page = &rv370_pcie_gart_set_page,
420 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
423 .set = &r100_irq_set,
424 .process = &r100_irq_process,
427 .bandwidth_update = &r100_bandwidth_update,
428 .get_vblank_counter = &r100_get_vblank_counter,
429 .wait_for_vblank = &r100_wait_for_vblank,
430 .set_backlight_level = &radeon_legacy_set_backlight_level,
431 .get_backlight_level = &radeon_legacy_get_backlight_level,
434 .blit = &r100_copy_blit,
435 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
436 .dma = &r200_copy_dma,
437 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
438 .copy = &r100_copy_blit,
439 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
442 .set_reg = r100_set_surface_reg,
443 .clear_reg = r100_clear_surface_reg,
446 .init = &r100_hpd_init,
447 .fini = &r100_hpd_fini,
448 .sense = &r100_hpd_sense,
449 .set_polarity = &r100_hpd_set_polarity,
452 .misc = &r100_pm_misc,
453 .prepare = &r100_pm_prepare,
454 .finish = &r100_pm_finish,
455 .init_profile = &r100_pm_init_profile,
456 .get_dynpm_state = &r100_pm_get_dynpm_state,
457 .get_engine_clock = &radeon_legacy_get_engine_clock,
458 .set_engine_clock = &radeon_legacy_set_engine_clock,
459 .get_memory_clock = &radeon_legacy_get_memory_clock,
460 .set_memory_clock = NULL,
461 .get_pcie_lanes = &rv370_get_pcie_lanes,
462 .set_pcie_lanes = &rv370_set_pcie_lanes,
463 .set_clock_gating = &radeon_legacy_set_clock_gating,
466 .pre_page_flip = &r100_pre_page_flip,
467 .page_flip = &r100_page_flip,
468 .post_page_flip = &r100_post_page_flip,
472 static struct radeon_asic r420_asic = {
475 .suspend = &r420_suspend,
476 .resume = &r420_resume,
477 .vga_set_state = &r100_vga_set_state,
478 .asic_reset = &r300_asic_reset,
479 .ioctl_wait_idle = NULL,
480 .gui_idle = &r100_gui_idle,
481 .mc_wait_for_idle = &r300_mc_wait_for_idle,
483 .tlb_flush = &rv370_pcie_gart_tlb_flush,
484 .set_page = &rv370_pcie_gart_set_page,
487 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
490 .set = &r100_irq_set,
491 .process = &r100_irq_process,
494 .bandwidth_update = &r100_bandwidth_update,
495 .get_vblank_counter = &r100_get_vblank_counter,
496 .wait_for_vblank = &r100_wait_for_vblank,
497 .set_backlight_level = &atombios_set_backlight_level,
498 .get_backlight_level = &atombios_get_backlight_level,
501 .blit = &r100_copy_blit,
502 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
503 .dma = &r200_copy_dma,
504 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
505 .copy = &r100_copy_blit,
506 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
509 .set_reg = r100_set_surface_reg,
510 .clear_reg = r100_clear_surface_reg,
513 .init = &r100_hpd_init,
514 .fini = &r100_hpd_fini,
515 .sense = &r100_hpd_sense,
516 .set_polarity = &r100_hpd_set_polarity,
519 .misc = &r100_pm_misc,
520 .prepare = &r100_pm_prepare,
521 .finish = &r100_pm_finish,
522 .init_profile = &r420_pm_init_profile,
523 .get_dynpm_state = &r100_pm_get_dynpm_state,
524 .get_engine_clock = &radeon_atom_get_engine_clock,
525 .set_engine_clock = &radeon_atom_set_engine_clock,
526 .get_memory_clock = &radeon_atom_get_memory_clock,
527 .set_memory_clock = &radeon_atom_set_memory_clock,
528 .get_pcie_lanes = &rv370_get_pcie_lanes,
529 .set_pcie_lanes = &rv370_set_pcie_lanes,
530 .set_clock_gating = &radeon_atom_set_clock_gating,
533 .pre_page_flip = &r100_pre_page_flip,
534 .page_flip = &r100_page_flip,
535 .post_page_flip = &r100_post_page_flip,
539 static struct radeon_asic rs400_asic = {
542 .suspend = &rs400_suspend,
543 .resume = &rs400_resume,
544 .vga_set_state = &r100_vga_set_state,
545 .asic_reset = &r300_asic_reset,
546 .ioctl_wait_idle = NULL,
547 .gui_idle = &r100_gui_idle,
548 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
550 .tlb_flush = &rs400_gart_tlb_flush,
551 .set_page = &rs400_gart_set_page,
554 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
557 .set = &r100_irq_set,
558 .process = &r100_irq_process,
561 .bandwidth_update = &r100_bandwidth_update,
562 .get_vblank_counter = &r100_get_vblank_counter,
563 .wait_for_vblank = &r100_wait_for_vblank,
564 .set_backlight_level = &radeon_legacy_set_backlight_level,
565 .get_backlight_level = &radeon_legacy_get_backlight_level,
568 .blit = &r100_copy_blit,
569 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
570 .dma = &r200_copy_dma,
571 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
572 .copy = &r100_copy_blit,
573 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
576 .set_reg = r100_set_surface_reg,
577 .clear_reg = r100_clear_surface_reg,
580 .init = &r100_hpd_init,
581 .fini = &r100_hpd_fini,
582 .sense = &r100_hpd_sense,
583 .set_polarity = &r100_hpd_set_polarity,
586 .misc = &r100_pm_misc,
587 .prepare = &r100_pm_prepare,
588 .finish = &r100_pm_finish,
589 .init_profile = &r100_pm_init_profile,
590 .get_dynpm_state = &r100_pm_get_dynpm_state,
591 .get_engine_clock = &radeon_legacy_get_engine_clock,
592 .set_engine_clock = &radeon_legacy_set_engine_clock,
593 .get_memory_clock = &radeon_legacy_get_memory_clock,
594 .set_memory_clock = NULL,
595 .get_pcie_lanes = NULL,
596 .set_pcie_lanes = NULL,
597 .set_clock_gating = &radeon_legacy_set_clock_gating,
600 .pre_page_flip = &r100_pre_page_flip,
601 .page_flip = &r100_page_flip,
602 .post_page_flip = &r100_post_page_flip,
606 static struct radeon_asic rs600_asic = {
609 .suspend = &rs600_suspend,
610 .resume = &rs600_resume,
611 .vga_set_state = &r100_vga_set_state,
612 .asic_reset = &rs600_asic_reset,
613 .ioctl_wait_idle = NULL,
614 .gui_idle = &r100_gui_idle,
615 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
617 .tlb_flush = &rs600_gart_tlb_flush,
618 .set_page = &rs600_gart_set_page,
621 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
624 .set = &rs600_irq_set,
625 .process = &rs600_irq_process,
628 .bandwidth_update = &rs600_bandwidth_update,
629 .get_vblank_counter = &rs600_get_vblank_counter,
630 .wait_for_vblank = &avivo_wait_for_vblank,
631 .set_backlight_level = &atombios_set_backlight_level,
632 .get_backlight_level = &atombios_get_backlight_level,
633 .hdmi_enable = &r600_hdmi_enable,
634 .hdmi_setmode = &r600_hdmi_setmode,
637 .blit = &r100_copy_blit,
638 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
639 .dma = &r200_copy_dma,
640 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
641 .copy = &r100_copy_blit,
642 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
645 .set_reg = r100_set_surface_reg,
646 .clear_reg = r100_clear_surface_reg,
649 .init = &rs600_hpd_init,
650 .fini = &rs600_hpd_fini,
651 .sense = &rs600_hpd_sense,
652 .set_polarity = &rs600_hpd_set_polarity,
655 .misc = &rs600_pm_misc,
656 .prepare = &rs600_pm_prepare,
657 .finish = &rs600_pm_finish,
658 .init_profile = &r420_pm_init_profile,
659 .get_dynpm_state = &r100_pm_get_dynpm_state,
660 .get_engine_clock = &radeon_atom_get_engine_clock,
661 .set_engine_clock = &radeon_atom_set_engine_clock,
662 .get_memory_clock = &radeon_atom_get_memory_clock,
663 .set_memory_clock = &radeon_atom_set_memory_clock,
664 .get_pcie_lanes = NULL,
665 .set_pcie_lanes = NULL,
666 .set_clock_gating = &radeon_atom_set_clock_gating,
669 .pre_page_flip = &rs600_pre_page_flip,
670 .page_flip = &rs600_page_flip,
671 .post_page_flip = &rs600_post_page_flip,
675 static struct radeon_asic rs690_asic = {
678 .suspend = &rs690_suspend,
679 .resume = &rs690_resume,
680 .vga_set_state = &r100_vga_set_state,
681 .asic_reset = &rs600_asic_reset,
682 .ioctl_wait_idle = NULL,
683 .gui_idle = &r100_gui_idle,
684 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
686 .tlb_flush = &rs400_gart_tlb_flush,
687 .set_page = &rs400_gart_set_page,
690 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
693 .set = &rs600_irq_set,
694 .process = &rs600_irq_process,
697 .get_vblank_counter = &rs600_get_vblank_counter,
698 .bandwidth_update = &rs690_bandwidth_update,
699 .wait_for_vblank = &avivo_wait_for_vblank,
700 .set_backlight_level = &atombios_set_backlight_level,
701 .get_backlight_level = &atombios_get_backlight_level,
702 .hdmi_enable = &r600_hdmi_enable,
703 .hdmi_setmode = &r600_hdmi_setmode,
706 .blit = &r100_copy_blit,
707 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
708 .dma = &r200_copy_dma,
709 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
710 .copy = &r200_copy_dma,
711 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
714 .set_reg = r100_set_surface_reg,
715 .clear_reg = r100_clear_surface_reg,
718 .init = &rs600_hpd_init,
719 .fini = &rs600_hpd_fini,
720 .sense = &rs600_hpd_sense,
721 .set_polarity = &rs600_hpd_set_polarity,
724 .misc = &rs600_pm_misc,
725 .prepare = &rs600_pm_prepare,
726 .finish = &rs600_pm_finish,
727 .init_profile = &r420_pm_init_profile,
728 .get_dynpm_state = &r100_pm_get_dynpm_state,
729 .get_engine_clock = &radeon_atom_get_engine_clock,
730 .set_engine_clock = &radeon_atom_set_engine_clock,
731 .get_memory_clock = &radeon_atom_get_memory_clock,
732 .set_memory_clock = &radeon_atom_set_memory_clock,
733 .get_pcie_lanes = NULL,
734 .set_pcie_lanes = NULL,
735 .set_clock_gating = &radeon_atom_set_clock_gating,
738 .pre_page_flip = &rs600_pre_page_flip,
739 .page_flip = &rs600_page_flip,
740 .post_page_flip = &rs600_post_page_flip,
744 static struct radeon_asic rv515_asic = {
747 .suspend = &rv515_suspend,
748 .resume = &rv515_resume,
749 .vga_set_state = &r100_vga_set_state,
750 .asic_reset = &rs600_asic_reset,
751 .ioctl_wait_idle = NULL,
752 .gui_idle = &r100_gui_idle,
753 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
755 .tlb_flush = &rv370_pcie_gart_tlb_flush,
756 .set_page = &rv370_pcie_gart_set_page,
759 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
762 .set = &rs600_irq_set,
763 .process = &rs600_irq_process,
766 .get_vblank_counter = &rs600_get_vblank_counter,
767 .bandwidth_update = &rv515_bandwidth_update,
768 .wait_for_vblank = &avivo_wait_for_vblank,
769 .set_backlight_level = &atombios_set_backlight_level,
770 .get_backlight_level = &atombios_get_backlight_level,
773 .blit = &r100_copy_blit,
774 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
775 .dma = &r200_copy_dma,
776 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
777 .copy = &r100_copy_blit,
778 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
781 .set_reg = r100_set_surface_reg,
782 .clear_reg = r100_clear_surface_reg,
785 .init = &rs600_hpd_init,
786 .fini = &rs600_hpd_fini,
787 .sense = &rs600_hpd_sense,
788 .set_polarity = &rs600_hpd_set_polarity,
791 .misc = &rs600_pm_misc,
792 .prepare = &rs600_pm_prepare,
793 .finish = &rs600_pm_finish,
794 .init_profile = &r420_pm_init_profile,
795 .get_dynpm_state = &r100_pm_get_dynpm_state,
796 .get_engine_clock = &radeon_atom_get_engine_clock,
797 .set_engine_clock = &radeon_atom_set_engine_clock,
798 .get_memory_clock = &radeon_atom_get_memory_clock,
799 .set_memory_clock = &radeon_atom_set_memory_clock,
800 .get_pcie_lanes = &rv370_get_pcie_lanes,
801 .set_pcie_lanes = &rv370_set_pcie_lanes,
802 .set_clock_gating = &radeon_atom_set_clock_gating,
805 .pre_page_flip = &rs600_pre_page_flip,
806 .page_flip = &rs600_page_flip,
807 .post_page_flip = &rs600_post_page_flip,
811 static struct radeon_asic r520_asic = {
814 .suspend = &rv515_suspend,
815 .resume = &r520_resume,
816 .vga_set_state = &r100_vga_set_state,
817 .asic_reset = &rs600_asic_reset,
818 .ioctl_wait_idle = NULL,
819 .gui_idle = &r100_gui_idle,
820 .mc_wait_for_idle = &r520_mc_wait_for_idle,
822 .tlb_flush = &rv370_pcie_gart_tlb_flush,
823 .set_page = &rv370_pcie_gart_set_page,
826 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
829 .set = &rs600_irq_set,
830 .process = &rs600_irq_process,
833 .bandwidth_update = &rv515_bandwidth_update,
834 .get_vblank_counter = &rs600_get_vblank_counter,
835 .wait_for_vblank = &avivo_wait_for_vblank,
836 .set_backlight_level = &atombios_set_backlight_level,
837 .get_backlight_level = &atombios_get_backlight_level,
840 .blit = &r100_copy_blit,
841 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
842 .dma = &r200_copy_dma,
843 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
844 .copy = &r100_copy_blit,
845 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
848 .set_reg = r100_set_surface_reg,
849 .clear_reg = r100_clear_surface_reg,
852 .init = &rs600_hpd_init,
853 .fini = &rs600_hpd_fini,
854 .sense = &rs600_hpd_sense,
855 .set_polarity = &rs600_hpd_set_polarity,
858 .misc = &rs600_pm_misc,
859 .prepare = &rs600_pm_prepare,
860 .finish = &rs600_pm_finish,
861 .init_profile = &r420_pm_init_profile,
862 .get_dynpm_state = &r100_pm_get_dynpm_state,
863 .get_engine_clock = &radeon_atom_get_engine_clock,
864 .set_engine_clock = &radeon_atom_set_engine_clock,
865 .get_memory_clock = &radeon_atom_get_memory_clock,
866 .set_memory_clock = &radeon_atom_set_memory_clock,
867 .get_pcie_lanes = &rv370_get_pcie_lanes,
868 .set_pcie_lanes = &rv370_set_pcie_lanes,
869 .set_clock_gating = &radeon_atom_set_clock_gating,
872 .pre_page_flip = &rs600_pre_page_flip,
873 .page_flip = &rs600_page_flip,
874 .post_page_flip = &rs600_post_page_flip,
878 static struct radeon_asic_ring r600_gfx_ring = {
879 .ib_execute = &r600_ring_ib_execute,
880 .emit_fence = &r600_fence_ring_emit,
881 .emit_semaphore = &r600_semaphore_ring_emit,
882 .cs_parse = &r600_cs_parse,
883 .ring_test = &r600_ring_test,
884 .ib_test = &r600_ib_test,
885 .is_lockup = &r600_gfx_is_lockup,
886 .get_rptr = &radeon_ring_generic_get_rptr,
887 .get_wptr = &radeon_ring_generic_get_wptr,
888 .set_wptr = &radeon_ring_generic_set_wptr,
891 static struct radeon_asic_ring r600_dma_ring = {
892 .ib_execute = &r600_dma_ring_ib_execute,
893 .emit_fence = &r600_dma_fence_ring_emit,
894 .emit_semaphore = &r600_dma_semaphore_ring_emit,
895 .cs_parse = &r600_dma_cs_parse,
896 .ring_test = &r600_dma_ring_test,
897 .ib_test = &r600_dma_ib_test,
898 .is_lockup = &r600_dma_is_lockup,
899 .get_rptr = &r600_dma_get_rptr,
900 .get_wptr = &r600_dma_get_wptr,
901 .set_wptr = &r600_dma_set_wptr,
904 static struct radeon_asic r600_asic = {
907 .suspend = &r600_suspend,
908 .resume = &r600_resume,
909 .vga_set_state = &r600_vga_set_state,
910 .asic_reset = &r600_asic_reset,
911 .ioctl_wait_idle = r600_ioctl_wait_idle,
912 .gui_idle = &r600_gui_idle,
913 .mc_wait_for_idle = &r600_mc_wait_for_idle,
914 .get_xclk = &r600_get_xclk,
915 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
917 .tlb_flush = &r600_pcie_gart_tlb_flush,
918 .set_page = &rs600_gart_set_page,
921 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
922 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
925 .set = &r600_irq_set,
926 .process = &r600_irq_process,
929 .bandwidth_update = &rv515_bandwidth_update,
930 .get_vblank_counter = &rs600_get_vblank_counter,
931 .wait_for_vblank = &avivo_wait_for_vblank,
932 .set_backlight_level = &atombios_set_backlight_level,
933 .get_backlight_level = &atombios_get_backlight_level,
934 .hdmi_enable = &r600_hdmi_enable,
935 .hdmi_setmode = &r600_hdmi_setmode,
938 .blit = &r600_copy_cpdma,
939 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
940 .dma = &r600_copy_dma,
941 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
942 .copy = &r600_copy_cpdma,
943 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
946 .set_reg = r600_set_surface_reg,
947 .clear_reg = r600_clear_surface_reg,
950 .init = &r600_hpd_init,
951 .fini = &r600_hpd_fini,
952 .sense = &r600_hpd_sense,
953 .set_polarity = &r600_hpd_set_polarity,
956 .misc = &r600_pm_misc,
957 .prepare = &rs600_pm_prepare,
958 .finish = &rs600_pm_finish,
959 .init_profile = &r600_pm_init_profile,
960 .get_dynpm_state = &r600_pm_get_dynpm_state,
961 .get_engine_clock = &radeon_atom_get_engine_clock,
962 .set_engine_clock = &radeon_atom_set_engine_clock,
963 .get_memory_clock = &radeon_atom_get_memory_clock,
964 .set_memory_clock = &radeon_atom_set_memory_clock,
965 .get_pcie_lanes = &r600_get_pcie_lanes,
966 .set_pcie_lanes = &r600_set_pcie_lanes,
967 .set_clock_gating = NULL,
968 .get_temperature = &rv6xx_get_temp,
971 .pre_page_flip = &rs600_pre_page_flip,
972 .page_flip = &rs600_page_flip,
973 .post_page_flip = &rs600_post_page_flip,
977 static struct radeon_asic rv6xx_asic = {
980 .suspend = &r600_suspend,
981 .resume = &r600_resume,
982 .vga_set_state = &r600_vga_set_state,
983 .asic_reset = &r600_asic_reset,
984 .ioctl_wait_idle = r600_ioctl_wait_idle,
985 .gui_idle = &r600_gui_idle,
986 .mc_wait_for_idle = &r600_mc_wait_for_idle,
987 .get_xclk = &r600_get_xclk,
988 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
990 .tlb_flush = &r600_pcie_gart_tlb_flush,
991 .set_page = &rs600_gart_set_page,
994 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
995 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
998 .set = &r600_irq_set,
999 .process = &r600_irq_process,
1002 .bandwidth_update = &rv515_bandwidth_update,
1003 .get_vblank_counter = &rs600_get_vblank_counter,
1004 .wait_for_vblank = &avivo_wait_for_vblank,
1005 .set_backlight_level = &atombios_set_backlight_level,
1006 .get_backlight_level = &atombios_get_backlight_level,
1007 .hdmi_enable = &r600_hdmi_enable,
1008 .hdmi_setmode = &r600_hdmi_setmode,
1011 .blit = &r600_copy_cpdma,
1012 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1013 .dma = &r600_copy_dma,
1014 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1015 .copy = &r600_copy_cpdma,
1016 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1019 .set_reg = r600_set_surface_reg,
1020 .clear_reg = r600_clear_surface_reg,
1023 .init = &r600_hpd_init,
1024 .fini = &r600_hpd_fini,
1025 .sense = &r600_hpd_sense,
1026 .set_polarity = &r600_hpd_set_polarity,
1029 .misc = &r600_pm_misc,
1030 .prepare = &rs600_pm_prepare,
1031 .finish = &rs600_pm_finish,
1032 .init_profile = &r600_pm_init_profile,
1033 .get_dynpm_state = &r600_pm_get_dynpm_state,
1034 .get_engine_clock = &radeon_atom_get_engine_clock,
1035 .set_engine_clock = &radeon_atom_set_engine_clock,
1036 .get_memory_clock = &radeon_atom_get_memory_clock,
1037 .set_memory_clock = &radeon_atom_set_memory_clock,
1038 .get_pcie_lanes = &r600_get_pcie_lanes,
1039 .set_pcie_lanes = &r600_set_pcie_lanes,
1040 .set_clock_gating = NULL,
1041 .get_temperature = &rv6xx_get_temp,
1042 .set_uvd_clocks = &r600_set_uvd_clocks,
1045 .init = &rv6xx_dpm_init,
1046 .setup_asic = &rv6xx_setup_asic,
1047 .enable = &rv6xx_dpm_enable,
1048 .disable = &rv6xx_dpm_disable,
1049 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1050 .set_power_state = &rv6xx_dpm_set_power_state,
1051 .post_set_power_state = &r600_dpm_post_set_power_state,
1052 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1053 .fini = &rv6xx_dpm_fini,
1054 .get_sclk = &rv6xx_dpm_get_sclk,
1055 .get_mclk = &rv6xx_dpm_get_mclk,
1056 .print_power_state = &rv6xx_dpm_print_power_state,
1057 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1058 .force_performance_level = &rv6xx_dpm_force_performance_level,
1061 .pre_page_flip = &rs600_pre_page_flip,
1062 .page_flip = &rs600_page_flip,
1063 .post_page_flip = &rs600_post_page_flip,
1067 static struct radeon_asic rs780_asic = {
1070 .suspend = &r600_suspend,
1071 .resume = &r600_resume,
1072 .vga_set_state = &r600_vga_set_state,
1073 .asic_reset = &r600_asic_reset,
1074 .ioctl_wait_idle = r600_ioctl_wait_idle,
1075 .gui_idle = &r600_gui_idle,
1076 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1077 .get_xclk = &r600_get_xclk,
1078 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1080 .tlb_flush = &r600_pcie_gart_tlb_flush,
1081 .set_page = &rs600_gart_set_page,
1084 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1085 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1088 .set = &r600_irq_set,
1089 .process = &r600_irq_process,
1092 .bandwidth_update = &rs690_bandwidth_update,
1093 .get_vblank_counter = &rs600_get_vblank_counter,
1094 .wait_for_vblank = &avivo_wait_for_vblank,
1095 .set_backlight_level = &atombios_set_backlight_level,
1096 .get_backlight_level = &atombios_get_backlight_level,
1097 .hdmi_enable = &r600_hdmi_enable,
1098 .hdmi_setmode = &r600_hdmi_setmode,
1101 .blit = &r600_copy_cpdma,
1102 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1103 .dma = &r600_copy_dma,
1104 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1105 .copy = &r600_copy_cpdma,
1106 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1109 .set_reg = r600_set_surface_reg,
1110 .clear_reg = r600_clear_surface_reg,
1113 .init = &r600_hpd_init,
1114 .fini = &r600_hpd_fini,
1115 .sense = &r600_hpd_sense,
1116 .set_polarity = &r600_hpd_set_polarity,
1119 .misc = &r600_pm_misc,
1120 .prepare = &rs600_pm_prepare,
1121 .finish = &rs600_pm_finish,
1122 .init_profile = &rs780_pm_init_profile,
1123 .get_dynpm_state = &r600_pm_get_dynpm_state,
1124 .get_engine_clock = &radeon_atom_get_engine_clock,
1125 .set_engine_clock = &radeon_atom_set_engine_clock,
1126 .get_memory_clock = NULL,
1127 .set_memory_clock = NULL,
1128 .get_pcie_lanes = NULL,
1129 .set_pcie_lanes = NULL,
1130 .set_clock_gating = NULL,
1131 .get_temperature = &rv6xx_get_temp,
1132 .set_uvd_clocks = &r600_set_uvd_clocks,
1135 .init = &rs780_dpm_init,
1136 .setup_asic = &rs780_dpm_setup_asic,
1137 .enable = &rs780_dpm_enable,
1138 .disable = &rs780_dpm_disable,
1139 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1140 .set_power_state = &rs780_dpm_set_power_state,
1141 .post_set_power_state = &r600_dpm_post_set_power_state,
1142 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1143 .fini = &rs780_dpm_fini,
1144 .get_sclk = &rs780_dpm_get_sclk,
1145 .get_mclk = &rs780_dpm_get_mclk,
1146 .print_power_state = &rs780_dpm_print_power_state,
1147 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1148 .force_performance_level = &rs780_dpm_force_performance_level,
1151 .pre_page_flip = &rs600_pre_page_flip,
1152 .page_flip = &rs600_page_flip,
1153 .post_page_flip = &rs600_post_page_flip,
1157 static struct radeon_asic_ring rv770_uvd_ring = {
1158 .ib_execute = &uvd_v1_0_ib_execute,
1159 .emit_fence = &uvd_v2_2_fence_emit,
1160 .emit_semaphore = &uvd_v1_0_semaphore_emit,
1161 .cs_parse = &radeon_uvd_cs_parse,
1162 .ring_test = &uvd_v1_0_ring_test,
1163 .ib_test = &uvd_v1_0_ib_test,
1164 .is_lockup = &radeon_ring_test_lockup,
1165 .get_rptr = &uvd_v1_0_get_rptr,
1166 .get_wptr = &uvd_v1_0_get_wptr,
1167 .set_wptr = &uvd_v1_0_set_wptr,
1170 static struct radeon_asic rv770_asic = {
1171 .init = &rv770_init,
1172 .fini = &rv770_fini,
1173 .suspend = &rv770_suspend,
1174 .resume = &rv770_resume,
1175 .asic_reset = &r600_asic_reset,
1176 .vga_set_state = &r600_vga_set_state,
1177 .ioctl_wait_idle = r600_ioctl_wait_idle,
1178 .gui_idle = &r600_gui_idle,
1179 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1180 .get_xclk = &rv770_get_xclk,
1181 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1183 .tlb_flush = &r600_pcie_gart_tlb_flush,
1184 .set_page = &rs600_gart_set_page,
1187 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1188 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1189 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1192 .set = &r600_irq_set,
1193 .process = &r600_irq_process,
1196 .bandwidth_update = &rv515_bandwidth_update,
1197 .get_vblank_counter = &rs600_get_vblank_counter,
1198 .wait_for_vblank = &avivo_wait_for_vblank,
1199 .set_backlight_level = &atombios_set_backlight_level,
1200 .get_backlight_level = &atombios_get_backlight_level,
1201 .hdmi_enable = &r600_hdmi_enable,
1202 .hdmi_setmode = &r600_hdmi_setmode,
1205 .blit = &r600_copy_cpdma,
1206 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1207 .dma = &rv770_copy_dma,
1208 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1209 .copy = &rv770_copy_dma,
1210 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1213 .set_reg = r600_set_surface_reg,
1214 .clear_reg = r600_clear_surface_reg,
1217 .init = &r600_hpd_init,
1218 .fini = &r600_hpd_fini,
1219 .sense = &r600_hpd_sense,
1220 .set_polarity = &r600_hpd_set_polarity,
1223 .misc = &rv770_pm_misc,
1224 .prepare = &rs600_pm_prepare,
1225 .finish = &rs600_pm_finish,
1226 .init_profile = &r600_pm_init_profile,
1227 .get_dynpm_state = &r600_pm_get_dynpm_state,
1228 .get_engine_clock = &radeon_atom_get_engine_clock,
1229 .set_engine_clock = &radeon_atom_set_engine_clock,
1230 .get_memory_clock = &radeon_atom_get_memory_clock,
1231 .set_memory_clock = &radeon_atom_set_memory_clock,
1232 .get_pcie_lanes = &r600_get_pcie_lanes,
1233 .set_pcie_lanes = &r600_set_pcie_lanes,
1234 .set_clock_gating = &radeon_atom_set_clock_gating,
1235 .set_uvd_clocks = &rv770_set_uvd_clocks,
1236 .get_temperature = &rv770_get_temp,
1239 .init = &rv770_dpm_init,
1240 .setup_asic = &rv770_dpm_setup_asic,
1241 .enable = &rv770_dpm_enable,
1242 .disable = &rv770_dpm_disable,
1243 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1244 .set_power_state = &rv770_dpm_set_power_state,
1245 .post_set_power_state = &r600_dpm_post_set_power_state,
1246 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1247 .fini = &rv770_dpm_fini,
1248 .get_sclk = &rv770_dpm_get_sclk,
1249 .get_mclk = &rv770_dpm_get_mclk,
1250 .print_power_state = &rv770_dpm_print_power_state,
1251 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1252 .force_performance_level = &rv770_dpm_force_performance_level,
1253 .vblank_too_short = &rv770_dpm_vblank_too_short,
1256 .pre_page_flip = &rs600_pre_page_flip,
1257 .page_flip = &rv770_page_flip,
1258 .post_page_flip = &rs600_post_page_flip,
1262 static struct radeon_asic_ring evergreen_gfx_ring = {
1263 .ib_execute = &evergreen_ring_ib_execute,
1264 .emit_fence = &r600_fence_ring_emit,
1265 .emit_semaphore = &r600_semaphore_ring_emit,
1266 .cs_parse = &evergreen_cs_parse,
1267 .ring_test = &r600_ring_test,
1268 .ib_test = &r600_ib_test,
1269 .is_lockup = &evergreen_gfx_is_lockup,
1270 .get_rptr = &radeon_ring_generic_get_rptr,
1271 .get_wptr = &radeon_ring_generic_get_wptr,
1272 .set_wptr = &radeon_ring_generic_set_wptr,
1275 static struct radeon_asic_ring evergreen_dma_ring = {
1276 .ib_execute = &evergreen_dma_ring_ib_execute,
1277 .emit_fence = &evergreen_dma_fence_ring_emit,
1278 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1279 .cs_parse = &evergreen_dma_cs_parse,
1280 .ring_test = &r600_dma_ring_test,
1281 .ib_test = &r600_dma_ib_test,
1282 .is_lockup = &evergreen_dma_is_lockup,
1283 .get_rptr = &r600_dma_get_rptr,
1284 .get_wptr = &r600_dma_get_wptr,
1285 .set_wptr = &r600_dma_set_wptr,
1288 static struct radeon_asic evergreen_asic = {
1289 .init = &evergreen_init,
1290 .fini = &evergreen_fini,
1291 .suspend = &evergreen_suspend,
1292 .resume = &evergreen_resume,
1293 .asic_reset = &evergreen_asic_reset,
1294 .vga_set_state = &r600_vga_set_state,
1295 .ioctl_wait_idle = r600_ioctl_wait_idle,
1296 .gui_idle = &r600_gui_idle,
1297 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1298 .get_xclk = &rv770_get_xclk,
1299 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1301 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1302 .set_page = &rs600_gart_set_page,
1305 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1306 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1307 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1310 .set = &evergreen_irq_set,
1311 .process = &evergreen_irq_process,
1314 .bandwidth_update = &evergreen_bandwidth_update,
1315 .get_vblank_counter = &evergreen_get_vblank_counter,
1316 .wait_for_vblank = &dce4_wait_for_vblank,
1317 .set_backlight_level = &atombios_set_backlight_level,
1318 .get_backlight_level = &atombios_get_backlight_level,
1319 .hdmi_enable = &evergreen_hdmi_enable,
1320 .hdmi_setmode = &evergreen_hdmi_setmode,
1323 .blit = &r600_copy_cpdma,
1324 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1325 .dma = &evergreen_copy_dma,
1326 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1327 .copy = &evergreen_copy_dma,
1328 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1331 .set_reg = r600_set_surface_reg,
1332 .clear_reg = r600_clear_surface_reg,
1335 .init = &evergreen_hpd_init,
1336 .fini = &evergreen_hpd_fini,
1337 .sense = &evergreen_hpd_sense,
1338 .set_polarity = &evergreen_hpd_set_polarity,
1341 .misc = &evergreen_pm_misc,
1342 .prepare = &evergreen_pm_prepare,
1343 .finish = &evergreen_pm_finish,
1344 .init_profile = &r600_pm_init_profile,
1345 .get_dynpm_state = &r600_pm_get_dynpm_state,
1346 .get_engine_clock = &radeon_atom_get_engine_clock,
1347 .set_engine_clock = &radeon_atom_set_engine_clock,
1348 .get_memory_clock = &radeon_atom_get_memory_clock,
1349 .set_memory_clock = &radeon_atom_set_memory_clock,
1350 .get_pcie_lanes = &r600_get_pcie_lanes,
1351 .set_pcie_lanes = &r600_set_pcie_lanes,
1352 .set_clock_gating = NULL,
1353 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1354 .get_temperature = &evergreen_get_temp,
1357 .init = &cypress_dpm_init,
1358 .setup_asic = &cypress_dpm_setup_asic,
1359 .enable = &cypress_dpm_enable,
1360 .disable = &cypress_dpm_disable,
1361 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1362 .set_power_state = &cypress_dpm_set_power_state,
1363 .post_set_power_state = &r600_dpm_post_set_power_state,
1364 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1365 .fini = &cypress_dpm_fini,
1366 .get_sclk = &rv770_dpm_get_sclk,
1367 .get_mclk = &rv770_dpm_get_mclk,
1368 .print_power_state = &rv770_dpm_print_power_state,
1369 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1370 .force_performance_level = &rv770_dpm_force_performance_level,
1371 .vblank_too_short = &cypress_dpm_vblank_too_short,
1374 .pre_page_flip = &evergreen_pre_page_flip,
1375 .page_flip = &evergreen_page_flip,
1376 .post_page_flip = &evergreen_post_page_flip,
1380 static struct radeon_asic sumo_asic = {
1381 .init = &evergreen_init,
1382 .fini = &evergreen_fini,
1383 .suspend = &evergreen_suspend,
1384 .resume = &evergreen_resume,
1385 .asic_reset = &evergreen_asic_reset,
1386 .vga_set_state = &r600_vga_set_state,
1387 .ioctl_wait_idle = r600_ioctl_wait_idle,
1388 .gui_idle = &r600_gui_idle,
1389 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1390 .get_xclk = &r600_get_xclk,
1391 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1393 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1394 .set_page = &rs600_gart_set_page,
1397 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1398 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1399 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1402 .set = &evergreen_irq_set,
1403 .process = &evergreen_irq_process,
1406 .bandwidth_update = &evergreen_bandwidth_update,
1407 .get_vblank_counter = &evergreen_get_vblank_counter,
1408 .wait_for_vblank = &dce4_wait_for_vblank,
1409 .set_backlight_level = &atombios_set_backlight_level,
1410 .get_backlight_level = &atombios_get_backlight_level,
1411 .hdmi_enable = &evergreen_hdmi_enable,
1412 .hdmi_setmode = &evergreen_hdmi_setmode,
1415 .blit = &r600_copy_cpdma,
1416 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1417 .dma = &evergreen_copy_dma,
1418 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1419 .copy = &evergreen_copy_dma,
1420 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1423 .set_reg = r600_set_surface_reg,
1424 .clear_reg = r600_clear_surface_reg,
1427 .init = &evergreen_hpd_init,
1428 .fini = &evergreen_hpd_fini,
1429 .sense = &evergreen_hpd_sense,
1430 .set_polarity = &evergreen_hpd_set_polarity,
1433 .misc = &evergreen_pm_misc,
1434 .prepare = &evergreen_pm_prepare,
1435 .finish = &evergreen_pm_finish,
1436 .init_profile = &sumo_pm_init_profile,
1437 .get_dynpm_state = &r600_pm_get_dynpm_state,
1438 .get_engine_clock = &radeon_atom_get_engine_clock,
1439 .set_engine_clock = &radeon_atom_set_engine_clock,
1440 .get_memory_clock = NULL,
1441 .set_memory_clock = NULL,
1442 .get_pcie_lanes = NULL,
1443 .set_pcie_lanes = NULL,
1444 .set_clock_gating = NULL,
1445 .set_uvd_clocks = &sumo_set_uvd_clocks,
1446 .get_temperature = &sumo_get_temp,
1449 .init = &sumo_dpm_init,
1450 .setup_asic = &sumo_dpm_setup_asic,
1451 .enable = &sumo_dpm_enable,
1452 .disable = &sumo_dpm_disable,
1453 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1454 .set_power_state = &sumo_dpm_set_power_state,
1455 .post_set_power_state = &sumo_dpm_post_set_power_state,
1456 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1457 .fini = &sumo_dpm_fini,
1458 .get_sclk = &sumo_dpm_get_sclk,
1459 .get_mclk = &sumo_dpm_get_mclk,
1460 .print_power_state = &sumo_dpm_print_power_state,
1461 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1462 .force_performance_level = &sumo_dpm_force_performance_level,
1465 .pre_page_flip = &evergreen_pre_page_flip,
1466 .page_flip = &evergreen_page_flip,
1467 .post_page_flip = &evergreen_post_page_flip,
1471 static struct radeon_asic btc_asic = {
1472 .init = &evergreen_init,
1473 .fini = &evergreen_fini,
1474 .suspend = &evergreen_suspend,
1475 .resume = &evergreen_resume,
1476 .asic_reset = &evergreen_asic_reset,
1477 .vga_set_state = &r600_vga_set_state,
1478 .ioctl_wait_idle = r600_ioctl_wait_idle,
1479 .gui_idle = &r600_gui_idle,
1480 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1481 .get_xclk = &rv770_get_xclk,
1482 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1484 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1485 .set_page = &rs600_gart_set_page,
1488 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1489 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1490 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1493 .set = &evergreen_irq_set,
1494 .process = &evergreen_irq_process,
1497 .bandwidth_update = &evergreen_bandwidth_update,
1498 .get_vblank_counter = &evergreen_get_vblank_counter,
1499 .wait_for_vblank = &dce4_wait_for_vblank,
1500 .set_backlight_level = &atombios_set_backlight_level,
1501 .get_backlight_level = &atombios_get_backlight_level,
1502 .hdmi_enable = &evergreen_hdmi_enable,
1503 .hdmi_setmode = &evergreen_hdmi_setmode,
1506 .blit = &r600_copy_cpdma,
1507 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1508 .dma = &evergreen_copy_dma,
1509 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1510 .copy = &evergreen_copy_dma,
1511 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1514 .set_reg = r600_set_surface_reg,
1515 .clear_reg = r600_clear_surface_reg,
1518 .init = &evergreen_hpd_init,
1519 .fini = &evergreen_hpd_fini,
1520 .sense = &evergreen_hpd_sense,
1521 .set_polarity = &evergreen_hpd_set_polarity,
1524 .misc = &evergreen_pm_misc,
1525 .prepare = &evergreen_pm_prepare,
1526 .finish = &evergreen_pm_finish,
1527 .init_profile = &btc_pm_init_profile,
1528 .get_dynpm_state = &r600_pm_get_dynpm_state,
1529 .get_engine_clock = &radeon_atom_get_engine_clock,
1530 .set_engine_clock = &radeon_atom_set_engine_clock,
1531 .get_memory_clock = &radeon_atom_get_memory_clock,
1532 .set_memory_clock = &radeon_atom_set_memory_clock,
1533 .get_pcie_lanes = &r600_get_pcie_lanes,
1534 .set_pcie_lanes = &r600_set_pcie_lanes,
1535 .set_clock_gating = NULL,
1536 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1537 .get_temperature = &evergreen_get_temp,
1540 .init = &btc_dpm_init,
1541 .setup_asic = &btc_dpm_setup_asic,
1542 .enable = &btc_dpm_enable,
1543 .disable = &btc_dpm_disable,
1544 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1545 .set_power_state = &btc_dpm_set_power_state,
1546 .post_set_power_state = &btc_dpm_post_set_power_state,
1547 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1548 .fini = &btc_dpm_fini,
1549 .get_sclk = &btc_dpm_get_sclk,
1550 .get_mclk = &btc_dpm_get_mclk,
1551 .print_power_state = &rv770_dpm_print_power_state,
1552 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1553 .force_performance_level = &rv770_dpm_force_performance_level,
1554 .vblank_too_short = &btc_dpm_vblank_too_short,
1557 .pre_page_flip = &evergreen_pre_page_flip,
1558 .page_flip = &evergreen_page_flip,
1559 .post_page_flip = &evergreen_post_page_flip,
1563 static struct radeon_asic_ring cayman_gfx_ring = {
1564 .ib_execute = &cayman_ring_ib_execute,
1565 .ib_parse = &evergreen_ib_parse,
1566 .emit_fence = &cayman_fence_ring_emit,
1567 .emit_semaphore = &r600_semaphore_ring_emit,
1568 .cs_parse = &evergreen_cs_parse,
1569 .ring_test = &r600_ring_test,
1570 .ib_test = &r600_ib_test,
1571 .is_lockup = &cayman_gfx_is_lockup,
1572 .vm_flush = &cayman_vm_flush,
1573 .get_rptr = &radeon_ring_generic_get_rptr,
1574 .get_wptr = &radeon_ring_generic_get_wptr,
1575 .set_wptr = &radeon_ring_generic_set_wptr,
1578 static struct radeon_asic_ring cayman_dma_ring = {
1579 .ib_execute = &cayman_dma_ring_ib_execute,
1580 .ib_parse = &evergreen_dma_ib_parse,
1581 .emit_fence = &evergreen_dma_fence_ring_emit,
1582 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1583 .cs_parse = &evergreen_dma_cs_parse,
1584 .ring_test = &r600_dma_ring_test,
1585 .ib_test = &r600_dma_ib_test,
1586 .is_lockup = &cayman_dma_is_lockup,
1587 .vm_flush = &cayman_dma_vm_flush,
1588 .get_rptr = &r600_dma_get_rptr,
1589 .get_wptr = &r600_dma_get_wptr,
1590 .set_wptr = &r600_dma_set_wptr
1593 static struct radeon_asic_ring cayman_uvd_ring = {
1594 .ib_execute = &uvd_v1_0_ib_execute,
1595 .emit_fence = &uvd_v2_2_fence_emit,
1596 .emit_semaphore = &uvd_v3_1_semaphore_emit,
1597 .cs_parse = &radeon_uvd_cs_parse,
1598 .ring_test = &uvd_v1_0_ring_test,
1599 .ib_test = &uvd_v1_0_ib_test,
1600 .is_lockup = &radeon_ring_test_lockup,
1601 .get_rptr = &uvd_v1_0_get_rptr,
1602 .get_wptr = &uvd_v1_0_get_wptr,
1603 .set_wptr = &uvd_v1_0_set_wptr,
1606 static struct radeon_asic cayman_asic = {
1607 .init = &cayman_init,
1608 .fini = &cayman_fini,
1609 .suspend = &cayman_suspend,
1610 .resume = &cayman_resume,
1611 .asic_reset = &cayman_asic_reset,
1612 .vga_set_state = &r600_vga_set_state,
1613 .ioctl_wait_idle = r600_ioctl_wait_idle,
1614 .gui_idle = &r600_gui_idle,
1615 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1616 .get_xclk = &rv770_get_xclk,
1617 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1619 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1620 .set_page = &rs600_gart_set_page,
1623 .init = &cayman_vm_init,
1624 .fini = &cayman_vm_fini,
1625 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1626 .set_page = &cayman_vm_set_page,
1629 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1630 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1631 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1632 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1633 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1634 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1637 .set = &evergreen_irq_set,
1638 .process = &evergreen_irq_process,
1641 .bandwidth_update = &evergreen_bandwidth_update,
1642 .get_vblank_counter = &evergreen_get_vblank_counter,
1643 .wait_for_vblank = &dce4_wait_for_vblank,
1644 .set_backlight_level = &atombios_set_backlight_level,
1645 .get_backlight_level = &atombios_get_backlight_level,
1646 .hdmi_enable = &evergreen_hdmi_enable,
1647 .hdmi_setmode = &evergreen_hdmi_setmode,
1650 .blit = &r600_copy_cpdma,
1651 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1652 .dma = &evergreen_copy_dma,
1653 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1654 .copy = &evergreen_copy_dma,
1655 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1658 .set_reg = r600_set_surface_reg,
1659 .clear_reg = r600_clear_surface_reg,
1662 .init = &evergreen_hpd_init,
1663 .fini = &evergreen_hpd_fini,
1664 .sense = &evergreen_hpd_sense,
1665 .set_polarity = &evergreen_hpd_set_polarity,
1668 .misc = &evergreen_pm_misc,
1669 .prepare = &evergreen_pm_prepare,
1670 .finish = &evergreen_pm_finish,
1671 .init_profile = &btc_pm_init_profile,
1672 .get_dynpm_state = &r600_pm_get_dynpm_state,
1673 .get_engine_clock = &radeon_atom_get_engine_clock,
1674 .set_engine_clock = &radeon_atom_set_engine_clock,
1675 .get_memory_clock = &radeon_atom_get_memory_clock,
1676 .set_memory_clock = &radeon_atom_set_memory_clock,
1677 .get_pcie_lanes = &r600_get_pcie_lanes,
1678 .set_pcie_lanes = &r600_set_pcie_lanes,
1679 .set_clock_gating = NULL,
1680 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1681 .get_temperature = &evergreen_get_temp,
1684 .init = &ni_dpm_init,
1685 .setup_asic = &ni_dpm_setup_asic,
1686 .enable = &ni_dpm_enable,
1687 .disable = &ni_dpm_disable,
1688 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1689 .set_power_state = &ni_dpm_set_power_state,
1690 .post_set_power_state = &ni_dpm_post_set_power_state,
1691 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1692 .fini = &ni_dpm_fini,
1693 .get_sclk = &ni_dpm_get_sclk,
1694 .get_mclk = &ni_dpm_get_mclk,
1695 .print_power_state = &ni_dpm_print_power_state,
1696 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1697 .force_performance_level = &ni_dpm_force_performance_level,
1698 .vblank_too_short = &ni_dpm_vblank_too_short,
1701 .pre_page_flip = &evergreen_pre_page_flip,
1702 .page_flip = &evergreen_page_flip,
1703 .post_page_flip = &evergreen_post_page_flip,
1707 static struct radeon_asic trinity_asic = {
1708 .init = &cayman_init,
1709 .fini = &cayman_fini,
1710 .suspend = &cayman_suspend,
1711 .resume = &cayman_resume,
1712 .asic_reset = &cayman_asic_reset,
1713 .vga_set_state = &r600_vga_set_state,
1714 .ioctl_wait_idle = r600_ioctl_wait_idle,
1715 .gui_idle = &r600_gui_idle,
1716 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1717 .get_xclk = &r600_get_xclk,
1718 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1720 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1721 .set_page = &rs600_gart_set_page,
1724 .init = &cayman_vm_init,
1725 .fini = &cayman_vm_fini,
1726 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1727 .set_page = &cayman_vm_set_page,
1730 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1731 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1732 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1733 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1734 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1735 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1738 .set = &evergreen_irq_set,
1739 .process = &evergreen_irq_process,
1742 .bandwidth_update = &dce6_bandwidth_update,
1743 .get_vblank_counter = &evergreen_get_vblank_counter,
1744 .wait_for_vblank = &dce4_wait_for_vblank,
1745 .set_backlight_level = &atombios_set_backlight_level,
1746 .get_backlight_level = &atombios_get_backlight_level,
1747 .hdmi_enable = &evergreen_hdmi_enable,
1748 .hdmi_setmode = &evergreen_hdmi_setmode,
1751 .blit = &r600_copy_cpdma,
1752 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1753 .dma = &evergreen_copy_dma,
1754 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1755 .copy = &evergreen_copy_dma,
1756 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1759 .set_reg = r600_set_surface_reg,
1760 .clear_reg = r600_clear_surface_reg,
1763 .init = &evergreen_hpd_init,
1764 .fini = &evergreen_hpd_fini,
1765 .sense = &evergreen_hpd_sense,
1766 .set_polarity = &evergreen_hpd_set_polarity,
1769 .misc = &evergreen_pm_misc,
1770 .prepare = &evergreen_pm_prepare,
1771 .finish = &evergreen_pm_finish,
1772 .init_profile = &sumo_pm_init_profile,
1773 .get_dynpm_state = &r600_pm_get_dynpm_state,
1774 .get_engine_clock = &radeon_atom_get_engine_clock,
1775 .set_engine_clock = &radeon_atom_set_engine_clock,
1776 .get_memory_clock = NULL,
1777 .set_memory_clock = NULL,
1778 .get_pcie_lanes = NULL,
1779 .set_pcie_lanes = NULL,
1780 .set_clock_gating = NULL,
1781 .set_uvd_clocks = &sumo_set_uvd_clocks,
1782 .get_temperature = &tn_get_temp,
1785 .init = &trinity_dpm_init,
1786 .setup_asic = &trinity_dpm_setup_asic,
1787 .enable = &trinity_dpm_enable,
1788 .disable = &trinity_dpm_disable,
1789 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
1790 .set_power_state = &trinity_dpm_set_power_state,
1791 .post_set_power_state = &trinity_dpm_post_set_power_state,
1792 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1793 .fini = &trinity_dpm_fini,
1794 .get_sclk = &trinity_dpm_get_sclk,
1795 .get_mclk = &trinity_dpm_get_mclk,
1796 .print_power_state = &trinity_dpm_print_power_state,
1797 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1798 .force_performance_level = &trinity_dpm_force_performance_level,
1799 .enable_bapm = &trinity_dpm_enable_bapm,
1802 .pre_page_flip = &evergreen_pre_page_flip,
1803 .page_flip = &evergreen_page_flip,
1804 .post_page_flip = &evergreen_post_page_flip,
1808 static struct radeon_asic_ring si_gfx_ring = {
1809 .ib_execute = &si_ring_ib_execute,
1810 .ib_parse = &si_ib_parse,
1811 .emit_fence = &si_fence_ring_emit,
1812 .emit_semaphore = &r600_semaphore_ring_emit,
1814 .ring_test = &r600_ring_test,
1815 .ib_test = &r600_ib_test,
1816 .is_lockup = &si_gfx_is_lockup,
1817 .vm_flush = &si_vm_flush,
1818 .get_rptr = &radeon_ring_generic_get_rptr,
1819 .get_wptr = &radeon_ring_generic_get_wptr,
1820 .set_wptr = &radeon_ring_generic_set_wptr,
1823 static struct radeon_asic_ring si_dma_ring = {
1824 .ib_execute = &cayman_dma_ring_ib_execute,
1825 .ib_parse = &evergreen_dma_ib_parse,
1826 .emit_fence = &evergreen_dma_fence_ring_emit,
1827 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1829 .ring_test = &r600_dma_ring_test,
1830 .ib_test = &r600_dma_ib_test,
1831 .is_lockup = &si_dma_is_lockup,
1832 .vm_flush = &si_dma_vm_flush,
1833 .get_rptr = &r600_dma_get_rptr,
1834 .get_wptr = &r600_dma_get_wptr,
1835 .set_wptr = &r600_dma_set_wptr,
1838 static struct radeon_asic si_asic = {
1841 .suspend = &si_suspend,
1842 .resume = &si_resume,
1843 .asic_reset = &si_asic_reset,
1844 .vga_set_state = &r600_vga_set_state,
1845 .ioctl_wait_idle = r600_ioctl_wait_idle,
1846 .gui_idle = &r600_gui_idle,
1847 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1848 .get_xclk = &si_get_xclk,
1849 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1851 .tlb_flush = &si_pcie_gart_tlb_flush,
1852 .set_page = &rs600_gart_set_page,
1855 .init = &si_vm_init,
1856 .fini = &si_vm_fini,
1857 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1858 .set_page = &si_vm_set_page,
1861 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1862 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1863 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1864 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1865 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1866 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1870 .process = &si_irq_process,
1873 .bandwidth_update = &dce6_bandwidth_update,
1874 .get_vblank_counter = &evergreen_get_vblank_counter,
1875 .wait_for_vblank = &dce4_wait_for_vblank,
1876 .set_backlight_level = &atombios_set_backlight_level,
1877 .get_backlight_level = &atombios_get_backlight_level,
1878 .hdmi_enable = &evergreen_hdmi_enable,
1879 .hdmi_setmode = &evergreen_hdmi_setmode,
1883 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1884 .dma = &si_copy_dma,
1885 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1886 .copy = &si_copy_dma,
1887 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1890 .set_reg = r600_set_surface_reg,
1891 .clear_reg = r600_clear_surface_reg,
1894 .init = &evergreen_hpd_init,
1895 .fini = &evergreen_hpd_fini,
1896 .sense = &evergreen_hpd_sense,
1897 .set_polarity = &evergreen_hpd_set_polarity,
1900 .misc = &evergreen_pm_misc,
1901 .prepare = &evergreen_pm_prepare,
1902 .finish = &evergreen_pm_finish,
1903 .init_profile = &sumo_pm_init_profile,
1904 .get_dynpm_state = &r600_pm_get_dynpm_state,
1905 .get_engine_clock = &radeon_atom_get_engine_clock,
1906 .set_engine_clock = &radeon_atom_set_engine_clock,
1907 .get_memory_clock = &radeon_atom_get_memory_clock,
1908 .set_memory_clock = &radeon_atom_set_memory_clock,
1909 .get_pcie_lanes = &r600_get_pcie_lanes,
1910 .set_pcie_lanes = &r600_set_pcie_lanes,
1911 .set_clock_gating = NULL,
1912 .set_uvd_clocks = &si_set_uvd_clocks,
1913 .get_temperature = &si_get_temp,
1916 .init = &si_dpm_init,
1917 .setup_asic = &si_dpm_setup_asic,
1918 .enable = &si_dpm_enable,
1919 .disable = &si_dpm_disable,
1920 .pre_set_power_state = &si_dpm_pre_set_power_state,
1921 .set_power_state = &si_dpm_set_power_state,
1922 .post_set_power_state = &si_dpm_post_set_power_state,
1923 .display_configuration_changed = &si_dpm_display_configuration_changed,
1924 .fini = &si_dpm_fini,
1925 .get_sclk = &ni_dpm_get_sclk,
1926 .get_mclk = &ni_dpm_get_mclk,
1927 .print_power_state = &ni_dpm_print_power_state,
1928 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
1929 .force_performance_level = &si_dpm_force_performance_level,
1930 .vblank_too_short = &ni_dpm_vblank_too_short,
1933 .pre_page_flip = &evergreen_pre_page_flip,
1934 .page_flip = &evergreen_page_flip,
1935 .post_page_flip = &evergreen_post_page_flip,
1939 static struct radeon_asic_ring ci_gfx_ring = {
1940 .ib_execute = &cik_ring_ib_execute,
1941 .ib_parse = &cik_ib_parse,
1942 .emit_fence = &cik_fence_gfx_ring_emit,
1943 .emit_semaphore = &cik_semaphore_ring_emit,
1945 .ring_test = &cik_ring_test,
1946 .ib_test = &cik_ib_test,
1947 .is_lockup = &cik_gfx_is_lockup,
1948 .vm_flush = &cik_vm_flush,
1949 .get_rptr = &radeon_ring_generic_get_rptr,
1950 .get_wptr = &radeon_ring_generic_get_wptr,
1951 .set_wptr = &radeon_ring_generic_set_wptr,
1954 static struct radeon_asic_ring ci_cp_ring = {
1955 .ib_execute = &cik_ring_ib_execute,
1956 .ib_parse = &cik_ib_parse,
1957 .emit_fence = &cik_fence_compute_ring_emit,
1958 .emit_semaphore = &cik_semaphore_ring_emit,
1960 .ring_test = &cik_ring_test,
1961 .ib_test = &cik_ib_test,
1962 .is_lockup = &cik_gfx_is_lockup,
1963 .vm_flush = &cik_vm_flush,
1964 .get_rptr = &cik_compute_ring_get_rptr,
1965 .get_wptr = &cik_compute_ring_get_wptr,
1966 .set_wptr = &cik_compute_ring_set_wptr,
1969 static struct radeon_asic_ring ci_dma_ring = {
1970 .ib_execute = &cik_sdma_ring_ib_execute,
1971 .ib_parse = &cik_ib_parse,
1972 .emit_fence = &cik_sdma_fence_ring_emit,
1973 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
1975 .ring_test = &cik_sdma_ring_test,
1976 .ib_test = &cik_sdma_ib_test,
1977 .is_lockup = &cik_sdma_is_lockup,
1978 .vm_flush = &cik_dma_vm_flush,
1979 .get_rptr = &r600_dma_get_rptr,
1980 .get_wptr = &r600_dma_get_wptr,
1981 .set_wptr = &r600_dma_set_wptr,
1984 static struct radeon_asic ci_asic = {
1987 .suspend = &cik_suspend,
1988 .resume = &cik_resume,
1989 .asic_reset = &cik_asic_reset,
1990 .vga_set_state = &r600_vga_set_state,
1991 .ioctl_wait_idle = NULL,
1992 .gui_idle = &r600_gui_idle,
1993 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1994 .get_xclk = &cik_get_xclk,
1995 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
1997 .tlb_flush = &cik_pcie_gart_tlb_flush,
1998 .set_page = &rs600_gart_set_page,
2001 .init = &cik_vm_init,
2002 .fini = &cik_vm_fini,
2003 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2004 .set_page = &cik_vm_set_page,
2007 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2008 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2009 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2010 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2011 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2012 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2015 .set = &cik_irq_set,
2016 .process = &cik_irq_process,
2019 .bandwidth_update = &dce8_bandwidth_update,
2020 .get_vblank_counter = &evergreen_get_vblank_counter,
2021 .wait_for_vblank = &dce4_wait_for_vblank,
2022 .hdmi_enable = &evergreen_hdmi_enable,
2023 .hdmi_setmode = &evergreen_hdmi_setmode,
2027 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2028 .dma = &cik_copy_dma,
2029 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2030 .copy = &cik_copy_dma,
2031 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2034 .set_reg = r600_set_surface_reg,
2035 .clear_reg = r600_clear_surface_reg,
2038 .init = &evergreen_hpd_init,
2039 .fini = &evergreen_hpd_fini,
2040 .sense = &evergreen_hpd_sense,
2041 .set_polarity = &evergreen_hpd_set_polarity,
2044 .misc = &evergreen_pm_misc,
2045 .prepare = &evergreen_pm_prepare,
2046 .finish = &evergreen_pm_finish,
2047 .init_profile = &sumo_pm_init_profile,
2048 .get_dynpm_state = &r600_pm_get_dynpm_state,
2049 .get_engine_clock = &radeon_atom_get_engine_clock,
2050 .set_engine_clock = &radeon_atom_set_engine_clock,
2051 .get_memory_clock = &radeon_atom_get_memory_clock,
2052 .set_memory_clock = &radeon_atom_set_memory_clock,
2053 .get_pcie_lanes = NULL,
2054 .set_pcie_lanes = NULL,
2055 .set_clock_gating = NULL,
2056 .set_uvd_clocks = &cik_set_uvd_clocks,
2057 .get_temperature = &ci_get_temp,
2060 .init = &ci_dpm_init,
2061 .setup_asic = &ci_dpm_setup_asic,
2062 .enable = &ci_dpm_enable,
2063 .disable = &ci_dpm_disable,
2064 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2065 .set_power_state = &ci_dpm_set_power_state,
2066 .post_set_power_state = &ci_dpm_post_set_power_state,
2067 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2068 .fini = &ci_dpm_fini,
2069 .get_sclk = &ci_dpm_get_sclk,
2070 .get_mclk = &ci_dpm_get_mclk,
2071 .print_power_state = &ci_dpm_print_power_state,
2072 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2073 .force_performance_level = &ci_dpm_force_performance_level,
2074 .vblank_too_short = &ci_dpm_vblank_too_short,
2075 .powergate_uvd = &ci_dpm_powergate_uvd,
2078 .pre_page_flip = &evergreen_pre_page_flip,
2079 .page_flip = &evergreen_page_flip,
2080 .post_page_flip = &evergreen_post_page_flip,
2084 static struct radeon_asic kv_asic = {
2087 .suspend = &cik_suspend,
2088 .resume = &cik_resume,
2089 .asic_reset = &cik_asic_reset,
2090 .vga_set_state = &r600_vga_set_state,
2091 .ioctl_wait_idle = NULL,
2092 .gui_idle = &r600_gui_idle,
2093 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2094 .get_xclk = &cik_get_xclk,
2095 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2097 .tlb_flush = &cik_pcie_gart_tlb_flush,
2098 .set_page = &rs600_gart_set_page,
2101 .init = &cik_vm_init,
2102 .fini = &cik_vm_fini,
2103 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2104 .set_page = &cik_vm_set_page,
2107 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2108 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2109 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2110 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2111 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2112 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2115 .set = &cik_irq_set,
2116 .process = &cik_irq_process,
2119 .bandwidth_update = &dce8_bandwidth_update,
2120 .get_vblank_counter = &evergreen_get_vblank_counter,
2121 .wait_for_vblank = &dce4_wait_for_vblank,
2122 .hdmi_enable = &evergreen_hdmi_enable,
2123 .hdmi_setmode = &evergreen_hdmi_setmode,
2127 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2128 .dma = &cik_copy_dma,
2129 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2130 .copy = &cik_copy_dma,
2131 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2134 .set_reg = r600_set_surface_reg,
2135 .clear_reg = r600_clear_surface_reg,
2138 .init = &evergreen_hpd_init,
2139 .fini = &evergreen_hpd_fini,
2140 .sense = &evergreen_hpd_sense,
2141 .set_polarity = &evergreen_hpd_set_polarity,
2144 .misc = &evergreen_pm_misc,
2145 .prepare = &evergreen_pm_prepare,
2146 .finish = &evergreen_pm_finish,
2147 .init_profile = &sumo_pm_init_profile,
2148 .get_dynpm_state = &r600_pm_get_dynpm_state,
2149 .get_engine_clock = &radeon_atom_get_engine_clock,
2150 .set_engine_clock = &radeon_atom_set_engine_clock,
2151 .get_memory_clock = &radeon_atom_get_memory_clock,
2152 .set_memory_clock = &radeon_atom_set_memory_clock,
2153 .get_pcie_lanes = NULL,
2154 .set_pcie_lanes = NULL,
2155 .set_clock_gating = NULL,
2156 .set_uvd_clocks = &cik_set_uvd_clocks,
2157 .get_temperature = &kv_get_temp,
2160 .init = &kv_dpm_init,
2161 .setup_asic = &kv_dpm_setup_asic,
2162 .enable = &kv_dpm_enable,
2163 .disable = &kv_dpm_disable,
2164 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2165 .set_power_state = &kv_dpm_set_power_state,
2166 .post_set_power_state = &kv_dpm_post_set_power_state,
2167 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2168 .fini = &kv_dpm_fini,
2169 .get_sclk = &kv_dpm_get_sclk,
2170 .get_mclk = &kv_dpm_get_mclk,
2171 .print_power_state = &kv_dpm_print_power_state,
2172 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2173 .force_performance_level = &kv_dpm_force_performance_level,
2174 .powergate_uvd = &kv_dpm_powergate_uvd,
2175 .enable_bapm = &kv_dpm_enable_bapm,
2178 .pre_page_flip = &evergreen_pre_page_flip,
2179 .page_flip = &evergreen_page_flip,
2180 .post_page_flip = &evergreen_post_page_flip,
2185 * radeon_asic_init - register asic specific callbacks
2187 * @rdev: radeon device pointer
2189 * Registers the appropriate asic specific callbacks for each
2190 * chip family. Also sets other asics specific info like the number
2191 * of crtcs and the register aperture accessors (all asics).
2192 * Returns 0 for success.
2194 int radeon_asic_init(struct radeon_device *rdev)
2196 radeon_register_accessor_init(rdev);
2198 /* set the number of crtcs */
2199 if (rdev->flags & RADEON_SINGLE_CRTC)
2204 rdev->has_uvd = false;
2206 switch (rdev->family) {
2212 rdev->asic = &r100_asic;
2218 rdev->asic = &r200_asic;
2224 if (rdev->flags & RADEON_IS_PCIE)
2225 rdev->asic = &r300_asic_pcie;
2227 rdev->asic = &r300_asic;
2232 rdev->asic = &r420_asic;
2234 if (rdev->bios == NULL) {
2235 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2236 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2237 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2238 rdev->asic->pm.set_memory_clock = NULL;
2239 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2244 rdev->asic = &rs400_asic;
2247 rdev->asic = &rs600_asic;
2251 rdev->asic = &rs690_asic;
2254 rdev->asic = &rv515_asic;
2261 rdev->asic = &r520_asic;
2264 rdev->asic = &r600_asic;
2271 rdev->asic = &rv6xx_asic;
2272 rdev->has_uvd = true;
2276 rdev->asic = &rs780_asic;
2277 rdev->has_uvd = true;
2283 rdev->asic = &rv770_asic;
2284 rdev->has_uvd = true;
2292 if (rdev->family == CHIP_CEDAR)
2296 rdev->asic = &evergreen_asic;
2297 rdev->has_uvd = true;
2302 rdev->asic = &sumo_asic;
2303 rdev->has_uvd = true;
2309 if (rdev->family == CHIP_CAICOS)
2313 rdev->asic = &btc_asic;
2314 rdev->has_uvd = true;
2317 rdev->asic = &cayman_asic;
2320 rdev->has_uvd = true;
2323 rdev->asic = &trinity_asic;
2326 rdev->has_uvd = true;
2333 rdev->asic = &si_asic;
2335 if (rdev->family == CHIP_HAINAN)
2337 else if (rdev->family == CHIP_OLAND)
2341 if (rdev->family == CHIP_HAINAN)
2342 rdev->has_uvd = false;
2344 rdev->has_uvd = true;
2345 switch (rdev->family) {
2348 RADEON_CG_SUPPORT_GFX_MGCG |
2349 RADEON_CG_SUPPORT_GFX_MGLS |
2350 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2351 RADEON_CG_SUPPORT_GFX_CGLS |
2352 RADEON_CG_SUPPORT_GFX_CGTS |
2353 RADEON_CG_SUPPORT_GFX_CP_LS |
2354 RADEON_CG_SUPPORT_MC_MGCG |
2355 RADEON_CG_SUPPORT_SDMA_MGCG |
2356 RADEON_CG_SUPPORT_BIF_LS |
2357 RADEON_CG_SUPPORT_VCE_MGCG |
2358 RADEON_CG_SUPPORT_UVD_MGCG |
2359 RADEON_CG_SUPPORT_HDP_LS |
2360 RADEON_CG_SUPPORT_HDP_MGCG;
2365 RADEON_CG_SUPPORT_GFX_MGCG |
2366 RADEON_CG_SUPPORT_GFX_MGLS |
2367 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2368 RADEON_CG_SUPPORT_GFX_CGLS |
2369 RADEON_CG_SUPPORT_GFX_CGTS |
2370 RADEON_CG_SUPPORT_GFX_CP_LS |
2371 RADEON_CG_SUPPORT_GFX_RLC_LS |
2372 RADEON_CG_SUPPORT_MC_LS |
2373 RADEON_CG_SUPPORT_MC_MGCG |
2374 RADEON_CG_SUPPORT_SDMA_MGCG |
2375 RADEON_CG_SUPPORT_BIF_LS |
2376 RADEON_CG_SUPPORT_VCE_MGCG |
2377 RADEON_CG_SUPPORT_UVD_MGCG |
2378 RADEON_CG_SUPPORT_HDP_LS |
2379 RADEON_CG_SUPPORT_HDP_MGCG;
2384 RADEON_CG_SUPPORT_GFX_MGCG |
2385 RADEON_CG_SUPPORT_GFX_MGLS |
2386 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2387 RADEON_CG_SUPPORT_GFX_CGLS |
2388 RADEON_CG_SUPPORT_GFX_CGTS |
2389 RADEON_CG_SUPPORT_GFX_CP_LS |
2390 RADEON_CG_SUPPORT_GFX_RLC_LS |
2391 RADEON_CG_SUPPORT_MC_LS |
2392 RADEON_CG_SUPPORT_MC_MGCG |
2393 RADEON_CG_SUPPORT_SDMA_MGCG |
2394 RADEON_CG_SUPPORT_BIF_LS |
2395 RADEON_CG_SUPPORT_VCE_MGCG |
2396 RADEON_CG_SUPPORT_UVD_MGCG |
2397 RADEON_CG_SUPPORT_HDP_LS |
2398 RADEON_CG_SUPPORT_HDP_MGCG;
2399 rdev->pg_flags = 0 |
2400 /*RADEON_PG_SUPPORT_GFX_PG | */
2401 RADEON_PG_SUPPORT_SDMA;
2405 RADEON_CG_SUPPORT_GFX_MGCG |
2406 RADEON_CG_SUPPORT_GFX_MGLS |
2407 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2408 RADEON_CG_SUPPORT_GFX_CGLS |
2409 RADEON_CG_SUPPORT_GFX_CGTS |
2410 RADEON_CG_SUPPORT_GFX_CP_LS |
2411 RADEON_CG_SUPPORT_GFX_RLC_LS |
2412 RADEON_CG_SUPPORT_MC_LS |
2413 RADEON_CG_SUPPORT_MC_MGCG |
2414 RADEON_CG_SUPPORT_SDMA_MGCG |
2415 RADEON_CG_SUPPORT_BIF_LS |
2416 RADEON_CG_SUPPORT_UVD_MGCG |
2417 RADEON_CG_SUPPORT_HDP_LS |
2418 RADEON_CG_SUPPORT_HDP_MGCG;
2423 RADEON_CG_SUPPORT_GFX_MGCG |
2424 RADEON_CG_SUPPORT_GFX_MGLS |
2425 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2426 RADEON_CG_SUPPORT_GFX_CGLS |
2427 RADEON_CG_SUPPORT_GFX_CGTS |
2428 RADEON_CG_SUPPORT_GFX_CP_LS |
2429 RADEON_CG_SUPPORT_GFX_RLC_LS |
2430 RADEON_CG_SUPPORT_MC_LS |
2431 RADEON_CG_SUPPORT_MC_MGCG |
2432 RADEON_CG_SUPPORT_SDMA_MGCG |
2433 RADEON_CG_SUPPORT_BIF_LS |
2434 RADEON_CG_SUPPORT_HDP_LS |
2435 RADEON_CG_SUPPORT_HDP_MGCG;
2445 rdev->asic = &ci_asic;
2447 rdev->has_uvd = true;
2449 RADEON_CG_SUPPORT_GFX_MGCG |
2450 RADEON_CG_SUPPORT_GFX_MGLS |
2451 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2452 RADEON_CG_SUPPORT_GFX_CGLS |
2453 RADEON_CG_SUPPORT_GFX_CGTS |
2454 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2455 RADEON_CG_SUPPORT_GFX_CP_LS |
2456 RADEON_CG_SUPPORT_MC_LS |
2457 RADEON_CG_SUPPORT_MC_MGCG |
2458 RADEON_CG_SUPPORT_SDMA_MGCG |
2459 RADEON_CG_SUPPORT_SDMA_LS |
2460 RADEON_CG_SUPPORT_BIF_LS |
2461 RADEON_CG_SUPPORT_VCE_MGCG |
2462 RADEON_CG_SUPPORT_UVD_MGCG |
2463 RADEON_CG_SUPPORT_HDP_LS |
2464 RADEON_CG_SUPPORT_HDP_MGCG;
2469 rdev->asic = &kv_asic;
2471 if (rdev->family == CHIP_KAVERI) {
2474 RADEON_CG_SUPPORT_GFX_MGCG |
2475 RADEON_CG_SUPPORT_GFX_MGLS |
2476 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2477 RADEON_CG_SUPPORT_GFX_CGLS |
2478 RADEON_CG_SUPPORT_GFX_CGTS |
2479 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2480 RADEON_CG_SUPPORT_GFX_CP_LS |
2481 RADEON_CG_SUPPORT_SDMA_MGCG |
2482 RADEON_CG_SUPPORT_SDMA_LS |
2483 RADEON_CG_SUPPORT_BIF_LS |
2484 RADEON_CG_SUPPORT_VCE_MGCG |
2485 RADEON_CG_SUPPORT_UVD_MGCG |
2486 RADEON_CG_SUPPORT_HDP_LS |
2487 RADEON_CG_SUPPORT_HDP_MGCG;
2489 /*RADEON_PG_SUPPORT_GFX_PG |
2490 RADEON_PG_SUPPORT_GFX_SMG |
2491 RADEON_PG_SUPPORT_GFX_DMG |
2492 RADEON_PG_SUPPORT_UVD |
2493 RADEON_PG_SUPPORT_VCE |
2494 RADEON_PG_SUPPORT_CP |
2495 RADEON_PG_SUPPORT_GDS |
2496 RADEON_PG_SUPPORT_RLC_SMU_HS |
2497 RADEON_PG_SUPPORT_ACP |
2498 RADEON_PG_SUPPORT_SAMU;*/
2502 RADEON_CG_SUPPORT_GFX_MGCG |
2503 RADEON_CG_SUPPORT_GFX_MGLS |
2504 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2505 RADEON_CG_SUPPORT_GFX_CGLS |
2506 RADEON_CG_SUPPORT_GFX_CGTS |
2507 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2508 RADEON_CG_SUPPORT_GFX_CP_LS |
2509 RADEON_CG_SUPPORT_SDMA_MGCG |
2510 RADEON_CG_SUPPORT_SDMA_LS |
2511 RADEON_CG_SUPPORT_BIF_LS |
2512 RADEON_CG_SUPPORT_VCE_MGCG |
2513 RADEON_CG_SUPPORT_UVD_MGCG |
2514 RADEON_CG_SUPPORT_HDP_LS |
2515 RADEON_CG_SUPPORT_HDP_MGCG;
2517 /*RADEON_PG_SUPPORT_GFX_PG |
2518 RADEON_PG_SUPPORT_GFX_SMG |
2519 RADEON_PG_SUPPORT_UVD |
2520 RADEON_PG_SUPPORT_VCE |
2521 RADEON_PG_SUPPORT_CP |
2522 RADEON_PG_SUPPORT_GDS |
2523 RADEON_PG_SUPPORT_RLC_SMU_HS |
2524 RADEON_PG_SUPPORT_SAMU;*/
2526 rdev->has_uvd = true;
2529 /* FIXME: not supported yet */
2533 if (rdev->flags & RADEON_IS_IGP) {
2534 rdev->asic->pm.get_memory_clock = NULL;
2535 rdev->asic->pm.set_memory_clock = NULL;