2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
101 * Copy from radeon_drv.h so we don't have to include both and have conflicting
104 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
105 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
106 /* RADEON_IB_POOL_SIZE must be a power of 2 */
107 #define RADEON_IB_POOL_SIZE 16
108 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
109 #define RADEONFB_CONN_LIMIT 4
110 #define RADEON_BIOS_NUM_SCRATCH 8
112 /* max number of rings */
113 #define RADEON_NUM_RINGS 6
115 /* fence seq are set to this number when signaled */
116 #define RADEON_FENCE_SIGNALED_SEQ 0LL
118 /* internal ring indices */
119 /* r1xx+ has gfx CP ring */
120 #define RADEON_RING_TYPE_GFX_INDEX 0
122 /* cayman has 2 compute CP rings */
123 #define CAYMAN_RING_TYPE_CP1_INDEX 1
124 #define CAYMAN_RING_TYPE_CP2_INDEX 2
126 /* R600+ has an async dma ring */
127 #define R600_RING_TYPE_DMA_INDEX 3
128 /* cayman add a second async dma ring */
129 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
132 #define R600_RING_TYPE_UVD_INDEX 5
134 /* hardcode those limit for now */
135 #define RADEON_VA_IB_OFFSET (1 << 20)
136 #define RADEON_VA_RESERVED_SIZE (8 << 20)
137 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
140 #define RADEON_RESET_GFX (1 << 0)
141 #define RADEON_RESET_COMPUTE (1 << 1)
142 #define RADEON_RESET_DMA (1 << 2)
143 #define RADEON_RESET_CP (1 << 3)
144 #define RADEON_RESET_GRBM (1 << 4)
145 #define RADEON_RESET_DMA1 (1 << 5)
146 #define RADEON_RESET_RLC (1 << 6)
147 #define RADEON_RESET_SEM (1 << 7)
148 #define RADEON_RESET_IH (1 << 8)
149 #define RADEON_RESET_VMC (1 << 9)
150 #define RADEON_RESET_MC (1 << 10)
151 #define RADEON_RESET_DISPLAY (1 << 11)
154 * Errata workarounds.
156 enum radeon_pll_errata {
157 CHIP_ERRATA_R300_CG = 0x00000001,
158 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
159 CHIP_ERRATA_PLL_DELAY = 0x00000004
163 struct radeon_device;
169 bool radeon_get_bios(struct radeon_device *rdev);
174 struct radeon_dummy_page {
178 int radeon_dummy_page_init(struct radeon_device *rdev);
179 void radeon_dummy_page_fini(struct radeon_device *rdev);
185 struct radeon_clock {
186 struct radeon_pll p1pll;
187 struct radeon_pll p2pll;
188 struct radeon_pll dcpll;
189 struct radeon_pll spll;
190 struct radeon_pll mpll;
192 uint32_t default_mclk;
193 uint32_t default_sclk;
194 uint32_t default_dispclk;
196 uint32_t max_pixel_clock;
202 int radeon_pm_init(struct radeon_device *rdev);
203 void radeon_pm_fini(struct radeon_device *rdev);
204 void radeon_pm_compute_clocks(struct radeon_device *rdev);
205 void radeon_pm_suspend(struct radeon_device *rdev);
206 void radeon_pm_resume(struct radeon_device *rdev);
207 void radeon_combios_get_power_modes(struct radeon_device *rdev);
208 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
209 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
213 struct atom_clock_dividers *dividers);
214 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
215 void rs690_pm_info(struct radeon_device *rdev);
216 extern int rv6xx_get_temp(struct radeon_device *rdev);
217 extern int rv770_get_temp(struct radeon_device *rdev);
218 extern int evergreen_get_temp(struct radeon_device *rdev);
219 extern int sumo_get_temp(struct radeon_device *rdev);
220 extern int si_get_temp(struct radeon_device *rdev);
221 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
222 unsigned *bankh, unsigned *mtaspect,
223 unsigned *tile_split);
228 struct radeon_fence_driver {
229 uint32_t scratch_reg;
231 volatile uint32_t *cpu_addr;
232 /* sync_seq is protected by ring emission lock */
233 uint64_t sync_seq[RADEON_NUM_RINGS];
235 unsigned long last_activity;
239 struct radeon_fence {
240 struct radeon_device *rdev;
242 /* protected by radeon_fence.lock */
248 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
249 int radeon_fence_driver_init(struct radeon_device *rdev);
250 void radeon_fence_driver_fini(struct radeon_device *rdev);
251 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
252 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
253 void radeon_fence_process(struct radeon_device *rdev, int ring);
254 bool radeon_fence_signaled(struct radeon_fence *fence);
255 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
256 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
257 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
258 int radeon_fence_wait_any(struct radeon_device *rdev,
259 struct radeon_fence **fences,
261 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
262 void radeon_fence_unref(struct radeon_fence **fence);
263 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
264 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
265 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
266 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
267 struct radeon_fence *b)
277 BUG_ON(a->ring != b->ring);
279 if (a->seq > b->seq) {
286 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
287 struct radeon_fence *b)
297 BUG_ON(a->ring != b->ring);
299 return a->seq < b->seq;
305 struct radeon_surface_reg {
306 struct radeon_bo *bo;
309 #define RADEON_GEM_MAX_SURFACES 8
315 struct ttm_bo_global_ref bo_global_ref;
316 struct drm_global_reference mem_global_ref;
317 struct ttm_bo_device bdev;
318 bool mem_global_referenced;
322 /* bo virtual address in a specific vm */
323 struct radeon_bo_va {
324 /* protected by bo being reserved */
325 struct list_head bo_list;
332 /* protected by vm mutex */
333 struct list_head vm_list;
335 /* constant after initialization */
336 struct radeon_vm *vm;
337 struct radeon_bo *bo;
341 /* Protected by gem.mutex */
342 struct list_head list;
343 /* Protected by tbo.reserved */
345 struct ttm_placement placement;
346 struct ttm_buffer_object tbo;
347 struct ttm_bo_kmap_obj kmap;
353 /* list of all virtual address to which this bo
357 /* Constant after initialization */
358 struct radeon_device *rdev;
359 struct drm_gem_object gem_base;
361 struct ttm_bo_kmap_obj dma_buf_vmap;
363 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
365 struct radeon_bo_list {
366 struct ttm_validate_buffer tv;
367 struct radeon_bo *bo;
375 /* sub-allocation manager, it has to be protected by another lock.
376 * By conception this is an helper for other part of the driver
377 * like the indirect buffer or semaphore, which both have their
380 * Principe is simple, we keep a list of sub allocation in offset
381 * order (first entry has offset == 0, last entry has the highest
384 * When allocating new object we first check if there is room at
385 * the end total_size - (last_object_offset + last_object_size) >=
386 * alloc_size. If so we allocate new object there.
388 * When there is not enough room at the end, we start waiting for
389 * each sub object until we reach object_offset+object_size >=
390 * alloc_size, this object then become the sub object we return.
392 * Alignment can't be bigger than page size.
394 * Hole are not considered for allocation to keep things simple.
395 * Assumption is that there won't be hole (all object on same
398 struct radeon_sa_manager {
399 wait_queue_head_t wq;
400 struct radeon_bo *bo;
401 struct list_head *hole;
402 struct list_head flist[RADEON_NUM_RINGS];
403 struct list_head olist;
412 /* sub-allocation buffer */
413 struct radeon_sa_bo {
414 struct list_head olist;
415 struct list_head flist;
416 struct radeon_sa_manager *manager;
419 struct radeon_fence *fence;
427 struct list_head objects;
430 int radeon_gem_init(struct radeon_device *rdev);
431 void radeon_gem_fini(struct radeon_device *rdev);
432 int radeon_gem_object_create(struct radeon_device *rdev, int size,
433 int alignment, int initial_domain,
434 bool discardable, bool kernel,
435 struct drm_gem_object **obj);
437 int radeon_mode_dumb_create(struct drm_file *file_priv,
438 struct drm_device *dev,
439 struct drm_mode_create_dumb *args);
440 int radeon_mode_dumb_mmap(struct drm_file *filp,
441 struct drm_device *dev,
442 uint32_t handle, uint64_t *offset_p);
443 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
444 struct drm_device *dev,
450 /* everything here is constant */
451 struct radeon_semaphore {
452 struct radeon_sa_bo *sa_bo;
457 int radeon_semaphore_create(struct radeon_device *rdev,
458 struct radeon_semaphore **semaphore);
459 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
460 struct radeon_semaphore *semaphore);
461 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
462 struct radeon_semaphore *semaphore);
463 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
464 struct radeon_semaphore *semaphore,
465 int signaler, int waiter);
466 void radeon_semaphore_free(struct radeon_device *rdev,
467 struct radeon_semaphore **semaphore,
468 struct radeon_fence *fence);
471 * GART structures, functions & helpers
475 #define RADEON_GPU_PAGE_SIZE 4096
476 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
477 #define RADEON_GPU_PAGE_SHIFT 12
478 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
481 dma_addr_t table_addr;
482 struct radeon_bo *robj;
484 unsigned num_gpu_pages;
485 unsigned num_cpu_pages;
488 dma_addr_t *pages_addr;
492 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
493 void radeon_gart_table_ram_free(struct radeon_device *rdev);
494 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
495 void radeon_gart_table_vram_free(struct radeon_device *rdev);
496 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
497 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
498 int radeon_gart_init(struct radeon_device *rdev);
499 void radeon_gart_fini(struct radeon_device *rdev);
500 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
502 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
503 int pages, struct page **pagelist,
504 dma_addr_t *dma_addr);
505 void radeon_gart_restore(struct radeon_device *rdev);
509 * GPU MC structures, functions & helpers
512 resource_size_t aper_size;
513 resource_size_t aper_base;
514 resource_size_t agp_base;
515 /* for some chips with <= 32MB we need to lie
516 * about vram size near mc fb location */
518 u64 visible_vram_size;
528 bool igp_sideport_enabled;
533 bool radeon_combios_sideport_present(struct radeon_device *rdev);
534 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
537 * GPU scratch registers structures, functions & helpers
539 struct radeon_scratch {
546 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
547 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
554 struct radeon_unpin_work {
555 struct work_struct work;
556 struct radeon_device *rdev;
558 struct radeon_fence *fence;
559 struct drm_pending_vblank_event *event;
560 struct radeon_bo *old_rbo;
564 struct r500_irq_stat_regs {
569 struct r600_irq_stat_regs {
579 struct evergreen_irq_stat_regs {
600 union radeon_irq_stat_regs {
601 struct r500_irq_stat_regs r500;
602 struct r600_irq_stat_regs r600;
603 struct evergreen_irq_stat_regs evergreen;
606 #define RADEON_MAX_HPD_PINS 6
607 #define RADEON_MAX_CRTCS 6
608 #define RADEON_MAX_AFMT_BLOCKS 6
613 atomic_t ring_int[RADEON_NUM_RINGS];
614 bool crtc_vblank_int[RADEON_MAX_CRTCS];
615 atomic_t pflip[RADEON_MAX_CRTCS];
616 wait_queue_head_t vblank_queue;
617 bool hpd[RADEON_MAX_HPD_PINS];
618 bool afmt[RADEON_MAX_AFMT_BLOCKS];
619 union radeon_irq_stat_regs stat_regs;
622 int radeon_irq_kms_init(struct radeon_device *rdev);
623 void radeon_irq_kms_fini(struct radeon_device *rdev);
624 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
625 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
626 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
627 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
628 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
629 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
630 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
631 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
638 struct radeon_sa_bo *sa_bo;
643 struct radeon_fence *fence;
644 struct radeon_vm *vm;
646 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
647 struct radeon_semaphore *semaphore;
651 struct radeon_bo *ring_obj;
652 volatile uint32_t *ring;
656 unsigned rptr_save_reg;
657 u64 next_rptr_gpu_addr;
658 volatile u32 *next_rptr_cpu_addr;
663 unsigned ring_free_dw;
665 unsigned long last_activity;
675 u64 last_semaphore_signal_addr;
676 u64 last_semaphore_wait_addr;
683 /* maximum number of VMIDs */
684 #define RADEON_NUM_VM 16
686 /* defines number of bits in page table versus page directory,
687 * a page is 4KB so we have 12 bits offset, 9 bits in the page
688 * table and the remaining 19 bits are in the page directory */
689 #define RADEON_VM_BLOCK_SIZE 9
691 /* number of entries in page table */
692 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
695 struct list_head list;
699 /* contains the page directory */
700 struct radeon_sa_bo *page_directory;
701 uint64_t pd_gpu_addr;
703 /* array of page tables, one for each page directory entry */
704 struct radeon_sa_bo **page_tables;
707 /* last fence for cs using this vm */
708 struct radeon_fence *fence;
709 /* last flush or NULL if we still need to flush */
710 struct radeon_fence *last_flush;
713 struct radeon_vm_manager {
715 struct list_head lru_vm;
716 struct radeon_fence *active[RADEON_NUM_VM];
717 struct radeon_sa_manager sa_manager;
719 /* number of VMIDs */
721 /* vram base address for page table entry */
722 u64 vram_base_offset;
728 * file private structure
730 struct radeon_fpriv {
738 struct radeon_bo *ring_obj;
739 volatile uint32_t *ring;
748 struct r600_blit_cp_primitives {
749 void (*set_render_target)(struct radeon_device *rdev, int format,
750 int w, int h, u64 gpu_addr);
751 void (*cp_set_surface_sync)(struct radeon_device *rdev,
752 u32 sync_type, u32 size,
754 void (*set_shaders)(struct radeon_device *rdev);
755 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
756 void (*set_tex_resource)(struct radeon_device *rdev,
757 int format, int w, int h, int pitch,
758 u64 gpu_addr, u32 size);
759 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
761 void (*draw_auto)(struct radeon_device *rdev);
762 void (*set_default_state)(struct radeon_device *rdev);
766 struct radeon_bo *shader_obj;
767 struct r600_blit_cp_primitives primitives;
769 int ring_size_common;
770 int ring_size_per_loop;
772 u32 vs_offset, ps_offset;
781 /* for power gating */
782 struct radeon_bo *save_restore_obj;
783 uint64_t save_restore_gpu_addr;
784 /* for clear state */
785 struct radeon_bo *clear_state_obj;
786 uint64_t clear_state_gpu_addr;
789 int radeon_ib_get(struct radeon_device *rdev, int ring,
790 struct radeon_ib *ib, struct radeon_vm *vm,
792 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
793 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
794 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
795 struct radeon_ib *const_ib);
796 int radeon_ib_pool_init(struct radeon_device *rdev);
797 void radeon_ib_pool_fini(struct radeon_device *rdev);
798 int radeon_ib_ring_tests(struct radeon_device *rdev);
799 /* Ring access between begin & end cannot sleep */
800 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
801 struct radeon_ring *ring);
802 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
803 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
804 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
805 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
806 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
807 void radeon_ring_undo(struct radeon_ring *ring);
808 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
809 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
810 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
811 void radeon_ring_lockup_update(struct radeon_ring *ring);
812 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
813 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
815 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
816 unsigned size, uint32_t *data);
817 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
818 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
819 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
820 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
824 void r600_dma_stop(struct radeon_device *rdev);
825 int r600_dma_resume(struct radeon_device *rdev);
826 void r600_dma_fini(struct radeon_device *rdev);
828 void cayman_dma_stop(struct radeon_device *rdev);
829 int cayman_dma_resume(struct radeon_device *rdev);
830 void cayman_dma_fini(struct radeon_device *rdev);
835 struct radeon_cs_reloc {
836 struct drm_gem_object *gobj;
837 struct radeon_bo *robj;
838 struct radeon_bo_list lobj;
843 struct radeon_cs_chunk {
849 void __user *user_ptr;
850 int last_copied_page;
854 struct radeon_cs_parser {
856 struct radeon_device *rdev;
857 struct drm_file *filp;
860 struct radeon_cs_chunk *chunks;
861 uint64_t *chunks_array;
866 struct radeon_cs_reloc *relocs;
867 struct radeon_cs_reloc **relocs_ptr;
868 struct list_head validated;
869 unsigned dma_reloc_idx;
870 /* indices of various chunks */
872 int chunk_relocs_idx;
874 int chunk_const_ib_idx;
876 struct radeon_ib const_ib;
885 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
886 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
888 struct radeon_cs_packet {
897 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
898 struct radeon_cs_packet *pkt,
899 unsigned idx, unsigned reg);
900 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
901 struct radeon_cs_packet *pkt);
907 int radeon_agp_init(struct radeon_device *rdev);
908 void radeon_agp_resume(struct radeon_device *rdev);
909 void radeon_agp_suspend(struct radeon_device *rdev);
910 void radeon_agp_fini(struct radeon_device *rdev);
917 struct radeon_bo *wb_obj;
918 volatile uint32_t *wb;
924 #define RADEON_WB_SCRATCH_OFFSET 0
925 #define RADEON_WB_RING0_NEXT_RPTR 256
926 #define RADEON_WB_CP_RPTR_OFFSET 1024
927 #define RADEON_WB_CP1_RPTR_OFFSET 1280
928 #define RADEON_WB_CP2_RPTR_OFFSET 1536
929 #define R600_WB_DMA_RPTR_OFFSET 1792
930 #define R600_WB_IH_WPTR_OFFSET 2048
931 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
932 #define R600_WB_UVD_RPTR_OFFSET 2560
933 #define R600_WB_EVENT_OFFSET 3072
936 * struct radeon_pm - power management datas
937 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
938 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
939 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
940 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
941 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
942 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
943 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
944 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
945 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
946 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
947 * @needed_bandwidth: current bandwidth needs
949 * It keeps track of various data needed to take powermanagement decision.
950 * Bandwidth need is used to determine minimun clock of the GPU and memory.
951 * Equation between gpu/memory clock and available bandwidth is hw dependent
952 * (type of memory, bus size, efficiency, ...)
955 enum radeon_pm_method {
960 enum radeon_dynpm_state {
961 DYNPM_STATE_DISABLED,
965 DYNPM_STATE_SUSPENDED,
967 enum radeon_dynpm_action {
969 DYNPM_ACTION_MINIMUM,
970 DYNPM_ACTION_DOWNCLOCK,
971 DYNPM_ACTION_UPCLOCK,
975 enum radeon_voltage_type {
982 enum radeon_pm_state_type {
983 POWER_STATE_TYPE_DEFAULT,
984 POWER_STATE_TYPE_POWERSAVE,
985 POWER_STATE_TYPE_BATTERY,
986 POWER_STATE_TYPE_BALANCED,
987 POWER_STATE_TYPE_PERFORMANCE,
990 enum radeon_pm_profile_type {
998 #define PM_PROFILE_DEFAULT_IDX 0
999 #define PM_PROFILE_LOW_SH_IDX 1
1000 #define PM_PROFILE_MID_SH_IDX 2
1001 #define PM_PROFILE_HIGH_SH_IDX 3
1002 #define PM_PROFILE_LOW_MH_IDX 4
1003 #define PM_PROFILE_MID_MH_IDX 5
1004 #define PM_PROFILE_HIGH_MH_IDX 6
1005 #define PM_PROFILE_MAX 7
1007 struct radeon_pm_profile {
1008 int dpms_off_ps_idx;
1010 int dpms_off_cm_idx;
1014 enum radeon_int_thermal_type {
1018 THERMAL_TYPE_EVERGREEN,
1024 struct radeon_voltage {
1025 enum radeon_voltage_type type;
1027 struct radeon_gpio_rec gpio;
1028 u32 delay; /* delay in usec from voltage drop to sclk change */
1029 bool active_high; /* voltage drop is active when bit is high */
1031 u8 vddc_id; /* index into vddc voltage table */
1032 u8 vddci_id; /* index into vddci voltage table */
1036 /* evergreen+ vddci */
1040 /* clock mode flags */
1041 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1043 struct radeon_pm_clock_info {
1049 struct radeon_voltage voltage;
1050 /* standardized clock flags */
1055 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1057 struct radeon_power_state {
1058 enum radeon_pm_state_type type;
1059 struct radeon_pm_clock_info *clock_info;
1060 /* number of valid clock modes in this power state */
1061 int num_clock_modes;
1062 struct radeon_pm_clock_info *default_clock_mode;
1063 /* standardized state flags */
1065 u32 misc; /* vbios specific flags */
1066 u32 misc2; /* vbios specific flags */
1067 int pcie_lanes; /* pcie lanes */
1071 * Some modes are overclocked by very low value, accept them
1073 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1077 /* write locked while reprogramming mclk */
1078 struct rw_semaphore mclk_lock;
1080 int active_crtc_count;
1083 fixed20_12 max_bandwidth;
1084 fixed20_12 igp_sideport_mclk;
1085 fixed20_12 igp_system_mclk;
1086 fixed20_12 igp_ht_link_clk;
1087 fixed20_12 igp_ht_link_width;
1088 fixed20_12 k8_bandwidth;
1089 fixed20_12 sideport_bandwidth;
1090 fixed20_12 ht_bandwidth;
1091 fixed20_12 core_bandwidth;
1094 fixed20_12 needed_bandwidth;
1095 struct radeon_power_state *power_state;
1096 /* number of valid power states */
1097 int num_power_states;
1098 int current_power_state_index;
1099 int current_clock_mode_index;
1100 int requested_power_state_index;
1101 int requested_clock_mode_index;
1102 int default_power_state_index;
1111 struct radeon_i2c_chan *i2c_bus;
1112 /* selected pm method */
1113 enum radeon_pm_method pm_method;
1114 /* dynpm power management */
1115 struct delayed_work dynpm_idle_work;
1116 enum radeon_dynpm_state dynpm_state;
1117 enum radeon_dynpm_action dynpm_planned_action;
1118 unsigned long dynpm_action_timeout;
1119 bool dynpm_can_upclock;
1120 bool dynpm_can_downclock;
1121 /* profile-based power management */
1122 enum radeon_pm_profile_type profile;
1124 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1125 /* internal thermal controller on rv6xx+ */
1126 enum radeon_int_thermal_type int_thermal_type;
1127 struct device *int_hwmon_dev;
1130 int radeon_pm_get_type_index(struct radeon_device *rdev,
1131 enum radeon_pm_state_type ps_type,
1136 #define RADEON_MAX_UVD_HANDLES 10
1137 #define RADEON_UVD_STACK_SIZE (1024*1024)
1138 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1141 struct radeon_bo *vcpu_bo;
1144 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1145 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1148 int radeon_uvd_init(struct radeon_device *rdev);
1149 void radeon_uvd_fini(struct radeon_device *rdev);
1150 int radeon_uvd_suspend(struct radeon_device *rdev);
1151 int radeon_uvd_resume(struct radeon_device *rdev);
1152 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1153 uint32_t handle, struct radeon_fence **fence);
1154 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1155 uint32_t handle, struct radeon_fence **fence);
1156 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1157 void radeon_uvd_free_handles(struct radeon_device *rdev,
1158 struct drm_file *filp);
1159 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1164 int bits_per_sample;
1172 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1178 void radeon_test_moves(struct radeon_device *rdev);
1179 void radeon_test_ring_sync(struct radeon_device *rdev,
1180 struct radeon_ring *cpA,
1181 struct radeon_ring *cpB);
1182 void radeon_test_syncing(struct radeon_device *rdev);
1188 struct radeon_debugfs {
1189 struct drm_info_list *files;
1193 int radeon_debugfs_add_files(struct radeon_device *rdev,
1194 struct drm_info_list *files,
1196 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1200 * ASIC specific functions.
1202 struct radeon_asic {
1203 int (*init)(struct radeon_device *rdev);
1204 void (*fini)(struct radeon_device *rdev);
1205 int (*resume)(struct radeon_device *rdev);
1206 int (*suspend)(struct radeon_device *rdev);
1207 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1208 int (*asic_reset)(struct radeon_device *rdev);
1209 /* ioctl hw specific callback. Some hw might want to perform special
1210 * operation on specific ioctl. For instance on wait idle some hw
1211 * might want to perform and HDP flush through MMIO as it seems that
1212 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1215 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1216 /* check if 3D engine is idle */
1217 bool (*gui_idle)(struct radeon_device *rdev);
1218 /* wait for mc_idle */
1219 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1220 /* get the reference clock */
1221 u32 (*get_xclk)(struct radeon_device *rdev);
1222 /* get the gpu clock counter */
1223 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1226 void (*tlb_flush)(struct radeon_device *rdev);
1227 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1230 int (*init)(struct radeon_device *rdev);
1231 void (*fini)(struct radeon_device *rdev);
1234 void (*set_page)(struct radeon_device *rdev,
1235 struct radeon_ib *ib,
1237 uint64_t addr, unsigned count,
1238 uint32_t incr, uint32_t flags);
1240 /* ring specific callbacks */
1242 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1243 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1244 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1245 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1246 struct radeon_semaphore *semaphore, bool emit_wait);
1247 int (*cs_parse)(struct radeon_cs_parser *p);
1248 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1249 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1250 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1251 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1252 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1253 } ring[RADEON_NUM_RINGS];
1256 int (*set)(struct radeon_device *rdev);
1257 int (*process)(struct radeon_device *rdev);
1261 /* display watermarks */
1262 void (*bandwidth_update)(struct radeon_device *rdev);
1263 /* get frame count */
1264 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1265 /* wait for vblank */
1266 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1267 /* set backlight level */
1268 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1269 /* get backlight level */
1270 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1272 /* copy functions for bo handling */
1274 int (*blit)(struct radeon_device *rdev,
1275 uint64_t src_offset,
1276 uint64_t dst_offset,
1277 unsigned num_gpu_pages,
1278 struct radeon_fence **fence);
1279 u32 blit_ring_index;
1280 int (*dma)(struct radeon_device *rdev,
1281 uint64_t src_offset,
1282 uint64_t dst_offset,
1283 unsigned num_gpu_pages,
1284 struct radeon_fence **fence);
1286 /* method used for bo copy */
1287 int (*copy)(struct radeon_device *rdev,
1288 uint64_t src_offset,
1289 uint64_t dst_offset,
1290 unsigned num_gpu_pages,
1291 struct radeon_fence **fence);
1292 /* ring used for bo copies */
1293 u32 copy_ring_index;
1297 int (*set_reg)(struct radeon_device *rdev, int reg,
1298 uint32_t tiling_flags, uint32_t pitch,
1299 uint32_t offset, uint32_t obj_size);
1300 void (*clear_reg)(struct radeon_device *rdev, int reg);
1302 /* hotplug detect */
1304 void (*init)(struct radeon_device *rdev);
1305 void (*fini)(struct radeon_device *rdev);
1306 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1307 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1309 /* power management */
1311 void (*misc)(struct radeon_device *rdev);
1312 void (*prepare)(struct radeon_device *rdev);
1313 void (*finish)(struct radeon_device *rdev);
1314 void (*init_profile)(struct radeon_device *rdev);
1315 void (*get_dynpm_state)(struct radeon_device *rdev);
1316 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1317 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1318 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1319 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1320 int (*get_pcie_lanes)(struct radeon_device *rdev);
1321 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1322 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1323 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1327 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1328 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1329 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1337 const unsigned *reg_safe_bm;
1338 unsigned reg_safe_bm_size;
1343 const unsigned *reg_safe_bm;
1344 unsigned reg_safe_bm_size;
1351 unsigned max_tile_pipes;
1353 unsigned max_backends;
1355 unsigned max_threads;
1356 unsigned max_stack_entries;
1357 unsigned max_hw_contexts;
1358 unsigned max_gs_threads;
1359 unsigned sx_max_export_size;
1360 unsigned sx_max_export_pos_size;
1361 unsigned sx_max_export_smx_size;
1362 unsigned sq_num_cf_insts;
1363 unsigned tiling_nbanks;
1364 unsigned tiling_npipes;
1365 unsigned tiling_group_size;
1366 unsigned tile_config;
1367 unsigned backend_map;
1372 unsigned max_tile_pipes;
1374 unsigned max_backends;
1376 unsigned max_threads;
1377 unsigned max_stack_entries;
1378 unsigned max_hw_contexts;
1379 unsigned max_gs_threads;
1380 unsigned sx_max_export_size;
1381 unsigned sx_max_export_pos_size;
1382 unsigned sx_max_export_smx_size;
1383 unsigned sq_num_cf_insts;
1384 unsigned sx_num_of_sets;
1385 unsigned sc_prim_fifo_size;
1386 unsigned sc_hiz_tile_fifo_size;
1387 unsigned sc_earlyz_tile_fifo_fize;
1388 unsigned tiling_nbanks;
1389 unsigned tiling_npipes;
1390 unsigned tiling_group_size;
1391 unsigned tile_config;
1392 unsigned backend_map;
1395 struct evergreen_asic {
1398 unsigned max_tile_pipes;
1400 unsigned max_backends;
1402 unsigned max_threads;
1403 unsigned max_stack_entries;
1404 unsigned max_hw_contexts;
1405 unsigned max_gs_threads;
1406 unsigned sx_max_export_size;
1407 unsigned sx_max_export_pos_size;
1408 unsigned sx_max_export_smx_size;
1409 unsigned sq_num_cf_insts;
1410 unsigned sx_num_of_sets;
1411 unsigned sc_prim_fifo_size;
1412 unsigned sc_hiz_tile_fifo_size;
1413 unsigned sc_earlyz_tile_fifo_size;
1414 unsigned tiling_nbanks;
1415 unsigned tiling_npipes;
1416 unsigned tiling_group_size;
1417 unsigned tile_config;
1418 unsigned backend_map;
1421 struct cayman_asic {
1422 unsigned max_shader_engines;
1423 unsigned max_pipes_per_simd;
1424 unsigned max_tile_pipes;
1425 unsigned max_simds_per_se;
1426 unsigned max_backends_per_se;
1427 unsigned max_texture_channel_caches;
1429 unsigned max_threads;
1430 unsigned max_gs_threads;
1431 unsigned max_stack_entries;
1432 unsigned sx_num_of_sets;
1433 unsigned sx_max_export_size;
1434 unsigned sx_max_export_pos_size;
1435 unsigned sx_max_export_smx_size;
1436 unsigned max_hw_contexts;
1437 unsigned sq_num_cf_insts;
1438 unsigned sc_prim_fifo_size;
1439 unsigned sc_hiz_tile_fifo_size;
1440 unsigned sc_earlyz_tile_fifo_size;
1442 unsigned num_shader_engines;
1443 unsigned num_shader_pipes_per_simd;
1444 unsigned num_tile_pipes;
1445 unsigned num_simds_per_se;
1446 unsigned num_backends_per_se;
1447 unsigned backend_disable_mask_per_asic;
1448 unsigned backend_map;
1449 unsigned num_texture_channel_caches;
1450 unsigned mem_max_burst_length_bytes;
1451 unsigned mem_row_size_in_kb;
1452 unsigned shader_engine_tile_size;
1454 unsigned multi_gpu_tile_size;
1456 unsigned tile_config;
1460 unsigned max_shader_engines;
1461 unsigned max_tile_pipes;
1462 unsigned max_cu_per_sh;
1463 unsigned max_sh_per_se;
1464 unsigned max_backends_per_se;
1465 unsigned max_texture_channel_caches;
1467 unsigned max_gs_threads;
1468 unsigned max_hw_contexts;
1469 unsigned sc_prim_fifo_size_frontend;
1470 unsigned sc_prim_fifo_size_backend;
1471 unsigned sc_hiz_tile_fifo_size;
1472 unsigned sc_earlyz_tile_fifo_size;
1474 unsigned num_tile_pipes;
1475 unsigned num_backends_per_se;
1476 unsigned backend_disable_mask_per_asic;
1477 unsigned backend_map;
1478 unsigned num_texture_channel_caches;
1479 unsigned mem_max_burst_length_bytes;
1480 unsigned mem_row_size_in_kb;
1481 unsigned shader_engine_tile_size;
1483 unsigned multi_gpu_tile_size;
1485 unsigned tile_config;
1486 uint32_t tile_mode_array[32];
1489 union radeon_asic_config {
1490 struct r300_asic r300;
1491 struct r100_asic r100;
1492 struct r600_asic r600;
1493 struct rv770_asic rv770;
1494 struct evergreen_asic evergreen;
1495 struct cayman_asic cayman;
1500 * asic initizalization from radeon_asic.c
1502 void radeon_agp_disable(struct radeon_device *rdev);
1503 int radeon_asic_init(struct radeon_device *rdev);
1509 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1510 struct drm_file *filp);
1511 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1512 struct drm_file *filp);
1513 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1514 struct drm_file *file_priv);
1515 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1516 struct drm_file *file_priv);
1517 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1518 struct drm_file *file_priv);
1519 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1520 struct drm_file *file_priv);
1521 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1522 struct drm_file *filp);
1523 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1524 struct drm_file *filp);
1525 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1526 struct drm_file *filp);
1527 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1528 struct drm_file *filp);
1529 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1530 struct drm_file *filp);
1531 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1532 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1533 struct drm_file *filp);
1534 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1535 struct drm_file *filp);
1537 /* VRAM scratch page for HDP bug, default vram page */
1538 struct r600_vram_scratch {
1539 struct radeon_bo *robj;
1540 volatile uint32_t *ptr;
1547 struct radeon_atif_notification_cfg {
1552 struct radeon_atif_notifications {
1553 bool display_switch;
1554 bool expansion_mode_change;
1556 bool forced_power_state;
1557 bool system_power_state;
1558 bool display_conf_change;
1560 bool brightness_change;
1561 bool dgpu_display_event;
1564 struct radeon_atif_functions {
1566 bool sbios_requests;
1567 bool select_active_disp;
1569 bool get_tv_standard;
1570 bool set_tv_standard;
1571 bool get_panel_expansion_mode;
1572 bool set_panel_expansion_mode;
1573 bool temperature_change;
1574 bool graphics_device_types;
1577 struct radeon_atif {
1578 struct radeon_atif_notifications notifications;
1579 struct radeon_atif_functions functions;
1580 struct radeon_atif_notification_cfg notification_cfg;
1581 struct radeon_encoder *encoder_for_bl;
1584 struct radeon_atcs_functions {
1588 bool pcie_bus_width;
1591 struct radeon_atcs {
1592 struct radeon_atcs_functions functions;
1596 * Core structure, functions and helpers.
1598 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1599 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1601 struct radeon_device {
1603 struct drm_device *ddev;
1604 struct pci_dev *pdev;
1605 struct rw_semaphore exclusive_lock;
1607 union radeon_asic_config config;
1608 enum radeon_family family;
1609 unsigned long flags;
1611 enum radeon_pll_errata pll_errata;
1618 uint16_t bios_header_start;
1619 struct radeon_bo *stollen_vga_memory;
1621 resource_size_t rmmio_base;
1622 resource_size_t rmmio_size;
1623 /* protects concurrent MM_INDEX/DATA based register access */
1624 spinlock_t mmio_idx_lock;
1625 void __iomem *rmmio;
1626 radeon_rreg_t mc_rreg;
1627 radeon_wreg_t mc_wreg;
1628 radeon_rreg_t pll_rreg;
1629 radeon_wreg_t pll_wreg;
1630 uint32_t pcie_reg_mask;
1631 radeon_rreg_t pciep_rreg;
1632 radeon_wreg_t pciep_wreg;
1634 void __iomem *rio_mem;
1635 resource_size_t rio_mem_size;
1636 struct radeon_clock clock;
1637 struct radeon_mc mc;
1638 struct radeon_gart gart;
1639 struct radeon_mode_info mode_info;
1640 struct radeon_scratch scratch;
1641 struct radeon_mman mman;
1642 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1643 wait_queue_head_t fence_queue;
1644 struct mutex ring_lock;
1645 struct radeon_ring ring[RADEON_NUM_RINGS];
1647 struct radeon_sa_manager ring_tmp_bo;
1648 struct radeon_irq irq;
1649 struct radeon_asic *asic;
1650 struct radeon_gem gem;
1651 struct radeon_pm pm;
1652 struct radeon_uvd uvd;
1653 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1654 struct radeon_wb wb;
1655 struct radeon_dummy_page dummy_page;
1660 bool fastfb_working; /* IGP feature*/
1661 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1662 const struct firmware *me_fw; /* all family ME firmware */
1663 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1664 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1665 const struct firmware *mc_fw; /* NI MC firmware */
1666 const struct firmware *ce_fw; /* SI CE firmware */
1667 const struct firmware *uvd_fw; /* UVD firmware */
1668 struct r600_blit r600_blit;
1669 struct r600_vram_scratch vram_scratch;
1670 int msi_enabled; /* msi enabled */
1671 struct r600_ih ih; /* r6/700 interrupt ring */
1673 struct work_struct hotplug_work;
1674 struct work_struct audio_work;
1675 int num_crtc; /* number of crtcs */
1676 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1678 struct r600_audio audio_status; /* audio stuff */
1679 struct notifier_block acpi_nb;
1680 /* only one userspace can use Hyperz features or CMASK at a time */
1681 struct drm_file *hyperz_filp;
1682 struct drm_file *cmask_filp;
1684 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1686 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1687 unsigned debugfs_count;
1688 /* virtual memory */
1689 struct radeon_vm_manager vm_manager;
1690 struct mutex gpu_clock_mutex;
1691 /* ACPI interface */
1692 struct radeon_atif atif;
1693 struct radeon_atcs atcs;
1696 int radeon_device_init(struct radeon_device *rdev,
1697 struct drm_device *ddev,
1698 struct pci_dev *pdev,
1700 void radeon_device_fini(struct radeon_device *rdev);
1701 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1703 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
1704 bool always_indirect);
1705 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
1706 bool always_indirect);
1707 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1708 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1713 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1716 * Registers read & write functions.
1718 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1719 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1720 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1721 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1722 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
1723 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
1724 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
1725 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
1726 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
1727 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1728 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1729 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1730 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1731 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1732 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1733 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1734 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1735 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
1736 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1737 #define WREG32_P(reg, val, mask) \
1739 uint32_t tmp_ = RREG32(reg); \
1741 tmp_ |= ((val) & ~(mask)); \
1742 WREG32(reg, tmp_); \
1744 #define WREG32_PLL_P(reg, val, mask) \
1746 uint32_t tmp_ = RREG32_PLL(reg); \
1748 tmp_ |= ((val) & ~(mask)); \
1749 WREG32_PLL(reg, tmp_); \
1751 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
1752 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1753 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1756 * Indirect registers accessor
1758 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1762 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1763 r = RREG32(RADEON_PCIE_DATA);
1767 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1769 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1770 WREG32(RADEON_PCIE_DATA, (v));
1773 void r100_pll_errata_after_index(struct radeon_device *rdev);
1779 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1780 (rdev->pdev->device == 0x5969))
1781 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1782 (rdev->family == CHIP_RV200) || \
1783 (rdev->family == CHIP_RS100) || \
1784 (rdev->family == CHIP_RS200) || \
1785 (rdev->family == CHIP_RV250) || \
1786 (rdev->family == CHIP_RV280) || \
1787 (rdev->family == CHIP_RS300))
1788 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1789 (rdev->family == CHIP_RV350) || \
1790 (rdev->family == CHIP_R350) || \
1791 (rdev->family == CHIP_RV380) || \
1792 (rdev->family == CHIP_R420) || \
1793 (rdev->family == CHIP_R423) || \
1794 (rdev->family == CHIP_RV410) || \
1795 (rdev->family == CHIP_RS400) || \
1796 (rdev->family == CHIP_RS480))
1797 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1798 (rdev->ddev->pdev->device == 0x9443) || \
1799 (rdev->ddev->pdev->device == 0x944B) || \
1800 (rdev->ddev->pdev->device == 0x9506) || \
1801 (rdev->ddev->pdev->device == 0x9509) || \
1802 (rdev->ddev->pdev->device == 0x950F) || \
1803 (rdev->ddev->pdev->device == 0x689C) || \
1804 (rdev->ddev->pdev->device == 0x689D))
1805 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1806 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1807 (rdev->family == CHIP_RS690) || \
1808 (rdev->family == CHIP_RS740) || \
1809 (rdev->family >= CHIP_R600))
1810 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1811 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1812 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1813 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1814 (rdev->flags & RADEON_IS_IGP))
1815 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1816 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1817 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1818 (rdev->flags & RADEON_IS_IGP))
1819 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
1824 #define RBIOS8(i) (rdev->bios[i])
1825 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1826 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1828 int radeon_combios_init(struct radeon_device *rdev);
1829 void radeon_combios_fini(struct radeon_device *rdev);
1830 int radeon_atombios_init(struct radeon_device *rdev);
1831 void radeon_atombios_fini(struct radeon_device *rdev);
1837 #if DRM_DEBUG_CODE == 0
1838 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1840 ring->ring[ring->wptr++] = v;
1841 ring->wptr &= ring->ptr_mask;
1843 ring->ring_free_dw--;
1846 /* With debugging this is just too big to inline */
1847 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1853 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1854 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1855 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1856 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1857 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1858 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1859 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1860 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1861 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1862 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
1863 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
1864 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
1865 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1866 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1867 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1868 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1869 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1870 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1871 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
1872 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1873 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1874 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1875 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
1876 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
1877 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1878 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1879 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1880 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1881 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1882 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1883 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1884 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1885 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1886 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1887 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1888 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1889 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1890 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1891 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1892 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
1893 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1894 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1895 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1896 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1897 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1898 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1899 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1900 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1901 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1902 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1903 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1904 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1905 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1906 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
1907 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
1908 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
1909 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
1910 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
1911 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
1912 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
1914 /* Common functions */
1916 extern int radeon_gpu_reset(struct radeon_device *rdev);
1917 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
1918 extern void radeon_agp_disable(struct radeon_device *rdev);
1919 extern int radeon_modeset_init(struct radeon_device *rdev);
1920 extern void radeon_modeset_fini(struct radeon_device *rdev);
1921 extern bool radeon_card_posted(struct radeon_device *rdev);
1922 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1923 extern void radeon_update_display_priority(struct radeon_device *rdev);
1924 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1925 extern void radeon_scratch_init(struct radeon_device *rdev);
1926 extern void radeon_wb_fini(struct radeon_device *rdev);
1927 extern int radeon_wb_init(struct radeon_device *rdev);
1928 extern void radeon_wb_disable(struct radeon_device *rdev);
1929 extern void radeon_surface_init(struct radeon_device *rdev);
1930 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1931 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1932 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1933 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1934 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1935 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1936 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1937 extern int radeon_resume_kms(struct drm_device *dev);
1938 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1939 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1944 int radeon_vm_manager_init(struct radeon_device *rdev);
1945 void radeon_vm_manager_fini(struct radeon_device *rdev);
1946 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1947 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1948 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
1949 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
1950 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
1951 struct radeon_vm *vm, int ring);
1952 void radeon_vm_fence(struct radeon_device *rdev,
1953 struct radeon_vm *vm,
1954 struct radeon_fence *fence);
1955 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
1956 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1957 struct radeon_vm *vm,
1958 struct radeon_bo *bo,
1959 struct ttm_mem_reg *mem);
1960 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1961 struct radeon_bo *bo);
1962 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
1963 struct radeon_bo *bo);
1964 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
1965 struct radeon_vm *vm,
1966 struct radeon_bo *bo);
1967 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
1968 struct radeon_bo_va *bo_va,
1971 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1972 struct radeon_bo_va *bo_va);
1975 void r600_audio_update_hdmi(struct work_struct *work);
1978 * R600 vram scratch functions
1980 int r600_vram_scratch_init(struct radeon_device *rdev);
1981 void r600_vram_scratch_fini(struct radeon_device *rdev);
1984 * r600 cs checking helper
1986 unsigned r600_mip_minify(unsigned size, unsigned level);
1987 bool r600_fmt_is_valid_color(u32 format);
1988 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1989 int r600_fmt_get_blocksize(u32 format);
1990 int r600_fmt_get_nblocksx(u32 format, u32 w);
1991 int r600_fmt_get_nblocksy(u32 format, u32 h);
1994 * r600 functions used by radeon_encoder.c
1996 struct radeon_hdmi_acr {
2010 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2012 extern void r600_hdmi_enable(struct drm_encoder *encoder);
2013 extern void r600_hdmi_disable(struct drm_encoder *encoder);
2014 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
2015 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2016 u32 tiling_pipe_num,
2018 u32 total_max_rb_num,
2019 u32 enabled_rb_mask);
2022 * evergreen functions used by radeon_encoder.c
2025 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
2027 extern int ni_init_microcode(struct radeon_device *rdev);
2028 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2031 #if defined(CONFIG_ACPI)
2032 extern int radeon_acpi_init(struct radeon_device *rdev);
2033 extern void radeon_acpi_fini(struct radeon_device *rdev);
2035 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2036 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2039 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2040 struct radeon_cs_packet *pkt,
2042 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2043 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2044 struct radeon_cs_packet *pkt);
2045 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2046 struct radeon_cs_reloc **cs_reloc,
2048 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2049 uint32_t *vline_start_end,
2050 uint32_t *vline_status);
2052 #include "radeon_object.h"