2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
98 * Copy from radeon_drv.h so we don't have to include both and have conflicting
101 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
102 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
103 /* RADEON_IB_POOL_SIZE must be a power of 2 */
104 #define RADEON_IB_POOL_SIZE 16
105 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
106 #define RADEONFB_CONN_LIMIT 4
107 #define RADEON_BIOS_NUM_SCRATCH 8
110 * Errata workarounds.
112 enum radeon_pll_errata {
113 CHIP_ERRATA_R300_CG = 0x00000001,
114 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
115 CHIP_ERRATA_PLL_DELAY = 0x00000004
119 struct radeon_device;
125 #define ATRM_BIOS_PAGE 4096
127 #if defined(CONFIG_VGA_SWITCHEROO)
128 bool radeon_atrm_supported(struct pci_dev *pdev);
129 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
131 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
136 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
140 bool radeon_get_bios(struct radeon_device *rdev);
146 struct radeon_dummy_page {
150 int radeon_dummy_page_init(struct radeon_device *rdev);
151 void radeon_dummy_page_fini(struct radeon_device *rdev);
157 struct radeon_clock {
158 struct radeon_pll p1pll;
159 struct radeon_pll p2pll;
160 struct radeon_pll dcpll;
161 struct radeon_pll spll;
162 struct radeon_pll mpll;
164 uint32_t default_mclk;
165 uint32_t default_sclk;
166 uint32_t default_dispclk;
173 int radeon_pm_init(struct radeon_device *rdev);
174 void radeon_pm_fini(struct radeon_device *rdev);
175 void radeon_pm_compute_clocks(struct radeon_device *rdev);
176 void radeon_pm_suspend(struct radeon_device *rdev);
177 void radeon_pm_resume(struct radeon_device *rdev);
178 void radeon_combios_get_power_modes(struct radeon_device *rdev);
179 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
180 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
181 void rs690_pm_info(struct radeon_device *rdev);
182 extern int rv6xx_get_temp(struct radeon_device *rdev);
183 extern int rv770_get_temp(struct radeon_device *rdev);
184 extern int evergreen_get_temp(struct radeon_device *rdev);
185 extern int sumo_get_temp(struct radeon_device *rdev);
190 struct radeon_fence_driver {
191 uint32_t scratch_reg;
194 unsigned long last_jiffies;
195 unsigned long last_timeout;
196 wait_queue_head_t queue;
198 struct list_head created;
199 struct list_head emited;
200 struct list_head signaled;
204 struct radeon_fence {
205 struct radeon_device *rdev;
207 struct list_head list;
208 /* protected by radeon_fence.lock */
214 int radeon_fence_driver_init(struct radeon_device *rdev);
215 void radeon_fence_driver_fini(struct radeon_device *rdev);
216 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
217 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
218 void radeon_fence_process(struct radeon_device *rdev);
219 bool radeon_fence_signaled(struct radeon_fence *fence);
220 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
221 int radeon_fence_wait_next(struct radeon_device *rdev);
222 int radeon_fence_wait_last(struct radeon_device *rdev);
223 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
224 void radeon_fence_unref(struct radeon_fence **fence);
229 struct radeon_surface_reg {
230 struct radeon_bo *bo;
233 #define RADEON_GEM_MAX_SURFACES 8
239 struct ttm_bo_global_ref bo_global_ref;
240 struct drm_global_reference mem_global_ref;
241 struct ttm_bo_device bdev;
242 bool mem_global_referenced;
247 /* Protected by gem.mutex */
248 struct list_head list;
249 /* Protected by tbo.reserved */
251 struct ttm_placement placement;
252 struct ttm_buffer_object tbo;
253 struct ttm_bo_kmap_obj kmap;
259 /* Constant after initialization */
260 struct radeon_device *rdev;
261 struct drm_gem_object *gobj;
264 struct radeon_bo_list {
265 struct ttm_validate_buffer tv;
266 struct radeon_bo *bo;
278 struct list_head objects;
281 int radeon_gem_init(struct radeon_device *rdev);
282 void radeon_gem_fini(struct radeon_device *rdev);
283 int radeon_gem_object_create(struct radeon_device *rdev, int size,
284 int alignment, int initial_domain,
285 bool discardable, bool kernel,
286 struct drm_gem_object **obj);
287 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
289 void radeon_gem_object_unpin(struct drm_gem_object *obj);
293 * GART structures, functions & helpers
297 struct radeon_gart_table_ram {
298 volatile uint32_t *ptr;
301 struct radeon_gart_table_vram {
302 struct radeon_bo *robj;
303 volatile uint32_t *ptr;
306 union radeon_gart_table {
307 struct radeon_gart_table_ram ram;
308 struct radeon_gart_table_vram vram;
311 #define RADEON_GPU_PAGE_SIZE 4096
312 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
315 dma_addr_t table_addr;
316 unsigned num_gpu_pages;
317 unsigned num_cpu_pages;
319 union radeon_gart_table table;
321 dma_addr_t *pages_addr;
325 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
326 void radeon_gart_table_ram_free(struct radeon_device *rdev);
327 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
328 void radeon_gart_table_vram_free(struct radeon_device *rdev);
329 int radeon_gart_init(struct radeon_device *rdev);
330 void radeon_gart_fini(struct radeon_device *rdev);
331 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
333 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
334 int pages, struct page **pagelist);
338 * GPU MC structures, functions & helpers
341 resource_size_t aper_size;
342 resource_size_t aper_base;
343 resource_size_t agp_base;
344 /* for some chips with <= 32MB we need to lie
345 * about vram size near mc fb location */
347 u64 visible_vram_size;
357 bool igp_sideport_enabled;
361 bool radeon_combios_sideport_present(struct radeon_device *rdev);
362 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
365 * GPU scratch registers structures, functions & helpers
367 struct radeon_scratch {
374 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
375 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
382 struct radeon_unpin_work {
383 struct work_struct work;
384 struct radeon_device *rdev;
386 struct radeon_fence *fence;
387 struct drm_pending_vblank_event *event;
388 struct radeon_bo *old_rbo;
392 struct r500_irq_stat_regs {
396 struct r600_irq_stat_regs {
404 struct evergreen_irq_stat_regs {
419 union radeon_irq_stat_regs {
420 struct r500_irq_stat_regs r500;
421 struct r600_irq_stat_regs r600;
422 struct evergreen_irq_stat_regs evergreen;
428 /* FIXME: use a define max crtc rather than hardcode it */
429 bool crtc_vblank_int[6];
431 wait_queue_head_t vblank_queue;
432 /* FIXME: use defines for max hpd/dacs */
436 wait_queue_head_t idle_queue;
437 /* FIXME: use defines for max HDMI blocks */
441 union radeon_irq_stat_regs stat_regs;
442 spinlock_t pflip_lock[6];
443 int pflip_refcount[6];
446 int radeon_irq_kms_init(struct radeon_device *rdev);
447 void radeon_irq_kms_fini(struct radeon_device *rdev);
448 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
449 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
450 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
451 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
457 struct list_head list;
460 struct radeon_fence *fence;
468 * mutex protects scheduled_ibs, ready, alloc_bm
470 struct radeon_ib_pool {
472 struct radeon_bo *robj;
473 struct list_head bogus_ib;
474 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
480 struct radeon_bo *ring_obj;
481 volatile uint32_t *ring;
486 unsigned ring_free_dw;
499 struct radeon_bo *ring_obj;
500 volatile uint32_t *ring;
513 struct radeon_bo *shader_obj;
515 u32 vs_offset, ps_offset;
518 u32 vb_used, vb_total;
519 struct radeon_ib *vb_ib;
522 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
523 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
524 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
525 int radeon_ib_pool_init(struct radeon_device *rdev);
526 void radeon_ib_pool_fini(struct radeon_device *rdev);
527 int radeon_ib_test(struct radeon_device *rdev);
528 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
529 /* Ring access between begin & end cannot sleep */
530 void radeon_ring_free_size(struct radeon_device *rdev);
531 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
532 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
533 void radeon_ring_commit(struct radeon_device *rdev);
534 void radeon_ring_unlock_commit(struct radeon_device *rdev);
535 void radeon_ring_unlock_undo(struct radeon_device *rdev);
536 int radeon_ring_test(struct radeon_device *rdev);
537 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
538 void radeon_ring_fini(struct radeon_device *rdev);
544 struct radeon_cs_reloc {
545 struct drm_gem_object *gobj;
546 struct radeon_bo *robj;
547 struct radeon_bo_list lobj;
552 struct radeon_cs_chunk {
558 void __user *user_ptr;
559 int last_copied_page;
563 struct radeon_cs_parser {
565 struct radeon_device *rdev;
566 struct drm_file *filp;
569 struct radeon_cs_chunk *chunks;
570 uint64_t *chunks_array;
575 struct radeon_cs_reloc *relocs;
576 struct radeon_cs_reloc **relocs_ptr;
577 struct list_head validated;
578 /* indices of various chunks */
580 int chunk_relocs_idx;
581 struct radeon_ib *ib;
587 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
588 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
591 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
593 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
594 u32 pg_idx, pg_offset;
598 pg_idx = (idx * 4) / PAGE_SIZE;
599 pg_offset = (idx * 4) % PAGE_SIZE;
601 if (ibc->kpage_idx[0] == pg_idx)
602 return ibc->kpage[0][pg_offset/4];
603 if (ibc->kpage_idx[1] == pg_idx)
604 return ibc->kpage[1][pg_offset/4];
606 new_page = radeon_cs_update_pages(p, pg_idx);
608 p->parser_error = new_page;
612 idx_value = ibc->kpage[new_page][pg_offset/4];
616 struct radeon_cs_packet {
625 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
626 struct radeon_cs_packet *pkt,
627 unsigned idx, unsigned reg);
628 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
629 struct radeon_cs_packet *pkt);
635 int radeon_agp_init(struct radeon_device *rdev);
636 void radeon_agp_resume(struct radeon_device *rdev);
637 void radeon_agp_suspend(struct radeon_device *rdev);
638 void radeon_agp_fini(struct radeon_device *rdev);
645 struct radeon_bo *wb_obj;
646 volatile uint32_t *wb;
652 #define RADEON_WB_SCRATCH_OFFSET 0
653 #define RADEON_WB_CP_RPTR_OFFSET 1024
654 #define R600_WB_IH_WPTR_OFFSET 2048
655 #define R600_WB_EVENT_OFFSET 3072
658 * struct radeon_pm - power management datas
659 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
660 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
661 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
662 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
663 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
664 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
665 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
666 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
667 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
668 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
669 * @needed_bandwidth: current bandwidth needs
671 * It keeps track of various data needed to take powermanagement decision.
672 * Bandwith need is used to determine minimun clock of the GPU and memory.
673 * Equation between gpu/memory clock and available bandwidth is hw dependent
674 * (type of memory, bus size, efficiency, ...)
677 enum radeon_pm_method {
682 enum radeon_dynpm_state {
683 DYNPM_STATE_DISABLED,
687 DYNPM_STATE_SUSPENDED,
689 enum radeon_dynpm_action {
691 DYNPM_ACTION_MINIMUM,
692 DYNPM_ACTION_DOWNCLOCK,
693 DYNPM_ACTION_UPCLOCK,
697 enum radeon_voltage_type {
704 enum radeon_pm_state_type {
705 POWER_STATE_TYPE_DEFAULT,
706 POWER_STATE_TYPE_POWERSAVE,
707 POWER_STATE_TYPE_BATTERY,
708 POWER_STATE_TYPE_BALANCED,
709 POWER_STATE_TYPE_PERFORMANCE,
712 enum radeon_pm_profile_type {
720 #define PM_PROFILE_DEFAULT_IDX 0
721 #define PM_PROFILE_LOW_SH_IDX 1
722 #define PM_PROFILE_MID_SH_IDX 2
723 #define PM_PROFILE_HIGH_SH_IDX 3
724 #define PM_PROFILE_LOW_MH_IDX 4
725 #define PM_PROFILE_MID_MH_IDX 5
726 #define PM_PROFILE_HIGH_MH_IDX 6
727 #define PM_PROFILE_MAX 7
729 struct radeon_pm_profile {
736 enum radeon_int_thermal_type {
740 THERMAL_TYPE_EVERGREEN,
745 struct radeon_voltage {
746 enum radeon_voltage_type type;
748 struct radeon_gpio_rec gpio;
749 u32 delay; /* delay in usec from voltage drop to sclk change */
750 bool active_high; /* voltage drop is active when bit is high */
752 u8 vddc_id; /* index into vddc voltage table */
753 u8 vddci_id; /* index into vddci voltage table */
759 /* clock mode flags */
760 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
762 struct radeon_pm_clock_info {
768 struct radeon_voltage voltage;
769 /* standardized clock flags */
774 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
776 struct radeon_power_state {
777 enum radeon_pm_state_type type;
778 /* XXX: use a define for num clock modes */
779 struct radeon_pm_clock_info clock_info[8];
780 /* number of valid clock modes in this power state */
782 struct radeon_pm_clock_info *default_clock_mode;
783 /* standardized state flags */
785 u32 misc; /* vbios specific flags */
786 u32 misc2; /* vbios specific flags */
787 int pcie_lanes; /* pcie lanes */
791 * Some modes are overclocked by very low value, accept them
793 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
798 int active_crtc_count;
802 fixed20_12 max_bandwidth;
803 fixed20_12 igp_sideport_mclk;
804 fixed20_12 igp_system_mclk;
805 fixed20_12 igp_ht_link_clk;
806 fixed20_12 igp_ht_link_width;
807 fixed20_12 k8_bandwidth;
808 fixed20_12 sideport_bandwidth;
809 fixed20_12 ht_bandwidth;
810 fixed20_12 core_bandwidth;
813 fixed20_12 needed_bandwidth;
814 struct radeon_power_state *power_state;
815 /* number of valid power states */
816 int num_power_states;
817 int current_power_state_index;
818 int current_clock_mode_index;
819 int requested_power_state_index;
820 int requested_clock_mode_index;
821 int default_power_state_index;
828 struct radeon_i2c_chan *i2c_bus;
829 /* selected pm method */
830 enum radeon_pm_method pm_method;
831 /* dynpm power management */
832 struct delayed_work dynpm_idle_work;
833 enum radeon_dynpm_state dynpm_state;
834 enum radeon_dynpm_action dynpm_planned_action;
835 unsigned long dynpm_action_timeout;
836 bool dynpm_can_upclock;
837 bool dynpm_can_downclock;
838 /* profile-based power management */
839 enum radeon_pm_profile_type profile;
841 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
842 /* internal thermal controller on rv6xx+ */
843 enum radeon_int_thermal_type int_thermal_type;
844 struct device *int_hwmon_dev;
851 void radeon_benchmark(struct radeon_device *rdev);
857 void radeon_test_moves(struct radeon_device *rdev);
863 int radeon_debugfs_add_files(struct radeon_device *rdev,
864 struct drm_info_list *files,
866 int radeon_debugfs_fence_init(struct radeon_device *rdev);
870 * ASIC specific functions.
873 int (*init)(struct radeon_device *rdev);
874 void (*fini)(struct radeon_device *rdev);
875 int (*resume)(struct radeon_device *rdev);
876 int (*suspend)(struct radeon_device *rdev);
877 void (*vga_set_state)(struct radeon_device *rdev, bool state);
878 bool (*gpu_is_lockup)(struct radeon_device *rdev);
879 int (*asic_reset)(struct radeon_device *rdev);
880 void (*gart_tlb_flush)(struct radeon_device *rdev);
881 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
882 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
883 void (*cp_fini)(struct radeon_device *rdev);
884 void (*cp_disable)(struct radeon_device *rdev);
885 void (*cp_commit)(struct radeon_device *rdev);
886 void (*ring_start)(struct radeon_device *rdev);
887 int (*ring_test)(struct radeon_device *rdev);
888 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
889 int (*irq_set)(struct radeon_device *rdev);
890 int (*irq_process)(struct radeon_device *rdev);
891 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
892 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
893 int (*cs_parse)(struct radeon_cs_parser *p);
894 int (*copy_blit)(struct radeon_device *rdev,
898 struct radeon_fence *fence);
899 int (*copy_dma)(struct radeon_device *rdev,
903 struct radeon_fence *fence);
904 int (*copy)(struct radeon_device *rdev,
908 struct radeon_fence *fence);
909 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
910 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
911 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
912 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
913 int (*get_pcie_lanes)(struct radeon_device *rdev);
914 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
915 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
916 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
917 uint32_t tiling_flags, uint32_t pitch,
918 uint32_t offset, uint32_t obj_size);
919 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
920 void (*bandwidth_update)(struct radeon_device *rdev);
921 void (*hpd_init)(struct radeon_device *rdev);
922 void (*hpd_fini)(struct radeon_device *rdev);
923 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
924 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
925 /* ioctl hw specific callback. Some hw might want to perform special
926 * operation on specific ioctl. For instance on wait idle some hw
927 * might want to perform and HDP flush through MMIO as it seems that
928 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
931 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
932 bool (*gui_idle)(struct radeon_device *rdev);
933 /* power management */
934 void (*pm_misc)(struct radeon_device *rdev);
935 void (*pm_prepare)(struct radeon_device *rdev);
936 void (*pm_finish)(struct radeon_device *rdev);
937 void (*pm_init_profile)(struct radeon_device *rdev);
938 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
940 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
941 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
942 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
948 struct r100_gpu_lockup {
949 unsigned long last_jiffies;
954 const unsigned *reg_safe_bm;
955 unsigned reg_safe_bm_size;
957 struct r100_gpu_lockup lockup;
961 const unsigned *reg_safe_bm;
962 unsigned reg_safe_bm_size;
965 struct r100_gpu_lockup lockup;
970 unsigned max_tile_pipes;
972 unsigned max_backends;
974 unsigned max_threads;
975 unsigned max_stack_entries;
976 unsigned max_hw_contexts;
977 unsigned max_gs_threads;
978 unsigned sx_max_export_size;
979 unsigned sx_max_export_pos_size;
980 unsigned sx_max_export_smx_size;
981 unsigned sq_num_cf_insts;
982 unsigned tiling_nbanks;
983 unsigned tiling_npipes;
984 unsigned tiling_group_size;
985 unsigned tile_config;
986 struct r100_gpu_lockup lockup;
991 unsigned max_tile_pipes;
993 unsigned max_backends;
995 unsigned max_threads;
996 unsigned max_stack_entries;
997 unsigned max_hw_contexts;
998 unsigned max_gs_threads;
999 unsigned sx_max_export_size;
1000 unsigned sx_max_export_pos_size;
1001 unsigned sx_max_export_smx_size;
1002 unsigned sq_num_cf_insts;
1003 unsigned sx_num_of_sets;
1004 unsigned sc_prim_fifo_size;
1005 unsigned sc_hiz_tile_fifo_size;
1006 unsigned sc_earlyz_tile_fifo_fize;
1007 unsigned tiling_nbanks;
1008 unsigned tiling_npipes;
1009 unsigned tiling_group_size;
1010 unsigned tile_config;
1011 struct r100_gpu_lockup lockup;
1014 struct evergreen_asic {
1017 unsigned max_tile_pipes;
1019 unsigned max_backends;
1021 unsigned max_threads;
1022 unsigned max_stack_entries;
1023 unsigned max_hw_contexts;
1024 unsigned max_gs_threads;
1025 unsigned sx_max_export_size;
1026 unsigned sx_max_export_pos_size;
1027 unsigned sx_max_export_smx_size;
1028 unsigned sq_num_cf_insts;
1029 unsigned sx_num_of_sets;
1030 unsigned sc_prim_fifo_size;
1031 unsigned sc_hiz_tile_fifo_size;
1032 unsigned sc_earlyz_tile_fifo_size;
1033 unsigned tiling_nbanks;
1034 unsigned tiling_npipes;
1035 unsigned tiling_group_size;
1036 unsigned tile_config;
1037 struct r100_gpu_lockup lockup;
1040 union radeon_asic_config {
1041 struct r300_asic r300;
1042 struct r100_asic r100;
1043 struct r600_asic r600;
1044 struct rv770_asic rv770;
1045 struct evergreen_asic evergreen;
1049 * asic initizalization from radeon_asic.c
1051 void radeon_agp_disable(struct radeon_device *rdev);
1052 int radeon_asic_init(struct radeon_device *rdev);
1058 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1059 struct drm_file *filp);
1060 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1061 struct drm_file *filp);
1062 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1063 struct drm_file *file_priv);
1064 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1065 struct drm_file *file_priv);
1066 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1067 struct drm_file *file_priv);
1068 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1069 struct drm_file *file_priv);
1070 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1071 struct drm_file *filp);
1072 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1073 struct drm_file *filp);
1074 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1075 struct drm_file *filp);
1076 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1077 struct drm_file *filp);
1078 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1079 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1080 struct drm_file *filp);
1081 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1082 struct drm_file *filp);
1084 /* VRAM scratch page for HDP bug */
1085 struct r700_vram_scratch {
1086 struct radeon_bo *robj;
1087 volatile uint32_t *ptr;
1091 * Core structure, functions and helpers.
1093 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1094 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1096 struct radeon_device {
1098 struct drm_device *ddev;
1099 struct pci_dev *pdev;
1101 union radeon_asic_config config;
1102 enum radeon_family family;
1103 unsigned long flags;
1105 enum radeon_pll_errata pll_errata;
1112 uint16_t bios_header_start;
1113 struct radeon_bo *stollen_vga_memory;
1115 resource_size_t rmmio_base;
1116 resource_size_t rmmio_size;
1118 radeon_rreg_t mc_rreg;
1119 radeon_wreg_t mc_wreg;
1120 radeon_rreg_t pll_rreg;
1121 radeon_wreg_t pll_wreg;
1122 uint32_t pcie_reg_mask;
1123 radeon_rreg_t pciep_rreg;
1124 radeon_wreg_t pciep_wreg;
1126 void __iomem *rio_mem;
1127 resource_size_t rio_mem_size;
1128 struct radeon_clock clock;
1129 struct radeon_mc mc;
1130 struct radeon_gart gart;
1131 struct radeon_mode_info mode_info;
1132 struct radeon_scratch scratch;
1133 struct radeon_mman mman;
1134 struct radeon_fence_driver fence_drv;
1135 struct radeon_cp cp;
1136 struct radeon_ib_pool ib_pool;
1137 struct radeon_irq irq;
1138 struct radeon_asic *asic;
1139 struct radeon_gem gem;
1140 struct radeon_pm pm;
1141 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1142 struct mutex cs_mutex;
1143 struct radeon_wb wb;
1144 struct radeon_dummy_page dummy_page;
1150 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1151 const struct firmware *me_fw; /* all family ME firmware */
1152 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1153 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1154 const struct firmware *mc_fw; /* NI MC firmware */
1155 struct r600_blit r600_blit;
1156 struct r700_vram_scratch vram_scratch;
1157 int msi_enabled; /* msi enabled */
1158 struct r600_ih ih; /* r6/700 interrupt ring */
1159 struct work_struct hotplug_work;
1160 int num_crtc; /* number of crtcs */
1161 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1162 struct mutex vram_mutex;
1166 struct timer_list audio_timer;
1169 int audio_bits_per_sample;
1170 uint8_t audio_status_bits;
1171 uint8_t audio_category_code;
1173 struct notifier_block acpi_nb;
1174 /* only one userspace can use Hyperz features or CMASK at a time */
1175 struct drm_file *hyperz_filp;
1176 struct drm_file *cmask_filp;
1178 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1181 int radeon_device_init(struct radeon_device *rdev,
1182 struct drm_device *ddev,
1183 struct pci_dev *pdev,
1185 void radeon_device_fini(struct radeon_device *rdev);
1186 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1189 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1190 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1191 void r600_kms_blit_copy(struct radeon_device *rdev,
1192 u64 src_gpu_addr, u64 dst_gpu_addr,
1194 /* evergreen blit */
1195 int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1196 void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1197 void evergreen_kms_blit_copy(struct radeon_device *rdev,
1198 u64 src_gpu_addr, u64 dst_gpu_addr,
1201 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1203 if (reg < rdev->rmmio_size)
1204 return readl(((void __iomem *)rdev->rmmio) + reg);
1206 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1207 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1211 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1213 if (reg < rdev->rmmio_size)
1214 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1216 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1217 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1221 static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
1223 if (reg < rdev->rio_mem_size)
1224 return ioread32(rdev->rio_mem + reg);
1226 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1227 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
1231 static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1233 if (reg < rdev->rio_mem_size)
1234 iowrite32(v, rdev->rio_mem + reg);
1236 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1237 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
1244 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1247 * Registers read & write functions.
1249 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1250 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1251 #define RREG16(reg) readw(((void __iomem *)rdev->rmmio) + (reg))
1252 #define WREG16(reg, v) writew(v, ((void __iomem *)rdev->rmmio) + (reg))
1253 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1254 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1255 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1256 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1257 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1258 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1259 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1260 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1261 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1262 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1263 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1264 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1265 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1266 #define WREG32_P(reg, val, mask) \
1268 uint32_t tmp_ = RREG32(reg); \
1270 tmp_ |= ((val) & ~(mask)); \
1271 WREG32(reg, tmp_); \
1273 #define WREG32_PLL_P(reg, val, mask) \
1275 uint32_t tmp_ = RREG32_PLL(reg); \
1277 tmp_ |= ((val) & ~(mask)); \
1278 WREG32_PLL(reg, tmp_); \
1280 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1281 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1282 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1285 * Indirect registers accessor
1287 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1291 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1292 r = RREG32(RADEON_PCIE_DATA);
1296 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1298 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1299 WREG32(RADEON_PCIE_DATA, (v));
1302 void r100_pll_errata_after_index(struct radeon_device *rdev);
1308 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1309 (rdev->pdev->device == 0x5969))
1310 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1311 (rdev->family == CHIP_RV200) || \
1312 (rdev->family == CHIP_RS100) || \
1313 (rdev->family == CHIP_RS200) || \
1314 (rdev->family == CHIP_RV250) || \
1315 (rdev->family == CHIP_RV280) || \
1316 (rdev->family == CHIP_RS300))
1317 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1318 (rdev->family == CHIP_RV350) || \
1319 (rdev->family == CHIP_R350) || \
1320 (rdev->family == CHIP_RV380) || \
1321 (rdev->family == CHIP_R420) || \
1322 (rdev->family == CHIP_R423) || \
1323 (rdev->family == CHIP_RV410) || \
1324 (rdev->family == CHIP_RS400) || \
1325 (rdev->family == CHIP_RS480))
1326 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1327 (rdev->ddev->pdev->device == 0x9443) || \
1328 (rdev->ddev->pdev->device == 0x944B) || \
1329 (rdev->ddev->pdev->device == 0x9506) || \
1330 (rdev->ddev->pdev->device == 0x9509) || \
1331 (rdev->ddev->pdev->device == 0x950F) || \
1332 (rdev->ddev->pdev->device == 0x689C) || \
1333 (rdev->ddev->pdev->device == 0x689D))
1334 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1335 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1336 (rdev->family == CHIP_RS690) || \
1337 (rdev->family == CHIP_RS740) || \
1338 (rdev->family >= CHIP_R600))
1339 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1340 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1341 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1342 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1343 (rdev->flags & RADEON_IS_IGP))
1344 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1349 #define RBIOS8(i) (rdev->bios[i])
1350 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1351 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1353 int radeon_combios_init(struct radeon_device *rdev);
1354 void radeon_combios_fini(struct radeon_device *rdev);
1355 int radeon_atombios_init(struct radeon_device *rdev);
1356 void radeon_atombios_fini(struct radeon_device *rdev);
1362 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1365 if (rdev->cp.count_dw <= 0) {
1366 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1369 rdev->cp.ring[rdev->cp.wptr++] = v;
1370 rdev->cp.wptr &= rdev->cp.ptr_mask;
1371 rdev->cp.count_dw--;
1372 rdev->cp.ring_free_dw--;
1379 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1380 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1381 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1382 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1383 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1384 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1385 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1386 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1387 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1388 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1389 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1390 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1391 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1392 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1393 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1394 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1395 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1396 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1397 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1398 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1399 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1400 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1401 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1402 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1403 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1404 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1405 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1406 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1407 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1408 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1409 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1410 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1411 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1412 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1413 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1414 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1415 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1416 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1417 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1418 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1419 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1420 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1421 #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1422 #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
1424 /* Common functions */
1426 extern int radeon_gpu_reset(struct radeon_device *rdev);
1427 extern void radeon_agp_disable(struct radeon_device *rdev);
1428 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1429 extern void radeon_gart_restore(struct radeon_device *rdev);
1430 extern int radeon_modeset_init(struct radeon_device *rdev);
1431 extern void radeon_modeset_fini(struct radeon_device *rdev);
1432 extern bool radeon_card_posted(struct radeon_device *rdev);
1433 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1434 extern void radeon_update_display_priority(struct radeon_device *rdev);
1435 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1436 extern void radeon_scratch_init(struct radeon_device *rdev);
1437 extern void radeon_wb_fini(struct radeon_device *rdev);
1438 extern int radeon_wb_init(struct radeon_device *rdev);
1439 extern void radeon_wb_disable(struct radeon_device *rdev);
1440 extern void radeon_surface_init(struct radeon_device *rdev);
1441 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1442 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1443 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1444 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1445 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1446 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1447 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1448 extern int radeon_resume_kms(struct drm_device *dev);
1449 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1450 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1452 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1453 extern bool r600_card_posted(struct radeon_device *rdev);
1454 extern void r600_cp_stop(struct radeon_device *rdev);
1455 extern int r600_cp_start(struct radeon_device *rdev);
1456 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1457 extern int r600_cp_resume(struct radeon_device *rdev);
1458 extern void r600_cp_fini(struct radeon_device *rdev);
1459 extern int r600_count_pipe_bits(uint32_t val);
1460 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1461 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1462 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1463 extern int r600_ib_test(struct radeon_device *rdev);
1464 extern int r600_ring_test(struct radeon_device *rdev);
1465 extern void r600_scratch_init(struct radeon_device *rdev);
1466 extern int r600_blit_init(struct radeon_device *rdev);
1467 extern void r600_blit_fini(struct radeon_device *rdev);
1468 extern int r600_init_microcode(struct radeon_device *rdev);
1469 extern int r600_asic_reset(struct radeon_device *rdev);
1471 extern int r600_irq_init(struct radeon_device *rdev);
1472 extern void r600_irq_fini(struct radeon_device *rdev);
1473 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1474 extern int r600_irq_set(struct radeon_device *rdev);
1475 extern void r600_irq_suspend(struct radeon_device *rdev);
1476 extern void r600_disable_interrupts(struct radeon_device *rdev);
1477 extern void r600_rlc_stop(struct radeon_device *rdev);
1479 extern int r600_audio_init(struct radeon_device *rdev);
1480 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1481 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1482 extern int r600_audio_channels(struct radeon_device *rdev);
1483 extern int r600_audio_bits_per_sample(struct radeon_device *rdev);
1484 extern int r600_audio_rate(struct radeon_device *rdev);
1485 extern uint8_t r600_audio_status_bits(struct radeon_device *rdev);
1486 extern uint8_t r600_audio_category_code(struct radeon_device *rdev);
1487 extern void r600_audio_schedule_polling(struct radeon_device *rdev);
1488 extern void r600_audio_enable_polling(struct drm_encoder *encoder);
1489 extern void r600_audio_disable_polling(struct drm_encoder *encoder);
1490 extern void r600_audio_fini(struct radeon_device *rdev);
1491 extern void r600_hdmi_init(struct drm_encoder *encoder);
1492 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1493 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1494 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1495 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1496 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
1498 extern void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1499 extern void r700_cp_stop(struct radeon_device *rdev);
1500 extern void r700_cp_fini(struct radeon_device *rdev);
1501 extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
1502 extern int evergreen_irq_set(struct radeon_device *rdev);
1503 extern int evergreen_blit_init(struct radeon_device *rdev);
1504 extern void evergreen_blit_fini(struct radeon_device *rdev);
1506 extern int ni_init_microcode(struct radeon_device *rdev);
1507 extern int btc_mc_load_microcode(struct radeon_device *rdev);
1510 #if defined(CONFIG_ACPI)
1511 extern int radeon_acpi_init(struct radeon_device *rdev);
1513 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1517 struct evergreen_mc_save {
1519 u32 vga_render_control;
1520 u32 vga_hdp_control;
1521 u32 crtc_control[6];
1524 #include "radeon_object.h"