2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
100 extern int radeon_aspm;
103 * Copy from radeon_drv.h so we don't have to include both and have conflicting
106 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
107 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
108 /* RADEON_IB_POOL_SIZE must be a power of 2 */
109 #define RADEON_IB_POOL_SIZE 16
110 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
111 #define RADEONFB_CONN_LIMIT 4
112 #define RADEON_BIOS_NUM_SCRATCH 8
114 /* max number of rings */
115 #define RADEON_NUM_RINGS 6
117 /* fence seq are set to this number when signaled */
118 #define RADEON_FENCE_SIGNALED_SEQ 0LL
120 /* internal ring indices */
121 /* r1xx+ has gfx CP ring */
122 #define RADEON_RING_TYPE_GFX_INDEX 0
124 /* cayman has 2 compute CP rings */
125 #define CAYMAN_RING_TYPE_CP1_INDEX 1
126 #define CAYMAN_RING_TYPE_CP2_INDEX 2
128 /* R600+ has an async dma ring */
129 #define R600_RING_TYPE_DMA_INDEX 3
130 /* cayman add a second async dma ring */
131 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
134 #define R600_RING_TYPE_UVD_INDEX 5
136 /* hardcode those limit for now */
137 #define RADEON_VA_IB_OFFSET (1 << 20)
138 #define RADEON_VA_RESERVED_SIZE (8 << 20)
139 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
142 #define RADEON_RESET_GFX (1 << 0)
143 #define RADEON_RESET_COMPUTE (1 << 1)
144 #define RADEON_RESET_DMA (1 << 2)
145 #define RADEON_RESET_CP (1 << 3)
146 #define RADEON_RESET_GRBM (1 << 4)
147 #define RADEON_RESET_DMA1 (1 << 5)
148 #define RADEON_RESET_RLC (1 << 6)
149 #define RADEON_RESET_SEM (1 << 7)
150 #define RADEON_RESET_IH (1 << 8)
151 #define RADEON_RESET_VMC (1 << 9)
152 #define RADEON_RESET_MC (1 << 10)
153 #define RADEON_RESET_DISPLAY (1 << 11)
155 /* max cursor sizes (in pixels) */
156 #define CURSOR_WIDTH 64
157 #define CURSOR_HEIGHT 64
159 #define CIK_CURSOR_WIDTH 128
160 #define CIK_CURSOR_HEIGHT 128
163 * Errata workarounds.
165 enum radeon_pll_errata {
166 CHIP_ERRATA_R300_CG = 0x00000001,
167 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
168 CHIP_ERRATA_PLL_DELAY = 0x00000004
172 struct radeon_device;
178 bool radeon_get_bios(struct radeon_device *rdev);
183 struct radeon_dummy_page {
187 int radeon_dummy_page_init(struct radeon_device *rdev);
188 void radeon_dummy_page_fini(struct radeon_device *rdev);
194 struct radeon_clock {
195 struct radeon_pll p1pll;
196 struct radeon_pll p2pll;
197 struct radeon_pll dcpll;
198 struct radeon_pll spll;
199 struct radeon_pll mpll;
201 uint32_t default_mclk;
202 uint32_t default_sclk;
203 uint32_t default_dispclk;
204 uint32_t current_dispclk;
206 uint32_t max_pixel_clock;
212 int radeon_pm_init(struct radeon_device *rdev);
213 void radeon_pm_fini(struct radeon_device *rdev);
214 void radeon_pm_compute_clocks(struct radeon_device *rdev);
215 void radeon_pm_suspend(struct radeon_device *rdev);
216 void radeon_pm_resume(struct radeon_device *rdev);
217 void radeon_combios_get_power_modes(struct radeon_device *rdev);
218 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
219 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
223 struct atom_clock_dividers *dividers);
224 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
227 struct atom_mpll_param *mpll_param);
228 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
229 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
230 u16 voltage_level, u8 voltage_type,
231 u32 *gpio_value, u32 *gpio_mask);
232 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
233 u32 eng_clock, u32 mem_clock);
234 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
235 u8 voltage_type, u16 *voltage_step);
236 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
237 u16 voltage_id, u16 *voltage);
238 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
241 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
245 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
246 u8 voltage_type, u16 *min_voltage);
247 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
248 u8 voltage_type, u16 *max_voltage);
249 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
250 u8 voltage_type, u8 voltage_mode,
251 struct atom_voltage_table *voltage_table);
252 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
253 u8 voltage_type, u8 voltage_mode);
254 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
256 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
258 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
260 struct atom_mc_reg_table *reg_table);
261 int radeon_atom_get_memory_info(struct radeon_device *rdev,
262 u8 module_index, struct atom_memory_info *mem_info);
263 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
264 bool gddr5, u8 module_index,
265 struct atom_memory_clock_range_table *mclk_range_table);
266 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
267 u16 voltage_id, u16 *voltage);
268 void rs690_pm_info(struct radeon_device *rdev);
269 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
270 unsigned *bankh, unsigned *mtaspect,
271 unsigned *tile_split);
276 struct radeon_fence_driver {
277 uint32_t scratch_reg;
279 volatile uint32_t *cpu_addr;
280 /* sync_seq is protected by ring emission lock */
281 uint64_t sync_seq[RADEON_NUM_RINGS];
283 unsigned long last_activity;
287 struct radeon_fence {
288 struct radeon_device *rdev;
290 /* protected by radeon_fence.lock */
296 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
297 int radeon_fence_driver_init(struct radeon_device *rdev);
298 void radeon_fence_driver_fini(struct radeon_device *rdev);
299 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
300 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
301 void radeon_fence_process(struct radeon_device *rdev, int ring);
302 bool radeon_fence_signaled(struct radeon_fence *fence);
303 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
304 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
305 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
306 int radeon_fence_wait_any(struct radeon_device *rdev,
307 struct radeon_fence **fences,
309 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
310 void radeon_fence_unref(struct radeon_fence **fence);
311 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
312 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
313 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
314 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
315 struct radeon_fence *b)
325 BUG_ON(a->ring != b->ring);
327 if (a->seq > b->seq) {
334 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
335 struct radeon_fence *b)
345 BUG_ON(a->ring != b->ring);
347 return a->seq < b->seq;
353 struct radeon_surface_reg {
354 struct radeon_bo *bo;
357 #define RADEON_GEM_MAX_SURFACES 8
363 struct ttm_bo_global_ref bo_global_ref;
364 struct drm_global_reference mem_global_ref;
365 struct ttm_bo_device bdev;
366 bool mem_global_referenced;
370 /* bo virtual address in a specific vm */
371 struct radeon_bo_va {
372 /* protected by bo being reserved */
373 struct list_head bo_list;
380 /* protected by vm mutex */
381 struct list_head vm_list;
383 /* constant after initialization */
384 struct radeon_vm *vm;
385 struct radeon_bo *bo;
389 /* Protected by gem.mutex */
390 struct list_head list;
391 /* Protected by tbo.reserved */
393 struct ttm_placement placement;
394 struct ttm_buffer_object tbo;
395 struct ttm_bo_kmap_obj kmap;
401 /* list of all virtual address to which this bo
405 /* Constant after initialization */
406 struct radeon_device *rdev;
407 struct drm_gem_object gem_base;
409 struct ttm_bo_kmap_obj dma_buf_vmap;
412 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
414 struct radeon_bo_list {
415 struct ttm_validate_buffer tv;
416 struct radeon_bo *bo;
424 int radeon_gem_debugfs_init(struct radeon_device *rdev);
426 /* sub-allocation manager, it has to be protected by another lock.
427 * By conception this is an helper for other part of the driver
428 * like the indirect buffer or semaphore, which both have their
431 * Principe is simple, we keep a list of sub allocation in offset
432 * order (first entry has offset == 0, last entry has the highest
435 * When allocating new object we first check if there is room at
436 * the end total_size - (last_object_offset + last_object_size) >=
437 * alloc_size. If so we allocate new object there.
439 * When there is not enough room at the end, we start waiting for
440 * each sub object until we reach object_offset+object_size >=
441 * alloc_size, this object then become the sub object we return.
443 * Alignment can't be bigger than page size.
445 * Hole are not considered for allocation to keep things simple.
446 * Assumption is that there won't be hole (all object on same
449 struct radeon_sa_manager {
450 wait_queue_head_t wq;
451 struct radeon_bo *bo;
452 struct list_head *hole;
453 struct list_head flist[RADEON_NUM_RINGS];
454 struct list_head olist;
464 /* sub-allocation buffer */
465 struct radeon_sa_bo {
466 struct list_head olist;
467 struct list_head flist;
468 struct radeon_sa_manager *manager;
471 struct radeon_fence *fence;
479 struct list_head objects;
482 int radeon_gem_init(struct radeon_device *rdev);
483 void radeon_gem_fini(struct radeon_device *rdev);
484 int radeon_gem_object_create(struct radeon_device *rdev, int size,
485 int alignment, int initial_domain,
486 bool discardable, bool kernel,
487 struct drm_gem_object **obj);
489 int radeon_mode_dumb_create(struct drm_file *file_priv,
490 struct drm_device *dev,
491 struct drm_mode_create_dumb *args);
492 int radeon_mode_dumb_mmap(struct drm_file *filp,
493 struct drm_device *dev,
494 uint32_t handle, uint64_t *offset_p);
495 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
496 struct drm_device *dev,
502 /* everything here is constant */
503 struct radeon_semaphore {
504 struct radeon_sa_bo *sa_bo;
509 int radeon_semaphore_create(struct radeon_device *rdev,
510 struct radeon_semaphore **semaphore);
511 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
512 struct radeon_semaphore *semaphore);
513 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
514 struct radeon_semaphore *semaphore);
515 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
516 struct radeon_semaphore *semaphore,
517 int signaler, int waiter);
518 void radeon_semaphore_free(struct radeon_device *rdev,
519 struct radeon_semaphore **semaphore,
520 struct radeon_fence *fence);
523 * GART structures, functions & helpers
527 #define RADEON_GPU_PAGE_SIZE 4096
528 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
529 #define RADEON_GPU_PAGE_SHIFT 12
530 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
533 dma_addr_t table_addr;
534 struct radeon_bo *robj;
536 unsigned num_gpu_pages;
537 unsigned num_cpu_pages;
540 dma_addr_t *pages_addr;
544 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
545 void radeon_gart_table_ram_free(struct radeon_device *rdev);
546 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
547 void radeon_gart_table_vram_free(struct radeon_device *rdev);
548 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
549 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
550 int radeon_gart_init(struct radeon_device *rdev);
551 void radeon_gart_fini(struct radeon_device *rdev);
552 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
554 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
555 int pages, struct page **pagelist,
556 dma_addr_t *dma_addr);
557 void radeon_gart_restore(struct radeon_device *rdev);
561 * GPU MC structures, functions & helpers
564 resource_size_t aper_size;
565 resource_size_t aper_base;
566 resource_size_t agp_base;
567 /* for some chips with <= 32MB we need to lie
568 * about vram size near mc fb location */
570 u64 visible_vram_size;
580 bool igp_sideport_enabled;
585 bool radeon_combios_sideport_present(struct radeon_device *rdev);
586 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
589 * GPU scratch registers structures, functions & helpers
591 struct radeon_scratch {
598 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
599 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
602 * GPU doorbell structures, functions & helpers
604 struct radeon_doorbell {
608 resource_size_t base;
609 resource_size_t size;
613 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
614 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
620 struct radeon_unpin_work {
621 struct work_struct work;
622 struct radeon_device *rdev;
624 struct radeon_fence *fence;
625 struct drm_pending_vblank_event *event;
626 struct radeon_bo *old_rbo;
630 struct r500_irq_stat_regs {
635 struct r600_irq_stat_regs {
645 struct evergreen_irq_stat_regs {
666 struct cik_irq_stat_regs {
676 union radeon_irq_stat_regs {
677 struct r500_irq_stat_regs r500;
678 struct r600_irq_stat_regs r600;
679 struct evergreen_irq_stat_regs evergreen;
680 struct cik_irq_stat_regs cik;
683 #define RADEON_MAX_HPD_PINS 6
684 #define RADEON_MAX_CRTCS 6
685 #define RADEON_MAX_AFMT_BLOCKS 6
690 atomic_t ring_int[RADEON_NUM_RINGS];
691 bool crtc_vblank_int[RADEON_MAX_CRTCS];
692 atomic_t pflip[RADEON_MAX_CRTCS];
693 wait_queue_head_t vblank_queue;
694 bool hpd[RADEON_MAX_HPD_PINS];
695 bool afmt[RADEON_MAX_AFMT_BLOCKS];
696 union radeon_irq_stat_regs stat_regs;
700 int radeon_irq_kms_init(struct radeon_device *rdev);
701 void radeon_irq_kms_fini(struct radeon_device *rdev);
702 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
703 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
704 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
705 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
706 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
707 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
708 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
709 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
716 struct radeon_sa_bo *sa_bo;
721 struct radeon_fence *fence;
722 struct radeon_vm *vm;
724 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
725 struct radeon_semaphore *semaphore;
729 struct radeon_bo *ring_obj;
730 volatile uint32_t *ring;
734 unsigned rptr_save_reg;
735 u64 next_rptr_gpu_addr;
736 volatile u32 *next_rptr_cpu_addr;
741 unsigned ring_free_dw;
743 unsigned long last_activity;
753 u64 last_semaphore_signal_addr;
754 u64 last_semaphore_wait_addr;
759 struct radeon_bo *mqd_obj;
760 u32 doorbell_page_num;
766 struct radeon_bo *hpd_eop_obj;
767 u64 hpd_eop_gpu_addr;
777 /* maximum number of VMIDs */
778 #define RADEON_NUM_VM 16
780 /* defines number of bits in page table versus page directory,
781 * a page is 4KB so we have 12 bits offset, 9 bits in the page
782 * table and the remaining 19 bits are in the page directory */
783 #define RADEON_VM_BLOCK_SIZE 9
785 /* number of entries in page table */
786 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
788 /* PTBs (Page Table Blocks) need to be aligned to 32K */
789 #define RADEON_VM_PTB_ALIGN_SIZE 32768
790 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
791 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
794 struct list_head list;
798 /* contains the page directory */
799 struct radeon_sa_bo *page_directory;
800 uint64_t pd_gpu_addr;
802 /* array of page tables, one for each page directory entry */
803 struct radeon_sa_bo **page_tables;
806 /* last fence for cs using this vm */
807 struct radeon_fence *fence;
808 /* last flush or NULL if we still need to flush */
809 struct radeon_fence *last_flush;
812 struct radeon_vm_manager {
814 struct list_head lru_vm;
815 struct radeon_fence *active[RADEON_NUM_VM];
816 struct radeon_sa_manager sa_manager;
818 /* number of VMIDs */
820 /* vram base address for page table entry */
821 u64 vram_base_offset;
827 * file private structure
829 struct radeon_fpriv {
837 struct radeon_bo *ring_obj;
838 volatile uint32_t *ring;
850 #include "clearstate_defs.h"
853 /* for power gating */
854 struct radeon_bo *save_restore_obj;
855 uint64_t save_restore_gpu_addr;
856 volatile uint32_t *sr_ptr;
859 /* for clear state */
860 struct radeon_bo *clear_state_obj;
861 uint64_t clear_state_gpu_addr;
862 volatile uint32_t *cs_ptr;
863 const struct cs_section_def *cs_data;
866 int radeon_ib_get(struct radeon_device *rdev, int ring,
867 struct radeon_ib *ib, struct radeon_vm *vm,
869 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
870 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
871 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
872 struct radeon_ib *const_ib);
873 int radeon_ib_pool_init(struct radeon_device *rdev);
874 void radeon_ib_pool_fini(struct radeon_device *rdev);
875 int radeon_ib_ring_tests(struct radeon_device *rdev);
876 /* Ring access between begin & end cannot sleep */
877 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
878 struct radeon_ring *ring);
879 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
880 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
881 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
882 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
883 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
884 void radeon_ring_undo(struct radeon_ring *ring);
885 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
886 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
887 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
888 void radeon_ring_lockup_update(struct radeon_ring *ring);
889 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
890 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
892 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
893 unsigned size, uint32_t *data);
894 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
895 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
896 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
897 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
901 void r600_dma_stop(struct radeon_device *rdev);
902 int r600_dma_resume(struct radeon_device *rdev);
903 void r600_dma_fini(struct radeon_device *rdev);
905 void cayman_dma_stop(struct radeon_device *rdev);
906 int cayman_dma_resume(struct radeon_device *rdev);
907 void cayman_dma_fini(struct radeon_device *rdev);
912 struct radeon_cs_reloc {
913 struct drm_gem_object *gobj;
914 struct radeon_bo *robj;
915 struct radeon_bo_list lobj;
920 struct radeon_cs_chunk {
926 void __user *user_ptr;
927 int last_copied_page;
931 struct radeon_cs_parser {
933 struct radeon_device *rdev;
934 struct drm_file *filp;
937 struct radeon_cs_chunk *chunks;
938 uint64_t *chunks_array;
943 struct radeon_cs_reloc *relocs;
944 struct radeon_cs_reloc **relocs_ptr;
945 struct list_head validated;
946 unsigned dma_reloc_idx;
947 /* indices of various chunks */
949 int chunk_relocs_idx;
951 int chunk_const_ib_idx;
953 struct radeon_ib const_ib;
960 struct ww_acquire_ctx ticket;
963 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
964 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
966 struct radeon_cs_packet {
975 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
976 struct radeon_cs_packet *pkt,
977 unsigned idx, unsigned reg);
978 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
979 struct radeon_cs_packet *pkt);
985 int radeon_agp_init(struct radeon_device *rdev);
986 void radeon_agp_resume(struct radeon_device *rdev);
987 void radeon_agp_suspend(struct radeon_device *rdev);
988 void radeon_agp_fini(struct radeon_device *rdev);
995 struct radeon_bo *wb_obj;
996 volatile uint32_t *wb;
1002 #define RADEON_WB_SCRATCH_OFFSET 0
1003 #define RADEON_WB_RING0_NEXT_RPTR 256
1004 #define RADEON_WB_CP_RPTR_OFFSET 1024
1005 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1006 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1007 #define R600_WB_DMA_RPTR_OFFSET 1792
1008 #define R600_WB_IH_WPTR_OFFSET 2048
1009 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1010 #define R600_WB_UVD_RPTR_OFFSET 2560
1011 #define R600_WB_EVENT_OFFSET 3072
1012 #define CIK_WB_CP1_WPTR_OFFSET 3328
1013 #define CIK_WB_CP2_WPTR_OFFSET 3584
1016 * struct radeon_pm - power management datas
1017 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1018 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1019 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1020 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1021 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1022 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1023 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1024 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1025 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1026 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1027 * @needed_bandwidth: current bandwidth needs
1029 * It keeps track of various data needed to take powermanagement decision.
1030 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1031 * Equation between gpu/memory clock and available bandwidth is hw dependent
1032 * (type of memory, bus size, efficiency, ...)
1035 enum radeon_pm_method {
1041 enum radeon_dynpm_state {
1042 DYNPM_STATE_DISABLED,
1043 DYNPM_STATE_MINIMUM,
1046 DYNPM_STATE_SUSPENDED,
1048 enum radeon_dynpm_action {
1050 DYNPM_ACTION_MINIMUM,
1051 DYNPM_ACTION_DOWNCLOCK,
1052 DYNPM_ACTION_UPCLOCK,
1053 DYNPM_ACTION_DEFAULT
1056 enum radeon_voltage_type {
1063 enum radeon_pm_state_type {
1064 /* not used for dpm */
1065 POWER_STATE_TYPE_DEFAULT,
1066 POWER_STATE_TYPE_POWERSAVE,
1067 /* user selectable states */
1068 POWER_STATE_TYPE_BATTERY,
1069 POWER_STATE_TYPE_BALANCED,
1070 POWER_STATE_TYPE_PERFORMANCE,
1071 /* internal states */
1072 POWER_STATE_TYPE_INTERNAL_UVD,
1073 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1074 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1075 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1076 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1077 POWER_STATE_TYPE_INTERNAL_BOOT,
1078 POWER_STATE_TYPE_INTERNAL_THERMAL,
1079 POWER_STATE_TYPE_INTERNAL_ACPI,
1080 POWER_STATE_TYPE_INTERNAL_ULV,
1081 POWER_STATE_TYPE_INTERNAL_3DPERF,
1084 enum radeon_pm_profile_type {
1092 #define PM_PROFILE_DEFAULT_IDX 0
1093 #define PM_PROFILE_LOW_SH_IDX 1
1094 #define PM_PROFILE_MID_SH_IDX 2
1095 #define PM_PROFILE_HIGH_SH_IDX 3
1096 #define PM_PROFILE_LOW_MH_IDX 4
1097 #define PM_PROFILE_MID_MH_IDX 5
1098 #define PM_PROFILE_HIGH_MH_IDX 6
1099 #define PM_PROFILE_MAX 7
1101 struct radeon_pm_profile {
1102 int dpms_off_ps_idx;
1104 int dpms_off_cm_idx;
1108 enum radeon_int_thermal_type {
1110 THERMAL_TYPE_EXTERNAL,
1111 THERMAL_TYPE_EXTERNAL_GPIO,
1114 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1115 THERMAL_TYPE_EVERGREEN,
1119 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1123 struct radeon_voltage {
1124 enum radeon_voltage_type type;
1126 struct radeon_gpio_rec gpio;
1127 u32 delay; /* delay in usec from voltage drop to sclk change */
1128 bool active_high; /* voltage drop is active when bit is high */
1130 u8 vddc_id; /* index into vddc voltage table */
1131 u8 vddci_id; /* index into vddci voltage table */
1135 /* evergreen+ vddci */
1139 /* clock mode flags */
1140 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1142 struct radeon_pm_clock_info {
1148 struct radeon_voltage voltage;
1149 /* standardized clock flags */
1154 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1156 struct radeon_power_state {
1157 enum radeon_pm_state_type type;
1158 struct radeon_pm_clock_info *clock_info;
1159 /* number of valid clock modes in this power state */
1160 int num_clock_modes;
1161 struct radeon_pm_clock_info *default_clock_mode;
1162 /* standardized state flags */
1164 u32 misc; /* vbios specific flags */
1165 u32 misc2; /* vbios specific flags */
1166 int pcie_lanes; /* pcie lanes */
1170 * Some modes are overclocked by very low value, accept them
1172 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1174 enum radeon_dpm_auto_throttle_src {
1175 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1176 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1179 enum radeon_dpm_event_src {
1180 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1181 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1182 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1183 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1184 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1188 u32 caps; /* vbios flags */
1189 u32 class; /* vbios flags */
1190 u32 class2; /* vbios flags */
1198 struct radeon_dpm_thermal {
1199 /* thermal interrupt work */
1200 struct work_struct work;
1201 /* low temperature threshold */
1203 /* high temperature threshold */
1205 /* was interrupt low to high or high to low */
1209 enum radeon_clk_action
1215 struct radeon_blacklist_clocks
1219 enum radeon_clk_action action;
1222 struct radeon_clock_and_voltage_limits {
1229 struct radeon_clock_array {
1234 struct radeon_clock_voltage_dependency_entry {
1239 struct radeon_clock_voltage_dependency_table {
1241 struct radeon_clock_voltage_dependency_entry *entries;
1244 struct radeon_cac_leakage_entry {
1249 struct radeon_cac_leakage_table {
1251 struct radeon_cac_leakage_entry *entries;
1254 struct radeon_phase_shedding_limits_entry {
1260 struct radeon_phase_shedding_limits_table {
1262 struct radeon_phase_shedding_limits_entry *entries;
1265 struct radeon_ppm_table {
1267 u16 cpu_core_number;
1269 u32 small_ac_platform_tdp;
1271 u32 small_ac_platform_tdc;
1278 struct radeon_dpm_dynamic_state {
1279 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1280 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1281 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1282 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1283 struct radeon_clock_array valid_sclk_values;
1284 struct radeon_clock_array valid_mclk_values;
1285 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1286 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1287 u32 mclk_sclk_ratio;
1288 u32 sclk_mclk_delta;
1289 u16 vddc_vddci_delta;
1290 u16 min_vddc_for_pcie_gen2;
1291 struct radeon_cac_leakage_table cac_leakage_table;
1292 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1293 struct radeon_ppm_table *ppm_table;
1296 struct radeon_dpm_fan {
1306 bool ucode_fan_control;
1309 enum radeon_pcie_gen {
1310 RADEON_PCIE_GEN1 = 0,
1311 RADEON_PCIE_GEN2 = 1,
1312 RADEON_PCIE_GEN3 = 2,
1313 RADEON_PCIE_GEN_INVALID = 0xffff
1316 enum radeon_dpm_forced_level {
1317 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1318 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1319 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1323 struct radeon_ps *ps;
1324 /* number of valid power states */
1326 /* current power state that is active */
1327 struct radeon_ps *current_ps;
1328 /* requested power state */
1329 struct radeon_ps *requested_ps;
1330 /* boot up power state */
1331 struct radeon_ps *boot_ps;
1332 /* default uvd power state */
1333 struct radeon_ps *uvd_ps;
1334 enum radeon_pm_state_type state;
1335 enum radeon_pm_state_type user_state;
1337 u32 voltage_response_time;
1338 u32 backbias_response_time;
1340 u32 new_active_crtcs;
1341 int new_active_crtc_count;
1342 u32 current_active_crtcs;
1343 int current_active_crtc_count;
1344 struct radeon_dpm_dynamic_state dyn_state;
1345 struct radeon_dpm_fan fan;
1348 u32 near_tdp_limit_adjusted;
1349 u32 sq_ramping_threshold;
1353 u16 load_line_slope;
1356 /* special states active */
1357 bool thermal_active;
1359 /* thermal handling */
1360 struct radeon_dpm_thermal thermal;
1362 enum radeon_dpm_forced_level forced_level;
1363 /* track UVD streams */
1368 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1372 /* write locked while reprogramming mclk */
1373 struct rw_semaphore mclk_lock;
1375 int active_crtc_count;
1378 fixed20_12 max_bandwidth;
1379 fixed20_12 igp_sideport_mclk;
1380 fixed20_12 igp_system_mclk;
1381 fixed20_12 igp_ht_link_clk;
1382 fixed20_12 igp_ht_link_width;
1383 fixed20_12 k8_bandwidth;
1384 fixed20_12 sideport_bandwidth;
1385 fixed20_12 ht_bandwidth;
1386 fixed20_12 core_bandwidth;
1389 fixed20_12 needed_bandwidth;
1390 struct radeon_power_state *power_state;
1391 /* number of valid power states */
1392 int num_power_states;
1393 int current_power_state_index;
1394 int current_clock_mode_index;
1395 int requested_power_state_index;
1396 int requested_clock_mode_index;
1397 int default_power_state_index;
1406 struct radeon_i2c_chan *i2c_bus;
1407 /* selected pm method */
1408 enum radeon_pm_method pm_method;
1409 /* dynpm power management */
1410 struct delayed_work dynpm_idle_work;
1411 enum radeon_dynpm_state dynpm_state;
1412 enum radeon_dynpm_action dynpm_planned_action;
1413 unsigned long dynpm_action_timeout;
1414 bool dynpm_can_upclock;
1415 bool dynpm_can_downclock;
1416 /* profile-based power management */
1417 enum radeon_pm_profile_type profile;
1419 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1420 /* internal thermal controller on rv6xx+ */
1421 enum radeon_int_thermal_type int_thermal_type;
1422 struct device *int_hwmon_dev;
1425 struct radeon_dpm dpm;
1428 int radeon_pm_get_type_index(struct radeon_device *rdev,
1429 enum radeon_pm_state_type ps_type,
1434 #define RADEON_MAX_UVD_HANDLES 10
1435 #define RADEON_UVD_STACK_SIZE (1024*1024)
1436 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1439 struct radeon_bo *vcpu_bo;
1443 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1444 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1445 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1446 struct delayed_work idle_work;
1449 int radeon_uvd_init(struct radeon_device *rdev);
1450 void radeon_uvd_fini(struct radeon_device *rdev);
1451 int radeon_uvd_suspend(struct radeon_device *rdev);
1452 int radeon_uvd_resume(struct radeon_device *rdev);
1453 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1454 uint32_t handle, struct radeon_fence **fence);
1455 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1456 uint32_t handle, struct radeon_fence **fence);
1457 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1458 void radeon_uvd_free_handles(struct radeon_device *rdev,
1459 struct drm_file *filp);
1460 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1461 void radeon_uvd_note_usage(struct radeon_device *rdev);
1462 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1463 unsigned vclk, unsigned dclk,
1464 unsigned vco_min, unsigned vco_max,
1465 unsigned fb_factor, unsigned fb_mask,
1466 unsigned pd_min, unsigned pd_max,
1468 unsigned *optimal_fb_div,
1469 unsigned *optimal_vclk_div,
1470 unsigned *optimal_dclk_div);
1471 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1472 unsigned cg_upll_func_cntl);
1477 int bits_per_sample;
1485 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1491 void radeon_test_moves(struct radeon_device *rdev);
1492 void radeon_test_ring_sync(struct radeon_device *rdev,
1493 struct radeon_ring *cpA,
1494 struct radeon_ring *cpB);
1495 void radeon_test_syncing(struct radeon_device *rdev);
1501 struct radeon_debugfs {
1502 struct drm_info_list *files;
1506 int radeon_debugfs_add_files(struct radeon_device *rdev,
1507 struct drm_info_list *files,
1509 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1513 * ASIC specific functions.
1515 struct radeon_asic {
1516 int (*init)(struct radeon_device *rdev);
1517 void (*fini)(struct radeon_device *rdev);
1518 int (*resume)(struct radeon_device *rdev);
1519 int (*suspend)(struct radeon_device *rdev);
1520 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1521 int (*asic_reset)(struct radeon_device *rdev);
1522 /* ioctl hw specific callback. Some hw might want to perform special
1523 * operation on specific ioctl. For instance on wait idle some hw
1524 * might want to perform and HDP flush through MMIO as it seems that
1525 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1528 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1529 /* check if 3D engine is idle */
1530 bool (*gui_idle)(struct radeon_device *rdev);
1531 /* wait for mc_idle */
1532 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1533 /* get the reference clock */
1534 u32 (*get_xclk)(struct radeon_device *rdev);
1535 /* get the gpu clock counter */
1536 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1539 void (*tlb_flush)(struct radeon_device *rdev);
1540 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1543 int (*init)(struct radeon_device *rdev);
1544 void (*fini)(struct radeon_device *rdev);
1547 void (*set_page)(struct radeon_device *rdev,
1548 struct radeon_ib *ib,
1550 uint64_t addr, unsigned count,
1551 uint32_t incr, uint32_t flags);
1553 /* ring specific callbacks */
1555 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1556 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1557 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1558 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1559 struct radeon_semaphore *semaphore, bool emit_wait);
1560 int (*cs_parse)(struct radeon_cs_parser *p);
1561 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1562 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1563 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1564 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1565 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1567 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1568 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1569 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1570 } ring[RADEON_NUM_RINGS];
1573 int (*set)(struct radeon_device *rdev);
1574 int (*process)(struct radeon_device *rdev);
1578 /* display watermarks */
1579 void (*bandwidth_update)(struct radeon_device *rdev);
1580 /* get frame count */
1581 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1582 /* wait for vblank */
1583 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1584 /* set backlight level */
1585 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1586 /* get backlight level */
1587 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1588 /* audio callbacks */
1589 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1590 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1592 /* copy functions for bo handling */
1594 int (*blit)(struct radeon_device *rdev,
1595 uint64_t src_offset,
1596 uint64_t dst_offset,
1597 unsigned num_gpu_pages,
1598 struct radeon_fence **fence);
1599 u32 blit_ring_index;
1600 int (*dma)(struct radeon_device *rdev,
1601 uint64_t src_offset,
1602 uint64_t dst_offset,
1603 unsigned num_gpu_pages,
1604 struct radeon_fence **fence);
1606 /* method used for bo copy */
1607 int (*copy)(struct radeon_device *rdev,
1608 uint64_t src_offset,
1609 uint64_t dst_offset,
1610 unsigned num_gpu_pages,
1611 struct radeon_fence **fence);
1612 /* ring used for bo copies */
1613 u32 copy_ring_index;
1617 int (*set_reg)(struct radeon_device *rdev, int reg,
1618 uint32_t tiling_flags, uint32_t pitch,
1619 uint32_t offset, uint32_t obj_size);
1620 void (*clear_reg)(struct radeon_device *rdev, int reg);
1622 /* hotplug detect */
1624 void (*init)(struct radeon_device *rdev);
1625 void (*fini)(struct radeon_device *rdev);
1626 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1627 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1629 /* static power management */
1631 void (*misc)(struct radeon_device *rdev);
1632 void (*prepare)(struct radeon_device *rdev);
1633 void (*finish)(struct radeon_device *rdev);
1634 void (*init_profile)(struct radeon_device *rdev);
1635 void (*get_dynpm_state)(struct radeon_device *rdev);
1636 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1637 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1638 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1639 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1640 int (*get_pcie_lanes)(struct radeon_device *rdev);
1641 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1642 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1643 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1644 int (*get_temperature)(struct radeon_device *rdev);
1646 /* dynamic power management */
1648 int (*init)(struct radeon_device *rdev);
1649 void (*setup_asic)(struct radeon_device *rdev);
1650 int (*enable)(struct radeon_device *rdev);
1651 void (*disable)(struct radeon_device *rdev);
1652 int (*pre_set_power_state)(struct radeon_device *rdev);
1653 int (*set_power_state)(struct radeon_device *rdev);
1654 void (*post_set_power_state)(struct radeon_device *rdev);
1655 void (*display_configuration_changed)(struct radeon_device *rdev);
1656 void (*fini)(struct radeon_device *rdev);
1657 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1658 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1659 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1660 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1661 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1662 bool (*vblank_too_short)(struct radeon_device *rdev);
1666 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1667 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1668 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1676 const unsigned *reg_safe_bm;
1677 unsigned reg_safe_bm_size;
1682 const unsigned *reg_safe_bm;
1683 unsigned reg_safe_bm_size;
1690 unsigned max_tile_pipes;
1692 unsigned max_backends;
1694 unsigned max_threads;
1695 unsigned max_stack_entries;
1696 unsigned max_hw_contexts;
1697 unsigned max_gs_threads;
1698 unsigned sx_max_export_size;
1699 unsigned sx_max_export_pos_size;
1700 unsigned sx_max_export_smx_size;
1701 unsigned sq_num_cf_insts;
1702 unsigned tiling_nbanks;
1703 unsigned tiling_npipes;
1704 unsigned tiling_group_size;
1705 unsigned tile_config;
1706 unsigned backend_map;
1711 unsigned max_tile_pipes;
1713 unsigned max_backends;
1715 unsigned max_threads;
1716 unsigned max_stack_entries;
1717 unsigned max_hw_contexts;
1718 unsigned max_gs_threads;
1719 unsigned sx_max_export_size;
1720 unsigned sx_max_export_pos_size;
1721 unsigned sx_max_export_smx_size;
1722 unsigned sq_num_cf_insts;
1723 unsigned sx_num_of_sets;
1724 unsigned sc_prim_fifo_size;
1725 unsigned sc_hiz_tile_fifo_size;
1726 unsigned sc_earlyz_tile_fifo_fize;
1727 unsigned tiling_nbanks;
1728 unsigned tiling_npipes;
1729 unsigned tiling_group_size;
1730 unsigned tile_config;
1731 unsigned backend_map;
1734 struct evergreen_asic {
1737 unsigned max_tile_pipes;
1739 unsigned max_backends;
1741 unsigned max_threads;
1742 unsigned max_stack_entries;
1743 unsigned max_hw_contexts;
1744 unsigned max_gs_threads;
1745 unsigned sx_max_export_size;
1746 unsigned sx_max_export_pos_size;
1747 unsigned sx_max_export_smx_size;
1748 unsigned sq_num_cf_insts;
1749 unsigned sx_num_of_sets;
1750 unsigned sc_prim_fifo_size;
1751 unsigned sc_hiz_tile_fifo_size;
1752 unsigned sc_earlyz_tile_fifo_size;
1753 unsigned tiling_nbanks;
1754 unsigned tiling_npipes;
1755 unsigned tiling_group_size;
1756 unsigned tile_config;
1757 unsigned backend_map;
1760 struct cayman_asic {
1761 unsigned max_shader_engines;
1762 unsigned max_pipes_per_simd;
1763 unsigned max_tile_pipes;
1764 unsigned max_simds_per_se;
1765 unsigned max_backends_per_se;
1766 unsigned max_texture_channel_caches;
1768 unsigned max_threads;
1769 unsigned max_gs_threads;
1770 unsigned max_stack_entries;
1771 unsigned sx_num_of_sets;
1772 unsigned sx_max_export_size;
1773 unsigned sx_max_export_pos_size;
1774 unsigned sx_max_export_smx_size;
1775 unsigned max_hw_contexts;
1776 unsigned sq_num_cf_insts;
1777 unsigned sc_prim_fifo_size;
1778 unsigned sc_hiz_tile_fifo_size;
1779 unsigned sc_earlyz_tile_fifo_size;
1781 unsigned num_shader_engines;
1782 unsigned num_shader_pipes_per_simd;
1783 unsigned num_tile_pipes;
1784 unsigned num_simds_per_se;
1785 unsigned num_backends_per_se;
1786 unsigned backend_disable_mask_per_asic;
1787 unsigned backend_map;
1788 unsigned num_texture_channel_caches;
1789 unsigned mem_max_burst_length_bytes;
1790 unsigned mem_row_size_in_kb;
1791 unsigned shader_engine_tile_size;
1793 unsigned multi_gpu_tile_size;
1795 unsigned tile_config;
1799 unsigned max_shader_engines;
1800 unsigned max_tile_pipes;
1801 unsigned max_cu_per_sh;
1802 unsigned max_sh_per_se;
1803 unsigned max_backends_per_se;
1804 unsigned max_texture_channel_caches;
1806 unsigned max_gs_threads;
1807 unsigned max_hw_contexts;
1808 unsigned sc_prim_fifo_size_frontend;
1809 unsigned sc_prim_fifo_size_backend;
1810 unsigned sc_hiz_tile_fifo_size;
1811 unsigned sc_earlyz_tile_fifo_size;
1813 unsigned num_tile_pipes;
1814 unsigned num_backends_per_se;
1815 unsigned backend_disable_mask_per_asic;
1816 unsigned backend_map;
1817 unsigned num_texture_channel_caches;
1818 unsigned mem_max_burst_length_bytes;
1819 unsigned mem_row_size_in_kb;
1820 unsigned shader_engine_tile_size;
1822 unsigned multi_gpu_tile_size;
1824 unsigned tile_config;
1825 uint32_t tile_mode_array[32];
1829 unsigned max_shader_engines;
1830 unsigned max_tile_pipes;
1831 unsigned max_cu_per_sh;
1832 unsigned max_sh_per_se;
1833 unsigned max_backends_per_se;
1834 unsigned max_texture_channel_caches;
1836 unsigned max_gs_threads;
1837 unsigned max_hw_contexts;
1838 unsigned sc_prim_fifo_size_frontend;
1839 unsigned sc_prim_fifo_size_backend;
1840 unsigned sc_hiz_tile_fifo_size;
1841 unsigned sc_earlyz_tile_fifo_size;
1843 unsigned num_tile_pipes;
1844 unsigned num_backends_per_se;
1845 unsigned backend_disable_mask_per_asic;
1846 unsigned backend_map;
1847 unsigned num_texture_channel_caches;
1848 unsigned mem_max_burst_length_bytes;
1849 unsigned mem_row_size_in_kb;
1850 unsigned shader_engine_tile_size;
1852 unsigned multi_gpu_tile_size;
1854 unsigned tile_config;
1855 uint32_t tile_mode_array[32];
1858 union radeon_asic_config {
1859 struct r300_asic r300;
1860 struct r100_asic r100;
1861 struct r600_asic r600;
1862 struct rv770_asic rv770;
1863 struct evergreen_asic evergreen;
1864 struct cayman_asic cayman;
1866 struct cik_asic cik;
1870 * asic initizalization from radeon_asic.c
1872 void radeon_agp_disable(struct radeon_device *rdev);
1873 int radeon_asic_init(struct radeon_device *rdev);
1879 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1880 struct drm_file *filp);
1881 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1882 struct drm_file *filp);
1883 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1884 struct drm_file *file_priv);
1885 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1886 struct drm_file *file_priv);
1887 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1888 struct drm_file *file_priv);
1889 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1890 struct drm_file *file_priv);
1891 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1892 struct drm_file *filp);
1893 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1894 struct drm_file *filp);
1895 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1896 struct drm_file *filp);
1897 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1898 struct drm_file *filp);
1899 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1900 struct drm_file *filp);
1901 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1902 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1903 struct drm_file *filp);
1904 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1905 struct drm_file *filp);
1907 /* VRAM scratch page for HDP bug, default vram page */
1908 struct r600_vram_scratch {
1909 struct radeon_bo *robj;
1910 volatile uint32_t *ptr;
1917 struct radeon_atif_notification_cfg {
1922 struct radeon_atif_notifications {
1923 bool display_switch;
1924 bool expansion_mode_change;
1926 bool forced_power_state;
1927 bool system_power_state;
1928 bool display_conf_change;
1930 bool brightness_change;
1931 bool dgpu_display_event;
1934 struct radeon_atif_functions {
1936 bool sbios_requests;
1937 bool select_active_disp;
1939 bool get_tv_standard;
1940 bool set_tv_standard;
1941 bool get_panel_expansion_mode;
1942 bool set_panel_expansion_mode;
1943 bool temperature_change;
1944 bool graphics_device_types;
1947 struct radeon_atif {
1948 struct radeon_atif_notifications notifications;
1949 struct radeon_atif_functions functions;
1950 struct radeon_atif_notification_cfg notification_cfg;
1951 struct radeon_encoder *encoder_for_bl;
1954 struct radeon_atcs_functions {
1958 bool pcie_bus_width;
1961 struct radeon_atcs {
1962 struct radeon_atcs_functions functions;
1966 * Core structure, functions and helpers.
1968 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1969 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1971 struct radeon_device {
1973 struct drm_device *ddev;
1974 struct pci_dev *pdev;
1975 struct rw_semaphore exclusive_lock;
1977 union radeon_asic_config config;
1978 enum radeon_family family;
1979 unsigned long flags;
1981 enum radeon_pll_errata pll_errata;
1988 uint16_t bios_header_start;
1989 struct radeon_bo *stollen_vga_memory;
1991 resource_size_t rmmio_base;
1992 resource_size_t rmmio_size;
1993 /* protects concurrent MM_INDEX/DATA based register access */
1994 spinlock_t mmio_idx_lock;
1995 void __iomem *rmmio;
1996 radeon_rreg_t mc_rreg;
1997 radeon_wreg_t mc_wreg;
1998 radeon_rreg_t pll_rreg;
1999 radeon_wreg_t pll_wreg;
2000 uint32_t pcie_reg_mask;
2001 radeon_rreg_t pciep_rreg;
2002 radeon_wreg_t pciep_wreg;
2004 void __iomem *rio_mem;
2005 resource_size_t rio_mem_size;
2006 struct radeon_clock clock;
2007 struct radeon_mc mc;
2008 struct radeon_gart gart;
2009 struct radeon_mode_info mode_info;
2010 struct radeon_scratch scratch;
2011 struct radeon_doorbell doorbell;
2012 struct radeon_mman mman;
2013 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2014 wait_queue_head_t fence_queue;
2015 struct mutex ring_lock;
2016 struct radeon_ring ring[RADEON_NUM_RINGS];
2018 struct radeon_sa_manager ring_tmp_bo;
2019 struct radeon_irq irq;
2020 struct radeon_asic *asic;
2021 struct radeon_gem gem;
2022 struct radeon_pm pm;
2023 struct radeon_uvd uvd;
2024 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2025 struct radeon_wb wb;
2026 struct radeon_dummy_page dummy_page;
2031 bool fastfb_working; /* IGP feature*/
2032 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2033 const struct firmware *me_fw; /* all family ME firmware */
2034 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2035 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2036 const struct firmware *mc_fw; /* NI MC firmware */
2037 const struct firmware *ce_fw; /* SI CE firmware */
2038 const struct firmware *mec_fw; /* CIK MEC firmware */
2039 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2040 const struct firmware *smc_fw; /* SMC firmware */
2041 const struct firmware *uvd_fw; /* UVD firmware */
2042 struct r600_vram_scratch vram_scratch;
2043 int msi_enabled; /* msi enabled */
2044 struct r600_ih ih; /* r6/700 interrupt ring */
2045 struct radeon_rlc rlc;
2046 struct radeon_mec mec;
2047 struct work_struct hotplug_work;
2048 struct work_struct audio_work;
2049 struct work_struct reset_work;
2050 int num_crtc; /* number of crtcs */
2051 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2054 struct r600_audio audio_status; /* audio stuff */
2055 struct notifier_block acpi_nb;
2056 /* only one userspace can use Hyperz features or CMASK at a time */
2057 struct drm_file *hyperz_filp;
2058 struct drm_file *cmask_filp;
2060 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2062 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2063 unsigned debugfs_count;
2064 /* virtual memory */
2065 struct radeon_vm_manager vm_manager;
2066 struct mutex gpu_clock_mutex;
2067 /* ACPI interface */
2068 struct radeon_atif atif;
2069 struct radeon_atcs atcs;
2070 /* srbm instance registers */
2071 struct mutex srbm_mutex;
2074 int radeon_device_init(struct radeon_device *rdev,
2075 struct drm_device *ddev,
2076 struct pci_dev *pdev,
2078 void radeon_device_fini(struct radeon_device *rdev);
2079 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2081 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2082 bool always_indirect);
2083 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2084 bool always_indirect);
2085 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2086 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2088 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
2089 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
2094 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2097 * Registers read & write functions.
2099 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2100 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2101 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2102 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2103 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2104 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2105 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2106 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2107 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2108 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2109 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2110 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2111 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2112 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2113 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2114 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2115 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2116 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2117 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2118 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2119 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2120 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2121 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2122 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2123 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2124 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2125 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2126 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2127 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2128 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2129 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2130 #define WREG32_P(reg, val, mask) \
2132 uint32_t tmp_ = RREG32(reg); \
2134 tmp_ |= ((val) & ~(mask)); \
2135 WREG32(reg, tmp_); \
2137 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2138 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2139 #define WREG32_PLL_P(reg, val, mask) \
2141 uint32_t tmp_ = RREG32_PLL(reg); \
2143 tmp_ |= ((val) & ~(mask)); \
2144 WREG32_PLL(reg, tmp_); \
2146 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2147 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2148 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2150 #define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2151 #define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2154 * Indirect registers accessor
2156 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2160 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2161 r = RREG32(RADEON_PCIE_DATA);
2165 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2167 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2168 WREG32(RADEON_PCIE_DATA, (v));
2171 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2175 WREG32(TN_SMC_IND_INDEX_0, (reg));
2176 r = RREG32(TN_SMC_IND_DATA_0);
2180 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2182 WREG32(TN_SMC_IND_INDEX_0, (reg));
2183 WREG32(TN_SMC_IND_DATA_0, (v));
2186 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2190 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2191 r = RREG32(R600_RCU_DATA);
2195 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2197 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2198 WREG32(R600_RCU_DATA, (v));
2201 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2205 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2206 r = RREG32(EVERGREEN_CG_IND_DATA);
2210 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2212 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2213 WREG32(EVERGREEN_CG_IND_DATA, (v));
2216 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2220 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2221 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2225 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2227 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2228 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2231 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2235 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2236 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2240 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2242 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2243 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2246 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2250 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2251 r = RREG32(R600_UVD_CTX_DATA);
2255 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2257 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2258 WREG32(R600_UVD_CTX_DATA, (v));
2261 void r100_pll_errata_after_index(struct radeon_device *rdev);
2267 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2268 (rdev->pdev->device == 0x5969))
2269 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2270 (rdev->family == CHIP_RV200) || \
2271 (rdev->family == CHIP_RS100) || \
2272 (rdev->family == CHIP_RS200) || \
2273 (rdev->family == CHIP_RV250) || \
2274 (rdev->family == CHIP_RV280) || \
2275 (rdev->family == CHIP_RS300))
2276 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2277 (rdev->family == CHIP_RV350) || \
2278 (rdev->family == CHIP_R350) || \
2279 (rdev->family == CHIP_RV380) || \
2280 (rdev->family == CHIP_R420) || \
2281 (rdev->family == CHIP_R423) || \
2282 (rdev->family == CHIP_RV410) || \
2283 (rdev->family == CHIP_RS400) || \
2284 (rdev->family == CHIP_RS480))
2285 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2286 (rdev->ddev->pdev->device == 0x9443) || \
2287 (rdev->ddev->pdev->device == 0x944B) || \
2288 (rdev->ddev->pdev->device == 0x9506) || \
2289 (rdev->ddev->pdev->device == 0x9509) || \
2290 (rdev->ddev->pdev->device == 0x950F) || \
2291 (rdev->ddev->pdev->device == 0x689C) || \
2292 (rdev->ddev->pdev->device == 0x689D))
2293 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2294 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2295 (rdev->family == CHIP_RS690) || \
2296 (rdev->family == CHIP_RS740) || \
2297 (rdev->family >= CHIP_R600))
2298 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2299 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2300 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2301 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2302 (rdev->flags & RADEON_IS_IGP))
2303 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2304 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2305 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2306 (rdev->flags & RADEON_IS_IGP))
2307 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2308 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2309 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2311 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2312 (rdev->ddev->pdev->device == 0x6850) || \
2313 (rdev->ddev->pdev->device == 0x6858) || \
2314 (rdev->ddev->pdev->device == 0x6859) || \
2315 (rdev->ddev->pdev->device == 0x6840) || \
2316 (rdev->ddev->pdev->device == 0x6841) || \
2317 (rdev->ddev->pdev->device == 0x6842) || \
2318 (rdev->ddev->pdev->device == 0x6843))
2323 #define RBIOS8(i) (rdev->bios[i])
2324 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2325 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2327 int radeon_combios_init(struct radeon_device *rdev);
2328 void radeon_combios_fini(struct radeon_device *rdev);
2329 int radeon_atombios_init(struct radeon_device *rdev);
2330 void radeon_atombios_fini(struct radeon_device *rdev);
2336 #if DRM_DEBUG_CODE == 0
2337 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2339 ring->ring[ring->wptr++] = v;
2340 ring->wptr &= ring->ptr_mask;
2342 ring->ring_free_dw--;
2345 /* With debugging this is just too big to inline */
2346 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2352 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2353 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2354 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2355 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2356 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
2357 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2358 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2359 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2360 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2361 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2362 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2363 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2364 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
2365 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
2366 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
2367 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
2368 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
2369 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
2370 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
2371 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r))
2372 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r))
2373 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r))
2374 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2375 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2376 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2377 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2378 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2379 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2380 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2381 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
2382 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2383 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2384 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2385 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2386 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2387 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2388 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2389 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2390 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2391 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2392 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2393 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2394 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2395 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2396 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2397 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2398 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2399 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2400 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2401 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2402 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2403 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2404 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2405 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2406 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2407 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2408 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2409 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2410 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2411 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2412 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2413 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2414 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2415 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2416 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2417 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2418 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2419 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2420 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2421 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2422 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2423 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2424 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2425 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2426 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2427 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2428 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2429 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2430 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2431 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2432 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2434 /* Common functions */
2436 extern int radeon_gpu_reset(struct radeon_device *rdev);
2437 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2438 extern void radeon_agp_disable(struct radeon_device *rdev);
2439 extern int radeon_modeset_init(struct radeon_device *rdev);
2440 extern void radeon_modeset_fini(struct radeon_device *rdev);
2441 extern bool radeon_card_posted(struct radeon_device *rdev);
2442 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2443 extern void radeon_update_display_priority(struct radeon_device *rdev);
2444 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2445 extern void radeon_scratch_init(struct radeon_device *rdev);
2446 extern void radeon_wb_fini(struct radeon_device *rdev);
2447 extern int radeon_wb_init(struct radeon_device *rdev);
2448 extern void radeon_wb_disable(struct radeon_device *rdev);
2449 extern void radeon_surface_init(struct radeon_device *rdev);
2450 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2451 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2452 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2453 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2454 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2455 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2456 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2457 extern int radeon_resume_kms(struct drm_device *dev);
2458 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
2459 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2460 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2461 const u32 *registers,
2462 const u32 array_size);
2467 int radeon_vm_manager_init(struct radeon_device *rdev);
2468 void radeon_vm_manager_fini(struct radeon_device *rdev);
2469 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2470 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2471 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
2472 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
2473 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2474 struct radeon_vm *vm, int ring);
2475 void radeon_vm_fence(struct radeon_device *rdev,
2476 struct radeon_vm *vm,
2477 struct radeon_fence *fence);
2478 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2479 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2480 struct radeon_vm *vm,
2481 struct radeon_bo *bo,
2482 struct ttm_mem_reg *mem);
2483 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2484 struct radeon_bo *bo);
2485 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2486 struct radeon_bo *bo);
2487 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2488 struct radeon_vm *vm,
2489 struct radeon_bo *bo);
2490 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2491 struct radeon_bo_va *bo_va,
2494 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2495 struct radeon_bo_va *bo_va);
2498 void r600_audio_update_hdmi(struct work_struct *work);
2501 * R600 vram scratch functions
2503 int r600_vram_scratch_init(struct radeon_device *rdev);
2504 void r600_vram_scratch_fini(struct radeon_device *rdev);
2507 * r600 cs checking helper
2509 unsigned r600_mip_minify(unsigned size, unsigned level);
2510 bool r600_fmt_is_valid_color(u32 format);
2511 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2512 int r600_fmt_get_blocksize(u32 format);
2513 int r600_fmt_get_nblocksx(u32 format, u32 w);
2514 int r600_fmt_get_nblocksy(u32 format, u32 h);
2517 * r600 functions used by radeon_encoder.c
2519 struct radeon_hdmi_acr {
2533 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2535 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2536 u32 tiling_pipe_num,
2538 u32 total_max_rb_num,
2539 u32 enabled_rb_mask);
2542 * evergreen functions used by radeon_encoder.c
2545 extern int ni_init_microcode(struct radeon_device *rdev);
2546 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2549 #if defined(CONFIG_ACPI)
2550 extern int radeon_acpi_init(struct radeon_device *rdev);
2551 extern void radeon_acpi_fini(struct radeon_device *rdev);
2552 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2553 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2554 u8 perf_req, bool advertise);
2555 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2557 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2558 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2561 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2562 struct radeon_cs_packet *pkt,
2564 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2565 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2566 struct radeon_cs_packet *pkt);
2567 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2568 struct radeon_cs_reloc **cs_reloc,
2570 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2571 uint32_t *vline_start_end,
2572 uint32_t *vline_status);
2574 #include "radeon_object.h"