2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
100 * Copy from radeon_drv.h so we don't have to include both and have conflicting
103 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
104 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
105 /* RADEON_IB_POOL_SIZE must be a power of 2 */
106 #define RADEON_IB_POOL_SIZE 16
107 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
108 #define RADEONFB_CONN_LIMIT 4
109 #define RADEON_BIOS_NUM_SCRATCH 8
111 /* max number of rings */
112 #define RADEON_NUM_RINGS 3
114 /* fence seq are set to this number when signaled */
115 #define RADEON_FENCE_SIGNALED_SEQ 0LL
117 /* internal ring indices */
118 /* r1xx+ has gfx CP ring */
119 #define RADEON_RING_TYPE_GFX_INDEX 0
121 /* cayman has 2 compute CP rings */
122 #define CAYMAN_RING_TYPE_CP1_INDEX 1
123 #define CAYMAN_RING_TYPE_CP2_INDEX 2
125 /* hardcode those limit for now */
126 #define RADEON_VA_RESERVED_SIZE (8 << 20)
127 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
130 * Errata workarounds.
132 enum radeon_pll_errata {
133 CHIP_ERRATA_R300_CG = 0x00000001,
134 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
135 CHIP_ERRATA_PLL_DELAY = 0x00000004
139 struct radeon_device;
145 #define ATRM_BIOS_PAGE 4096
147 #if defined(CONFIG_VGA_SWITCHEROO)
148 bool radeon_atrm_supported(struct pci_dev *pdev);
149 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
151 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
156 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
160 bool radeon_get_bios(struct radeon_device *rdev);
165 struct radeon_dummy_page {
169 int radeon_dummy_page_init(struct radeon_device *rdev);
170 void radeon_dummy_page_fini(struct radeon_device *rdev);
176 struct radeon_clock {
177 struct radeon_pll p1pll;
178 struct radeon_pll p2pll;
179 struct radeon_pll dcpll;
180 struct radeon_pll spll;
181 struct radeon_pll mpll;
183 uint32_t default_mclk;
184 uint32_t default_sclk;
185 uint32_t default_dispclk;
187 uint32_t max_pixel_clock;
193 int radeon_pm_init(struct radeon_device *rdev);
194 void radeon_pm_fini(struct radeon_device *rdev);
195 void radeon_pm_compute_clocks(struct radeon_device *rdev);
196 void radeon_pm_suspend(struct radeon_device *rdev);
197 void radeon_pm_resume(struct radeon_device *rdev);
198 void radeon_combios_get_power_modes(struct radeon_device *rdev);
199 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
200 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
201 void rs690_pm_info(struct radeon_device *rdev);
202 extern int rv6xx_get_temp(struct radeon_device *rdev);
203 extern int rv770_get_temp(struct radeon_device *rdev);
204 extern int evergreen_get_temp(struct radeon_device *rdev);
205 extern int sumo_get_temp(struct radeon_device *rdev);
206 extern int si_get_temp(struct radeon_device *rdev);
207 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
208 unsigned *bankh, unsigned *mtaspect,
209 unsigned *tile_split);
214 struct radeon_fence_driver {
215 uint32_t scratch_reg;
217 volatile uint32_t *cpu_addr;
218 /* sync_seq is protected by ring emission lock */
219 uint64_t sync_seq[RADEON_NUM_RINGS];
221 unsigned long last_activity;
225 struct radeon_fence {
226 struct radeon_device *rdev;
228 /* protected by radeon_fence.lock */
234 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
235 int radeon_fence_driver_init(struct radeon_device *rdev);
236 void radeon_fence_driver_fini(struct radeon_device *rdev);
237 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
238 void radeon_fence_process(struct radeon_device *rdev, int ring);
239 bool radeon_fence_signaled(struct radeon_fence *fence);
240 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
241 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
242 void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
243 int radeon_fence_wait_any(struct radeon_device *rdev,
244 struct radeon_fence **fences,
246 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
247 void radeon_fence_unref(struct radeon_fence **fence);
248 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
249 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
250 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
251 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
252 struct radeon_fence *b)
262 BUG_ON(a->ring != b->ring);
264 if (a->seq > b->seq) {
274 struct radeon_surface_reg {
275 struct radeon_bo *bo;
278 #define RADEON_GEM_MAX_SURFACES 8
284 struct ttm_bo_global_ref bo_global_ref;
285 struct drm_global_reference mem_global_ref;
286 struct ttm_bo_device bdev;
287 bool mem_global_referenced;
291 /* bo virtual address in a specific vm */
292 struct radeon_bo_va {
293 /* bo list is protected by bo being reserved */
294 struct list_head bo_list;
295 /* vm list is protected by vm mutex */
296 struct list_head vm_list;
297 /* constant after initialization */
298 struct radeon_vm *vm;
299 struct radeon_bo *bo;
307 /* Protected by gem.mutex */
308 struct list_head list;
309 /* Protected by tbo.reserved */
311 struct ttm_placement placement;
312 struct ttm_buffer_object tbo;
313 struct ttm_bo_kmap_obj kmap;
319 /* list of all virtual address to which this bo
323 /* Constant after initialization */
324 struct radeon_device *rdev;
325 struct drm_gem_object gem_base;
327 struct ttm_bo_kmap_obj dma_buf_vmap;
330 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
332 struct radeon_bo_list {
333 struct ttm_validate_buffer tv;
334 struct radeon_bo *bo;
341 /* sub-allocation manager, it has to be protected by another lock.
342 * By conception this is an helper for other part of the driver
343 * like the indirect buffer or semaphore, which both have their
346 * Principe is simple, we keep a list of sub allocation in offset
347 * order (first entry has offset == 0, last entry has the highest
350 * When allocating new object we first check if there is room at
351 * the end total_size - (last_object_offset + last_object_size) >=
352 * alloc_size. If so we allocate new object there.
354 * When there is not enough room at the end, we start waiting for
355 * each sub object until we reach object_offset+object_size >=
356 * alloc_size, this object then become the sub object we return.
358 * Alignment can't be bigger than page size.
360 * Hole are not considered for allocation to keep things simple.
361 * Assumption is that there won't be hole (all object on same
364 struct radeon_sa_manager {
366 struct radeon_bo *bo;
367 struct list_head *hole;
368 struct list_head flist[RADEON_NUM_RINGS];
369 struct list_head olist;
378 /* sub-allocation buffer */
379 struct radeon_sa_bo {
380 struct list_head olist;
381 struct list_head flist;
382 struct radeon_sa_manager *manager;
385 struct radeon_fence *fence;
393 struct list_head objects;
396 int radeon_gem_init(struct radeon_device *rdev);
397 void radeon_gem_fini(struct radeon_device *rdev);
398 int radeon_gem_object_create(struct radeon_device *rdev, int size,
399 int alignment, int initial_domain,
400 bool discardable, bool kernel,
401 struct drm_gem_object **obj);
403 int radeon_mode_dumb_create(struct drm_file *file_priv,
404 struct drm_device *dev,
405 struct drm_mode_create_dumb *args);
406 int radeon_mode_dumb_mmap(struct drm_file *filp,
407 struct drm_device *dev,
408 uint32_t handle, uint64_t *offset_p);
409 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
410 struct drm_device *dev,
416 /* everything here is constant */
417 struct radeon_semaphore {
418 struct radeon_sa_bo *sa_bo;
423 int radeon_semaphore_create(struct radeon_device *rdev,
424 struct radeon_semaphore **semaphore);
425 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
426 struct radeon_semaphore *semaphore);
427 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
428 struct radeon_semaphore *semaphore);
429 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
430 struct radeon_semaphore *semaphore,
431 int signaler, int waiter);
432 void radeon_semaphore_free(struct radeon_device *rdev,
433 struct radeon_semaphore **semaphore,
434 struct radeon_fence *fence);
437 * GART structures, functions & helpers
441 #define RADEON_GPU_PAGE_SIZE 4096
442 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
443 #define RADEON_GPU_PAGE_SHIFT 12
444 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
447 dma_addr_t table_addr;
448 struct radeon_bo *robj;
450 unsigned num_gpu_pages;
451 unsigned num_cpu_pages;
454 dma_addr_t *pages_addr;
458 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
459 void radeon_gart_table_ram_free(struct radeon_device *rdev);
460 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
461 void radeon_gart_table_vram_free(struct radeon_device *rdev);
462 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
463 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
464 int radeon_gart_init(struct radeon_device *rdev);
465 void radeon_gart_fini(struct radeon_device *rdev);
466 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
468 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
469 int pages, struct page **pagelist,
470 dma_addr_t *dma_addr);
471 void radeon_gart_restore(struct radeon_device *rdev);
475 * GPU MC structures, functions & helpers
478 resource_size_t aper_size;
479 resource_size_t aper_base;
480 resource_size_t agp_base;
481 /* for some chips with <= 32MB we need to lie
482 * about vram size near mc fb location */
484 u64 visible_vram_size;
494 bool igp_sideport_enabled;
498 bool radeon_combios_sideport_present(struct radeon_device *rdev);
499 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
502 * GPU scratch registers structures, functions & helpers
504 struct radeon_scratch {
511 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
512 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
519 struct radeon_unpin_work {
520 struct work_struct work;
521 struct radeon_device *rdev;
523 struct radeon_fence *fence;
524 struct drm_pending_vblank_event *event;
525 struct radeon_bo *old_rbo;
529 struct r500_irq_stat_regs {
534 struct r600_irq_stat_regs {
544 struct evergreen_irq_stat_regs {
565 union radeon_irq_stat_regs {
566 struct r500_irq_stat_regs r500;
567 struct r600_irq_stat_regs r600;
568 struct evergreen_irq_stat_regs evergreen;
571 #define RADEON_MAX_HPD_PINS 6
572 #define RADEON_MAX_CRTCS 6
573 #define RADEON_MAX_AFMT_BLOCKS 6
578 atomic_t ring_int[RADEON_NUM_RINGS];
579 bool crtc_vblank_int[RADEON_MAX_CRTCS];
580 atomic_t pflip[RADEON_MAX_CRTCS];
581 wait_queue_head_t vblank_queue;
582 bool hpd[RADEON_MAX_HPD_PINS];
585 wait_queue_head_t idle_queue;
586 bool afmt[RADEON_MAX_AFMT_BLOCKS];
587 union radeon_irq_stat_regs stat_regs;
590 int radeon_irq_kms_init(struct radeon_device *rdev);
591 void radeon_irq_kms_fini(struct radeon_device *rdev);
592 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
593 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
594 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
595 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
596 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
597 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
598 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
599 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
600 int radeon_irq_kms_wait_gui_idle(struct radeon_device *rdev);
607 struct radeon_sa_bo *sa_bo;
612 struct radeon_fence *fence;
615 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
616 struct radeon_semaphore *semaphore;
620 struct radeon_bo *ring_obj;
621 volatile uint32_t *ring;
629 unsigned ring_free_dw;
631 unsigned long last_activity;
646 struct list_head list;
652 struct radeon_sa_bo *sa_bo;
654 /* last fence for cs using this vm */
655 struct radeon_fence *fence;
658 struct radeon_vm_funcs {
659 int (*init)(struct radeon_device *rdev);
660 void (*fini)(struct radeon_device *rdev);
661 /* cs mutex must be lock for schedule_ib */
662 int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id);
663 void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm);
664 void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm);
665 uint32_t (*page_flags)(struct radeon_device *rdev,
666 struct radeon_vm *vm,
668 void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm,
669 unsigned pfn, uint64_t addr, uint32_t flags);
672 struct radeon_vm_manager {
674 struct list_head lru_vm;
676 struct radeon_sa_manager sa_manager;
678 /* fields constant after init */
679 const struct radeon_vm_funcs *funcs;
680 /* number of VMIDs */
682 /* vram base address for page table entry */
683 u64 vram_base_offset;
689 * file private structure
691 struct radeon_fpriv {
699 struct radeon_bo *ring_obj;
700 volatile uint32_t *ring;
709 struct r600_blit_cp_primitives {
710 void (*set_render_target)(struct radeon_device *rdev, int format,
711 int w, int h, u64 gpu_addr);
712 void (*cp_set_surface_sync)(struct radeon_device *rdev,
713 u32 sync_type, u32 size,
715 void (*set_shaders)(struct radeon_device *rdev);
716 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
717 void (*set_tex_resource)(struct radeon_device *rdev,
718 int format, int w, int h, int pitch,
719 u64 gpu_addr, u32 size);
720 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
722 void (*draw_auto)(struct radeon_device *rdev);
723 void (*set_default_state)(struct radeon_device *rdev);
727 struct radeon_bo *shader_obj;
728 struct r600_blit_cp_primitives primitives;
730 int ring_size_common;
731 int ring_size_per_loop;
733 u32 vs_offset, ps_offset;
742 /* for power gating */
743 struct radeon_bo *save_restore_obj;
744 uint64_t save_restore_gpu_addr;
745 /* for clear state */
746 struct radeon_bo *clear_state_obj;
747 uint64_t clear_state_gpu_addr;
750 int radeon_ib_get(struct radeon_device *rdev, int ring,
751 struct radeon_ib *ib, unsigned size);
752 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
753 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
754 int radeon_ib_pool_init(struct radeon_device *rdev);
755 void radeon_ib_pool_fini(struct radeon_device *rdev);
756 int radeon_ib_ring_tests(struct radeon_device *rdev);
757 /* Ring access between begin & end cannot sleep */
758 int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp);
759 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
760 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
761 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
762 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
763 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
764 void radeon_ring_undo(struct radeon_ring *ring);
765 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
766 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
767 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
768 void radeon_ring_lockup_update(struct radeon_ring *ring);
769 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
770 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
771 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
772 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
773 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
779 struct radeon_cs_reloc {
780 struct drm_gem_object *gobj;
781 struct radeon_bo *robj;
782 struct radeon_bo_list lobj;
787 struct radeon_cs_chunk {
793 void __user *user_ptr;
794 int last_copied_page;
798 struct radeon_cs_parser {
800 struct radeon_device *rdev;
801 struct drm_file *filp;
804 struct radeon_cs_chunk *chunks;
805 uint64_t *chunks_array;
810 struct radeon_cs_reloc *relocs;
811 struct radeon_cs_reloc **relocs_ptr;
812 struct list_head validated;
813 /* indices of various chunks */
815 int chunk_relocs_idx;
817 int chunk_const_ib_idx;
819 struct radeon_ib const_ib;
828 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
829 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
831 struct radeon_cs_packet {
840 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
841 struct radeon_cs_packet *pkt,
842 unsigned idx, unsigned reg);
843 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
844 struct radeon_cs_packet *pkt);
850 int radeon_agp_init(struct radeon_device *rdev);
851 void radeon_agp_resume(struct radeon_device *rdev);
852 void radeon_agp_suspend(struct radeon_device *rdev);
853 void radeon_agp_fini(struct radeon_device *rdev);
860 struct radeon_bo *wb_obj;
861 volatile uint32_t *wb;
867 #define RADEON_WB_SCRATCH_OFFSET 0
868 #define RADEON_WB_CP_RPTR_OFFSET 1024
869 #define RADEON_WB_CP1_RPTR_OFFSET 1280
870 #define RADEON_WB_CP2_RPTR_OFFSET 1536
871 #define R600_WB_IH_WPTR_OFFSET 2048
872 #define R600_WB_EVENT_OFFSET 3072
875 * struct radeon_pm - power management datas
876 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
877 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
878 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
879 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
880 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
881 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
882 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
883 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
884 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
885 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
886 * @needed_bandwidth: current bandwidth needs
888 * It keeps track of various data needed to take powermanagement decision.
889 * Bandwidth need is used to determine minimun clock of the GPU and memory.
890 * Equation between gpu/memory clock and available bandwidth is hw dependent
891 * (type of memory, bus size, efficiency, ...)
894 enum radeon_pm_method {
899 enum radeon_dynpm_state {
900 DYNPM_STATE_DISABLED,
904 DYNPM_STATE_SUSPENDED,
906 enum radeon_dynpm_action {
908 DYNPM_ACTION_MINIMUM,
909 DYNPM_ACTION_DOWNCLOCK,
910 DYNPM_ACTION_UPCLOCK,
914 enum radeon_voltage_type {
921 enum radeon_pm_state_type {
922 POWER_STATE_TYPE_DEFAULT,
923 POWER_STATE_TYPE_POWERSAVE,
924 POWER_STATE_TYPE_BATTERY,
925 POWER_STATE_TYPE_BALANCED,
926 POWER_STATE_TYPE_PERFORMANCE,
929 enum radeon_pm_profile_type {
937 #define PM_PROFILE_DEFAULT_IDX 0
938 #define PM_PROFILE_LOW_SH_IDX 1
939 #define PM_PROFILE_MID_SH_IDX 2
940 #define PM_PROFILE_HIGH_SH_IDX 3
941 #define PM_PROFILE_LOW_MH_IDX 4
942 #define PM_PROFILE_MID_MH_IDX 5
943 #define PM_PROFILE_HIGH_MH_IDX 6
944 #define PM_PROFILE_MAX 7
946 struct radeon_pm_profile {
953 enum radeon_int_thermal_type {
957 THERMAL_TYPE_EVERGREEN,
963 struct radeon_voltage {
964 enum radeon_voltage_type type;
966 struct radeon_gpio_rec gpio;
967 u32 delay; /* delay in usec from voltage drop to sclk change */
968 bool active_high; /* voltage drop is active when bit is high */
970 u8 vddc_id; /* index into vddc voltage table */
971 u8 vddci_id; /* index into vddci voltage table */
975 /* evergreen+ vddci */
979 /* clock mode flags */
980 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
982 struct radeon_pm_clock_info {
988 struct radeon_voltage voltage;
989 /* standardized clock flags */
994 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
996 struct radeon_power_state {
997 enum radeon_pm_state_type type;
998 struct radeon_pm_clock_info *clock_info;
999 /* number of valid clock modes in this power state */
1000 int num_clock_modes;
1001 struct radeon_pm_clock_info *default_clock_mode;
1002 /* standardized state flags */
1004 u32 misc; /* vbios specific flags */
1005 u32 misc2; /* vbios specific flags */
1006 int pcie_lanes; /* pcie lanes */
1010 * Some modes are overclocked by very low value, accept them
1012 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1016 /* write locked while reprogramming mclk */
1017 struct rw_semaphore mclk_lock;
1019 int active_crtc_count;
1022 fixed20_12 max_bandwidth;
1023 fixed20_12 igp_sideport_mclk;
1024 fixed20_12 igp_system_mclk;
1025 fixed20_12 igp_ht_link_clk;
1026 fixed20_12 igp_ht_link_width;
1027 fixed20_12 k8_bandwidth;
1028 fixed20_12 sideport_bandwidth;
1029 fixed20_12 ht_bandwidth;
1030 fixed20_12 core_bandwidth;
1033 fixed20_12 needed_bandwidth;
1034 struct radeon_power_state *power_state;
1035 /* number of valid power states */
1036 int num_power_states;
1037 int current_power_state_index;
1038 int current_clock_mode_index;
1039 int requested_power_state_index;
1040 int requested_clock_mode_index;
1041 int default_power_state_index;
1050 struct radeon_i2c_chan *i2c_bus;
1051 /* selected pm method */
1052 enum radeon_pm_method pm_method;
1053 /* dynpm power management */
1054 struct delayed_work dynpm_idle_work;
1055 enum radeon_dynpm_state dynpm_state;
1056 enum radeon_dynpm_action dynpm_planned_action;
1057 unsigned long dynpm_action_timeout;
1058 bool dynpm_can_upclock;
1059 bool dynpm_can_downclock;
1060 /* profile-based power management */
1061 enum radeon_pm_profile_type profile;
1063 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1064 /* internal thermal controller on rv6xx+ */
1065 enum radeon_int_thermal_type int_thermal_type;
1066 struct device *int_hwmon_dev;
1069 int radeon_pm_get_type_index(struct radeon_device *rdev,
1070 enum radeon_pm_state_type ps_type,
1076 int bits_per_sample;
1084 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1090 void radeon_test_moves(struct radeon_device *rdev);
1091 void radeon_test_ring_sync(struct radeon_device *rdev,
1092 struct radeon_ring *cpA,
1093 struct radeon_ring *cpB);
1094 void radeon_test_syncing(struct radeon_device *rdev);
1100 struct radeon_debugfs {
1101 struct drm_info_list *files;
1105 int radeon_debugfs_add_files(struct radeon_device *rdev,
1106 struct drm_info_list *files,
1108 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1112 * ASIC specific functions.
1114 struct radeon_asic {
1115 int (*init)(struct radeon_device *rdev);
1116 void (*fini)(struct radeon_device *rdev);
1117 int (*resume)(struct radeon_device *rdev);
1118 int (*suspend)(struct radeon_device *rdev);
1119 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1120 int (*asic_reset)(struct radeon_device *rdev);
1121 /* ioctl hw specific callback. Some hw might want to perform special
1122 * operation on specific ioctl. For instance on wait idle some hw
1123 * might want to perform and HDP flush through MMIO as it seems that
1124 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1127 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1128 /* check if 3D engine is idle */
1129 bool (*gui_idle)(struct radeon_device *rdev);
1130 /* wait for mc_idle */
1131 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1134 void (*tlb_flush)(struct radeon_device *rdev);
1135 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1137 /* ring specific callbacks */
1139 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1140 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1141 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1142 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1143 struct radeon_semaphore *semaphore, bool emit_wait);
1144 int (*cs_parse)(struct radeon_cs_parser *p);
1145 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1146 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1147 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1148 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1149 } ring[RADEON_NUM_RINGS];
1152 int (*set)(struct radeon_device *rdev);
1153 int (*process)(struct radeon_device *rdev);
1157 /* display watermarks */
1158 void (*bandwidth_update)(struct radeon_device *rdev);
1159 /* get frame count */
1160 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1161 /* wait for vblank */
1162 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1164 /* copy functions for bo handling */
1166 int (*blit)(struct radeon_device *rdev,
1167 uint64_t src_offset,
1168 uint64_t dst_offset,
1169 unsigned num_gpu_pages,
1170 struct radeon_fence **fence);
1171 u32 blit_ring_index;
1172 int (*dma)(struct radeon_device *rdev,
1173 uint64_t src_offset,
1174 uint64_t dst_offset,
1175 unsigned num_gpu_pages,
1176 struct radeon_fence **fence);
1178 /* method used for bo copy */
1179 int (*copy)(struct radeon_device *rdev,
1180 uint64_t src_offset,
1181 uint64_t dst_offset,
1182 unsigned num_gpu_pages,
1183 struct radeon_fence **fence);
1184 /* ring used for bo copies */
1185 u32 copy_ring_index;
1189 int (*set_reg)(struct radeon_device *rdev, int reg,
1190 uint32_t tiling_flags, uint32_t pitch,
1191 uint32_t offset, uint32_t obj_size);
1192 void (*clear_reg)(struct radeon_device *rdev, int reg);
1194 /* hotplug detect */
1196 void (*init)(struct radeon_device *rdev);
1197 void (*fini)(struct radeon_device *rdev);
1198 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1199 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1201 /* power management */
1203 void (*misc)(struct radeon_device *rdev);
1204 void (*prepare)(struct radeon_device *rdev);
1205 void (*finish)(struct radeon_device *rdev);
1206 void (*init_profile)(struct radeon_device *rdev);
1207 void (*get_dynpm_state)(struct radeon_device *rdev);
1208 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1209 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1210 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1211 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1212 int (*get_pcie_lanes)(struct radeon_device *rdev);
1213 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1214 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1218 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1219 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1220 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1228 const unsigned *reg_safe_bm;
1229 unsigned reg_safe_bm_size;
1234 const unsigned *reg_safe_bm;
1235 unsigned reg_safe_bm_size;
1242 unsigned max_tile_pipes;
1244 unsigned max_backends;
1246 unsigned max_threads;
1247 unsigned max_stack_entries;
1248 unsigned max_hw_contexts;
1249 unsigned max_gs_threads;
1250 unsigned sx_max_export_size;
1251 unsigned sx_max_export_pos_size;
1252 unsigned sx_max_export_smx_size;
1253 unsigned sq_num_cf_insts;
1254 unsigned tiling_nbanks;
1255 unsigned tiling_npipes;
1256 unsigned tiling_group_size;
1257 unsigned tile_config;
1258 unsigned backend_map;
1263 unsigned max_tile_pipes;
1265 unsigned max_backends;
1267 unsigned max_threads;
1268 unsigned max_stack_entries;
1269 unsigned max_hw_contexts;
1270 unsigned max_gs_threads;
1271 unsigned sx_max_export_size;
1272 unsigned sx_max_export_pos_size;
1273 unsigned sx_max_export_smx_size;
1274 unsigned sq_num_cf_insts;
1275 unsigned sx_num_of_sets;
1276 unsigned sc_prim_fifo_size;
1277 unsigned sc_hiz_tile_fifo_size;
1278 unsigned sc_earlyz_tile_fifo_fize;
1279 unsigned tiling_nbanks;
1280 unsigned tiling_npipes;
1281 unsigned tiling_group_size;
1282 unsigned tile_config;
1283 unsigned backend_map;
1286 struct evergreen_asic {
1289 unsigned max_tile_pipes;
1291 unsigned max_backends;
1293 unsigned max_threads;
1294 unsigned max_stack_entries;
1295 unsigned max_hw_contexts;
1296 unsigned max_gs_threads;
1297 unsigned sx_max_export_size;
1298 unsigned sx_max_export_pos_size;
1299 unsigned sx_max_export_smx_size;
1300 unsigned sq_num_cf_insts;
1301 unsigned sx_num_of_sets;
1302 unsigned sc_prim_fifo_size;
1303 unsigned sc_hiz_tile_fifo_size;
1304 unsigned sc_earlyz_tile_fifo_size;
1305 unsigned tiling_nbanks;
1306 unsigned tiling_npipes;
1307 unsigned tiling_group_size;
1308 unsigned tile_config;
1309 unsigned backend_map;
1312 struct cayman_asic {
1313 unsigned max_shader_engines;
1314 unsigned max_pipes_per_simd;
1315 unsigned max_tile_pipes;
1316 unsigned max_simds_per_se;
1317 unsigned max_backends_per_se;
1318 unsigned max_texture_channel_caches;
1320 unsigned max_threads;
1321 unsigned max_gs_threads;
1322 unsigned max_stack_entries;
1323 unsigned sx_num_of_sets;
1324 unsigned sx_max_export_size;
1325 unsigned sx_max_export_pos_size;
1326 unsigned sx_max_export_smx_size;
1327 unsigned max_hw_contexts;
1328 unsigned sq_num_cf_insts;
1329 unsigned sc_prim_fifo_size;
1330 unsigned sc_hiz_tile_fifo_size;
1331 unsigned sc_earlyz_tile_fifo_size;
1333 unsigned num_shader_engines;
1334 unsigned num_shader_pipes_per_simd;
1335 unsigned num_tile_pipes;
1336 unsigned num_simds_per_se;
1337 unsigned num_backends_per_se;
1338 unsigned backend_disable_mask_per_asic;
1339 unsigned backend_map;
1340 unsigned num_texture_channel_caches;
1341 unsigned mem_max_burst_length_bytes;
1342 unsigned mem_row_size_in_kb;
1343 unsigned shader_engine_tile_size;
1345 unsigned multi_gpu_tile_size;
1347 unsigned tile_config;
1351 unsigned max_shader_engines;
1352 unsigned max_tile_pipes;
1353 unsigned max_cu_per_sh;
1354 unsigned max_sh_per_se;
1355 unsigned max_backends_per_se;
1356 unsigned max_texture_channel_caches;
1358 unsigned max_gs_threads;
1359 unsigned max_hw_contexts;
1360 unsigned sc_prim_fifo_size_frontend;
1361 unsigned sc_prim_fifo_size_backend;
1362 unsigned sc_hiz_tile_fifo_size;
1363 unsigned sc_earlyz_tile_fifo_size;
1365 unsigned num_tile_pipes;
1366 unsigned num_backends_per_se;
1367 unsigned backend_disable_mask_per_asic;
1368 unsigned backend_map;
1369 unsigned num_texture_channel_caches;
1370 unsigned mem_max_burst_length_bytes;
1371 unsigned mem_row_size_in_kb;
1372 unsigned shader_engine_tile_size;
1374 unsigned multi_gpu_tile_size;
1376 unsigned tile_config;
1379 union radeon_asic_config {
1380 struct r300_asic r300;
1381 struct r100_asic r100;
1382 struct r600_asic r600;
1383 struct rv770_asic rv770;
1384 struct evergreen_asic evergreen;
1385 struct cayman_asic cayman;
1390 * asic initizalization from radeon_asic.c
1392 void radeon_agp_disable(struct radeon_device *rdev);
1393 int radeon_asic_init(struct radeon_device *rdev);
1399 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1400 struct drm_file *filp);
1401 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1402 struct drm_file *filp);
1403 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1404 struct drm_file *file_priv);
1405 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1406 struct drm_file *file_priv);
1407 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1408 struct drm_file *file_priv);
1409 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1410 struct drm_file *file_priv);
1411 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1412 struct drm_file *filp);
1413 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1414 struct drm_file *filp);
1415 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1416 struct drm_file *filp);
1417 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1418 struct drm_file *filp);
1419 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1420 struct drm_file *filp);
1421 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1422 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1423 struct drm_file *filp);
1424 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1425 struct drm_file *filp);
1427 /* VRAM scratch page for HDP bug, default vram page */
1428 struct r600_vram_scratch {
1429 struct radeon_bo *robj;
1430 volatile uint32_t *ptr;
1436 * Core structure, functions and helpers.
1438 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1439 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1441 struct radeon_device {
1443 struct drm_device *ddev;
1444 struct pci_dev *pdev;
1445 struct rw_semaphore exclusive_lock;
1447 union radeon_asic_config config;
1448 enum radeon_family family;
1449 unsigned long flags;
1451 enum radeon_pll_errata pll_errata;
1458 uint16_t bios_header_start;
1459 struct radeon_bo *stollen_vga_memory;
1461 resource_size_t rmmio_base;
1462 resource_size_t rmmio_size;
1463 void __iomem *rmmio;
1464 radeon_rreg_t mc_rreg;
1465 radeon_wreg_t mc_wreg;
1466 radeon_rreg_t pll_rreg;
1467 radeon_wreg_t pll_wreg;
1468 uint32_t pcie_reg_mask;
1469 radeon_rreg_t pciep_rreg;
1470 radeon_wreg_t pciep_wreg;
1472 void __iomem *rio_mem;
1473 resource_size_t rio_mem_size;
1474 struct radeon_clock clock;
1475 struct radeon_mc mc;
1476 struct radeon_gart gart;
1477 struct radeon_mode_info mode_info;
1478 struct radeon_scratch scratch;
1479 struct radeon_mman mman;
1480 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1481 wait_queue_head_t fence_queue;
1482 struct mutex ring_lock;
1483 struct radeon_ring ring[RADEON_NUM_RINGS];
1485 struct radeon_sa_manager ring_tmp_bo;
1486 struct radeon_irq irq;
1487 struct radeon_asic *asic;
1488 struct radeon_gem gem;
1489 struct radeon_pm pm;
1490 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1491 struct radeon_wb wb;
1492 struct radeon_dummy_page dummy_page;
1497 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1498 const struct firmware *me_fw; /* all family ME firmware */
1499 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1500 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1501 const struct firmware *mc_fw; /* NI MC firmware */
1502 const struct firmware *ce_fw; /* SI CE firmware */
1503 struct r600_blit r600_blit;
1504 struct r600_vram_scratch vram_scratch;
1505 int msi_enabled; /* msi enabled */
1506 struct r600_ih ih; /* r6/700 interrupt ring */
1508 struct work_struct hotplug_work;
1509 struct work_struct audio_work;
1510 int num_crtc; /* number of crtcs */
1511 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1513 struct r600_audio audio_status; /* audio stuff */
1514 struct notifier_block acpi_nb;
1515 /* only one userspace can use Hyperz features or CMASK at a time */
1516 struct drm_file *hyperz_filp;
1517 struct drm_file *cmask_filp;
1519 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1521 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1522 unsigned debugfs_count;
1523 /* virtual memory */
1524 struct radeon_vm_manager vm_manager;
1527 int radeon_device_init(struct radeon_device *rdev,
1528 struct drm_device *ddev,
1529 struct pci_dev *pdev,
1531 void radeon_device_fini(struct radeon_device *rdev);
1532 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1534 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1535 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1536 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1537 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1542 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1545 * Registers read & write functions.
1547 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1548 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1549 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1550 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1551 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1552 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1553 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1554 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1555 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1556 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1557 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1558 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1559 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1560 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1561 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1562 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1563 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1564 #define WREG32_P(reg, val, mask) \
1566 uint32_t tmp_ = RREG32(reg); \
1568 tmp_ |= ((val) & ~(mask)); \
1569 WREG32(reg, tmp_); \
1571 #define WREG32_PLL_P(reg, val, mask) \
1573 uint32_t tmp_ = RREG32_PLL(reg); \
1575 tmp_ |= ((val) & ~(mask)); \
1576 WREG32_PLL(reg, tmp_); \
1578 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1579 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1580 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1583 * Indirect registers accessor
1585 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1589 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1590 r = RREG32(RADEON_PCIE_DATA);
1594 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1596 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1597 WREG32(RADEON_PCIE_DATA, (v));
1600 void r100_pll_errata_after_index(struct radeon_device *rdev);
1606 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1607 (rdev->pdev->device == 0x5969))
1608 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1609 (rdev->family == CHIP_RV200) || \
1610 (rdev->family == CHIP_RS100) || \
1611 (rdev->family == CHIP_RS200) || \
1612 (rdev->family == CHIP_RV250) || \
1613 (rdev->family == CHIP_RV280) || \
1614 (rdev->family == CHIP_RS300))
1615 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1616 (rdev->family == CHIP_RV350) || \
1617 (rdev->family == CHIP_R350) || \
1618 (rdev->family == CHIP_RV380) || \
1619 (rdev->family == CHIP_R420) || \
1620 (rdev->family == CHIP_R423) || \
1621 (rdev->family == CHIP_RV410) || \
1622 (rdev->family == CHIP_RS400) || \
1623 (rdev->family == CHIP_RS480))
1624 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1625 (rdev->ddev->pdev->device == 0x9443) || \
1626 (rdev->ddev->pdev->device == 0x944B) || \
1627 (rdev->ddev->pdev->device == 0x9506) || \
1628 (rdev->ddev->pdev->device == 0x9509) || \
1629 (rdev->ddev->pdev->device == 0x950F) || \
1630 (rdev->ddev->pdev->device == 0x689C) || \
1631 (rdev->ddev->pdev->device == 0x689D))
1632 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1633 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1634 (rdev->family == CHIP_RS690) || \
1635 (rdev->family == CHIP_RS740) || \
1636 (rdev->family >= CHIP_R600))
1637 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1638 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1639 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1640 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1641 (rdev->flags & RADEON_IS_IGP))
1642 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1643 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1644 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1645 (rdev->flags & RADEON_IS_IGP))
1650 #define RBIOS8(i) (rdev->bios[i])
1651 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1652 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1654 int radeon_combios_init(struct radeon_device *rdev);
1655 void radeon_combios_fini(struct radeon_device *rdev);
1656 int radeon_atombios_init(struct radeon_device *rdev);
1657 void radeon_atombios_fini(struct radeon_device *rdev);
1663 #if DRM_DEBUG_CODE == 0
1664 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1666 ring->ring[ring->wptr++] = v;
1667 ring->wptr &= ring->ptr_mask;
1669 ring->ring_free_dw--;
1672 /* With debugging this is just too big to inline */
1673 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1679 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1680 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1681 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1682 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1683 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1684 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1685 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1686 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1687 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1688 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1689 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1690 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1691 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1692 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1693 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1694 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1695 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1696 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1697 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1698 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1699 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1700 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1701 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1702 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1703 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1704 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1705 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1706 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1707 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1708 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1709 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1710 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1711 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1712 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1713 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1714 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1715 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1716 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1717 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1718 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1719 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1720 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1721 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1722 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1723 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1724 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1725 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc))
1726 #define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base))
1727 #define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc))
1728 #define radeon_wait_for_vblank(rdev, crtc) rdev->asic->display.wait_for_vblank((rdev), (crtc))
1729 #define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev))
1731 /* Common functions */
1733 extern int radeon_gpu_reset(struct radeon_device *rdev);
1734 extern void radeon_agp_disable(struct radeon_device *rdev);
1735 extern int radeon_modeset_init(struct radeon_device *rdev);
1736 extern void radeon_modeset_fini(struct radeon_device *rdev);
1737 extern bool radeon_card_posted(struct radeon_device *rdev);
1738 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1739 extern void radeon_update_display_priority(struct radeon_device *rdev);
1740 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1741 extern void radeon_scratch_init(struct radeon_device *rdev);
1742 extern void radeon_wb_fini(struct radeon_device *rdev);
1743 extern int radeon_wb_init(struct radeon_device *rdev);
1744 extern void radeon_wb_disable(struct radeon_device *rdev);
1745 extern void radeon_surface_init(struct radeon_device *rdev);
1746 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1747 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1748 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1749 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1750 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1751 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1752 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1753 extern int radeon_resume_kms(struct drm_device *dev);
1754 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1755 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1760 int radeon_vm_manager_init(struct radeon_device *rdev);
1761 void radeon_vm_manager_fini(struct radeon_device *rdev);
1762 int radeon_vm_manager_start(struct radeon_device *rdev);
1763 int radeon_vm_manager_suspend(struct radeon_device *rdev);
1764 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1765 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1766 int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm);
1767 void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
1768 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1769 struct radeon_vm *vm,
1770 struct radeon_bo *bo,
1771 struct ttm_mem_reg *mem);
1772 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1773 struct radeon_bo *bo);
1774 int radeon_vm_bo_add(struct radeon_device *rdev,
1775 struct radeon_vm *vm,
1776 struct radeon_bo *bo,
1779 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1780 struct radeon_vm *vm,
1781 struct radeon_bo *bo);
1784 void r600_audio_update_hdmi(struct work_struct *work);
1787 * R600 vram scratch functions
1789 int r600_vram_scratch_init(struct radeon_device *rdev);
1790 void r600_vram_scratch_fini(struct radeon_device *rdev);
1793 * r600 cs checking helper
1795 unsigned r600_mip_minify(unsigned size, unsigned level);
1796 bool r600_fmt_is_valid_color(u32 format);
1797 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1798 int r600_fmt_get_blocksize(u32 format);
1799 int r600_fmt_get_nblocksx(u32 format, u32 w);
1800 int r600_fmt_get_nblocksy(u32 format, u32 h);
1803 * r600 functions used by radeon_encoder.c
1805 struct radeon_hdmi_acr {
1819 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
1821 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1822 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1823 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1824 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1825 u32 tiling_pipe_num,
1827 u32 total_max_rb_num,
1828 u32 enabled_rb_mask);
1831 * evergreen functions used by radeon_encoder.c
1834 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1836 extern int ni_init_microcode(struct radeon_device *rdev);
1837 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1840 #if defined(CONFIG_ACPI)
1841 extern int radeon_acpi_init(struct radeon_device *rdev);
1843 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1846 #include "radeon_object.h"