2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
100 * Copy from radeon_drv.h so we don't have to include both and have conflicting
103 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
104 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
105 /* RADEON_IB_POOL_SIZE must be a power of 2 */
106 #define RADEON_IB_POOL_SIZE 16
107 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
108 #define RADEONFB_CONN_LIMIT 4
109 #define RADEON_BIOS_NUM_SCRATCH 8
111 /* max number of rings */
112 #define RADEON_NUM_RINGS 3
114 /* fence seq are set to this number when signaled */
115 #define RADEON_FENCE_SIGNALED_SEQ 0LL
117 /* internal ring indices */
118 /* r1xx+ has gfx CP ring */
119 #define RADEON_RING_TYPE_GFX_INDEX 0
121 /* cayman has 2 compute CP rings */
122 #define CAYMAN_RING_TYPE_CP1_INDEX 1
123 #define CAYMAN_RING_TYPE_CP2_INDEX 2
125 /* hardcode those limit for now */
126 #define RADEON_VA_RESERVED_SIZE (8 << 20)
127 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
130 * Errata workarounds.
132 enum radeon_pll_errata {
133 CHIP_ERRATA_R300_CG = 0x00000001,
134 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
135 CHIP_ERRATA_PLL_DELAY = 0x00000004
139 struct radeon_device;
145 #define ATRM_BIOS_PAGE 4096
147 #if defined(CONFIG_VGA_SWITCHEROO)
148 bool radeon_atrm_supported(struct pci_dev *pdev);
149 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
151 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
156 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
160 bool radeon_get_bios(struct radeon_device *rdev);
164 * Mutex which allows recursive locking from the same process.
166 struct radeon_mutex {
168 struct task_struct *owner;
172 static inline void radeon_mutex_init(struct radeon_mutex *mutex)
174 mutex_init(&mutex->mutex);
179 static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
181 if (mutex_trylock(&mutex->mutex)) {
182 /* The mutex was unlocked before, so it's ours now */
183 mutex->owner = current;
184 } else if (mutex->owner != current) {
185 /* Another process locked the mutex, take it */
186 mutex_lock(&mutex->mutex);
187 mutex->owner = current;
189 /* Otherwise the mutex was already locked by this process */
194 static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
196 if (--mutex->level > 0)
200 mutex_unlock(&mutex->mutex);
207 struct radeon_dummy_page {
211 int radeon_dummy_page_init(struct radeon_device *rdev);
212 void radeon_dummy_page_fini(struct radeon_device *rdev);
218 struct radeon_clock {
219 struct radeon_pll p1pll;
220 struct radeon_pll p2pll;
221 struct radeon_pll dcpll;
222 struct radeon_pll spll;
223 struct radeon_pll mpll;
225 uint32_t default_mclk;
226 uint32_t default_sclk;
227 uint32_t default_dispclk;
229 uint32_t max_pixel_clock;
235 int radeon_pm_init(struct radeon_device *rdev);
236 void radeon_pm_fini(struct radeon_device *rdev);
237 void radeon_pm_compute_clocks(struct radeon_device *rdev);
238 void radeon_pm_suspend(struct radeon_device *rdev);
239 void radeon_pm_resume(struct radeon_device *rdev);
240 void radeon_combios_get_power_modes(struct radeon_device *rdev);
241 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
242 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
243 void rs690_pm_info(struct radeon_device *rdev);
244 extern int rv6xx_get_temp(struct radeon_device *rdev);
245 extern int rv770_get_temp(struct radeon_device *rdev);
246 extern int evergreen_get_temp(struct radeon_device *rdev);
247 extern int sumo_get_temp(struct radeon_device *rdev);
248 extern int si_get_temp(struct radeon_device *rdev);
249 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
250 unsigned *bankh, unsigned *mtaspect,
251 unsigned *tile_split);
256 struct radeon_fence_driver {
257 uint32_t scratch_reg;
259 volatile uint32_t *cpu_addr;
260 /* sync_seq is protected by ring emission lock */
261 uint64_t sync_seq[RADEON_NUM_RINGS];
263 unsigned long last_activity;
267 struct radeon_fence {
268 struct radeon_device *rdev;
270 /* protected by radeon_fence.lock */
276 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
277 int radeon_fence_driver_init(struct radeon_device *rdev);
278 void radeon_fence_driver_fini(struct radeon_device *rdev);
279 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
280 void radeon_fence_process(struct radeon_device *rdev, int ring);
281 bool radeon_fence_signaled(struct radeon_fence *fence);
282 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
283 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
284 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
285 int radeon_fence_wait_any(struct radeon_device *rdev,
286 struct radeon_fence **fences,
288 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
289 void radeon_fence_unref(struct radeon_fence **fence);
290 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
291 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
292 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
293 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
294 struct radeon_fence *b)
304 BUG_ON(a->ring != b->ring);
306 if (a->seq > b->seq) {
316 struct radeon_surface_reg {
317 struct radeon_bo *bo;
320 #define RADEON_GEM_MAX_SURFACES 8
326 struct ttm_bo_global_ref bo_global_ref;
327 struct drm_global_reference mem_global_ref;
328 struct ttm_bo_device bdev;
329 bool mem_global_referenced;
333 /* bo virtual address in a specific vm */
334 struct radeon_bo_va {
335 /* bo list is protected by bo being reserved */
336 struct list_head bo_list;
337 /* vm list is protected by vm mutex */
338 struct list_head vm_list;
339 /* constant after initialization */
340 struct radeon_vm *vm;
341 struct radeon_bo *bo;
349 /* Protected by gem.mutex */
350 struct list_head list;
351 /* Protected by tbo.reserved */
353 struct ttm_placement placement;
354 struct ttm_buffer_object tbo;
355 struct ttm_bo_kmap_obj kmap;
361 /* list of all virtual address to which this bo
365 /* Constant after initialization */
366 struct radeon_device *rdev;
367 struct drm_gem_object gem_base;
369 struct ttm_bo_kmap_obj dma_buf_vmap;
372 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
374 struct radeon_bo_list {
375 struct ttm_validate_buffer tv;
376 struct radeon_bo *bo;
383 /* sub-allocation manager, it has to be protected by another lock.
384 * By conception this is an helper for other part of the driver
385 * like the indirect buffer or semaphore, which both have their
388 * Principe is simple, we keep a list of sub allocation in offset
389 * order (first entry has offset == 0, last entry has the highest
392 * When allocating new object we first check if there is room at
393 * the end total_size - (last_object_offset + last_object_size) >=
394 * alloc_size. If so we allocate new object there.
396 * When there is not enough room at the end, we start waiting for
397 * each sub object until we reach object_offset+object_size >=
398 * alloc_size, this object then become the sub object we return.
400 * Alignment can't be bigger than page size.
402 * Hole are not considered for allocation to keep things simple.
403 * Assumption is that there won't be hole (all object on same
406 struct radeon_sa_manager {
408 struct radeon_bo *bo;
409 struct list_head *hole;
410 struct list_head flist[RADEON_NUM_RINGS];
411 struct list_head olist;
420 /* sub-allocation buffer */
421 struct radeon_sa_bo {
422 struct list_head olist;
423 struct list_head flist;
424 struct radeon_sa_manager *manager;
427 struct radeon_fence *fence;
435 struct list_head objects;
438 int radeon_gem_init(struct radeon_device *rdev);
439 void radeon_gem_fini(struct radeon_device *rdev);
440 int radeon_gem_object_create(struct radeon_device *rdev, int size,
441 int alignment, int initial_domain,
442 bool discardable, bool kernel,
443 struct drm_gem_object **obj);
445 int radeon_mode_dumb_create(struct drm_file *file_priv,
446 struct drm_device *dev,
447 struct drm_mode_create_dumb *args);
448 int radeon_mode_dumb_mmap(struct drm_file *filp,
449 struct drm_device *dev,
450 uint32_t handle, uint64_t *offset_p);
451 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
452 struct drm_device *dev,
458 /* everything here is constant */
459 struct radeon_semaphore {
460 struct radeon_sa_bo *sa_bo;
465 int radeon_semaphore_create(struct radeon_device *rdev,
466 struct radeon_semaphore **semaphore);
467 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
468 struct radeon_semaphore *semaphore);
469 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
470 struct radeon_semaphore *semaphore);
471 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
472 struct radeon_semaphore *semaphore,
473 int signaler, int waiter);
474 void radeon_semaphore_free(struct radeon_device *rdev,
475 struct radeon_semaphore **semaphore,
476 struct radeon_fence *fence);
479 * GART structures, functions & helpers
483 #define RADEON_GPU_PAGE_SIZE 4096
484 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
485 #define RADEON_GPU_PAGE_SHIFT 12
486 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
489 dma_addr_t table_addr;
490 struct radeon_bo *robj;
492 unsigned num_gpu_pages;
493 unsigned num_cpu_pages;
496 dma_addr_t *pages_addr;
500 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
501 void radeon_gart_table_ram_free(struct radeon_device *rdev);
502 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
503 void radeon_gart_table_vram_free(struct radeon_device *rdev);
504 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
505 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
506 int radeon_gart_init(struct radeon_device *rdev);
507 void radeon_gart_fini(struct radeon_device *rdev);
508 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
510 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
511 int pages, struct page **pagelist,
512 dma_addr_t *dma_addr);
513 void radeon_gart_restore(struct radeon_device *rdev);
517 * GPU MC structures, functions & helpers
520 resource_size_t aper_size;
521 resource_size_t aper_base;
522 resource_size_t agp_base;
523 /* for some chips with <= 32MB we need to lie
524 * about vram size near mc fb location */
526 u64 visible_vram_size;
536 bool igp_sideport_enabled;
540 bool radeon_combios_sideport_present(struct radeon_device *rdev);
541 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
544 * GPU scratch registers structures, functions & helpers
546 struct radeon_scratch {
553 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
554 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
561 struct radeon_unpin_work {
562 struct work_struct work;
563 struct radeon_device *rdev;
565 struct radeon_fence *fence;
566 struct drm_pending_vblank_event *event;
567 struct radeon_bo *old_rbo;
571 struct r500_irq_stat_regs {
576 struct r600_irq_stat_regs {
586 struct evergreen_irq_stat_regs {
607 union radeon_irq_stat_regs {
608 struct r500_irq_stat_regs r500;
609 struct r600_irq_stat_regs r600;
610 struct evergreen_irq_stat_regs evergreen;
613 #define RADEON_MAX_HPD_PINS 6
614 #define RADEON_MAX_CRTCS 6
615 #define RADEON_MAX_AFMT_BLOCKS 6
620 atomic_t ring_int[RADEON_NUM_RINGS];
621 bool crtc_vblank_int[RADEON_MAX_CRTCS];
622 atomic_t pflip[RADEON_MAX_CRTCS];
623 wait_queue_head_t vblank_queue;
624 bool hpd[RADEON_MAX_HPD_PINS];
627 wait_queue_head_t idle_queue;
628 bool afmt[RADEON_MAX_AFMT_BLOCKS];
629 union radeon_irq_stat_regs stat_regs;
632 int radeon_irq_kms_init(struct radeon_device *rdev);
633 void radeon_irq_kms_fini(struct radeon_device *rdev);
634 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
635 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
636 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
637 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
638 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
639 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
640 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
641 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
642 int radeon_irq_kms_wait_gui_idle(struct radeon_device *rdev);
649 struct radeon_sa_bo *sa_bo;
654 struct radeon_fence *fence;
657 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
658 struct radeon_semaphore *semaphore;
662 struct radeon_bo *ring_obj;
663 volatile uint32_t *ring;
671 unsigned ring_free_dw;
673 unsigned long last_activity;
688 struct list_head list;
694 struct radeon_sa_bo *sa_bo;
696 /* last fence for cs using this vm */
697 struct radeon_fence *fence;
700 struct radeon_vm_funcs {
701 int (*init)(struct radeon_device *rdev);
702 void (*fini)(struct radeon_device *rdev);
703 /* cs mutex must be lock for schedule_ib */
704 int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id);
705 void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm);
706 void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm);
707 uint32_t (*page_flags)(struct radeon_device *rdev,
708 struct radeon_vm *vm,
710 void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm,
711 unsigned pfn, uint64_t addr, uint32_t flags);
714 struct radeon_vm_manager {
715 struct list_head lru_vm;
717 struct radeon_sa_manager sa_manager;
719 /* fields constant after init */
720 const struct radeon_vm_funcs *funcs;
721 /* number of VMIDs */
723 /* vram base address for page table entry */
724 u64 vram_base_offset;
730 * file private structure
732 struct radeon_fpriv {
740 struct radeon_bo *ring_obj;
741 volatile uint32_t *ring;
750 struct r600_blit_cp_primitives {
751 void (*set_render_target)(struct radeon_device *rdev, int format,
752 int w, int h, u64 gpu_addr);
753 void (*cp_set_surface_sync)(struct radeon_device *rdev,
754 u32 sync_type, u32 size,
756 void (*set_shaders)(struct radeon_device *rdev);
757 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
758 void (*set_tex_resource)(struct radeon_device *rdev,
759 int format, int w, int h, int pitch,
760 u64 gpu_addr, u32 size);
761 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
763 void (*draw_auto)(struct radeon_device *rdev);
764 void (*set_default_state)(struct radeon_device *rdev);
768 struct radeon_bo *shader_obj;
769 struct r600_blit_cp_primitives primitives;
771 int ring_size_common;
772 int ring_size_per_loop;
774 u32 vs_offset, ps_offset;
779 void r600_blit_suspend(struct radeon_device *rdev);
785 /* for power gating */
786 struct radeon_bo *save_restore_obj;
787 uint64_t save_restore_gpu_addr;
788 /* for clear state */
789 struct radeon_bo *clear_state_obj;
790 uint64_t clear_state_gpu_addr;
793 int radeon_ib_get(struct radeon_device *rdev, int ring,
794 struct radeon_ib *ib, unsigned size);
795 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
796 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
797 int radeon_ib_pool_init(struct radeon_device *rdev);
798 void radeon_ib_pool_fini(struct radeon_device *rdev);
799 int radeon_ib_pool_start(struct radeon_device *rdev);
800 int radeon_ib_pool_suspend(struct radeon_device *rdev);
801 int radeon_ib_ring_tests(struct radeon_device *rdev);
802 /* Ring access between begin & end cannot sleep */
803 int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp);
804 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
805 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
806 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
807 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
808 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
809 void radeon_ring_undo(struct radeon_ring *ring);
810 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
811 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
812 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
813 void radeon_ring_lockup_update(struct radeon_ring *ring);
814 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
815 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
816 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
817 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
818 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
824 struct radeon_cs_reloc {
825 struct drm_gem_object *gobj;
826 struct radeon_bo *robj;
827 struct radeon_bo_list lobj;
832 struct radeon_cs_chunk {
838 void __user *user_ptr;
839 int last_copied_page;
843 struct radeon_cs_parser {
845 struct radeon_device *rdev;
846 struct drm_file *filp;
849 struct radeon_cs_chunk *chunks;
850 uint64_t *chunks_array;
855 struct radeon_cs_reloc *relocs;
856 struct radeon_cs_reloc **relocs_ptr;
857 struct list_head validated;
858 /* indices of various chunks */
860 int chunk_relocs_idx;
862 int chunk_const_ib_idx;
864 struct radeon_ib const_ib;
873 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
874 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
876 struct radeon_cs_packet {
885 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
886 struct radeon_cs_packet *pkt,
887 unsigned idx, unsigned reg);
888 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
889 struct radeon_cs_packet *pkt);
895 int radeon_agp_init(struct radeon_device *rdev);
896 void radeon_agp_resume(struct radeon_device *rdev);
897 void radeon_agp_suspend(struct radeon_device *rdev);
898 void radeon_agp_fini(struct radeon_device *rdev);
905 struct radeon_bo *wb_obj;
906 volatile uint32_t *wb;
912 #define RADEON_WB_SCRATCH_OFFSET 0
913 #define RADEON_WB_CP_RPTR_OFFSET 1024
914 #define RADEON_WB_CP1_RPTR_OFFSET 1280
915 #define RADEON_WB_CP2_RPTR_OFFSET 1536
916 #define R600_WB_IH_WPTR_OFFSET 2048
917 #define R600_WB_EVENT_OFFSET 3072
920 * struct radeon_pm - power management datas
921 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
922 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
923 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
924 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
925 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
926 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
927 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
928 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
929 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
930 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
931 * @needed_bandwidth: current bandwidth needs
933 * It keeps track of various data needed to take powermanagement decision.
934 * Bandwidth need is used to determine minimun clock of the GPU and memory.
935 * Equation between gpu/memory clock and available bandwidth is hw dependent
936 * (type of memory, bus size, efficiency, ...)
939 enum radeon_pm_method {
944 enum radeon_dynpm_state {
945 DYNPM_STATE_DISABLED,
949 DYNPM_STATE_SUSPENDED,
951 enum radeon_dynpm_action {
953 DYNPM_ACTION_MINIMUM,
954 DYNPM_ACTION_DOWNCLOCK,
955 DYNPM_ACTION_UPCLOCK,
959 enum radeon_voltage_type {
966 enum radeon_pm_state_type {
967 POWER_STATE_TYPE_DEFAULT,
968 POWER_STATE_TYPE_POWERSAVE,
969 POWER_STATE_TYPE_BATTERY,
970 POWER_STATE_TYPE_BALANCED,
971 POWER_STATE_TYPE_PERFORMANCE,
974 enum radeon_pm_profile_type {
982 #define PM_PROFILE_DEFAULT_IDX 0
983 #define PM_PROFILE_LOW_SH_IDX 1
984 #define PM_PROFILE_MID_SH_IDX 2
985 #define PM_PROFILE_HIGH_SH_IDX 3
986 #define PM_PROFILE_LOW_MH_IDX 4
987 #define PM_PROFILE_MID_MH_IDX 5
988 #define PM_PROFILE_HIGH_MH_IDX 6
989 #define PM_PROFILE_MAX 7
991 struct radeon_pm_profile {
998 enum radeon_int_thermal_type {
1002 THERMAL_TYPE_EVERGREEN,
1008 struct radeon_voltage {
1009 enum radeon_voltage_type type;
1011 struct radeon_gpio_rec gpio;
1012 u32 delay; /* delay in usec from voltage drop to sclk change */
1013 bool active_high; /* voltage drop is active when bit is high */
1015 u8 vddc_id; /* index into vddc voltage table */
1016 u8 vddci_id; /* index into vddci voltage table */
1020 /* evergreen+ vddci */
1024 /* clock mode flags */
1025 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1027 struct radeon_pm_clock_info {
1033 struct radeon_voltage voltage;
1034 /* standardized clock flags */
1039 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1041 struct radeon_power_state {
1042 enum radeon_pm_state_type type;
1043 struct radeon_pm_clock_info *clock_info;
1044 /* number of valid clock modes in this power state */
1045 int num_clock_modes;
1046 struct radeon_pm_clock_info *default_clock_mode;
1047 /* standardized state flags */
1049 u32 misc; /* vbios specific flags */
1050 u32 misc2; /* vbios specific flags */
1051 int pcie_lanes; /* pcie lanes */
1055 * Some modes are overclocked by very low value, accept them
1057 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1061 /* write locked while reprogramming mclk */
1062 struct rw_semaphore mclk_lock;
1064 int active_crtc_count;
1067 fixed20_12 max_bandwidth;
1068 fixed20_12 igp_sideport_mclk;
1069 fixed20_12 igp_system_mclk;
1070 fixed20_12 igp_ht_link_clk;
1071 fixed20_12 igp_ht_link_width;
1072 fixed20_12 k8_bandwidth;
1073 fixed20_12 sideport_bandwidth;
1074 fixed20_12 ht_bandwidth;
1075 fixed20_12 core_bandwidth;
1078 fixed20_12 needed_bandwidth;
1079 struct radeon_power_state *power_state;
1080 /* number of valid power states */
1081 int num_power_states;
1082 int current_power_state_index;
1083 int current_clock_mode_index;
1084 int requested_power_state_index;
1085 int requested_clock_mode_index;
1086 int default_power_state_index;
1095 struct radeon_i2c_chan *i2c_bus;
1096 /* selected pm method */
1097 enum radeon_pm_method pm_method;
1098 /* dynpm power management */
1099 struct delayed_work dynpm_idle_work;
1100 enum radeon_dynpm_state dynpm_state;
1101 enum radeon_dynpm_action dynpm_planned_action;
1102 unsigned long dynpm_action_timeout;
1103 bool dynpm_can_upclock;
1104 bool dynpm_can_downclock;
1105 /* profile-based power management */
1106 enum radeon_pm_profile_type profile;
1108 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1109 /* internal thermal controller on rv6xx+ */
1110 enum radeon_int_thermal_type int_thermal_type;
1111 struct device *int_hwmon_dev;
1114 int radeon_pm_get_type_index(struct radeon_device *rdev,
1115 enum radeon_pm_state_type ps_type,
1121 int bits_per_sample;
1129 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1135 void radeon_test_moves(struct radeon_device *rdev);
1136 void radeon_test_ring_sync(struct radeon_device *rdev,
1137 struct radeon_ring *cpA,
1138 struct radeon_ring *cpB);
1139 void radeon_test_syncing(struct radeon_device *rdev);
1145 struct radeon_debugfs {
1146 struct drm_info_list *files;
1150 int radeon_debugfs_add_files(struct radeon_device *rdev,
1151 struct drm_info_list *files,
1153 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1157 * ASIC specific functions.
1159 struct radeon_asic {
1160 int (*init)(struct radeon_device *rdev);
1161 void (*fini)(struct radeon_device *rdev);
1162 int (*resume)(struct radeon_device *rdev);
1163 int (*suspend)(struct radeon_device *rdev);
1164 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1165 int (*asic_reset)(struct radeon_device *rdev);
1166 /* ioctl hw specific callback. Some hw might want to perform special
1167 * operation on specific ioctl. For instance on wait idle some hw
1168 * might want to perform and HDP flush through MMIO as it seems that
1169 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1172 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1173 /* check if 3D engine is idle */
1174 bool (*gui_idle)(struct radeon_device *rdev);
1175 /* wait for mc_idle */
1176 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1179 void (*tlb_flush)(struct radeon_device *rdev);
1180 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1182 /* ring specific callbacks */
1184 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1185 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1186 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1187 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1188 struct radeon_semaphore *semaphore, bool emit_wait);
1189 int (*cs_parse)(struct radeon_cs_parser *p);
1190 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1191 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1192 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1193 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1194 } ring[RADEON_NUM_RINGS];
1197 int (*set)(struct radeon_device *rdev);
1198 int (*process)(struct radeon_device *rdev);
1202 /* display watermarks */
1203 void (*bandwidth_update)(struct radeon_device *rdev);
1204 /* get frame count */
1205 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1206 /* wait for vblank */
1207 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1209 /* copy functions for bo handling */
1211 int (*blit)(struct radeon_device *rdev,
1212 uint64_t src_offset,
1213 uint64_t dst_offset,
1214 unsigned num_gpu_pages,
1215 struct radeon_fence **fence);
1216 u32 blit_ring_index;
1217 int (*dma)(struct radeon_device *rdev,
1218 uint64_t src_offset,
1219 uint64_t dst_offset,
1220 unsigned num_gpu_pages,
1221 struct radeon_fence **fence);
1223 /* method used for bo copy */
1224 int (*copy)(struct radeon_device *rdev,
1225 uint64_t src_offset,
1226 uint64_t dst_offset,
1227 unsigned num_gpu_pages,
1228 struct radeon_fence **fence);
1229 /* ring used for bo copies */
1230 u32 copy_ring_index;
1234 int (*set_reg)(struct radeon_device *rdev, int reg,
1235 uint32_t tiling_flags, uint32_t pitch,
1236 uint32_t offset, uint32_t obj_size);
1237 void (*clear_reg)(struct radeon_device *rdev, int reg);
1239 /* hotplug detect */
1241 void (*init)(struct radeon_device *rdev);
1242 void (*fini)(struct radeon_device *rdev);
1243 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1244 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1246 /* power management */
1248 void (*misc)(struct radeon_device *rdev);
1249 void (*prepare)(struct radeon_device *rdev);
1250 void (*finish)(struct radeon_device *rdev);
1251 void (*init_profile)(struct radeon_device *rdev);
1252 void (*get_dynpm_state)(struct radeon_device *rdev);
1253 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1254 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1255 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1256 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1257 int (*get_pcie_lanes)(struct radeon_device *rdev);
1258 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1259 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1263 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1264 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1265 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1273 const unsigned *reg_safe_bm;
1274 unsigned reg_safe_bm_size;
1279 const unsigned *reg_safe_bm;
1280 unsigned reg_safe_bm_size;
1287 unsigned max_tile_pipes;
1289 unsigned max_backends;
1291 unsigned max_threads;
1292 unsigned max_stack_entries;
1293 unsigned max_hw_contexts;
1294 unsigned max_gs_threads;
1295 unsigned sx_max_export_size;
1296 unsigned sx_max_export_pos_size;
1297 unsigned sx_max_export_smx_size;
1298 unsigned sq_num_cf_insts;
1299 unsigned tiling_nbanks;
1300 unsigned tiling_npipes;
1301 unsigned tiling_group_size;
1302 unsigned tile_config;
1303 unsigned backend_map;
1308 unsigned max_tile_pipes;
1310 unsigned max_backends;
1312 unsigned max_threads;
1313 unsigned max_stack_entries;
1314 unsigned max_hw_contexts;
1315 unsigned max_gs_threads;
1316 unsigned sx_max_export_size;
1317 unsigned sx_max_export_pos_size;
1318 unsigned sx_max_export_smx_size;
1319 unsigned sq_num_cf_insts;
1320 unsigned sx_num_of_sets;
1321 unsigned sc_prim_fifo_size;
1322 unsigned sc_hiz_tile_fifo_size;
1323 unsigned sc_earlyz_tile_fifo_fize;
1324 unsigned tiling_nbanks;
1325 unsigned tiling_npipes;
1326 unsigned tiling_group_size;
1327 unsigned tile_config;
1328 unsigned backend_map;
1331 struct evergreen_asic {
1334 unsigned max_tile_pipes;
1336 unsigned max_backends;
1338 unsigned max_threads;
1339 unsigned max_stack_entries;
1340 unsigned max_hw_contexts;
1341 unsigned max_gs_threads;
1342 unsigned sx_max_export_size;
1343 unsigned sx_max_export_pos_size;
1344 unsigned sx_max_export_smx_size;
1345 unsigned sq_num_cf_insts;
1346 unsigned sx_num_of_sets;
1347 unsigned sc_prim_fifo_size;
1348 unsigned sc_hiz_tile_fifo_size;
1349 unsigned sc_earlyz_tile_fifo_size;
1350 unsigned tiling_nbanks;
1351 unsigned tiling_npipes;
1352 unsigned tiling_group_size;
1353 unsigned tile_config;
1354 unsigned backend_map;
1357 struct cayman_asic {
1358 unsigned max_shader_engines;
1359 unsigned max_pipes_per_simd;
1360 unsigned max_tile_pipes;
1361 unsigned max_simds_per_se;
1362 unsigned max_backends_per_se;
1363 unsigned max_texture_channel_caches;
1365 unsigned max_threads;
1366 unsigned max_gs_threads;
1367 unsigned max_stack_entries;
1368 unsigned sx_num_of_sets;
1369 unsigned sx_max_export_size;
1370 unsigned sx_max_export_pos_size;
1371 unsigned sx_max_export_smx_size;
1372 unsigned max_hw_contexts;
1373 unsigned sq_num_cf_insts;
1374 unsigned sc_prim_fifo_size;
1375 unsigned sc_hiz_tile_fifo_size;
1376 unsigned sc_earlyz_tile_fifo_size;
1378 unsigned num_shader_engines;
1379 unsigned num_shader_pipes_per_simd;
1380 unsigned num_tile_pipes;
1381 unsigned num_simds_per_se;
1382 unsigned num_backends_per_se;
1383 unsigned backend_disable_mask_per_asic;
1384 unsigned backend_map;
1385 unsigned num_texture_channel_caches;
1386 unsigned mem_max_burst_length_bytes;
1387 unsigned mem_row_size_in_kb;
1388 unsigned shader_engine_tile_size;
1390 unsigned multi_gpu_tile_size;
1392 unsigned tile_config;
1396 unsigned max_shader_engines;
1397 unsigned max_tile_pipes;
1398 unsigned max_cu_per_sh;
1399 unsigned max_sh_per_se;
1400 unsigned max_backends_per_se;
1401 unsigned max_texture_channel_caches;
1403 unsigned max_gs_threads;
1404 unsigned max_hw_contexts;
1405 unsigned sc_prim_fifo_size_frontend;
1406 unsigned sc_prim_fifo_size_backend;
1407 unsigned sc_hiz_tile_fifo_size;
1408 unsigned sc_earlyz_tile_fifo_size;
1410 unsigned num_tile_pipes;
1411 unsigned num_backends_per_se;
1412 unsigned backend_disable_mask_per_asic;
1413 unsigned backend_map;
1414 unsigned num_texture_channel_caches;
1415 unsigned mem_max_burst_length_bytes;
1416 unsigned mem_row_size_in_kb;
1417 unsigned shader_engine_tile_size;
1419 unsigned multi_gpu_tile_size;
1421 unsigned tile_config;
1424 union radeon_asic_config {
1425 struct r300_asic r300;
1426 struct r100_asic r100;
1427 struct r600_asic r600;
1428 struct rv770_asic rv770;
1429 struct evergreen_asic evergreen;
1430 struct cayman_asic cayman;
1435 * asic initizalization from radeon_asic.c
1437 void radeon_agp_disable(struct radeon_device *rdev);
1438 int radeon_asic_init(struct radeon_device *rdev);
1444 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1445 struct drm_file *filp);
1446 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1447 struct drm_file *filp);
1448 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1449 struct drm_file *file_priv);
1450 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1451 struct drm_file *file_priv);
1452 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1453 struct drm_file *file_priv);
1454 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1455 struct drm_file *file_priv);
1456 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1457 struct drm_file *filp);
1458 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1459 struct drm_file *filp);
1460 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1461 struct drm_file *filp);
1462 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1463 struct drm_file *filp);
1464 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1465 struct drm_file *filp);
1466 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1467 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1468 struct drm_file *filp);
1469 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1470 struct drm_file *filp);
1472 /* VRAM scratch page for HDP bug, default vram page */
1473 struct r600_vram_scratch {
1474 struct radeon_bo *robj;
1475 volatile uint32_t *ptr;
1481 * Core structure, functions and helpers.
1483 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1484 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1486 struct radeon_device {
1488 struct drm_device *ddev;
1489 struct pci_dev *pdev;
1491 union radeon_asic_config config;
1492 enum radeon_family family;
1493 unsigned long flags;
1495 enum radeon_pll_errata pll_errata;
1502 uint16_t bios_header_start;
1503 struct radeon_bo *stollen_vga_memory;
1505 resource_size_t rmmio_base;
1506 resource_size_t rmmio_size;
1507 void __iomem *rmmio;
1508 radeon_rreg_t mc_rreg;
1509 radeon_wreg_t mc_wreg;
1510 radeon_rreg_t pll_rreg;
1511 radeon_wreg_t pll_wreg;
1512 uint32_t pcie_reg_mask;
1513 radeon_rreg_t pciep_rreg;
1514 radeon_wreg_t pciep_wreg;
1516 void __iomem *rio_mem;
1517 resource_size_t rio_mem_size;
1518 struct radeon_clock clock;
1519 struct radeon_mc mc;
1520 struct radeon_gart gart;
1521 struct radeon_mode_info mode_info;
1522 struct radeon_scratch scratch;
1523 struct radeon_mman mman;
1524 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1525 wait_queue_head_t fence_queue;
1526 struct mutex ring_lock;
1527 struct radeon_ring ring[RADEON_NUM_RINGS];
1529 struct radeon_sa_manager ring_tmp_bo;
1530 struct radeon_irq irq;
1531 struct radeon_asic *asic;
1532 struct radeon_gem gem;
1533 struct radeon_pm pm;
1534 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1535 struct radeon_mutex cs_mutex;
1536 struct radeon_wb wb;
1537 struct radeon_dummy_page dummy_page;
1542 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1543 const struct firmware *me_fw; /* all family ME firmware */
1544 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1545 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1546 const struct firmware *mc_fw; /* NI MC firmware */
1547 const struct firmware *ce_fw; /* SI CE firmware */
1548 struct r600_blit r600_blit;
1549 struct r600_vram_scratch vram_scratch;
1550 int msi_enabled; /* msi enabled */
1551 struct r600_ih ih; /* r6/700 interrupt ring */
1553 struct work_struct hotplug_work;
1554 struct work_struct audio_work;
1555 int num_crtc; /* number of crtcs */
1556 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1558 struct r600_audio audio_status; /* audio stuff */
1559 struct notifier_block acpi_nb;
1560 /* only one userspace can use Hyperz features or CMASK at a time */
1561 struct drm_file *hyperz_filp;
1562 struct drm_file *cmask_filp;
1564 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1566 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1567 unsigned debugfs_count;
1568 /* virtual memory */
1569 struct radeon_vm_manager vm_manager;
1572 int radeon_device_init(struct radeon_device *rdev,
1573 struct drm_device *ddev,
1574 struct pci_dev *pdev,
1576 void radeon_device_fini(struct radeon_device *rdev);
1577 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1579 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1580 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1581 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1582 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1587 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1590 * Registers read & write functions.
1592 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1593 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1594 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1595 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1596 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1597 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1598 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1599 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1600 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1601 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1602 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1603 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1604 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1605 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1606 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1607 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1608 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1609 #define WREG32_P(reg, val, mask) \
1611 uint32_t tmp_ = RREG32(reg); \
1613 tmp_ |= ((val) & ~(mask)); \
1614 WREG32(reg, tmp_); \
1616 #define WREG32_PLL_P(reg, val, mask) \
1618 uint32_t tmp_ = RREG32_PLL(reg); \
1620 tmp_ |= ((val) & ~(mask)); \
1621 WREG32_PLL(reg, tmp_); \
1623 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1624 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1625 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1628 * Indirect registers accessor
1630 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1634 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1635 r = RREG32(RADEON_PCIE_DATA);
1639 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1641 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1642 WREG32(RADEON_PCIE_DATA, (v));
1645 void r100_pll_errata_after_index(struct radeon_device *rdev);
1651 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1652 (rdev->pdev->device == 0x5969))
1653 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1654 (rdev->family == CHIP_RV200) || \
1655 (rdev->family == CHIP_RS100) || \
1656 (rdev->family == CHIP_RS200) || \
1657 (rdev->family == CHIP_RV250) || \
1658 (rdev->family == CHIP_RV280) || \
1659 (rdev->family == CHIP_RS300))
1660 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1661 (rdev->family == CHIP_RV350) || \
1662 (rdev->family == CHIP_R350) || \
1663 (rdev->family == CHIP_RV380) || \
1664 (rdev->family == CHIP_R420) || \
1665 (rdev->family == CHIP_R423) || \
1666 (rdev->family == CHIP_RV410) || \
1667 (rdev->family == CHIP_RS400) || \
1668 (rdev->family == CHIP_RS480))
1669 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1670 (rdev->ddev->pdev->device == 0x9443) || \
1671 (rdev->ddev->pdev->device == 0x944B) || \
1672 (rdev->ddev->pdev->device == 0x9506) || \
1673 (rdev->ddev->pdev->device == 0x9509) || \
1674 (rdev->ddev->pdev->device == 0x950F) || \
1675 (rdev->ddev->pdev->device == 0x689C) || \
1676 (rdev->ddev->pdev->device == 0x689D))
1677 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1678 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1679 (rdev->family == CHIP_RS690) || \
1680 (rdev->family == CHIP_RS740) || \
1681 (rdev->family >= CHIP_R600))
1682 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1683 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1684 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1685 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1686 (rdev->flags & RADEON_IS_IGP))
1687 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1688 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1689 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1690 (rdev->flags & RADEON_IS_IGP))
1695 #define RBIOS8(i) (rdev->bios[i])
1696 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1697 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1699 int radeon_combios_init(struct radeon_device *rdev);
1700 void radeon_combios_fini(struct radeon_device *rdev);
1701 int radeon_atombios_init(struct radeon_device *rdev);
1702 void radeon_atombios_fini(struct radeon_device *rdev);
1708 #if DRM_DEBUG_CODE == 0
1709 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1711 ring->ring[ring->wptr++] = v;
1712 ring->wptr &= ring->ptr_mask;
1714 ring->ring_free_dw--;
1717 /* With debugging this is just too big to inline */
1718 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1724 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1725 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1726 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1727 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1728 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1729 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1730 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1731 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1732 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1733 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1734 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1735 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1736 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1737 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1738 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1739 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1740 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1741 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1742 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1743 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1744 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1745 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1746 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1747 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1748 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1749 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1750 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1751 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1752 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1753 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1754 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1755 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1756 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1757 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1758 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1759 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1760 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1761 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1762 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1763 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1764 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1765 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1766 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1767 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1768 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1769 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1770 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc))
1771 #define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base))
1772 #define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc))
1773 #define radeon_wait_for_vblank(rdev, crtc) rdev->asic->display.wait_for_vblank((rdev), (crtc))
1774 #define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev))
1776 /* Common functions */
1778 extern int radeon_gpu_reset(struct radeon_device *rdev);
1779 extern void radeon_agp_disable(struct radeon_device *rdev);
1780 extern int radeon_modeset_init(struct radeon_device *rdev);
1781 extern void radeon_modeset_fini(struct radeon_device *rdev);
1782 extern bool radeon_card_posted(struct radeon_device *rdev);
1783 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1784 extern void radeon_update_display_priority(struct radeon_device *rdev);
1785 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1786 extern void radeon_scratch_init(struct radeon_device *rdev);
1787 extern void radeon_wb_fini(struct radeon_device *rdev);
1788 extern int radeon_wb_init(struct radeon_device *rdev);
1789 extern void radeon_wb_disable(struct radeon_device *rdev);
1790 extern void radeon_surface_init(struct radeon_device *rdev);
1791 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1792 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1793 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1794 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1795 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1796 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1797 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1798 extern int radeon_resume_kms(struct drm_device *dev);
1799 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1800 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1805 int radeon_vm_manager_init(struct radeon_device *rdev);
1806 void radeon_vm_manager_fini(struct radeon_device *rdev);
1807 int radeon_vm_manager_start(struct radeon_device *rdev);
1808 int radeon_vm_manager_suspend(struct radeon_device *rdev);
1809 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1810 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1811 int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm);
1812 void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
1813 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1814 struct radeon_vm *vm,
1815 struct radeon_bo *bo,
1816 struct ttm_mem_reg *mem);
1817 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1818 struct radeon_bo *bo);
1819 int radeon_vm_bo_add(struct radeon_device *rdev,
1820 struct radeon_vm *vm,
1821 struct radeon_bo *bo,
1824 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1825 struct radeon_vm *vm,
1826 struct radeon_bo *bo);
1829 void r600_audio_update_hdmi(struct work_struct *work);
1832 * R600 vram scratch functions
1834 int r600_vram_scratch_init(struct radeon_device *rdev);
1835 void r600_vram_scratch_fini(struct radeon_device *rdev);
1838 * r600 cs checking helper
1840 unsigned r600_mip_minify(unsigned size, unsigned level);
1841 bool r600_fmt_is_valid_color(u32 format);
1842 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1843 int r600_fmt_get_blocksize(u32 format);
1844 int r600_fmt_get_nblocksx(u32 format, u32 w);
1845 int r600_fmt_get_nblocksy(u32 format, u32 h);
1848 * r600 functions used by radeon_encoder.c
1850 struct radeon_hdmi_acr {
1864 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
1866 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1867 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1868 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1869 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1870 u32 tiling_pipe_num,
1872 u32 total_max_rb_num,
1873 u32 enabled_rb_mask);
1876 * evergreen functions used by radeon_encoder.c
1879 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1881 extern int ni_init_microcode(struct radeon_device *rdev);
1882 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1885 #if defined(CONFIG_ACPI)
1886 extern int radeon_acpi_init(struct radeon_device *rdev);
1888 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1891 #include "radeon_object.h"