2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
26 #include "radeon_asic.h"
29 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev);
33 * Starting with R600, the GPU has an asynchronous
34 * DMA engine. The programming model is very similar
35 * to the 3D engine (ring buffer, IBs, etc.), but the
36 * DMA controller has it's own packet format that is
37 * different form the PM4 format used by the 3D engine.
38 * It supports copying data, writing embedded data,
39 * solid fills, and a number of other things. It also
40 * has support for tiling/detiling of buffers.
44 * r600_dma_get_rptr - get the current read pointer
46 * @rdev: radeon_device pointer
47 * @ring: radeon ring pointer
49 * Get the current rptr from the hardware (r6xx+).
51 uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
52 struct radeon_ring *ring)
57 rptr = rdev->wb.wb[ring->rptr_offs/4];
59 rptr = RREG32(DMA_RB_RPTR);
61 return (rptr & 0x3fffc) >> 2;
65 * r600_dma_get_wptr - get the current write pointer
67 * @rdev: radeon_device pointer
68 * @ring: radeon ring pointer
70 * Get the current wptr from the hardware (r6xx+).
72 uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
73 struct radeon_ring *ring)
75 return (RREG32(DMA_RB_WPTR) & 0x3fffc) >> 2;
79 * r600_dma_set_wptr - commit the write pointer
81 * @rdev: radeon_device pointer
82 * @ring: radeon ring pointer
84 * Write the wptr back to the hardware (r6xx+).
86 void r600_dma_set_wptr(struct radeon_device *rdev,
87 struct radeon_ring *ring)
89 WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc);
93 * r600_dma_stop - stop the async dma engine
95 * @rdev: radeon_device pointer
97 * Stop the async dma engine (r6xx-evergreen).
99 void r600_dma_stop(struct radeon_device *rdev)
101 u32 rb_cntl = RREG32(DMA_RB_CNTL);
103 if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX)
104 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
106 rb_cntl &= ~DMA_RB_ENABLE;
107 WREG32(DMA_RB_CNTL, rb_cntl);
109 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
113 * r600_dma_resume - setup and start the async dma engine
115 * @rdev: radeon_device pointer
117 * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
118 * Returns 0 for success, error for failure.
120 int r600_dma_resume(struct radeon_device *rdev)
122 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
123 u32 rb_cntl, dma_cntl, ib_cntl;
127 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
128 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
130 /* Set ring buffer size in dwords */
131 rb_bufsz = order_base_2(ring->ring_size / 4);
132 rb_cntl = rb_bufsz << 1;
134 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
136 WREG32(DMA_RB_CNTL, rb_cntl);
138 /* Initialize the ring buffer's read and write pointers */
139 WREG32(DMA_RB_RPTR, 0);
140 WREG32(DMA_RB_WPTR, 0);
142 /* set the wb address whether it's enabled or not */
143 WREG32(DMA_RB_RPTR_ADDR_HI,
144 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
145 WREG32(DMA_RB_RPTR_ADDR_LO,
146 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
148 if (rdev->wb.enabled)
149 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
151 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
154 ib_cntl = DMA_IB_ENABLE;
156 ib_cntl |= DMA_IB_SWAP_ENABLE;
158 WREG32(DMA_IB_CNTL, ib_cntl);
160 dma_cntl = RREG32(DMA_CNTL);
161 dma_cntl &= ~CTXEMPTY_INT_ENABLE;
162 WREG32(DMA_CNTL, dma_cntl);
164 if (rdev->family >= CHIP_RV770)
168 WREG32(DMA_RB_WPTR, ring->wptr << 2);
170 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
174 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
180 if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX)
181 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
187 * r600_dma_fini - tear down the async dma engine
189 * @rdev: radeon_device pointer
191 * Stop the async dma engine and free the ring (r6xx-evergreen).
193 void r600_dma_fini(struct radeon_device *rdev)
196 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
200 * r600_dma_is_lockup - Check if the DMA engine is locked up
202 * @rdev: radeon_device pointer
203 * @ring: radeon_ring structure holding ring information
205 * Check if the async DMA engine is locked up.
206 * Returns true if the engine appears to be locked up, false if not.
208 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
210 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
212 if (!(reset_mask & RADEON_RESET_DMA)) {
213 radeon_ring_lockup_update(rdev, ring);
216 return radeon_ring_test_lockup(rdev, ring);
221 * r600_dma_ring_test - simple async dma engine test
223 * @rdev: radeon_device pointer
224 * @ring: radeon_ring structure holding ring information
226 * Test the DMA engine by writing using it to write an
227 * value to memory. (r6xx-SI).
228 * Returns 0 for success, error for failure.
230 int r600_dma_ring_test(struct radeon_device *rdev,
231 struct radeon_ring *ring)
235 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
239 DRM_ERROR("invalid vram scratch pointer\n");
246 r = radeon_ring_lock(rdev, ring, 4);
248 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
251 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
252 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
253 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
254 radeon_ring_write(ring, 0xDEADBEEF);
255 radeon_ring_unlock_commit(rdev, ring, false);
257 for (i = 0; i < rdev->usec_timeout; i++) {
259 if (tmp == 0xDEADBEEF)
264 if (i < rdev->usec_timeout) {
265 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
267 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
275 * r600_dma_fence_ring_emit - emit a fence on the DMA ring
277 * @rdev: radeon_device pointer
278 * @fence: radeon fence object
280 * Add a DMA fence packet to the ring to write
281 * the fence seq number and DMA trap packet to generate
282 * an interrupt if needed (r6xx-r7xx).
284 void r600_dma_fence_ring_emit(struct radeon_device *rdev,
285 struct radeon_fence *fence)
287 struct radeon_ring *ring = &rdev->ring[fence->ring];
288 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
290 /* write the fence */
291 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
292 radeon_ring_write(ring, addr & 0xfffffffc);
293 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
294 radeon_ring_write(ring, lower_32_bits(fence->seq));
295 /* generate an interrupt */
296 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
300 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
302 * @rdev: radeon_device pointer
303 * @ring: radeon_ring structure holding ring information
304 * @semaphore: radeon semaphore object
305 * @emit_wait: wait or signal semaphore
307 * Add a DMA semaphore packet to the ring wait on or signal
308 * other rings (r6xx-SI).
310 bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
311 struct radeon_ring *ring,
312 struct radeon_semaphore *semaphore,
315 u64 addr = semaphore->gpu_addr;
316 u32 s = emit_wait ? 0 : 1;
318 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
319 radeon_ring_write(ring, addr & 0xfffffffc);
320 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
326 * r600_dma_ib_test - test an IB on the DMA engine
328 * @rdev: radeon_device pointer
329 * @ring: radeon_ring structure holding ring information
331 * Test a simple IB in the DMA ring (r6xx-SI).
332 * Returns 0 on success, error on failure.
334 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
339 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
343 DRM_ERROR("invalid vram scratch pointer\n");
350 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
352 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
356 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
357 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
358 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
359 ib.ptr[3] = 0xDEADBEEF;
362 r = radeon_ib_schedule(rdev, &ib, NULL, false);
364 radeon_ib_free(rdev, &ib);
365 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
368 r = radeon_fence_wait(ib.fence, false);
370 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
373 for (i = 0; i < rdev->usec_timeout; i++) {
375 if (tmp == 0xDEADBEEF)
379 if (i < rdev->usec_timeout) {
380 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
382 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
385 radeon_ib_free(rdev, &ib);
390 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
392 * @rdev: radeon_device pointer
393 * @ib: IB object to schedule
395 * Schedule an IB in the DMA ring (r6xx-r7xx).
397 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
399 struct radeon_ring *ring = &rdev->ring[ib->ring];
401 if (rdev->wb.enabled) {
402 u32 next_rptr = ring->wptr + 4;
403 while ((next_rptr & 7) != 5)
406 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
407 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
408 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
409 radeon_ring_write(ring, next_rptr);
412 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
413 * Pad as necessary with NOPs.
415 while ((ring->wptr & 7) != 5)
416 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
417 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
418 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
419 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
424 * r600_copy_dma - copy pages using the DMA engine
426 * @rdev: radeon_device pointer
427 * @src_offset: src GPU address
428 * @dst_offset: dst GPU address
429 * @num_gpu_pages: number of GPU pages to xfer
430 * @fence: radeon fence object
432 * Copy GPU paging using the DMA engine (r6xx).
433 * Used by the radeon ttm implementation to move pages if
434 * registered as the asic copy callback.
436 int r600_copy_dma(struct radeon_device *rdev,
437 uint64_t src_offset, uint64_t dst_offset,
438 unsigned num_gpu_pages,
439 struct radeon_fence **fence)
441 struct radeon_semaphore *sem = NULL;
442 int ring_index = rdev->asic->copy.dma_ring_index;
443 struct radeon_ring *ring = &rdev->ring[ring_index];
444 u32 size_in_dw, cur_size_in_dw;
448 r = radeon_semaphore_create(rdev, &sem);
450 DRM_ERROR("radeon: moving bo (%d).\n", r);
454 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
455 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE);
456 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
458 DRM_ERROR("radeon: moving bo (%d).\n", r);
459 radeon_semaphore_free(rdev, &sem, NULL);
463 radeon_semaphore_sync_to(sem, *fence);
464 radeon_semaphore_sync_rings(rdev, sem, ring->idx);
466 for (i = 0; i < num_loops; i++) {
467 cur_size_in_dw = size_in_dw;
468 if (cur_size_in_dw > 0xFFFE)
469 cur_size_in_dw = 0xFFFE;
470 size_in_dw -= cur_size_in_dw;
471 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
472 radeon_ring_write(ring, dst_offset & 0xfffffffc);
473 radeon_ring_write(ring, src_offset & 0xfffffffc);
474 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
475 (upper_32_bits(src_offset) & 0xff)));
476 src_offset += cur_size_in_dw * 4;
477 dst_offset += cur_size_in_dw * 4;
480 r = radeon_fence_emit(rdev, fence, ring->idx);
482 radeon_ring_unlock_undo(rdev, ring);
483 radeon_semaphore_free(rdev, &sem, NULL);
487 radeon_ring_unlock_commit(rdev, ring, false);
488 radeon_semaphore_free(rdev, &sem, *fence);