2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
30 #include "radeon_reg.h"
35 int r420_mc_init(struct radeon_device *rdev)
39 /* Setup GPU memory space */
40 rdev->mc.vram_location = 0xFFFFFFFFUL;
41 rdev->mc.gtt_location = 0xFFFFFFFFUL;
42 if (rdev->flags & RADEON_IS_AGP) {
43 r = radeon_agp_init(rdev);
45 printk(KERN_WARNING "[drm] Disabling AGP\n");
46 rdev->flags &= ~RADEON_IS_AGP;
47 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
49 rdev->mc.gtt_location = rdev->mc.agp_base;
52 r = radeon_mc_setup(rdev);
59 void r420_pipes_init(struct radeon_device *rdev)
62 unsigned gb_pipe_select;
65 /* GA_ENHANCE workaround TCL deadlock issue */
66 WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
67 /* add idle wait as per freedesktop.org bug 24041 */
68 if (r100_gui_wait_for_idle(rdev)) {
69 printk(KERN_WARNING "Failed to wait GUI idle while "
70 "programming pipes. Bad things might happen.\n");
72 /* get max number of pipes */
73 gb_pipe_select = RREG32(0x402C);
74 num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
75 rdev->num_gb_pipes = num_pipes;
94 WREG32(0x42C8, (1 << num_pipes) - 1);
95 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
96 tmp |= (1 << 4) | (1 << 0);
98 if (r100_gui_wait_for_idle(rdev)) {
99 printk(KERN_WARNING "Failed to wait GUI idle while "
100 "programming pipes. Bad things might happen.\n");
103 tmp = RREG32(0x170C);
104 WREG32(0x170C, tmp | (1 << 31));
106 WREG32(R300_RB2D_DSTCACHE_MODE,
107 RREG32(R300_RB2D_DSTCACHE_MODE) |
108 R300_DC_AUTOFLUSH_ENABLE |
109 R300_DC_DC_DISABLE_IGNORE_PE);
111 if (r100_gui_wait_for_idle(rdev)) {
112 printk(KERN_WARNING "Failed to wait GUI idle while "
113 "programming pipes. Bad things might happen.\n");
116 if (rdev->family == CHIP_RV530) {
117 tmp = RREG32(RV530_GB_PIPE_SELECT2);
119 rdev->num_z_pipes = 2;
121 rdev->num_z_pipes = 1;
123 rdev->num_z_pipes = 1;
125 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
126 rdev->num_gb_pipes, rdev->num_z_pipes);
129 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
133 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
134 r = RREG32(R_0001FC_MC_IND_DATA);
138 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
140 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
141 S_0001F8_MC_IND_WR_EN(1));
142 WREG32(R_0001FC_MC_IND_DATA, v);
145 static void r420_debugfs(struct radeon_device *rdev)
147 if (r100_debugfs_rbbm_init(rdev)) {
148 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
150 if (r420_debugfs_pipes_info_init(rdev)) {
151 DRM_ERROR("Failed to register debugfs file for pipes !\n");
155 static void r420_clock_resume(struct radeon_device *rdev)
159 if (radeon_dynclks != -1 && radeon_dynclks)
160 radeon_atom_set_clock_gating(rdev, 1);
161 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
162 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
163 if (rdev->family == CHIP_R420)
164 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
165 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
168 static int r420_startup(struct radeon_device *rdev)
172 /* set common regs */
173 r100_set_common_regs(rdev);
175 r300_mc_program(rdev);
177 r420_clock_resume(rdev);
178 /* Initialize GART (initialize after TTM so we can allocate
179 * memory through TTM but finalize after TTM) */
180 if (rdev->flags & RADEON_IS_PCIE) {
181 r = rv370_pcie_gart_enable(rdev);
185 if (rdev->flags & RADEON_IS_PCI) {
186 r = r100_pci_gart_enable(rdev);
190 r420_pipes_init(rdev);
194 r = r100_cp_init(rdev, 1024 * 1024);
196 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
199 r = r100_wb_init(rdev);
201 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
203 r = r100_ib_init(rdev);
205 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
211 int r420_resume(struct radeon_device *rdev)
213 /* Make sur GART are not working */
214 if (rdev->flags & RADEON_IS_PCIE)
215 rv370_pcie_gart_disable(rdev);
216 if (rdev->flags & RADEON_IS_PCI)
217 r100_pci_gart_disable(rdev);
218 /* Resume clock before doing reset */
219 r420_clock_resume(rdev);
220 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
221 if (radeon_gpu_reset(rdev)) {
222 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
223 RREG32(R_000E40_RBBM_STATUS),
224 RREG32(R_0007C0_CP_STAT));
226 /* check if cards are posted or not */
227 if (rdev->is_atom_bios) {
228 atom_asic_init(rdev->mode_info.atom_context);
230 radeon_combios_asic_init(rdev->ddev);
232 /* Resume clock after posting */
233 r420_clock_resume(rdev);
234 /* Initialize surface registers */
235 radeon_surface_init(rdev);
236 return r420_startup(rdev);
239 int r420_suspend(struct radeon_device *rdev)
241 r100_cp_disable(rdev);
242 r100_wb_disable(rdev);
243 r100_irq_disable(rdev);
244 if (rdev->flags & RADEON_IS_PCIE)
245 rv370_pcie_gart_disable(rdev);
246 if (rdev->flags & RADEON_IS_PCI)
247 r100_pci_gart_disable(rdev);
251 void r420_fini(struct radeon_device *rdev)
256 radeon_gem_fini(rdev);
257 if (rdev->flags & RADEON_IS_PCIE)
258 rv370_pcie_gart_fini(rdev);
259 if (rdev->flags & RADEON_IS_PCI)
260 r100_pci_gart_fini(rdev);
261 radeon_agp_fini(rdev);
262 radeon_irq_kms_fini(rdev);
263 radeon_fence_driver_fini(rdev);
264 radeon_bo_fini(rdev);
265 if (rdev->is_atom_bios) {
266 radeon_atombios_fini(rdev);
268 radeon_combios_fini(rdev);
274 int r420_init(struct radeon_device *rdev)
278 /* Initialize scratch registers */
279 radeon_scratch_init(rdev);
280 /* Initialize surface registers */
281 radeon_surface_init(rdev);
282 /* TODO: disable VGA need to use VGA request */
284 if (!radeon_get_bios(rdev)) {
285 if (ASIC_IS_AVIVO(rdev))
288 if (rdev->is_atom_bios) {
289 r = radeon_atombios_init(rdev);
294 r = radeon_combios_init(rdev);
299 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
300 if (radeon_gpu_reset(rdev)) {
302 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
303 RREG32(R_000E40_RBBM_STATUS),
304 RREG32(R_0007C0_CP_STAT));
306 /* check if cards are posted or not */
307 if (radeon_boot_test_post_card(rdev) == false)
310 /* Initialize clocks */
311 radeon_get_clock_info(rdev->ddev);
312 /* Initialize power management */
313 radeon_pm_init(rdev);
314 /* Get vram informations */
315 r300_vram_info(rdev);
316 /* Initialize memory controller (also test AGP) */
317 r = r420_mc_init(rdev);
323 r = radeon_fence_driver_init(rdev);
327 r = radeon_irq_kms_init(rdev);
332 r = radeon_bo_init(rdev);
336 if (rdev->family == CHIP_R420)
337 r100_enable_bm(rdev);
339 if (rdev->flags & RADEON_IS_PCIE) {
340 r = rv370_pcie_gart_init(rdev);
344 if (rdev->flags & RADEON_IS_PCI) {
345 r = r100_pci_gart_init(rdev);
349 r300_set_reg_safe(rdev);
350 rdev->accel_working = true;
351 r = r420_startup(rdev);
353 /* Somethings want wront with the accel init stop accel */
354 dev_err(rdev->dev, "Disabling GPU acceleration\n");
359 if (rdev->flags & RADEON_IS_PCIE)
360 rv370_pcie_gart_fini(rdev);
361 if (rdev->flags & RADEON_IS_PCI)
362 r100_pci_gart_fini(rdev);
363 radeon_agp_fini(rdev);
364 radeon_irq_kms_fini(rdev);
365 rdev->accel_working = false;
373 #if defined(CONFIG_DEBUG_FS)
374 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
376 struct drm_info_node *node = (struct drm_info_node *) m->private;
377 struct drm_device *dev = node->minor->dev;
378 struct radeon_device *rdev = dev->dev_private;
381 tmp = RREG32(R400_GB_PIPE_SELECT);
382 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
383 tmp = RREG32(R300_GB_TILE_CONFIG);
384 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
385 tmp = RREG32(R300_DST_PIPE_CONFIG);
386 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
390 static struct drm_info_list r420_pipes_info_list[] = {
391 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
395 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
397 #if defined(CONFIG_DEBUG_FS)
398 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);