2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
30 #include "radeon_reg.h"
35 #include "r420_reg_safe.h"
37 static void r420_set_reg_safe(struct radeon_device *rdev)
39 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
40 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
43 int r420_mc_init(struct radeon_device *rdev)
47 /* Setup GPU memory space */
48 rdev->mc.vram_location = 0xFFFFFFFFUL;
49 rdev->mc.gtt_location = 0xFFFFFFFFUL;
50 if (rdev->flags & RADEON_IS_AGP) {
51 r = radeon_agp_init(rdev);
53 printk(KERN_WARNING "[drm] Disabling AGP\n");
54 rdev->flags &= ~RADEON_IS_AGP;
55 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
57 rdev->mc.gtt_location = rdev->mc.agp_base;
60 r = radeon_mc_setup(rdev);
67 void r420_pipes_init(struct radeon_device *rdev)
70 unsigned gb_pipe_select;
73 /* GA_ENHANCE workaround TCL deadlock issue */
74 WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
75 /* add idle wait as per freedesktop.org bug 24041 */
76 if (r100_gui_wait_for_idle(rdev)) {
77 printk(KERN_WARNING "Failed to wait GUI idle while "
78 "programming pipes. Bad things might happen.\n");
80 /* get max number of pipes */
81 gb_pipe_select = RREG32(0x402C);
82 num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
83 rdev->num_gb_pipes = num_pipes;
102 WREG32(0x42C8, (1 << num_pipes) - 1);
103 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
104 tmp |= (1 << 4) | (1 << 0);
106 if (r100_gui_wait_for_idle(rdev)) {
107 printk(KERN_WARNING "Failed to wait GUI idle while "
108 "programming pipes. Bad things might happen.\n");
111 tmp = RREG32(0x170C);
112 WREG32(0x170C, tmp | (1 << 31));
114 WREG32(R300_RB2D_DSTCACHE_MODE,
115 RREG32(R300_RB2D_DSTCACHE_MODE) |
116 R300_DC_AUTOFLUSH_ENABLE |
117 R300_DC_DC_DISABLE_IGNORE_PE);
119 if (r100_gui_wait_for_idle(rdev)) {
120 printk(KERN_WARNING "Failed to wait GUI idle while "
121 "programming pipes. Bad things might happen.\n");
124 if (rdev->family == CHIP_RV530) {
125 tmp = RREG32(RV530_GB_PIPE_SELECT2);
127 rdev->num_z_pipes = 2;
129 rdev->num_z_pipes = 1;
131 rdev->num_z_pipes = 1;
133 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
134 rdev->num_gb_pipes, rdev->num_z_pipes);
137 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
141 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
142 r = RREG32(R_0001FC_MC_IND_DATA);
146 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
148 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
149 S_0001F8_MC_IND_WR_EN(1));
150 WREG32(R_0001FC_MC_IND_DATA, v);
153 static void r420_debugfs(struct radeon_device *rdev)
155 if (r100_debugfs_rbbm_init(rdev)) {
156 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
158 if (r420_debugfs_pipes_info_init(rdev)) {
159 DRM_ERROR("Failed to register debugfs file for pipes !\n");
163 static void r420_clock_resume(struct radeon_device *rdev)
167 if (radeon_dynclks != -1 && radeon_dynclks)
168 radeon_atom_set_clock_gating(rdev, 1);
169 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
170 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
171 if (rdev->family == CHIP_R420)
172 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
173 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
176 static void r420_cp_errata_init(struct radeon_device *rdev)
178 /* RV410 and R420 can lock up if CP DMA to host memory happens
179 * while the 2D engine is busy.
181 * The proper workaround is to queue a RESYNC at the beginning
182 * of the CP init, apparently.
184 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
185 radeon_ring_lock(rdev, 8);
186 radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
187 radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
188 radeon_ring_write(rdev, 0xDEADBEEF);
189 radeon_ring_unlock_commit(rdev);
192 static void r420_cp_errata_fini(struct radeon_device *rdev)
194 /* Catch the RESYNC we dispatched all the way back,
195 * at the very beginning of the CP init.
197 radeon_ring_lock(rdev, 8);
198 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
199 radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
200 radeon_ring_unlock_commit(rdev);
201 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
204 static int r420_startup(struct radeon_device *rdev)
208 /* set common regs */
209 r100_set_common_regs(rdev);
211 r300_mc_program(rdev);
213 r420_clock_resume(rdev);
214 /* Initialize GART (initialize after TTM so we can allocate
215 * memory through TTM but finalize after TTM) */
216 if (rdev->flags & RADEON_IS_PCIE) {
217 r = rv370_pcie_gart_enable(rdev);
221 if (rdev->flags & RADEON_IS_PCI) {
222 r = r100_pci_gart_enable(rdev);
226 r420_pipes_init(rdev);
229 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
231 r = r100_cp_init(rdev, 1024 * 1024);
233 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
236 r420_cp_errata_init(rdev);
237 r = r100_wb_init(rdev);
239 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
241 r = r100_ib_init(rdev);
243 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
249 int r420_resume(struct radeon_device *rdev)
251 /* Make sur GART are not working */
252 if (rdev->flags & RADEON_IS_PCIE)
253 rv370_pcie_gart_disable(rdev);
254 if (rdev->flags & RADEON_IS_PCI)
255 r100_pci_gart_disable(rdev);
256 /* Resume clock before doing reset */
257 r420_clock_resume(rdev);
258 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
259 if (radeon_gpu_reset(rdev)) {
260 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
261 RREG32(R_000E40_RBBM_STATUS),
262 RREG32(R_0007C0_CP_STAT));
264 /* check if cards are posted or not */
265 if (rdev->is_atom_bios) {
266 atom_asic_init(rdev->mode_info.atom_context);
268 radeon_combios_asic_init(rdev->ddev);
270 /* Resume clock after posting */
271 r420_clock_resume(rdev);
272 /* Initialize surface registers */
273 radeon_surface_init(rdev);
274 return r420_startup(rdev);
277 int r420_suspend(struct radeon_device *rdev)
279 r420_cp_errata_fini(rdev);
280 r100_cp_disable(rdev);
281 r100_wb_disable(rdev);
282 r100_irq_disable(rdev);
283 if (rdev->flags & RADEON_IS_PCIE)
284 rv370_pcie_gart_disable(rdev);
285 if (rdev->flags & RADEON_IS_PCI)
286 r100_pci_gart_disable(rdev);
290 void r420_fini(struct radeon_device *rdev)
295 radeon_gem_fini(rdev);
296 if (rdev->flags & RADEON_IS_PCIE)
297 rv370_pcie_gart_fini(rdev);
298 if (rdev->flags & RADEON_IS_PCI)
299 r100_pci_gart_fini(rdev);
300 radeon_agp_fini(rdev);
301 radeon_irq_kms_fini(rdev);
302 radeon_fence_driver_fini(rdev);
303 radeon_bo_fini(rdev);
304 if (rdev->is_atom_bios) {
305 radeon_atombios_fini(rdev);
307 radeon_combios_fini(rdev);
313 int r420_init(struct radeon_device *rdev)
317 /* Initialize scratch registers */
318 radeon_scratch_init(rdev);
319 /* Initialize surface registers */
320 radeon_surface_init(rdev);
321 /* TODO: disable VGA need to use VGA request */
323 if (!radeon_get_bios(rdev)) {
324 if (ASIC_IS_AVIVO(rdev))
327 if (rdev->is_atom_bios) {
328 r = radeon_atombios_init(rdev);
333 r = radeon_combios_init(rdev);
338 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
339 if (radeon_gpu_reset(rdev)) {
341 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
342 RREG32(R_000E40_RBBM_STATUS),
343 RREG32(R_0007C0_CP_STAT));
345 /* check if cards are posted or not */
346 if (radeon_boot_test_post_card(rdev) == false)
349 /* Initialize clocks */
350 radeon_get_clock_info(rdev->ddev);
351 /* Initialize power management */
352 radeon_pm_init(rdev);
353 /* Get vram informations */
354 r300_vram_info(rdev);
355 /* Initialize memory controller (also test AGP) */
356 r = r420_mc_init(rdev);
362 r = radeon_fence_driver_init(rdev);
366 r = radeon_irq_kms_init(rdev);
371 r = radeon_bo_init(rdev);
375 if (rdev->family == CHIP_R420)
376 r100_enable_bm(rdev);
378 if (rdev->flags & RADEON_IS_PCIE) {
379 r = rv370_pcie_gart_init(rdev);
383 if (rdev->flags & RADEON_IS_PCI) {
384 r = r100_pci_gart_init(rdev);
388 r420_set_reg_safe(rdev);
389 rdev->accel_working = true;
390 r = r420_startup(rdev);
392 /* Somethings want wront with the accel init stop accel */
393 dev_err(rdev->dev, "Disabling GPU acceleration\n");
398 if (rdev->flags & RADEON_IS_PCIE)
399 rv370_pcie_gart_fini(rdev);
400 if (rdev->flags & RADEON_IS_PCI)
401 r100_pci_gart_fini(rdev);
402 radeon_agp_fini(rdev);
403 radeon_irq_kms_fini(rdev);
404 rdev->accel_working = false;
412 #if defined(CONFIG_DEBUG_FS)
413 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
415 struct drm_info_node *node = (struct drm_info_node *) m->private;
416 struct drm_device *dev = node->minor->dev;
417 struct radeon_device *rdev = dev->dev_private;
420 tmp = RREG32(R400_GB_PIPE_SELECT);
421 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
422 tmp = RREG32(R300_GB_TILE_CONFIG);
423 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
424 tmp = RREG32(R300_DST_PIPE_CONFIG);
425 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
429 static struct drm_info_list r420_pipes_info_list[] = {
430 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
434 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
436 #if defined(CONFIG_DEBUG_FS)
437 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);