2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
31 #include "radeon_reg.h"
33 #include "radeon_drm.h"
34 #include "r100_track.h"
37 #include "r300_reg_safe.h"
39 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
42 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
43 * using MMIO to flush host path read cache, this lead to HARDLOCKUP.
44 * However, scheduling such write to the ring seems harmless, i suspect
45 * the CP read collide with the flush somehow, or maybe the MC, hard to
46 * tell. (Jerome Glisse)
50 * rv370,rv380 PCIE GART
52 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
54 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
59 /* Workaround HW bug do flush 2 times */
60 for (i = 0; i < 2; i++) {
61 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
62 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
63 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
64 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
69 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
71 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
73 if (i < 0 || i > rdev->gart.num_gpu_pages) {
76 addr = (lower_32_bits(addr) >> 8) |
77 ((upper_32_bits(addr) & 0xff) << 24) |
79 /* on x86 we want this to be CPU endian, on powerpc
80 * on powerpc without HW swappers, it'll get swapped on way
81 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
82 writel(addr, ((void __iomem *)ptr) + (i * 4));
86 int rv370_pcie_gart_init(struct radeon_device *rdev)
90 if (rdev->gart.table.vram.robj) {
91 WARN(1, "RV370 PCIE GART already initialized.\n");
94 /* Initialize common gart structure */
95 r = radeon_gart_init(rdev);
98 r = rv370_debugfs_pcie_gart_info_init(rdev);
100 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
101 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
102 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
103 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
104 return radeon_gart_table_vram_alloc(rdev);
107 int rv370_pcie_gart_enable(struct radeon_device *rdev)
113 if (rdev->gart.table.vram.robj == NULL) {
114 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
117 r = radeon_gart_table_vram_pin(rdev);
120 /* discard memory request outside of configured range */
121 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
122 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
123 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location);
124 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - RADEON_GPU_PAGE_SIZE;
125 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
126 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
127 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
128 table_addr = rdev->gart.table_addr;
129 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
130 /* FIXME: setup default page */
131 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location);
132 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
134 WREG32_PCIE(0x18, 0);
135 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
136 tmp |= RADEON_PCIE_TX_GART_EN;
137 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
138 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
139 rv370_pcie_gart_tlb_flush(rdev);
140 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
141 (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
142 rdev->gart.ready = true;
146 void rv370_pcie_gart_disable(struct radeon_device *rdev)
151 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
152 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
153 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
154 if (rdev->gart.table.vram.robj) {
155 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
156 if (likely(r == 0)) {
157 radeon_bo_kunmap(rdev->gart.table.vram.robj);
158 radeon_bo_unpin(rdev->gart.table.vram.robj);
159 radeon_bo_unreserve(rdev->gart.table.vram.robj);
164 void rv370_pcie_gart_fini(struct radeon_device *rdev)
166 rv370_pcie_gart_disable(rdev);
167 radeon_gart_table_vram_free(rdev);
168 radeon_gart_fini(rdev);
171 void r300_fence_ring_emit(struct radeon_device *rdev,
172 struct radeon_fence *fence)
174 /* Who ever call radeon_fence_emit should call ring_lock and ask
175 * for enough space (today caller are ib schedule and buffer move) */
176 /* Write SC register so SC & US assert idle */
177 radeon_ring_write(rdev, PACKET0(0x43E0, 0));
178 radeon_ring_write(rdev, 0);
179 radeon_ring_write(rdev, PACKET0(0x43E4, 0));
180 radeon_ring_write(rdev, 0);
182 radeon_ring_write(rdev, PACKET0(0x4E4C, 0));
183 radeon_ring_write(rdev, (2 << 0));
184 radeon_ring_write(rdev, PACKET0(0x4F18, 0));
185 radeon_ring_write(rdev, (1 << 0));
186 /* Wait until IDLE & CLEAN */
187 radeon_ring_write(rdev, PACKET0(0x1720, 0));
188 radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9));
189 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
190 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
191 RADEON_HDP_READ_BUFFER_INVALIDATE);
192 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
193 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
194 /* Emit fence sequence & fire IRQ */
195 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
196 radeon_ring_write(rdev, fence->seq);
197 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
198 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
201 int r300_copy_dma(struct radeon_device *rdev,
205 struct radeon_fence *fence)
212 /* radeon pitch is /64 */
213 size = num_pages << PAGE_SHIFT;
214 num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
215 r = radeon_ring_lock(rdev, num_loops * 4 + 64);
217 DRM_ERROR("radeon: moving bo (%d).\n", r);
220 /* Must wait for 2D idle & clean before DMA or hangs might happen */
221 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 ));
222 radeon_ring_write(rdev, (1 << 16));
223 for (i = 0; i < num_loops; i++) {
225 if (cur_size > 0x1FFFFF) {
229 radeon_ring_write(rdev, PACKET0(0x720, 2));
230 radeon_ring_write(rdev, src_offset);
231 radeon_ring_write(rdev, dst_offset);
232 radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30));
233 src_offset += cur_size;
234 dst_offset += cur_size;
236 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
237 radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
239 r = radeon_fence_emit(rdev, fence);
241 radeon_ring_unlock_commit(rdev);
245 void r300_ring_start(struct radeon_device *rdev)
247 unsigned gb_tile_config;
250 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
251 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
252 switch(rdev->num_gb_pipes) {
254 gb_tile_config |= R300_PIPE_COUNT_R300;
257 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
260 gb_tile_config |= R300_PIPE_COUNT_R420;
264 gb_tile_config |= R300_PIPE_COUNT_RV350;
268 r = radeon_ring_lock(rdev, 64);
272 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
273 radeon_ring_write(rdev,
274 RADEON_ISYNC_ANY2D_IDLE3D |
275 RADEON_ISYNC_ANY3D_IDLE2D |
276 RADEON_ISYNC_WAIT_IDLEGUI |
277 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
278 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
279 radeon_ring_write(rdev, gb_tile_config);
280 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
281 radeon_ring_write(rdev,
282 RADEON_WAIT_2D_IDLECLEAN |
283 RADEON_WAIT_3D_IDLECLEAN);
284 radeon_ring_write(rdev, PACKET0(0x170C, 0));
285 radeon_ring_write(rdev, 1 << 31);
286 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
287 radeon_ring_write(rdev, 0);
288 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
289 radeon_ring_write(rdev, 0);
290 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
291 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
292 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
293 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
294 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
295 radeon_ring_write(rdev,
296 RADEON_WAIT_2D_IDLECLEAN |
297 RADEON_WAIT_3D_IDLECLEAN);
298 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
299 radeon_ring_write(rdev, 0);
300 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
301 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
302 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
303 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
304 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
305 radeon_ring_write(rdev,
306 ((6 << R300_MS_X0_SHIFT) |
307 (6 << R300_MS_Y0_SHIFT) |
308 (6 << R300_MS_X1_SHIFT) |
309 (6 << R300_MS_Y1_SHIFT) |
310 (6 << R300_MS_X2_SHIFT) |
311 (6 << R300_MS_Y2_SHIFT) |
312 (6 << R300_MSBD0_Y_SHIFT) |
313 (6 << R300_MSBD0_X_SHIFT)));
314 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
315 radeon_ring_write(rdev,
316 ((6 << R300_MS_X3_SHIFT) |
317 (6 << R300_MS_Y3_SHIFT) |
318 (6 << R300_MS_X4_SHIFT) |
319 (6 << R300_MS_Y4_SHIFT) |
320 (6 << R300_MS_X5_SHIFT) |
321 (6 << R300_MS_Y5_SHIFT) |
322 (6 << R300_MSBD1_SHIFT)));
323 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
324 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
325 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
326 radeon_ring_write(rdev,
327 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
328 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
329 radeon_ring_write(rdev,
330 R300_GEOMETRY_ROUND_NEAREST |
331 R300_COLOR_ROUND_NEAREST);
332 radeon_ring_unlock_commit(rdev);
335 void r300_errata(struct radeon_device *rdev)
337 rdev->pll_errata = 0;
339 if (rdev->family == CHIP_R300 &&
340 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
341 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
345 int r300_mc_wait_for_idle(struct radeon_device *rdev)
350 for (i = 0; i < rdev->usec_timeout; i++) {
352 tmp = RREG32(0x0150);
353 if (tmp & (1 << 4)) {
361 void r300_gpu_init(struct radeon_device *rdev)
363 uint32_t gb_tile_config, tmp;
365 r100_hdp_reset(rdev);
366 /* FIXME: rv380 one pipes ? */
367 if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
369 rdev->num_gb_pipes = 2;
371 /* rv350,rv370,rv380 */
372 rdev->num_gb_pipes = 1;
374 rdev->num_z_pipes = 1;
375 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
376 switch (rdev->num_gb_pipes) {
378 gb_tile_config |= R300_PIPE_COUNT_R300;
381 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
384 gb_tile_config |= R300_PIPE_COUNT_R420;
388 gb_tile_config |= R300_PIPE_COUNT_RV350;
391 WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
393 if (r100_gui_wait_for_idle(rdev)) {
394 printk(KERN_WARNING "Failed to wait GUI idle while "
395 "programming pipes. Bad things might happen.\n");
398 tmp = RREG32(0x170C);
399 WREG32(0x170C, tmp | (1 << 31));
401 WREG32(R300_RB2D_DSTCACHE_MODE,
402 R300_DC_AUTOFLUSH_ENABLE |
403 R300_DC_DC_DISABLE_IGNORE_PE);
405 if (r100_gui_wait_for_idle(rdev)) {
406 printk(KERN_WARNING "Failed to wait GUI idle while "
407 "programming pipes. Bad things might happen.\n");
409 if (r300_mc_wait_for_idle(rdev)) {
410 printk(KERN_WARNING "Failed to wait MC idle while "
411 "programming pipes. Bad things might happen.\n");
413 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
414 rdev->num_gb_pipes, rdev->num_z_pipes);
417 int r300_ga_reset(struct radeon_device *rdev)
423 reinit_cp = rdev->cp.ready;
424 rdev->cp.ready = false;
425 for (i = 0; i < rdev->usec_timeout; i++) {
426 WREG32(RADEON_CP_CSQ_MODE, 0);
427 WREG32(RADEON_CP_CSQ_CNTL, 0);
428 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
429 (void)RREG32(RADEON_RBBM_SOFT_RESET);
431 WREG32(RADEON_RBBM_SOFT_RESET, 0);
432 /* Wait to prevent race in RBBM_STATUS */
434 tmp = RREG32(RADEON_RBBM_STATUS);
435 if (tmp & ((1 << 20) | (1 << 26))) {
436 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
437 /* GA still busy soft reset it */
438 WREG32(0x429C, 0x200);
439 WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
444 /* Wait to prevent race in RBBM_STATUS */
446 tmp = RREG32(RADEON_RBBM_STATUS);
447 if (!(tmp & ((1 << 20) | (1 << 26)))) {
451 for (i = 0; i < rdev->usec_timeout; i++) {
452 tmp = RREG32(RADEON_RBBM_STATUS);
453 if (!(tmp & ((1 << 20) | (1 << 26)))) {
454 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
457 return r100_cp_init(rdev, rdev->cp.ring_size);
463 tmp = RREG32(RADEON_RBBM_STATUS);
464 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
468 int r300_gpu_reset(struct radeon_device *rdev)
472 /* reset order likely matter */
473 status = RREG32(RADEON_RBBM_STATUS);
475 r100_hdp_reset(rdev);
477 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
478 r100_rb2d_reset(rdev);
481 if (status & ((1 << 20) | (1 << 26))) {
485 status = RREG32(RADEON_RBBM_STATUS);
486 if (status & (1 << 16)) {
489 /* Check if GPU is idle */
490 status = RREG32(RADEON_RBBM_STATUS);
491 if (status & (1 << 31)) {
492 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
495 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
501 * r300,r350,rv350,rv380 VRAM info
503 void r300_vram_info(struct radeon_device *rdev)
507 /* DDR for all card after R300 & IGP */
508 rdev->mc.vram_is_ddr = true;
510 tmp = RREG32(RADEON_MEM_CNTL);
511 tmp &= R300_MEM_NUM_CHANNELS_MASK;
513 case 0: rdev->mc.vram_width = 64; break;
514 case 1: rdev->mc.vram_width = 128; break;
515 case 2: rdev->mc.vram_width = 256; break;
516 default: rdev->mc.vram_width = 128; break;
519 r100_vram_init_sizes(rdev);
522 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
524 uint32_t link_width_cntl, mask;
526 if (rdev->flags & RADEON_IS_IGP)
529 if (!(rdev->flags & RADEON_IS_PCIE))
532 /* FIXME wait for idle */
536 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
539 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
542 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
545 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
548 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
551 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
555 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
559 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
561 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
562 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
565 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
566 RADEON_PCIE_LC_RECONFIG_NOW |
567 RADEON_PCIE_LC_RECONFIG_LATER |
568 RADEON_PCIE_LC_SHORT_RECONFIG_EN);
569 link_width_cntl |= mask;
570 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
571 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
572 RADEON_PCIE_LC_RECONFIG_NOW));
574 /* wait for lane set to complete */
575 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
576 while (link_width_cntl == 0xffffffff)
577 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
581 #if defined(CONFIG_DEBUG_FS)
582 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
584 struct drm_info_node *node = (struct drm_info_node *) m->private;
585 struct drm_device *dev = node->minor->dev;
586 struct radeon_device *rdev = dev->dev_private;
589 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
590 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
591 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
592 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
593 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
594 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
595 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
596 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
598 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
599 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
600 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
601 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
602 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
606 static struct drm_info_list rv370_pcie_gart_info_list[] = {
607 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
611 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
613 #if defined(CONFIG_DEBUG_FS)
614 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
620 static int r300_packet0_check(struct radeon_cs_parser *p,
621 struct radeon_cs_packet *pkt,
622 unsigned idx, unsigned reg)
624 struct radeon_cs_reloc *reloc;
625 struct r100_cs_track *track;
626 volatile uint32_t *ib;
627 uint32_t tmp, tile_flags = 0;
633 track = (struct r100_cs_track *)p->track;
634 idx_value = radeon_get_ib_value(p, idx);
637 case AVIVO_D1MODE_VLINE_START_END:
638 case RADEON_CRTC_GUI_TRIG_VLINE:
639 r = r100_cs_packet_parse_vline(p);
641 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
643 r100_cs_dump_packet(p, pkt);
647 case RADEON_DST_PITCH_OFFSET:
648 case RADEON_SRC_PITCH_OFFSET:
649 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
653 case R300_RB3D_COLOROFFSET0:
654 case R300_RB3D_COLOROFFSET1:
655 case R300_RB3D_COLOROFFSET2:
656 case R300_RB3D_COLOROFFSET3:
657 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
658 r = r100_cs_packet_next_reloc(p, &reloc);
660 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
662 r100_cs_dump_packet(p, pkt);
665 track->cb[i].robj = reloc->robj;
666 track->cb[i].offset = idx_value;
667 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
669 case R300_ZB_DEPTHOFFSET:
670 r = r100_cs_packet_next_reloc(p, &reloc);
672 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
674 r100_cs_dump_packet(p, pkt);
677 track->zb.robj = reloc->robj;
678 track->zb.offset = idx_value;
679 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
681 case R300_TX_OFFSET_0:
682 case R300_TX_OFFSET_0+4:
683 case R300_TX_OFFSET_0+8:
684 case R300_TX_OFFSET_0+12:
685 case R300_TX_OFFSET_0+16:
686 case R300_TX_OFFSET_0+20:
687 case R300_TX_OFFSET_0+24:
688 case R300_TX_OFFSET_0+28:
689 case R300_TX_OFFSET_0+32:
690 case R300_TX_OFFSET_0+36:
691 case R300_TX_OFFSET_0+40:
692 case R300_TX_OFFSET_0+44:
693 case R300_TX_OFFSET_0+48:
694 case R300_TX_OFFSET_0+52:
695 case R300_TX_OFFSET_0+56:
696 case R300_TX_OFFSET_0+60:
697 i = (reg - R300_TX_OFFSET_0) >> 2;
698 r = r100_cs_packet_next_reloc(p, &reloc);
700 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
702 r100_cs_dump_packet(p, pkt);
706 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
707 tile_flags |= R300_TXO_MACRO_TILE;
708 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
709 tile_flags |= R300_TXO_MICRO_TILE;
711 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
714 track->textures[i].robj = reloc->robj;
716 /* Tracked registers */
719 track->vap_vf_cntl = idx_value;
723 track->vtx_size = idx_value & 0x7F;
726 /* VAP_VF_MAX_VTX_INDX */
727 track->max_indx = idx_value & 0x00FFFFFFUL;
731 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
732 if (p->rdev->family < CHIP_RV515) {
738 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
744 /* RB3D_COLORPITCH0 */
745 /* RB3D_COLORPITCH1 */
746 /* RB3D_COLORPITCH2 */
747 /* RB3D_COLORPITCH3 */
748 r = r100_cs_packet_next_reloc(p, &reloc);
750 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
752 r100_cs_dump_packet(p, pkt);
756 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
757 tile_flags |= R300_COLOR_TILE_ENABLE;
758 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
759 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
761 tmp = idx_value & ~(0x7 << 16);
765 i = (reg - 0x4E38) >> 2;
766 track->cb[i].pitch = idx_value & 0x3FFE;
767 switch (((idx_value >> 21) & 0xF)) {
771 track->cb[i].cpp = 1;
777 track->cb[i].cpp = 2;
780 track->cb[i].cpp = 4;
783 track->cb[i].cpp = 8;
786 track->cb[i].cpp = 16;
789 DRM_ERROR("Invalid color buffer format (%d) !\n",
790 ((idx_value >> 21) & 0xF));
797 track->z_enabled = true;
799 track->z_enabled = false;
804 switch ((idx_value & 0xF)) {
813 DRM_ERROR("Invalid z buffer format (%d) !\n",
820 r = r100_cs_packet_next_reloc(p, &reloc);
822 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
824 r100_cs_dump_packet(p, pkt);
828 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
829 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
830 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
831 tile_flags |= R300_DEPTHMICROTILE_TILED;;
833 tmp = idx_value & ~(0x7 << 16);
837 track->zb.pitch = idx_value & 0x3FFC;
840 for (i = 0; i < 16; i++) {
843 enabled = !!(idx_value & (1 << i));
844 track->textures[i].enabled = enabled;
863 /* TX_FORMAT1_[0-15] */
864 i = (reg - 0x44C0) >> 2;
865 tmp = (idx_value >> 25) & 0x3;
866 track->textures[i].tex_coord_type = tmp;
867 switch ((idx_value & 0x1F)) {
868 case R300_TX_FORMAT_X8:
869 case R300_TX_FORMAT_Y4X4:
870 case R300_TX_FORMAT_Z3Y3X2:
871 track->textures[i].cpp = 1;
873 case R300_TX_FORMAT_X16:
874 case R300_TX_FORMAT_Y8X8:
875 case R300_TX_FORMAT_Z5Y6X5:
876 case R300_TX_FORMAT_Z6Y5X5:
877 case R300_TX_FORMAT_W4Z4Y4X4:
878 case R300_TX_FORMAT_W1Z5Y5X5:
879 case R300_TX_FORMAT_D3DMFT_CxV8U8:
880 case R300_TX_FORMAT_B8G8_B8G8:
881 case R300_TX_FORMAT_G8R8_G8B8:
882 track->textures[i].cpp = 2;
884 case R300_TX_FORMAT_Y16X16:
885 case R300_TX_FORMAT_Z11Y11X10:
886 case R300_TX_FORMAT_Z10Y11X11:
887 case R300_TX_FORMAT_W8Z8Y8X8:
888 case R300_TX_FORMAT_W2Z10Y10X10:
890 case R300_TX_FORMAT_FL_I32:
892 track->textures[i].cpp = 4;
894 case R300_TX_FORMAT_W16Z16Y16X16:
895 case R300_TX_FORMAT_FL_R16G16B16A16:
896 case R300_TX_FORMAT_FL_I32A32:
897 track->textures[i].cpp = 8;
899 case R300_TX_FORMAT_FL_R32G32B32A32:
900 track->textures[i].cpp = 16;
902 case R300_TX_FORMAT_DXT1:
903 track->textures[i].cpp = 1;
904 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
906 case R300_TX_FORMAT_ATI2N:
907 if (p->rdev->family < CHIP_R420) {
908 DRM_ERROR("Invalid texture format %u\n",
912 /* The same rules apply as for DXT3/5. */
914 case R300_TX_FORMAT_DXT3:
915 case R300_TX_FORMAT_DXT5:
916 track->textures[i].cpp = 1;
917 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
920 DRM_ERROR("Invalid texture format %u\n",
942 /* TX_FILTER0_[0-15] */
943 i = (reg - 0x4400) >> 2;
944 tmp = idx_value & 0x7;
945 if (tmp == 2 || tmp == 4 || tmp == 6) {
946 track->textures[i].roundup_w = false;
948 tmp = (idx_value >> 3) & 0x7;
949 if (tmp == 2 || tmp == 4 || tmp == 6) {
950 track->textures[i].roundup_h = false;
969 /* TX_FORMAT2_[0-15] */
970 i = (reg - 0x4500) >> 2;
971 tmp = idx_value & 0x3FFF;
972 track->textures[i].pitch = tmp + 1;
973 if (p->rdev->family >= CHIP_RV515) {
974 tmp = ((idx_value >> 15) & 1) << 11;
975 track->textures[i].width_11 = tmp;
976 tmp = ((idx_value >> 16) & 1) << 11;
977 track->textures[i].height_11 = tmp;
980 if (idx_value & (1 << 14)) {
981 /* The same rules apply as for DXT1. */
982 track->textures[i].compress_format =
983 R100_TRACK_COMP_DXT1;
985 } else if (idx_value & (1 << 14)) {
986 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1006 /* TX_FORMAT0_[0-15] */
1007 i = (reg - 0x4480) >> 2;
1008 tmp = idx_value & 0x7FF;
1009 track->textures[i].width = tmp + 1;
1010 tmp = (idx_value >> 11) & 0x7FF;
1011 track->textures[i].height = tmp + 1;
1012 tmp = (idx_value >> 26) & 0xF;
1013 track->textures[i].num_levels = tmp;
1014 tmp = idx_value & (1 << 31);
1015 track->textures[i].use_pitch = !!tmp;
1016 tmp = (idx_value >> 22) & 0xF;
1017 track->textures[i].txdepth = tmp;
1019 case R300_ZB_ZPASS_ADDR:
1020 r = r100_cs_packet_next_reloc(p, &reloc);
1022 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1024 r100_cs_dump_packet(p, pkt);
1027 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1030 /* RB3D_COLOR_CHANNEL_MASK */
1031 track->color_channel_mask = idx_value;
1035 track->fastfill = !!(idx_value & (1 << 2));
1038 /* RB3D_BLENDCNTL */
1039 track->blend_read_enable = !!(idx_value & (1 << 2));
1042 /* valid register only on RV530 */
1043 if (p->rdev->family == CHIP_RV530)
1045 /* fallthrough do not move */
1047 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1054 static int r300_packet3_check(struct radeon_cs_parser *p,
1055 struct radeon_cs_packet *pkt)
1057 struct radeon_cs_reloc *reloc;
1058 struct r100_cs_track *track;
1059 volatile uint32_t *ib;
1065 track = (struct r100_cs_track *)p->track;
1066 switch(pkt->opcode) {
1067 case PACKET3_3D_LOAD_VBPNTR:
1068 r = r100_packet3_load_vbpntr(p, pkt, idx);
1072 case PACKET3_INDX_BUFFER:
1073 r = r100_cs_packet_next_reloc(p, &reloc);
1075 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1076 r100_cs_dump_packet(p, pkt);
1079 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1080 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1086 case PACKET3_3D_DRAW_IMMD:
1087 /* Number of dwords is vtx_size * (num_vertices - 1)
1088 * PRIM_WALK must be equal to 3 vertex data in embedded
1090 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1091 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1094 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1095 track->immd_dwords = pkt->count - 1;
1096 r = r100_cs_track_check(p->rdev, track);
1101 case PACKET3_3D_DRAW_IMMD_2:
1102 /* Number of dwords is vtx_size * (num_vertices - 1)
1103 * PRIM_WALK must be equal to 3 vertex data in embedded
1105 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1106 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1109 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1110 track->immd_dwords = pkt->count;
1111 r = r100_cs_track_check(p->rdev, track);
1116 case PACKET3_3D_DRAW_VBUF:
1117 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1118 r = r100_cs_track_check(p->rdev, track);
1123 case PACKET3_3D_DRAW_VBUF_2:
1124 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1125 r = r100_cs_track_check(p->rdev, track);
1130 case PACKET3_3D_DRAW_INDX:
1131 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1132 r = r100_cs_track_check(p->rdev, track);
1137 case PACKET3_3D_DRAW_INDX_2:
1138 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1139 r = r100_cs_track_check(p->rdev, track);
1147 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1153 int r300_cs_parse(struct radeon_cs_parser *p)
1155 struct radeon_cs_packet pkt;
1156 struct r100_cs_track *track;
1159 track = kzalloc(sizeof(*track), GFP_KERNEL);
1160 r100_cs_track_clear(p->rdev, track);
1163 r = r100_cs_packet_parse(p, &pkt, p->idx);
1167 p->idx += pkt.count + 2;
1170 r = r100_cs_parse_packet0(p, &pkt,
1171 p->rdev->config.r300.reg_safe_bm,
1172 p->rdev->config.r300.reg_safe_bm_size,
1173 &r300_packet0_check);
1178 r = r300_packet3_check(p, &pkt);
1181 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1187 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1191 void r300_set_reg_safe(struct radeon_device *rdev)
1193 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1194 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1197 void r300_mc_program(struct radeon_device *rdev)
1199 struct r100_mc_save save;
1202 r = r100_debugfs_mc_info_init(rdev);
1204 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1207 /* Stops all mc clients */
1208 r100_mc_stop(rdev, &save);
1209 if (rdev->flags & RADEON_IS_AGP) {
1210 WREG32(R_00014C_MC_AGP_LOCATION,
1211 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1212 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1213 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1214 WREG32(R_00015C_AGP_BASE_2,
1215 upper_32_bits(rdev->mc.agp_base) & 0xff);
1217 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1218 WREG32(R_000170_AGP_BASE, 0);
1219 WREG32(R_00015C_AGP_BASE_2, 0);
1221 /* Wait for mc idle */
1222 if (r300_mc_wait_for_idle(rdev))
1223 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1224 /* Program MC, should be a 32bits limited address space */
1225 WREG32(R_000148_MC_FB_LOCATION,
1226 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1227 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1228 r100_mc_resume(rdev, &save);
1231 void r300_clock_startup(struct radeon_device *rdev)
1235 if (radeon_dynclks != -1 && radeon_dynclks)
1236 radeon_legacy_set_clock_gating(rdev, 1);
1237 /* We need to force on some of the block */
1238 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1239 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1240 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1241 tmp |= S_00000D_FORCE_VAP(1);
1242 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1245 static int r300_startup(struct radeon_device *rdev)
1249 /* set common regs */
1250 r100_set_common_regs(rdev);
1252 r300_mc_program(rdev);
1254 r300_clock_startup(rdev);
1255 /* Initialize GPU configuration (# pipes, ...) */
1256 r300_gpu_init(rdev);
1257 /* Initialize GART (initialize after TTM so we can allocate
1258 * memory through TTM but finalize after TTM) */
1259 if (rdev->flags & RADEON_IS_PCIE) {
1260 r = rv370_pcie_gart_enable(rdev);
1265 if (rdev->family == CHIP_R300 ||
1266 rdev->family == CHIP_R350 ||
1267 rdev->family == CHIP_RV350)
1268 r100_enable_bm(rdev);
1270 if (rdev->flags & RADEON_IS_PCI) {
1271 r = r100_pci_gart_enable(rdev);
1277 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1278 /* 1M ring buffer */
1279 r = r100_cp_init(rdev, 1024 * 1024);
1281 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1284 r = r100_wb_init(rdev);
1286 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
1287 r = r100_ib_init(rdev);
1289 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1295 int r300_resume(struct radeon_device *rdev)
1297 /* Make sur GART are not working */
1298 if (rdev->flags & RADEON_IS_PCIE)
1299 rv370_pcie_gart_disable(rdev);
1300 if (rdev->flags & RADEON_IS_PCI)
1301 r100_pci_gart_disable(rdev);
1302 /* Resume clock before doing reset */
1303 r300_clock_startup(rdev);
1304 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1305 if (radeon_gpu_reset(rdev)) {
1306 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1307 RREG32(R_000E40_RBBM_STATUS),
1308 RREG32(R_0007C0_CP_STAT));
1311 radeon_combios_asic_init(rdev->ddev);
1312 /* Resume clock after posting */
1313 r300_clock_startup(rdev);
1314 /* Initialize surface registers */
1315 radeon_surface_init(rdev);
1316 return r300_startup(rdev);
1319 int r300_suspend(struct radeon_device *rdev)
1321 r100_cp_disable(rdev);
1322 r100_wb_disable(rdev);
1323 r100_irq_disable(rdev);
1324 if (rdev->flags & RADEON_IS_PCIE)
1325 rv370_pcie_gart_disable(rdev);
1326 if (rdev->flags & RADEON_IS_PCI)
1327 r100_pci_gart_disable(rdev);
1331 void r300_fini(struct radeon_device *rdev)
1336 radeon_gem_fini(rdev);
1337 if (rdev->flags & RADEON_IS_PCIE)
1338 rv370_pcie_gart_fini(rdev);
1339 if (rdev->flags & RADEON_IS_PCI)
1340 r100_pci_gart_fini(rdev);
1341 radeon_agp_fini(rdev);
1342 radeon_irq_kms_fini(rdev);
1343 radeon_fence_driver_fini(rdev);
1344 radeon_bo_fini(rdev);
1345 radeon_atombios_fini(rdev);
1350 int r300_init(struct radeon_device *rdev)
1355 r100_vga_render_disable(rdev);
1356 /* Initialize scratch registers */
1357 radeon_scratch_init(rdev);
1358 /* Initialize surface registers */
1359 radeon_surface_init(rdev);
1360 /* TODO: disable VGA need to use VGA request */
1362 if (!radeon_get_bios(rdev)) {
1363 if (ASIC_IS_AVIVO(rdev))
1366 if (rdev->is_atom_bios) {
1367 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1370 r = radeon_combios_init(rdev);
1374 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1375 if (radeon_gpu_reset(rdev)) {
1377 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1378 RREG32(R_000E40_RBBM_STATUS),
1379 RREG32(R_0007C0_CP_STAT));
1381 /* check if cards are posted or not */
1382 if (radeon_boot_test_post_card(rdev) == false)
1384 /* Set asic errata */
1386 /* Initialize clocks */
1387 radeon_get_clock_info(rdev->ddev);
1388 /* Initialize power management */
1389 radeon_pm_init(rdev);
1390 /* Get vram informations */
1391 r300_vram_info(rdev);
1392 /* Initialize memory controller (also test AGP) */
1393 r = r420_mc_init(rdev);
1397 r = radeon_fence_driver_init(rdev);
1400 r = radeon_irq_kms_init(rdev);
1403 /* Memory manager */
1404 r = radeon_bo_init(rdev);
1407 if (rdev->flags & RADEON_IS_PCIE) {
1408 r = rv370_pcie_gart_init(rdev);
1412 if (rdev->flags & RADEON_IS_PCI) {
1413 r = r100_pci_gart_init(rdev);
1417 r300_set_reg_safe(rdev);
1418 rdev->accel_working = true;
1419 r = r300_startup(rdev);
1421 /* Somethings want wront with the accel init stop accel */
1422 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1426 radeon_irq_kms_fini(rdev);
1427 if (rdev->flags & RADEON_IS_PCIE)
1428 rv370_pcie_gart_fini(rdev);
1429 if (rdev->flags & RADEON_IS_PCI)
1430 r100_pci_gart_fini(rdev);
1431 radeon_agp_fini(rdev);
1432 rdev->accel_working = false;