2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
31 #include "radeon_drm.h"
32 #include "radeon_reg.h"
39 #include <linux/firmware.h>
40 #include <linux/platform_device.h>
42 #include "r100_reg_safe.h"
43 #include "rn50_reg_safe.h"
46 #define FIRMWARE_R100 "radeon/R100_cp.bin"
47 #define FIRMWARE_R200 "radeon/R200_cp.bin"
48 #define FIRMWARE_R300 "radeon/R300_cp.bin"
49 #define FIRMWARE_R420 "radeon/R420_cp.bin"
50 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
51 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
52 #define FIRMWARE_R520 "radeon/R520_cp.bin"
54 MODULE_FIRMWARE(FIRMWARE_R100);
55 MODULE_FIRMWARE(FIRMWARE_R200);
56 MODULE_FIRMWARE(FIRMWARE_R300);
57 MODULE_FIRMWARE(FIRMWARE_R420);
58 MODULE_FIRMWARE(FIRMWARE_RS690);
59 MODULE_FIRMWARE(FIRMWARE_RS600);
60 MODULE_FIRMWARE(FIRMWARE_R520);
62 #include "r100_track.h"
64 /* This files gather functions specifics to:
65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
68 /* hpd for digital panel detect/disconnect */
69 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
71 bool connected = false;
75 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
79 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
88 void r100_hpd_set_polarity(struct radeon_device *rdev,
89 enum radeon_hpd_id hpd)
92 bool connected = r100_hpd_sense(rdev, hpd);
96 tmp = RREG32(RADEON_FP_GEN_CNTL);
98 tmp &= ~RADEON_FP_DETECT_INT_POL;
100 tmp |= RADEON_FP_DETECT_INT_POL;
101 WREG32(RADEON_FP_GEN_CNTL, tmp);
104 tmp = RREG32(RADEON_FP2_GEN_CNTL);
106 tmp &= ~RADEON_FP2_DETECT_INT_POL;
108 tmp |= RADEON_FP2_DETECT_INT_POL;
109 WREG32(RADEON_FP2_GEN_CNTL, tmp);
116 void r100_hpd_init(struct radeon_device *rdev)
118 struct drm_device *dev = rdev->ddev;
119 struct drm_connector *connector;
121 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
122 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
123 switch (radeon_connector->hpd.hpd) {
125 rdev->irq.hpd[0] = true;
128 rdev->irq.hpd[1] = true;
137 void r100_hpd_fini(struct radeon_device *rdev)
139 struct drm_device *dev = rdev->ddev;
140 struct drm_connector *connector;
142 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
143 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
144 switch (radeon_connector->hpd.hpd) {
146 rdev->irq.hpd[0] = false;
149 rdev->irq.hpd[1] = false;
160 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
162 /* TODO: can we do somethings here ? */
163 /* It seems hw only cache one entry so we should discard this
164 * entry otherwise if first GPU GART read hit this entry it
165 * could end up in wrong address. */
168 int r100_pci_gart_init(struct radeon_device *rdev)
172 if (rdev->gart.table.ram.ptr) {
173 WARN(1, "R100 PCI GART already initialized.\n");
176 /* Initialize common gart structure */
177 r = radeon_gart_init(rdev);
180 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
181 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
182 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
183 return radeon_gart_table_ram_alloc(rdev);
186 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
187 void r100_enable_bm(struct radeon_device *rdev)
190 /* Enable bus mastering */
191 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
192 WREG32(RADEON_BUS_CNTL, tmp);
195 int r100_pci_gart_enable(struct radeon_device *rdev)
199 /* discard memory request outside of configured range */
200 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
201 WREG32(RADEON_AIC_CNTL, tmp);
202 /* set address range for PCI address translate */
203 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
204 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
205 WREG32(RADEON_AIC_HI_ADDR, tmp);
206 /* set PCI GART page-table base address */
207 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
208 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
209 WREG32(RADEON_AIC_CNTL, tmp);
210 r100_pci_gart_tlb_flush(rdev);
211 rdev->gart.ready = true;
215 void r100_pci_gart_disable(struct radeon_device *rdev)
219 /* discard memory request outside of configured range */
220 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
221 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
222 WREG32(RADEON_AIC_LO_ADDR, 0);
223 WREG32(RADEON_AIC_HI_ADDR, 0);
226 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
228 if (i < 0 || i > rdev->gart.num_gpu_pages) {
231 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
235 void r100_pci_gart_fini(struct radeon_device *rdev)
237 r100_pci_gart_disable(rdev);
238 radeon_gart_table_ram_free(rdev);
239 radeon_gart_fini(rdev);
242 int r100_irq_set(struct radeon_device *rdev)
246 if (rdev->irq.sw_int) {
247 tmp |= RADEON_SW_INT_ENABLE;
249 if (rdev->irq.crtc_vblank_int[0]) {
250 tmp |= RADEON_CRTC_VBLANK_MASK;
252 if (rdev->irq.crtc_vblank_int[1]) {
253 tmp |= RADEON_CRTC2_VBLANK_MASK;
255 if (rdev->irq.hpd[0]) {
256 tmp |= RADEON_FP_DETECT_MASK;
258 if (rdev->irq.hpd[1]) {
259 tmp |= RADEON_FP2_DETECT_MASK;
261 WREG32(RADEON_GEN_INT_CNTL, tmp);
265 void r100_irq_disable(struct radeon_device *rdev)
269 WREG32(R_000040_GEN_INT_CNTL, 0);
270 /* Wait and acknowledge irq */
272 tmp = RREG32(R_000044_GEN_INT_STATUS);
273 WREG32(R_000044_GEN_INT_STATUS, tmp);
276 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
278 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
279 uint32_t irq_mask = RADEON_SW_INT_TEST |
280 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
281 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
284 WREG32(RADEON_GEN_INT_STATUS, irqs);
286 return irqs & irq_mask;
289 int r100_irq_process(struct radeon_device *rdev)
291 uint32_t status, msi_rearm;
292 bool queue_hotplug = false;
294 status = r100_irq_ack(rdev);
298 if (rdev->shutdown) {
303 if (status & RADEON_SW_INT_TEST) {
304 radeon_fence_process(rdev);
306 /* Vertical blank interrupts */
307 if (status & RADEON_CRTC_VBLANK_STAT) {
308 drm_handle_vblank(rdev->ddev, 0);
310 if (status & RADEON_CRTC2_VBLANK_STAT) {
311 drm_handle_vblank(rdev->ddev, 1);
313 if (status & RADEON_FP_DETECT_STAT) {
314 queue_hotplug = true;
317 if (status & RADEON_FP2_DETECT_STAT) {
318 queue_hotplug = true;
321 status = r100_irq_ack(rdev);
324 queue_work(rdev->wq, &rdev->hotplug_work);
325 if (rdev->msi_enabled) {
326 switch (rdev->family) {
329 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
330 WREG32(RADEON_AIC_CNTL, msi_rearm);
331 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
334 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
335 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
336 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
343 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
346 return RREG32(RADEON_CRTC_CRNT_FRAME);
348 return RREG32(RADEON_CRTC2_CRNT_FRAME);
351 void r100_fence_ring_emit(struct radeon_device *rdev,
352 struct radeon_fence *fence)
354 /* Who ever call radeon_fence_emit should call ring_lock and ask
355 * for enough space (today caller are ib schedule and buffer move) */
356 /* Wait until IDLE & CLEAN */
357 radeon_ring_write(rdev, PACKET0(0x1720, 0));
358 radeon_ring_write(rdev, (1 << 16) | (1 << 17));
359 /* Emit fence sequence & fire IRQ */
360 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
361 radeon_ring_write(rdev, fence->seq);
362 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
363 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
366 int r100_wb_init(struct radeon_device *rdev)
370 if (rdev->wb.wb_obj == NULL) {
371 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
372 RADEON_GEM_DOMAIN_GTT,
375 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
378 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
379 if (unlikely(r != 0))
381 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
384 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
385 radeon_bo_unreserve(rdev->wb.wb_obj);
388 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
389 radeon_bo_unreserve(rdev->wb.wb_obj);
391 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
395 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
396 WREG32(R_00070C_CP_RB_RPTR_ADDR,
397 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
398 WREG32(R_000770_SCRATCH_UMSK, 0xff);
402 void r100_wb_disable(struct radeon_device *rdev)
404 WREG32(R_000770_SCRATCH_UMSK, 0);
407 void r100_wb_fini(struct radeon_device *rdev)
411 r100_wb_disable(rdev);
412 if (rdev->wb.wb_obj) {
413 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
414 if (unlikely(r != 0)) {
415 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
418 radeon_bo_kunmap(rdev->wb.wb_obj);
419 radeon_bo_unpin(rdev->wb.wb_obj);
420 radeon_bo_unreserve(rdev->wb.wb_obj);
421 radeon_bo_unref(&rdev->wb.wb_obj);
423 rdev->wb.wb_obj = NULL;
427 int r100_copy_blit(struct radeon_device *rdev,
431 struct radeon_fence *fence)
434 uint32_t stride_bytes = PAGE_SIZE;
436 uint32_t stride_pixels;
441 /* radeon limited to 16k stride */
442 stride_bytes &= 0x3fff;
443 /* radeon pitch is /64 */
444 pitch = stride_bytes / 64;
445 stride_pixels = stride_bytes / 4;
446 num_loops = DIV_ROUND_UP(num_pages, 8191);
448 /* Ask for enough room for blit + flush + fence */
449 ndw = 64 + (10 * num_loops);
450 r = radeon_ring_lock(rdev, ndw);
452 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
455 while (num_pages > 0) {
456 cur_pages = num_pages;
457 if (cur_pages > 8191) {
460 num_pages -= cur_pages;
462 /* pages are in Y direction - height
463 page width in X direction - width */
464 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
465 radeon_ring_write(rdev,
466 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
467 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
468 RADEON_GMC_SRC_CLIPPING |
469 RADEON_GMC_DST_CLIPPING |
470 RADEON_GMC_BRUSH_NONE |
471 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
472 RADEON_GMC_SRC_DATATYPE_COLOR |
474 RADEON_DP_SRC_SOURCE_MEMORY |
475 RADEON_GMC_CLR_CMP_CNTL_DIS |
476 RADEON_GMC_WR_MSK_DIS);
477 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
478 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
479 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
480 radeon_ring_write(rdev, 0);
481 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
482 radeon_ring_write(rdev, num_pages);
483 radeon_ring_write(rdev, num_pages);
484 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
486 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
487 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
488 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
489 radeon_ring_write(rdev,
490 RADEON_WAIT_2D_IDLECLEAN |
491 RADEON_WAIT_HOST_IDLECLEAN |
492 RADEON_WAIT_DMA_GUI_IDLE);
494 r = radeon_fence_emit(rdev, fence);
496 radeon_ring_unlock_commit(rdev);
500 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
505 for (i = 0; i < rdev->usec_timeout; i++) {
506 tmp = RREG32(R_000E40_RBBM_STATUS);
507 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
515 void r100_ring_start(struct radeon_device *rdev)
519 r = radeon_ring_lock(rdev, 2);
523 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
524 radeon_ring_write(rdev,
525 RADEON_ISYNC_ANY2D_IDLE3D |
526 RADEON_ISYNC_ANY3D_IDLE2D |
527 RADEON_ISYNC_WAIT_IDLEGUI |
528 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
529 radeon_ring_unlock_commit(rdev);
533 /* Load the microcode for the CP */
534 static int r100_cp_init_microcode(struct radeon_device *rdev)
536 struct platform_device *pdev;
537 const char *fw_name = NULL;
542 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
545 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
548 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
549 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
550 (rdev->family == CHIP_RS200)) {
551 DRM_INFO("Loading R100 Microcode\n");
552 fw_name = FIRMWARE_R100;
553 } else if ((rdev->family == CHIP_R200) ||
554 (rdev->family == CHIP_RV250) ||
555 (rdev->family == CHIP_RV280) ||
556 (rdev->family == CHIP_RS300)) {
557 DRM_INFO("Loading R200 Microcode\n");
558 fw_name = FIRMWARE_R200;
559 } else if ((rdev->family == CHIP_R300) ||
560 (rdev->family == CHIP_R350) ||
561 (rdev->family == CHIP_RV350) ||
562 (rdev->family == CHIP_RV380) ||
563 (rdev->family == CHIP_RS400) ||
564 (rdev->family == CHIP_RS480)) {
565 DRM_INFO("Loading R300 Microcode\n");
566 fw_name = FIRMWARE_R300;
567 } else if ((rdev->family == CHIP_R420) ||
568 (rdev->family == CHIP_R423) ||
569 (rdev->family == CHIP_RV410)) {
570 DRM_INFO("Loading R400 Microcode\n");
571 fw_name = FIRMWARE_R420;
572 } else if ((rdev->family == CHIP_RS690) ||
573 (rdev->family == CHIP_RS740)) {
574 DRM_INFO("Loading RS690/RS740 Microcode\n");
575 fw_name = FIRMWARE_RS690;
576 } else if (rdev->family == CHIP_RS600) {
577 DRM_INFO("Loading RS600 Microcode\n");
578 fw_name = FIRMWARE_RS600;
579 } else if ((rdev->family == CHIP_RV515) ||
580 (rdev->family == CHIP_R520) ||
581 (rdev->family == CHIP_RV530) ||
582 (rdev->family == CHIP_R580) ||
583 (rdev->family == CHIP_RV560) ||
584 (rdev->family == CHIP_RV570)) {
585 DRM_INFO("Loading R500 Microcode\n");
586 fw_name = FIRMWARE_R520;
589 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
590 platform_device_unregister(pdev);
592 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
594 } else if (rdev->me_fw->size % 8) {
596 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
597 rdev->me_fw->size, fw_name);
599 release_firmware(rdev->me_fw);
605 static void r100_cp_load_microcode(struct radeon_device *rdev)
607 const __be32 *fw_data;
610 if (r100_gui_wait_for_idle(rdev)) {
611 printk(KERN_WARNING "Failed to wait GUI idle while "
612 "programming pipes. Bad things might happen.\n");
616 size = rdev->me_fw->size / 4;
617 fw_data = (const __be32 *)&rdev->me_fw->data[0];
618 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
619 for (i = 0; i < size; i += 2) {
620 WREG32(RADEON_CP_ME_RAM_DATAH,
621 be32_to_cpup(&fw_data[i]));
622 WREG32(RADEON_CP_ME_RAM_DATAL,
623 be32_to_cpup(&fw_data[i + 1]));
628 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
633 unsigned pre_write_timer;
634 unsigned pre_write_limit;
635 unsigned indirect2_start;
636 unsigned indirect1_start;
640 if (r100_debugfs_cp_init(rdev)) {
641 DRM_ERROR("Failed to register debugfs file for CP !\n");
644 tmp = RREG32(RADEON_CP_CSQ_STAT);
645 if ((tmp & (1 << 31))) {
646 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
647 WREG32(RADEON_CP_CSQ_MODE, 0);
648 WREG32(RADEON_CP_CSQ_CNTL, 0);
649 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
650 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
652 WREG32(RADEON_RBBM_SOFT_RESET, 0);
653 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
655 tmp = RREG32(RADEON_CP_CSQ_STAT);
656 if ((tmp & (1 << 31))) {
657 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
660 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
664 r = r100_cp_init_microcode(rdev);
666 DRM_ERROR("Failed to load firmware!\n");
671 /* Align ring size */
672 rb_bufsz = drm_order(ring_size / 8);
673 ring_size = (1 << (rb_bufsz + 1)) * 4;
674 r100_cp_load_microcode(rdev);
675 r = radeon_ring_init(rdev, ring_size);
679 /* Each time the cp read 1024 bytes (16 dword/quadword) update
680 * the rptr copy in system ram */
682 /* cp will read 128bytes at a time (4 dwords) */
684 rdev->cp.align_mask = 16 - 1;
685 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
686 pre_write_timer = 64;
687 /* Force CP_RB_WPTR write if written more than one time before the
691 /* Setup the cp cache like this (cache size is 96 dwords) :
695 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
696 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
697 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
698 * Idea being that most of the gpu cmd will be through indirect1 buffer
699 * so it gets the bigger cache.
701 indirect2_start = 80;
702 indirect1_start = 16;
704 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
705 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
706 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
707 REG_SET(RADEON_MAX_FETCH, max_fetch) |
708 RADEON_RB_NO_UPDATE);
710 tmp |= RADEON_BUF_SWAP_32BIT;
712 WREG32(RADEON_CP_RB_CNTL, tmp);
714 /* Set ring address */
715 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
716 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
717 /* Force read & write ptr to 0 */
718 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
719 WREG32(RADEON_CP_RB_RPTR_WR, 0);
720 WREG32(RADEON_CP_RB_WPTR, 0);
721 WREG32(RADEON_CP_RB_CNTL, tmp);
723 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
724 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
725 /* Set cp mode to bus mastering & enable cp*/
726 WREG32(RADEON_CP_CSQ_MODE,
727 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
728 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
730 WREG32(0x744, 0x00004D4D);
731 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
732 radeon_ring_start(rdev);
733 r = radeon_ring_test(rdev);
735 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
738 rdev->cp.ready = true;
742 void r100_cp_fini(struct radeon_device *rdev)
744 if (r100_cp_wait_for_idle(rdev)) {
745 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
748 r100_cp_disable(rdev);
749 radeon_ring_fini(rdev);
750 DRM_INFO("radeon: cp finalized\n");
753 void r100_cp_disable(struct radeon_device *rdev)
756 rdev->cp.ready = false;
757 WREG32(RADEON_CP_CSQ_MODE, 0);
758 WREG32(RADEON_CP_CSQ_CNTL, 0);
759 if (r100_gui_wait_for_idle(rdev)) {
760 printk(KERN_WARNING "Failed to wait GUI idle while "
761 "programming pipes. Bad things might happen.\n");
765 int r100_cp_reset(struct radeon_device *rdev)
771 reinit_cp = rdev->cp.ready;
772 rdev->cp.ready = false;
773 WREG32(RADEON_CP_CSQ_MODE, 0);
774 WREG32(RADEON_CP_CSQ_CNTL, 0);
775 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
776 (void)RREG32(RADEON_RBBM_SOFT_RESET);
778 WREG32(RADEON_RBBM_SOFT_RESET, 0);
779 /* Wait to prevent race in RBBM_STATUS */
781 for (i = 0; i < rdev->usec_timeout; i++) {
782 tmp = RREG32(RADEON_RBBM_STATUS);
783 if (!(tmp & (1 << 16))) {
784 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
787 return r100_cp_init(rdev, rdev->cp.ring_size);
793 tmp = RREG32(RADEON_RBBM_STATUS);
794 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
798 void r100_cp_commit(struct radeon_device *rdev)
800 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
801 (void)RREG32(RADEON_CP_RB_WPTR);
808 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
809 struct radeon_cs_packet *pkt,
810 const unsigned *auth, unsigned n,
811 radeon_packet0_check_t check)
820 /* Check that register fall into register range
821 * determined by the number of entry (n) in the
822 * safe register bitmap.
824 if (pkt->one_reg_wr) {
825 if ((reg >> 7) > n) {
829 if (((reg + (pkt->count << 2)) >> 7) > n) {
833 for (i = 0; i <= pkt->count; i++, idx++) {
835 m = 1 << ((reg >> 2) & 31);
837 r = check(p, pkt, idx, reg);
842 if (pkt->one_reg_wr) {
843 if (!(auth[j] & m)) {
853 void r100_cs_dump_packet(struct radeon_cs_parser *p,
854 struct radeon_cs_packet *pkt)
856 volatile uint32_t *ib;
862 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
863 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
868 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
869 * @parser: parser structure holding parsing context.
870 * @pkt: where to store packet informations
872 * Assume that chunk_ib_index is properly set. Will return -EINVAL
873 * if packet is bigger than remaining ib size. or if packets is unknown.
875 int r100_cs_packet_parse(struct radeon_cs_parser *p,
876 struct radeon_cs_packet *pkt,
879 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
882 if (idx >= ib_chunk->length_dw) {
883 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
884 idx, ib_chunk->length_dw);
887 header = radeon_get_ib_value(p, idx);
889 pkt->type = CP_PACKET_GET_TYPE(header);
890 pkt->count = CP_PACKET_GET_COUNT(header);
893 pkt->reg = CP_PACKET0_GET_REG(header);
894 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
897 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
903 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
906 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
907 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
908 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
915 * r100_cs_packet_next_vline() - parse userspace VLINE packet
916 * @parser: parser structure holding parsing context.
918 * Userspace sends a special sequence for VLINE waits.
919 * PACKET0 - VLINE_START_END + value
920 * PACKET0 - WAIT_UNTIL +_value
921 * RELOC (P3) - crtc_id in reloc.
923 * This function parses this and relocates the VLINE START END
924 * and WAIT UNTIL packets to the correct crtc.
925 * It also detects a switched off crtc and nulls out the
928 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
930 struct drm_mode_object *obj;
931 struct drm_crtc *crtc;
932 struct radeon_crtc *radeon_crtc;
933 struct radeon_cs_packet p3reloc, waitreloc;
936 uint32_t header, h_idx, reg;
937 volatile uint32_t *ib;
941 /* parse the wait until */
942 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
946 /* check its a wait until and only 1 count */
947 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
948 waitreloc.count != 0) {
949 DRM_ERROR("vline wait had illegal wait until segment\n");
954 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
955 DRM_ERROR("vline wait had illegal wait until\n");
960 /* jump over the NOP */
961 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
966 p->idx += waitreloc.count + 2;
967 p->idx += p3reloc.count + 2;
969 header = radeon_get_ib_value(p, h_idx);
970 crtc_id = radeon_get_ib_value(p, h_idx + 5);
971 reg = CP_PACKET0_GET_REG(header);
972 mutex_lock(&p->rdev->ddev->mode_config.mutex);
973 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
975 DRM_ERROR("cannot find crtc %d\n", crtc_id);
979 crtc = obj_to_crtc(obj);
980 radeon_crtc = to_radeon_crtc(crtc);
981 crtc_id = radeon_crtc->crtc_id;
983 if (!crtc->enabled) {
984 /* if the CRTC isn't enabled - we need to nop out the wait until */
985 ib[h_idx + 2] = PACKET2(0);
986 ib[h_idx + 3] = PACKET2(0);
987 } else if (crtc_id == 1) {
989 case AVIVO_D1MODE_VLINE_START_END:
990 header &= ~R300_CP_PACKET0_REG_MASK;
991 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
993 case RADEON_CRTC_GUI_TRIG_VLINE:
994 header &= ~R300_CP_PACKET0_REG_MASK;
995 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
998 DRM_ERROR("unknown crtc reloc\n");
1003 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1006 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1011 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1012 * @parser: parser structure holding parsing context.
1013 * @data: pointer to relocation data
1014 * @offset_start: starting offset
1015 * @offset_mask: offset mask (to align start offset on)
1016 * @reloc: reloc informations
1018 * Check next packet is relocation packet3, do bo validation and compute
1019 * GPU offset using the provided start.
1021 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1022 struct radeon_cs_reloc **cs_reloc)
1024 struct radeon_cs_chunk *relocs_chunk;
1025 struct radeon_cs_packet p3reloc;
1029 if (p->chunk_relocs_idx == -1) {
1030 DRM_ERROR("No relocation chunk !\n");
1034 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1035 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1039 p->idx += p3reloc.count + 2;
1040 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1041 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1043 r100_cs_dump_packet(p, &p3reloc);
1046 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1047 if (idx >= relocs_chunk->length_dw) {
1048 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1049 idx, relocs_chunk->length_dw);
1050 r100_cs_dump_packet(p, &p3reloc);
1053 /* FIXME: we assume reloc size is 4 dwords */
1054 *cs_reloc = p->relocs_ptr[(idx / 4)];
1058 static int r100_get_vtx_size(uint32_t vtx_fmt)
1062 /* ordered according to bits in spec */
1063 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1065 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1067 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1069 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1071 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1073 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1075 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1077 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1079 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1081 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1083 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1085 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1087 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1089 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1091 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1094 if (vtx_fmt & (0x7 << 15))
1095 vtx_size += (vtx_fmt >> 15) & 0x7;
1096 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1098 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1100 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1102 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1104 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1106 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1111 static int r100_packet0_check(struct radeon_cs_parser *p,
1112 struct radeon_cs_packet *pkt,
1113 unsigned idx, unsigned reg)
1115 struct radeon_cs_reloc *reloc;
1116 struct r100_cs_track *track;
1117 volatile uint32_t *ib;
1125 track = (struct r100_cs_track *)p->track;
1127 idx_value = radeon_get_ib_value(p, idx);
1130 case RADEON_CRTC_GUI_TRIG_VLINE:
1131 r = r100_cs_packet_parse_vline(p);
1133 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1135 r100_cs_dump_packet(p, pkt);
1139 /* FIXME: only allow PACKET3 blit? easier to check for out of
1141 case RADEON_DST_PITCH_OFFSET:
1142 case RADEON_SRC_PITCH_OFFSET:
1143 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1147 case RADEON_RB3D_DEPTHOFFSET:
1148 r = r100_cs_packet_next_reloc(p, &reloc);
1150 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1152 r100_cs_dump_packet(p, pkt);
1155 track->zb.robj = reloc->robj;
1156 track->zb.offset = idx_value;
1157 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1159 case RADEON_RB3D_COLOROFFSET:
1160 r = r100_cs_packet_next_reloc(p, &reloc);
1162 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1164 r100_cs_dump_packet(p, pkt);
1167 track->cb[0].robj = reloc->robj;
1168 track->cb[0].offset = idx_value;
1169 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1171 case RADEON_PP_TXOFFSET_0:
1172 case RADEON_PP_TXOFFSET_1:
1173 case RADEON_PP_TXOFFSET_2:
1174 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1175 r = r100_cs_packet_next_reloc(p, &reloc);
1177 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1179 r100_cs_dump_packet(p, pkt);
1182 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1183 track->textures[i].robj = reloc->robj;
1185 case RADEON_PP_CUBIC_OFFSET_T0_0:
1186 case RADEON_PP_CUBIC_OFFSET_T0_1:
1187 case RADEON_PP_CUBIC_OFFSET_T0_2:
1188 case RADEON_PP_CUBIC_OFFSET_T0_3:
1189 case RADEON_PP_CUBIC_OFFSET_T0_4:
1190 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1191 r = r100_cs_packet_next_reloc(p, &reloc);
1193 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1195 r100_cs_dump_packet(p, pkt);
1198 track->textures[0].cube_info[i].offset = idx_value;
1199 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1200 track->textures[0].cube_info[i].robj = reloc->robj;
1202 case RADEON_PP_CUBIC_OFFSET_T1_0:
1203 case RADEON_PP_CUBIC_OFFSET_T1_1:
1204 case RADEON_PP_CUBIC_OFFSET_T1_2:
1205 case RADEON_PP_CUBIC_OFFSET_T1_3:
1206 case RADEON_PP_CUBIC_OFFSET_T1_4:
1207 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1208 r = r100_cs_packet_next_reloc(p, &reloc);
1210 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1212 r100_cs_dump_packet(p, pkt);
1215 track->textures[1].cube_info[i].offset = idx_value;
1216 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1217 track->textures[1].cube_info[i].robj = reloc->robj;
1219 case RADEON_PP_CUBIC_OFFSET_T2_0:
1220 case RADEON_PP_CUBIC_OFFSET_T2_1:
1221 case RADEON_PP_CUBIC_OFFSET_T2_2:
1222 case RADEON_PP_CUBIC_OFFSET_T2_3:
1223 case RADEON_PP_CUBIC_OFFSET_T2_4:
1224 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1225 r = r100_cs_packet_next_reloc(p, &reloc);
1227 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1229 r100_cs_dump_packet(p, pkt);
1232 track->textures[2].cube_info[i].offset = idx_value;
1233 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1234 track->textures[2].cube_info[i].robj = reloc->robj;
1236 case RADEON_RE_WIDTH_HEIGHT:
1237 track->maxy = ((idx_value >> 16) & 0x7FF);
1239 case RADEON_RB3D_COLORPITCH:
1240 r = r100_cs_packet_next_reloc(p, &reloc);
1242 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1244 r100_cs_dump_packet(p, pkt);
1248 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1249 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1250 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1251 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1253 tmp = idx_value & ~(0x7 << 16);
1257 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1259 case RADEON_RB3D_DEPTHPITCH:
1260 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1262 case RADEON_RB3D_CNTL:
1263 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1269 track->cb[0].cpp = 1;
1274 track->cb[0].cpp = 2;
1277 track->cb[0].cpp = 4;
1280 DRM_ERROR("Invalid color buffer format (%d) !\n",
1281 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1284 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1286 case RADEON_RB3D_ZSTENCILCNTL:
1287 switch (idx_value & 0xf) {
1303 case RADEON_RB3D_ZPASS_ADDR:
1304 r = r100_cs_packet_next_reloc(p, &reloc);
1306 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1308 r100_cs_dump_packet(p, pkt);
1311 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1313 case RADEON_PP_CNTL:
1315 uint32_t temp = idx_value >> 4;
1316 for (i = 0; i < track->num_texture; i++)
1317 track->textures[i].enabled = !!(temp & (1 << i));
1320 case RADEON_SE_VF_CNTL:
1321 track->vap_vf_cntl = idx_value;
1323 case RADEON_SE_VTX_FMT:
1324 track->vtx_size = r100_get_vtx_size(idx_value);
1326 case RADEON_PP_TEX_SIZE_0:
1327 case RADEON_PP_TEX_SIZE_1:
1328 case RADEON_PP_TEX_SIZE_2:
1329 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1330 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1331 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1333 case RADEON_PP_TEX_PITCH_0:
1334 case RADEON_PP_TEX_PITCH_1:
1335 case RADEON_PP_TEX_PITCH_2:
1336 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1337 track->textures[i].pitch = idx_value + 32;
1339 case RADEON_PP_TXFILTER_0:
1340 case RADEON_PP_TXFILTER_1:
1341 case RADEON_PP_TXFILTER_2:
1342 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1343 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1344 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1345 tmp = (idx_value >> 23) & 0x7;
1346 if (tmp == 2 || tmp == 6)
1347 track->textures[i].roundup_w = false;
1348 tmp = (idx_value >> 27) & 0x7;
1349 if (tmp == 2 || tmp == 6)
1350 track->textures[i].roundup_h = false;
1352 case RADEON_PP_TXFORMAT_0:
1353 case RADEON_PP_TXFORMAT_1:
1354 case RADEON_PP_TXFORMAT_2:
1355 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1356 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1357 track->textures[i].use_pitch = 1;
1359 track->textures[i].use_pitch = 0;
1360 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1361 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1363 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1364 track->textures[i].tex_coord_type = 2;
1365 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1366 case RADEON_TXFORMAT_I8:
1367 case RADEON_TXFORMAT_RGB332:
1368 case RADEON_TXFORMAT_Y8:
1369 track->textures[i].cpp = 1;
1371 case RADEON_TXFORMAT_AI88:
1372 case RADEON_TXFORMAT_ARGB1555:
1373 case RADEON_TXFORMAT_RGB565:
1374 case RADEON_TXFORMAT_ARGB4444:
1375 case RADEON_TXFORMAT_VYUY422:
1376 case RADEON_TXFORMAT_YVYU422:
1377 case RADEON_TXFORMAT_SHADOW16:
1378 case RADEON_TXFORMAT_LDUDV655:
1379 case RADEON_TXFORMAT_DUDV88:
1380 track->textures[i].cpp = 2;
1382 case RADEON_TXFORMAT_ARGB8888:
1383 case RADEON_TXFORMAT_RGBA8888:
1384 case RADEON_TXFORMAT_SHADOW32:
1385 case RADEON_TXFORMAT_LDUDUV8888:
1386 track->textures[i].cpp = 4;
1388 case RADEON_TXFORMAT_DXT1:
1389 track->textures[i].cpp = 1;
1390 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1392 case RADEON_TXFORMAT_DXT23:
1393 case RADEON_TXFORMAT_DXT45:
1394 track->textures[i].cpp = 1;
1395 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1398 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1399 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1401 case RADEON_PP_CUBIC_FACES_0:
1402 case RADEON_PP_CUBIC_FACES_1:
1403 case RADEON_PP_CUBIC_FACES_2:
1405 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1406 for (face = 0; face < 4; face++) {
1407 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1408 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1412 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1419 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1420 struct radeon_cs_packet *pkt,
1421 struct radeon_bo *robj)
1426 value = radeon_get_ib_value(p, idx + 2);
1427 if ((value + 1) > radeon_bo_size(robj)) {
1428 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1429 "(need %u have %lu) !\n",
1431 radeon_bo_size(robj));
1437 static int r100_packet3_check(struct radeon_cs_parser *p,
1438 struct radeon_cs_packet *pkt)
1440 struct radeon_cs_reloc *reloc;
1441 struct r100_cs_track *track;
1443 volatile uint32_t *ib;
1448 track = (struct r100_cs_track *)p->track;
1449 switch (pkt->opcode) {
1450 case PACKET3_3D_LOAD_VBPNTR:
1451 r = r100_packet3_load_vbpntr(p, pkt, idx);
1455 case PACKET3_INDX_BUFFER:
1456 r = r100_cs_packet_next_reloc(p, &reloc);
1458 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1459 r100_cs_dump_packet(p, pkt);
1462 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1463 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1469 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1470 r = r100_cs_packet_next_reloc(p, &reloc);
1472 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1473 r100_cs_dump_packet(p, pkt);
1476 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1477 track->num_arrays = 1;
1478 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1480 track->arrays[0].robj = reloc->robj;
1481 track->arrays[0].esize = track->vtx_size;
1483 track->max_indx = radeon_get_ib_value(p, idx+1);
1485 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1486 track->immd_dwords = pkt->count - 1;
1487 r = r100_cs_track_check(p->rdev, track);
1491 case PACKET3_3D_DRAW_IMMD:
1492 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1493 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1496 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1497 track->immd_dwords = pkt->count - 1;
1498 r = r100_cs_track_check(p->rdev, track);
1502 /* triggers drawing using in-packet vertex data */
1503 case PACKET3_3D_DRAW_IMMD_2:
1504 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1505 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1508 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1509 track->immd_dwords = pkt->count;
1510 r = r100_cs_track_check(p->rdev, track);
1514 /* triggers drawing using in-packet vertex data */
1515 case PACKET3_3D_DRAW_VBUF_2:
1516 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1517 r = r100_cs_track_check(p->rdev, track);
1521 /* triggers drawing of vertex buffers setup elsewhere */
1522 case PACKET3_3D_DRAW_INDX_2:
1523 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1524 r = r100_cs_track_check(p->rdev, track);
1528 /* triggers drawing using indices to vertex buffer */
1529 case PACKET3_3D_DRAW_VBUF:
1530 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1531 r = r100_cs_track_check(p->rdev, track);
1535 /* triggers drawing of vertex buffers setup elsewhere */
1536 case PACKET3_3D_DRAW_INDX:
1537 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1538 r = r100_cs_track_check(p->rdev, track);
1542 /* triggers drawing using indices to vertex buffer */
1546 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1552 int r100_cs_parse(struct radeon_cs_parser *p)
1554 struct radeon_cs_packet pkt;
1555 struct r100_cs_track *track;
1558 track = kzalloc(sizeof(*track), GFP_KERNEL);
1559 r100_cs_track_clear(p->rdev, track);
1562 r = r100_cs_packet_parse(p, &pkt, p->idx);
1566 p->idx += pkt.count + 2;
1569 if (p->rdev->family >= CHIP_R200)
1570 r = r100_cs_parse_packet0(p, &pkt,
1571 p->rdev->config.r100.reg_safe_bm,
1572 p->rdev->config.r100.reg_safe_bm_size,
1573 &r200_packet0_check);
1575 r = r100_cs_parse_packet0(p, &pkt,
1576 p->rdev->config.r100.reg_safe_bm,
1577 p->rdev->config.r100.reg_safe_bm_size,
1578 &r100_packet0_check);
1583 r = r100_packet3_check(p, &pkt);
1586 DRM_ERROR("Unknown packet type %d !\n",
1593 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1599 * Global GPU functions
1601 void r100_errata(struct radeon_device *rdev)
1603 rdev->pll_errata = 0;
1605 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1606 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1609 if (rdev->family == CHIP_RV100 ||
1610 rdev->family == CHIP_RS100 ||
1611 rdev->family == CHIP_RS200) {
1612 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1616 /* Wait for vertical sync on primary CRTC */
1617 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1619 uint32_t crtc_gen_cntl, tmp;
1622 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1623 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1624 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1627 /* Clear the CRTC_VBLANK_SAVE bit */
1628 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1629 for (i = 0; i < rdev->usec_timeout; i++) {
1630 tmp = RREG32(RADEON_CRTC_STATUS);
1631 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1638 /* Wait for vertical sync on secondary CRTC */
1639 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1641 uint32_t crtc2_gen_cntl, tmp;
1644 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1645 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1646 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1649 /* Clear the CRTC_VBLANK_SAVE bit */
1650 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1651 for (i = 0; i < rdev->usec_timeout; i++) {
1652 tmp = RREG32(RADEON_CRTC2_STATUS);
1653 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1660 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1665 for (i = 0; i < rdev->usec_timeout; i++) {
1666 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1675 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1680 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1681 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1682 " Bad things might happen.\n");
1684 for (i = 0; i < rdev->usec_timeout; i++) {
1685 tmp = RREG32(RADEON_RBBM_STATUS);
1686 if (!(tmp & (1 << 31))) {
1694 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1699 for (i = 0; i < rdev->usec_timeout; i++) {
1700 /* read MC_STATUS */
1701 tmp = RREG32(0x0150);
1702 if (tmp & (1 << 2)) {
1710 void r100_gpu_init(struct radeon_device *rdev)
1712 /* TODO: anythings to do here ? pipes ? */
1713 r100_hdp_reset(rdev);
1716 void r100_hdp_flush(struct radeon_device *rdev)
1719 tmp = RREG32(RADEON_HOST_PATH_CNTL);
1720 tmp |= RADEON_HDP_READ_BUFFER_INVALIDATE;
1721 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1724 void r100_hdp_reset(struct radeon_device *rdev)
1728 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1730 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1731 (void)RREG32(RADEON_HOST_PATH_CNTL);
1733 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1734 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1735 (void)RREG32(RADEON_HOST_PATH_CNTL);
1738 int r100_rb2d_reset(struct radeon_device *rdev)
1743 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1744 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1746 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1747 /* Wait to prevent race in RBBM_STATUS */
1749 for (i = 0; i < rdev->usec_timeout; i++) {
1750 tmp = RREG32(RADEON_RBBM_STATUS);
1751 if (!(tmp & (1 << 26))) {
1752 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1758 tmp = RREG32(RADEON_RBBM_STATUS);
1759 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1763 int r100_gpu_reset(struct radeon_device *rdev)
1767 /* reset order likely matter */
1768 status = RREG32(RADEON_RBBM_STATUS);
1770 r100_hdp_reset(rdev);
1772 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1773 r100_rb2d_reset(rdev);
1775 /* TODO: reset 3D engine */
1777 status = RREG32(RADEON_RBBM_STATUS);
1778 if (status & (1 << 16)) {
1779 r100_cp_reset(rdev);
1781 /* Check if GPU is idle */
1782 status = RREG32(RADEON_RBBM_STATUS);
1783 if (status & (1 << 31)) {
1784 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1787 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1791 void r100_set_common_regs(struct radeon_device *rdev)
1793 /* set these so they don't interfere with anything */
1794 WREG32(RADEON_OV0_SCALE_CNTL, 0);
1795 WREG32(RADEON_SUBPIC_CNTL, 0);
1796 WREG32(RADEON_VIPH_CONTROL, 0);
1797 WREG32(RADEON_I2C_CNTL_1, 0);
1798 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1799 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1800 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1806 static void r100_vram_get_type(struct radeon_device *rdev)
1810 rdev->mc.vram_is_ddr = false;
1811 if (rdev->flags & RADEON_IS_IGP)
1812 rdev->mc.vram_is_ddr = true;
1813 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1814 rdev->mc.vram_is_ddr = true;
1815 if ((rdev->family == CHIP_RV100) ||
1816 (rdev->family == CHIP_RS100) ||
1817 (rdev->family == CHIP_RS200)) {
1818 tmp = RREG32(RADEON_MEM_CNTL);
1819 if (tmp & RV100_HALF_MODE) {
1820 rdev->mc.vram_width = 32;
1822 rdev->mc.vram_width = 64;
1824 if (rdev->flags & RADEON_SINGLE_CRTC) {
1825 rdev->mc.vram_width /= 4;
1826 rdev->mc.vram_is_ddr = true;
1828 } else if (rdev->family <= CHIP_RV280) {
1829 tmp = RREG32(RADEON_MEM_CNTL);
1830 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1831 rdev->mc.vram_width = 128;
1833 rdev->mc.vram_width = 64;
1837 rdev->mc.vram_width = 128;
1841 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1846 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1848 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1849 * that is has the 2nd generation multifunction PCI interface
1851 if (rdev->family == CHIP_RV280 ||
1852 rdev->family >= CHIP_RV350) {
1853 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1854 ~RADEON_HDP_APER_CNTL);
1855 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1856 return aper_size * 2;
1859 /* Older cards have all sorts of funny issues to deal with. First
1860 * check if it's a multifunction card by reading the PCI config
1861 * header type... Limit those to one aperture size
1863 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1865 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1866 DRM_INFO("Limiting VRAM to one aperture\n");
1870 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1871 * have set it up. We don't write this as it's broken on some ASICs but
1872 * we expect the BIOS to have done the right thing (might be too optimistic...)
1874 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1875 return aper_size * 2;
1879 void r100_vram_init_sizes(struct radeon_device *rdev)
1881 u64 config_aper_size;
1884 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1886 if (rdev->flags & RADEON_IS_IGP) {
1888 /* read NB_TOM to get the amount of ram stolen for the GPU */
1889 tom = RREG32(RADEON_NB_TOM);
1890 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1891 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1892 rdev->mc.vram_location = (tom & 0xffff) << 16;
1893 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1894 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1896 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1897 /* Some production boards of m6 will report 0
1900 if (rdev->mc.real_vram_size == 0) {
1901 rdev->mc.real_vram_size = 8192 * 1024;
1902 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1904 /* let driver place VRAM */
1905 rdev->mc.vram_location = 0xFFFFFFFFUL;
1906 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1907 * Novell bug 204882 + along with lots of ubuntu ones */
1908 if (config_aper_size > rdev->mc.real_vram_size)
1909 rdev->mc.mc_vram_size = config_aper_size;
1911 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1914 /* work out accessible VRAM */
1915 accessible = r100_get_accessible_vram(rdev);
1917 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1918 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1920 if (accessible > rdev->mc.aper_size)
1921 accessible = rdev->mc.aper_size;
1923 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
1924 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1926 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
1927 rdev->mc.real_vram_size = rdev->mc.aper_size;
1930 void r100_vga_set_state(struct radeon_device *rdev, bool state)
1934 temp = RREG32(RADEON_CONFIG_CNTL);
1935 if (state == false) {
1941 WREG32(RADEON_CONFIG_CNTL, temp);
1944 void r100_vram_info(struct radeon_device *rdev)
1946 r100_vram_get_type(rdev);
1948 r100_vram_init_sizes(rdev);
1953 * Indirect registers accessor
1955 void r100_pll_errata_after_index(struct radeon_device *rdev)
1957 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1960 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1961 (void)RREG32(RADEON_CRTC_GEN_CNTL);
1964 static void r100_pll_errata_after_data(struct radeon_device *rdev)
1966 /* This workarounds is necessary on RV100, RS100 and RS200 chips
1967 * or the chip could hang on a subsequent access
1969 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1973 /* This function is required to workaround a hardware bug in some (all?)
1974 * revisions of the R300. This workaround should be called after every
1975 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
1976 * may not be correct.
1978 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1981 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1982 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1983 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1984 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1985 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1989 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1993 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1994 r100_pll_errata_after_index(rdev);
1995 data = RREG32(RADEON_CLOCK_CNTL_DATA);
1996 r100_pll_errata_after_data(rdev);
2000 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2002 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2003 r100_pll_errata_after_index(rdev);
2004 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2005 r100_pll_errata_after_data(rdev);
2008 void r100_set_safe_registers(struct radeon_device *rdev)
2010 if (ASIC_IS_RN50(rdev)) {
2011 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2012 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2013 } else if (rdev->family < CHIP_R200) {
2014 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2015 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2017 r200_set_safe_registers(rdev);
2024 #if defined(CONFIG_DEBUG_FS)
2025 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2027 struct drm_info_node *node = (struct drm_info_node *) m->private;
2028 struct drm_device *dev = node->minor->dev;
2029 struct radeon_device *rdev = dev->dev_private;
2030 uint32_t reg, value;
2033 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2034 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2035 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2036 for (i = 0; i < 64; i++) {
2037 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2038 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2039 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2040 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2041 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2046 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2048 struct drm_info_node *node = (struct drm_info_node *) m->private;
2049 struct drm_device *dev = node->minor->dev;
2050 struct radeon_device *rdev = dev->dev_private;
2052 unsigned count, i, j;
2054 radeon_ring_free_size(rdev);
2055 rdp = RREG32(RADEON_CP_RB_RPTR);
2056 wdp = RREG32(RADEON_CP_RB_WPTR);
2057 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2058 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2059 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2060 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2061 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2062 seq_printf(m, "%u dwords in ring\n", count);
2063 for (j = 0; j <= count; j++) {
2064 i = (rdp + j) & rdev->cp.ptr_mask;
2065 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2071 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2073 struct drm_info_node *node = (struct drm_info_node *) m->private;
2074 struct drm_device *dev = node->minor->dev;
2075 struct radeon_device *rdev = dev->dev_private;
2076 uint32_t csq_stat, csq2_stat, tmp;
2077 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2080 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2081 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2082 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2083 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2084 r_rptr = (csq_stat >> 0) & 0x3ff;
2085 r_wptr = (csq_stat >> 10) & 0x3ff;
2086 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2087 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2088 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2089 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2090 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2091 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2092 seq_printf(m, "Ring rptr %u\n", r_rptr);
2093 seq_printf(m, "Ring wptr %u\n", r_wptr);
2094 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2095 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2096 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2097 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2098 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2099 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2100 seq_printf(m, "Ring fifo:\n");
2101 for (i = 0; i < 256; i++) {
2102 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2103 tmp = RREG32(RADEON_CP_CSQ_DATA);
2104 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2106 seq_printf(m, "Indirect1 fifo:\n");
2107 for (i = 256; i <= 512; i++) {
2108 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2109 tmp = RREG32(RADEON_CP_CSQ_DATA);
2110 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2112 seq_printf(m, "Indirect2 fifo:\n");
2113 for (i = 640; i < ib1_wptr; i++) {
2114 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2115 tmp = RREG32(RADEON_CP_CSQ_DATA);
2116 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2121 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2123 struct drm_info_node *node = (struct drm_info_node *) m->private;
2124 struct drm_device *dev = node->minor->dev;
2125 struct radeon_device *rdev = dev->dev_private;
2128 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2129 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2130 tmp = RREG32(RADEON_MC_FB_LOCATION);
2131 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2132 tmp = RREG32(RADEON_BUS_CNTL);
2133 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2134 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2135 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2136 tmp = RREG32(RADEON_AGP_BASE);
2137 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2138 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2139 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2140 tmp = RREG32(0x01D0);
2141 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2142 tmp = RREG32(RADEON_AIC_LO_ADDR);
2143 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2144 tmp = RREG32(RADEON_AIC_HI_ADDR);
2145 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2146 tmp = RREG32(0x01E4);
2147 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2151 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2152 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2155 static struct drm_info_list r100_debugfs_cp_list[] = {
2156 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2157 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2160 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2161 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2165 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2167 #if defined(CONFIG_DEBUG_FS)
2168 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2174 int r100_debugfs_cp_init(struct radeon_device *rdev)
2176 #if defined(CONFIG_DEBUG_FS)
2177 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2183 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2185 #if defined(CONFIG_DEBUG_FS)
2186 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2192 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2193 uint32_t tiling_flags, uint32_t pitch,
2194 uint32_t offset, uint32_t obj_size)
2196 int surf_index = reg * 16;
2199 /* r100/r200 divide by 16 */
2200 if (rdev->family < CHIP_R300)
2205 if (rdev->family <= CHIP_RS200) {
2206 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2207 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2208 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2209 if (tiling_flags & RADEON_TILING_MACRO)
2210 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2211 } else if (rdev->family <= CHIP_RV280) {
2212 if (tiling_flags & (RADEON_TILING_MACRO))
2213 flags |= R200_SURF_TILE_COLOR_MACRO;
2214 if (tiling_flags & RADEON_TILING_MICRO)
2215 flags |= R200_SURF_TILE_COLOR_MICRO;
2217 if (tiling_flags & RADEON_TILING_MACRO)
2218 flags |= R300_SURF_TILE_MACRO;
2219 if (tiling_flags & RADEON_TILING_MICRO)
2220 flags |= R300_SURF_TILE_MICRO;
2223 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2224 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2225 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2226 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2228 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2229 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2230 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2231 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2235 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2237 int surf_index = reg * 16;
2238 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2241 void r100_bandwidth_update(struct radeon_device *rdev)
2243 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2244 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2245 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2246 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2247 fixed20_12 memtcas_ff[8] = {
2256 fixed20_12 memtcas_rs480_ff[8] = {
2266 fixed20_12 memtcas2_ff[8] = {
2276 fixed20_12 memtrbs[8] = {
2286 fixed20_12 memtrbs_r4xx[8] = {
2296 fixed20_12 min_mem_eff;
2297 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2298 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2299 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2300 disp_drain_rate2, read_return_rate;
2301 fixed20_12 time_disp1_drop_priority;
2303 int cur_size = 16; /* in octawords */
2304 int critical_point = 0, critical_point2;
2305 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2306 int stop_req, max_stop_req;
2307 struct drm_display_mode *mode1 = NULL;
2308 struct drm_display_mode *mode2 = NULL;
2309 uint32_t pixel_bytes1 = 0;
2310 uint32_t pixel_bytes2 = 0;
2312 if (rdev->mode_info.crtcs[0]->base.enabled) {
2313 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2314 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2316 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2317 if (rdev->mode_info.crtcs[1]->base.enabled) {
2318 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2319 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2323 min_mem_eff.full = rfixed_const_8(0);
2325 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2326 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2327 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2328 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2329 /* check crtc enables */
2331 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2333 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2334 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2338 * determine is there is enough bw for current mode
2340 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2341 temp_ff.full = rfixed_const(100);
2342 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2343 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2344 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2346 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2347 temp_ff.full = rfixed_const(temp);
2348 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2352 peak_disp_bw.full = 0;
2354 temp_ff.full = rfixed_const(1000);
2355 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2356 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2357 temp_ff.full = rfixed_const(pixel_bytes1);
2358 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2361 temp_ff.full = rfixed_const(1000);
2362 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2363 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2364 temp_ff.full = rfixed_const(pixel_bytes2);
2365 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2368 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2369 if (peak_disp_bw.full >= mem_bw.full) {
2370 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2371 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2374 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2375 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2376 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2377 mem_trcd = ((temp >> 2) & 0x3) + 1;
2378 mem_trp = ((temp & 0x3)) + 1;
2379 mem_tras = ((temp & 0x70) >> 4) + 1;
2380 } else if (rdev->family == CHIP_R300 ||
2381 rdev->family == CHIP_R350) { /* r300, r350 */
2382 mem_trcd = (temp & 0x7) + 1;
2383 mem_trp = ((temp >> 8) & 0x7) + 1;
2384 mem_tras = ((temp >> 11) & 0xf) + 4;
2385 } else if (rdev->family == CHIP_RV350 ||
2386 rdev->family <= CHIP_RV380) {
2388 mem_trcd = (temp & 0x7) + 3;
2389 mem_trp = ((temp >> 8) & 0x7) + 3;
2390 mem_tras = ((temp >> 11) & 0xf) + 6;
2391 } else if (rdev->family == CHIP_R420 ||
2392 rdev->family == CHIP_R423 ||
2393 rdev->family == CHIP_RV410) {
2395 mem_trcd = (temp & 0xf) + 3;
2398 mem_trp = ((temp >> 8) & 0xf) + 3;
2401 mem_tras = ((temp >> 12) & 0x1f) + 6;
2404 } else { /* RV200, R200 */
2405 mem_trcd = (temp & 0x7) + 1;
2406 mem_trp = ((temp >> 8) & 0x7) + 1;
2407 mem_tras = ((temp >> 12) & 0xf) + 4;
2410 trcd_ff.full = rfixed_const(mem_trcd);
2411 trp_ff.full = rfixed_const(mem_trp);
2412 tras_ff.full = rfixed_const(mem_tras);
2414 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2415 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2416 data = (temp & (7 << 20)) >> 20;
2417 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2418 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2419 tcas_ff = memtcas_rs480_ff[data];
2421 tcas_ff = memtcas_ff[data];
2423 tcas_ff = memtcas2_ff[data];
2425 if (rdev->family == CHIP_RS400 ||
2426 rdev->family == CHIP_RS480) {
2427 /* extra cas latency stored in bits 23-25 0-4 clocks */
2428 data = (temp >> 23) & 0x7;
2430 tcas_ff.full += rfixed_const(data);
2433 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2434 /* on the R300, Tcas is included in Trbs.
2436 temp = RREG32(RADEON_MEM_CNTL);
2437 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2439 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2440 temp = RREG32(R300_MC_IND_INDEX);
2441 temp &= ~R300_MC_IND_ADDR_MASK;
2442 temp |= R300_MC_READ_CNTL_CD_mcind;
2443 WREG32(R300_MC_IND_INDEX, temp);
2444 temp = RREG32(R300_MC_IND_DATA);
2445 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2447 temp = RREG32(R300_MC_READ_CNTL_AB);
2448 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2451 temp = RREG32(R300_MC_READ_CNTL_AB);
2452 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2454 if (rdev->family == CHIP_RV410 ||
2455 rdev->family == CHIP_R420 ||
2456 rdev->family == CHIP_R423)
2457 trbs_ff = memtrbs_r4xx[data];
2459 trbs_ff = memtrbs[data];
2460 tcas_ff.full += trbs_ff.full;
2463 sclk_eff_ff.full = sclk_ff.full;
2465 if (rdev->flags & RADEON_IS_AGP) {
2466 fixed20_12 agpmode_ff;
2467 agpmode_ff.full = rfixed_const(radeon_agpmode);
2468 temp_ff.full = rfixed_const_666(16);
2469 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2471 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2473 if (ASIC_IS_R300(rdev)) {
2474 sclk_delay_ff.full = rfixed_const(250);
2476 if ((rdev->family == CHIP_RV100) ||
2477 rdev->flags & RADEON_IS_IGP) {
2478 if (rdev->mc.vram_is_ddr)
2479 sclk_delay_ff.full = rfixed_const(41);
2481 sclk_delay_ff.full = rfixed_const(33);
2483 if (rdev->mc.vram_width == 128)
2484 sclk_delay_ff.full = rfixed_const(57);
2486 sclk_delay_ff.full = rfixed_const(41);
2490 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2492 if (rdev->mc.vram_is_ddr) {
2493 if (rdev->mc.vram_width == 32) {
2494 k1.full = rfixed_const(40);
2497 k1.full = rfixed_const(20);
2501 k1.full = rfixed_const(40);
2505 temp_ff.full = rfixed_const(2);
2506 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2507 temp_ff.full = rfixed_const(c);
2508 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2509 temp_ff.full = rfixed_const(4);
2510 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2511 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2512 mc_latency_mclk.full += k1.full;
2514 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2515 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2518 HW cursor time assuming worst case of full size colour cursor.
2520 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2521 temp_ff.full += trcd_ff.full;
2522 if (temp_ff.full < tras_ff.full)
2523 temp_ff.full = tras_ff.full;
2524 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2526 temp_ff.full = rfixed_const(cur_size);
2527 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2529 Find the total latency for the display data.
2531 disp_latency_overhead.full = rfixed_const(8);
2532 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2533 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2534 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2536 if (mc_latency_mclk.full > mc_latency_sclk.full)
2537 disp_latency.full = mc_latency_mclk.full;
2539 disp_latency.full = mc_latency_sclk.full;
2541 /* setup Max GRPH_STOP_REQ default value */
2542 if (ASIC_IS_RV100(rdev))
2543 max_stop_req = 0x5c;
2545 max_stop_req = 0x7c;
2549 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2550 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2552 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2554 if (stop_req > max_stop_req)
2555 stop_req = max_stop_req;
2558 Find the drain rate of the display buffer.
2560 temp_ff.full = rfixed_const((16/pixel_bytes1));
2561 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2564 Find the critical point of the display buffer.
2566 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2567 crit_point_ff.full += rfixed_const_half(0);
2569 critical_point = rfixed_trunc(crit_point_ff);
2571 if (rdev->disp_priority == 2) {
2576 The critical point should never be above max_stop_req-4. Setting
2577 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2579 if (max_stop_req - critical_point < 4)
2582 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2583 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2584 critical_point = 0x10;
2587 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2588 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2589 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2590 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2591 if ((rdev->family == CHIP_R350) &&
2592 (stop_req > 0x15)) {
2595 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2596 temp |= RADEON_GRPH_BUFFER_SIZE;
2597 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2598 RADEON_GRPH_CRITICAL_AT_SOF |
2599 RADEON_GRPH_STOP_CNTL);
2601 Write the result into the register.
2603 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2604 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2607 if ((rdev->family == CHIP_RS400) ||
2608 (rdev->family == CHIP_RS480)) {
2609 /* attempt to program RS400 disp regs correctly ??? */
2610 temp = RREG32(RS400_DISP1_REG_CNTL);
2611 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2612 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2613 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2614 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2615 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2616 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2617 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2618 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2619 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2620 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2621 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2625 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2626 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2627 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2632 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2634 if (stop_req > max_stop_req)
2635 stop_req = max_stop_req;
2638 Find the drain rate of the display buffer.
2640 temp_ff.full = rfixed_const((16/pixel_bytes2));
2641 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2643 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2644 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2645 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2646 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2647 if ((rdev->family == CHIP_R350) &&
2648 (stop_req > 0x15)) {
2651 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2652 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2653 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2654 RADEON_GRPH_CRITICAL_AT_SOF |
2655 RADEON_GRPH_STOP_CNTL);
2657 if ((rdev->family == CHIP_RS100) ||
2658 (rdev->family == CHIP_RS200))
2659 critical_point2 = 0;
2661 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2662 temp_ff.full = rfixed_const(temp);
2663 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2664 if (sclk_ff.full < temp_ff.full)
2665 temp_ff.full = sclk_ff.full;
2667 read_return_rate.full = temp_ff.full;
2670 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2671 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2673 time_disp1_drop_priority.full = 0;
2675 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2676 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2677 crit_point_ff.full += rfixed_const_half(0);
2679 critical_point2 = rfixed_trunc(crit_point_ff);
2681 if (rdev->disp_priority == 2) {
2682 critical_point2 = 0;
2685 if (max_stop_req - critical_point2 < 4)
2686 critical_point2 = 0;
2690 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2691 /* some R300 cards have problem with this set to 0 */
2692 critical_point2 = 0x10;
2695 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2696 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2698 if ((rdev->family == CHIP_RS400) ||
2699 (rdev->family == CHIP_RS480)) {
2701 /* attempt to program RS400 disp2 regs correctly ??? */
2702 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2703 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2704 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2705 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2706 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2707 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2708 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2709 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2710 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2711 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2712 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2713 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2715 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2716 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2717 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2718 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2721 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2722 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2726 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2728 DRM_ERROR("pitch %d\n", t->pitch);
2729 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2730 DRM_ERROR("width %d\n", t->width);
2731 DRM_ERROR("width_11 %d\n", t->width_11);
2732 DRM_ERROR("height %d\n", t->height);
2733 DRM_ERROR("height_11 %d\n", t->height_11);
2734 DRM_ERROR("num levels %d\n", t->num_levels);
2735 DRM_ERROR("depth %d\n", t->txdepth);
2736 DRM_ERROR("bpp %d\n", t->cpp);
2737 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2738 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2739 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2740 DRM_ERROR("compress format %d\n", t->compress_format);
2743 static int r100_cs_track_cube(struct radeon_device *rdev,
2744 struct r100_cs_track *track, unsigned idx)
2746 unsigned face, w, h;
2747 struct radeon_bo *cube_robj;
2750 for (face = 0; face < 5; face++) {
2751 cube_robj = track->textures[idx].cube_info[face].robj;
2752 w = track->textures[idx].cube_info[face].width;
2753 h = track->textures[idx].cube_info[face].height;
2756 size *= track->textures[idx].cpp;
2758 size += track->textures[idx].cube_info[face].offset;
2760 if (size > radeon_bo_size(cube_robj)) {
2761 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2762 size, radeon_bo_size(cube_robj));
2763 r100_cs_track_texture_print(&track->textures[idx]);
2770 static int r100_track_compress_size(int compress_format, int w, int h)
2772 int block_width, block_height, block_bytes;
2773 int wblocks, hblocks;
2780 switch (compress_format) {
2781 case R100_TRACK_COMP_DXT1:
2786 case R100_TRACK_COMP_DXT35:
2792 hblocks = (h + block_height - 1) / block_height;
2793 wblocks = (w + block_width - 1) / block_width;
2794 if (wblocks < min_wblocks)
2795 wblocks = min_wblocks;
2796 sz = wblocks * hblocks * block_bytes;
2800 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2801 struct r100_cs_track *track)
2803 struct radeon_bo *robj;
2805 unsigned u, i, w, h;
2808 for (u = 0; u < track->num_texture; u++) {
2809 if (!track->textures[u].enabled)
2811 robj = track->textures[u].robj;
2813 DRM_ERROR("No texture bound to unit %u\n", u);
2817 for (i = 0; i <= track->textures[u].num_levels; i++) {
2818 if (track->textures[u].use_pitch) {
2819 if (rdev->family < CHIP_R300)
2820 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2822 w = track->textures[u].pitch / (1 << i);
2824 w = track->textures[u].width;
2825 if (rdev->family >= CHIP_RV515)
2826 w |= track->textures[u].width_11;
2828 if (track->textures[u].roundup_w)
2829 w = roundup_pow_of_two(w);
2831 h = track->textures[u].height;
2832 if (rdev->family >= CHIP_RV515)
2833 h |= track->textures[u].height_11;
2835 if (track->textures[u].roundup_h)
2836 h = roundup_pow_of_two(h);
2837 if (track->textures[u].compress_format) {
2839 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2840 /* compressed textures are block based */
2844 size *= track->textures[u].cpp;
2846 switch (track->textures[u].tex_coord_type) {
2850 size *= (1 << track->textures[u].txdepth);
2853 if (track->separate_cube) {
2854 ret = r100_cs_track_cube(rdev, track, u);
2861 DRM_ERROR("Invalid texture coordinate type %u for unit "
2862 "%u\n", track->textures[u].tex_coord_type, u);
2865 if (size > radeon_bo_size(robj)) {
2866 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2867 "%lu\n", u, size, radeon_bo_size(robj));
2868 r100_cs_track_texture_print(&track->textures[u]);
2875 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2882 for (i = 0; i < track->num_cb; i++) {
2883 if (track->cb[i].robj == NULL) {
2884 if (!(track->fastfill || track->color_channel_mask ||
2885 track->blend_read_enable)) {
2888 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2891 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2892 size += track->cb[i].offset;
2893 if (size > radeon_bo_size(track->cb[i].robj)) {
2894 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2895 "(need %lu have %lu) !\n", i, size,
2896 radeon_bo_size(track->cb[i].robj));
2897 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2898 i, track->cb[i].pitch, track->cb[i].cpp,
2899 track->cb[i].offset, track->maxy);
2903 if (track->z_enabled) {
2904 if (track->zb.robj == NULL) {
2905 DRM_ERROR("[drm] No buffer for z buffer !\n");
2908 size = track->zb.pitch * track->zb.cpp * track->maxy;
2909 size += track->zb.offset;
2910 if (size > radeon_bo_size(track->zb.robj)) {
2911 DRM_ERROR("[drm] Buffer too small for z buffer "
2912 "(need %lu have %lu) !\n", size,
2913 radeon_bo_size(track->zb.robj));
2914 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2915 track->zb.pitch, track->zb.cpp,
2916 track->zb.offset, track->maxy);
2920 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2921 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2922 switch (prim_walk) {
2924 for (i = 0; i < track->num_arrays; i++) {
2925 size = track->arrays[i].esize * track->max_indx * 4;
2926 if (track->arrays[i].robj == NULL) {
2927 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2928 "bound\n", prim_walk, i);
2931 if (size > radeon_bo_size(track->arrays[i].robj)) {
2932 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2933 "need %lu dwords have %lu dwords\n",
2934 prim_walk, i, size >> 2,
2935 radeon_bo_size(track->arrays[i].robj)
2937 DRM_ERROR("Max indices %u\n", track->max_indx);
2943 for (i = 0; i < track->num_arrays; i++) {
2944 size = track->arrays[i].esize * (nverts - 1) * 4;
2945 if (track->arrays[i].robj == NULL) {
2946 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2947 "bound\n", prim_walk, i);
2950 if (size > radeon_bo_size(track->arrays[i].robj)) {
2951 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2952 "need %lu dwords have %lu dwords\n",
2953 prim_walk, i, size >> 2,
2954 radeon_bo_size(track->arrays[i].robj)
2961 size = track->vtx_size * nverts;
2962 if (size != track->immd_dwords) {
2963 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2964 track->immd_dwords, size);
2965 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2966 nverts, track->vtx_size);
2971 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2975 return r100_cs_track_texture_check(rdev, track);
2978 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2982 if (rdev->family < CHIP_R300) {
2984 if (rdev->family <= CHIP_RS200)
2985 track->num_texture = 3;
2987 track->num_texture = 6;
2989 track->separate_cube = 1;
2992 track->num_texture = 16;
2994 track->separate_cube = 0;
2997 for (i = 0; i < track->num_cb; i++) {
2998 track->cb[i].robj = NULL;
2999 track->cb[i].pitch = 8192;
3000 track->cb[i].cpp = 16;
3001 track->cb[i].offset = 0;
3003 track->z_enabled = true;
3004 track->zb.robj = NULL;
3005 track->zb.pitch = 8192;
3007 track->zb.offset = 0;
3008 track->vtx_size = 0x7F;
3009 track->immd_dwords = 0xFFFFFFFFUL;
3010 track->num_arrays = 11;
3011 track->max_indx = 0x00FFFFFFUL;
3012 for (i = 0; i < track->num_arrays; i++) {
3013 track->arrays[i].robj = NULL;
3014 track->arrays[i].esize = 0x7F;
3016 for (i = 0; i < track->num_texture; i++) {
3017 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3018 track->textures[i].pitch = 16536;
3019 track->textures[i].width = 16536;
3020 track->textures[i].height = 16536;
3021 track->textures[i].width_11 = 1 << 11;
3022 track->textures[i].height_11 = 1 << 11;
3023 track->textures[i].num_levels = 12;
3024 if (rdev->family <= CHIP_RS200) {
3025 track->textures[i].tex_coord_type = 0;
3026 track->textures[i].txdepth = 0;
3028 track->textures[i].txdepth = 16;
3029 track->textures[i].tex_coord_type = 1;
3031 track->textures[i].cpp = 64;
3032 track->textures[i].robj = NULL;
3033 /* CS IB emission code makes sure texture unit are disabled */
3034 track->textures[i].enabled = false;
3035 track->textures[i].roundup_w = true;
3036 track->textures[i].roundup_h = true;
3037 if (track->separate_cube)
3038 for (face = 0; face < 5; face++) {
3039 track->textures[i].cube_info[face].robj = NULL;
3040 track->textures[i].cube_info[face].width = 16536;
3041 track->textures[i].cube_info[face].height = 16536;
3042 track->textures[i].cube_info[face].offset = 0;
3047 int r100_ring_test(struct radeon_device *rdev)
3054 r = radeon_scratch_get(rdev, &scratch);
3056 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3059 WREG32(scratch, 0xCAFEDEAD);
3060 r = radeon_ring_lock(rdev, 2);
3062 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3063 radeon_scratch_free(rdev, scratch);
3066 radeon_ring_write(rdev, PACKET0(scratch, 0));
3067 radeon_ring_write(rdev, 0xDEADBEEF);
3068 radeon_ring_unlock_commit(rdev);
3069 for (i = 0; i < rdev->usec_timeout; i++) {
3070 tmp = RREG32(scratch);
3071 if (tmp == 0xDEADBEEF) {
3076 if (i < rdev->usec_timeout) {
3077 DRM_INFO("ring test succeeded in %d usecs\n", i);
3079 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3083 radeon_scratch_free(rdev, scratch);
3087 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3089 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3090 radeon_ring_write(rdev, ib->gpu_addr);
3091 radeon_ring_write(rdev, ib->length_dw);
3094 int r100_ib_test(struct radeon_device *rdev)
3096 struct radeon_ib *ib;
3102 r = radeon_scratch_get(rdev, &scratch);
3104 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3107 WREG32(scratch, 0xCAFEDEAD);
3108 r = radeon_ib_get(rdev, &ib);
3112 ib->ptr[0] = PACKET0(scratch, 0);
3113 ib->ptr[1] = 0xDEADBEEF;
3114 ib->ptr[2] = PACKET2(0);
3115 ib->ptr[3] = PACKET2(0);
3116 ib->ptr[4] = PACKET2(0);
3117 ib->ptr[5] = PACKET2(0);
3118 ib->ptr[6] = PACKET2(0);
3119 ib->ptr[7] = PACKET2(0);
3121 r = radeon_ib_schedule(rdev, ib);
3123 radeon_scratch_free(rdev, scratch);
3124 radeon_ib_free(rdev, &ib);
3127 r = radeon_fence_wait(ib->fence, false);
3131 for (i = 0; i < rdev->usec_timeout; i++) {
3132 tmp = RREG32(scratch);
3133 if (tmp == 0xDEADBEEF) {
3138 if (i < rdev->usec_timeout) {
3139 DRM_INFO("ib test succeeded in %u usecs\n", i);
3141 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3145 radeon_scratch_free(rdev, scratch);
3146 radeon_ib_free(rdev, &ib);
3150 void r100_ib_fini(struct radeon_device *rdev)
3152 radeon_ib_pool_fini(rdev);
3155 int r100_ib_init(struct radeon_device *rdev)
3159 r = radeon_ib_pool_init(rdev);
3161 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3165 r = r100_ib_test(rdev);
3167 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3174 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3176 /* Shutdown CP we shouldn't need to do that but better be safe than
3179 rdev->cp.ready = false;
3180 WREG32(R_000740_CP_CSQ_CNTL, 0);
3182 /* Save few CRTC registers */
3183 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3184 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3185 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3186 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3187 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3188 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3189 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3192 /* Disable VGA aperture access */
3193 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3194 /* Disable cursor, overlay, crtc */
3195 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3196 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3197 S_000054_CRTC_DISPLAY_DIS(1));
3198 WREG32(R_000050_CRTC_GEN_CNTL,
3199 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3200 S_000050_CRTC_DISP_REQ_EN_B(1));
3201 WREG32(R_000420_OV0_SCALE_CNTL,
3202 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3203 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3204 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3205 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3206 S_000360_CUR2_LOCK(1));
3207 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3208 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3209 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3210 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3211 WREG32(R_000360_CUR2_OFFSET,
3212 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3216 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3218 /* Update base address for crtc */
3219 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
3220 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3221 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
3222 rdev->mc.vram_location);
3224 /* Restore CRTC registers */
3225 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3226 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3227 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3228 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3229 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3233 void r100_vga_render_disable(struct radeon_device *rdev)
3237 tmp = RREG8(R_0003C2_GENMO_WT);
3238 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3241 static void r100_debugfs(struct radeon_device *rdev)
3245 r = r100_debugfs_mc_info_init(rdev);
3247 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3250 static void r100_mc_program(struct radeon_device *rdev)
3252 struct r100_mc_save save;
3254 /* Stops all mc clients */
3255 r100_mc_stop(rdev, &save);
3256 if (rdev->flags & RADEON_IS_AGP) {
3257 WREG32(R_00014C_MC_AGP_LOCATION,
3258 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3259 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3260 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3261 if (rdev->family > CHIP_RV200)
3262 WREG32(R_00015C_AGP_BASE_2,
3263 upper_32_bits(rdev->mc.agp_base) & 0xff);
3265 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3266 WREG32(R_000170_AGP_BASE, 0);
3267 if (rdev->family > CHIP_RV200)
3268 WREG32(R_00015C_AGP_BASE_2, 0);
3270 /* Wait for mc idle */
3271 if (r100_mc_wait_for_idle(rdev))
3272 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3273 /* Program MC, should be a 32bits limited address space */
3274 WREG32(R_000148_MC_FB_LOCATION,
3275 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3276 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3277 r100_mc_resume(rdev, &save);
3280 void r100_clock_startup(struct radeon_device *rdev)
3284 if (radeon_dynclks != -1 && radeon_dynclks)
3285 radeon_legacy_set_clock_gating(rdev, 1);
3286 /* We need to force on some of the block */
3287 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3288 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3289 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3290 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3291 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3294 static int r100_startup(struct radeon_device *rdev)
3298 /* set common regs */
3299 r100_set_common_regs(rdev);
3301 r100_mc_program(rdev);
3303 r100_clock_startup(rdev);
3304 /* Initialize GPU configuration (# pipes, ...) */
3305 r100_gpu_init(rdev);
3306 /* Initialize GART (initialize after TTM so we can allocate
3307 * memory through TTM but finalize after TTM) */
3308 r100_enable_bm(rdev);
3309 if (rdev->flags & RADEON_IS_PCI) {
3310 r = r100_pci_gart_enable(rdev);
3316 /* 1M ring buffer */
3317 r = r100_cp_init(rdev, 1024 * 1024);
3319 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3322 r = r100_wb_init(rdev);
3324 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3325 r = r100_ib_init(rdev);
3327 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3333 int r100_resume(struct radeon_device *rdev)
3335 /* Make sur GART are not working */
3336 if (rdev->flags & RADEON_IS_PCI)
3337 r100_pci_gart_disable(rdev);
3338 /* Resume clock before doing reset */
3339 r100_clock_startup(rdev);
3340 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3341 if (radeon_gpu_reset(rdev)) {
3342 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3343 RREG32(R_000E40_RBBM_STATUS),
3344 RREG32(R_0007C0_CP_STAT));
3347 radeon_combios_asic_init(rdev->ddev);
3348 /* Resume clock after posting */
3349 r100_clock_startup(rdev);
3350 /* Initialize surface registers */
3351 radeon_surface_init(rdev);
3352 return r100_startup(rdev);
3355 int r100_suspend(struct radeon_device *rdev)
3357 r100_cp_disable(rdev);
3358 r100_wb_disable(rdev);
3359 r100_irq_disable(rdev);
3360 if (rdev->flags & RADEON_IS_PCI)
3361 r100_pci_gart_disable(rdev);
3365 void r100_fini(struct radeon_device *rdev)
3371 radeon_gem_fini(rdev);
3372 if (rdev->flags & RADEON_IS_PCI)
3373 r100_pci_gart_fini(rdev);
3374 radeon_irq_kms_fini(rdev);
3375 radeon_fence_driver_fini(rdev);
3376 radeon_bo_fini(rdev);
3377 radeon_atombios_fini(rdev);
3382 int r100_mc_init(struct radeon_device *rdev)
3387 /* Setup GPU memory space */
3388 rdev->mc.vram_location = 0xFFFFFFFFUL;
3389 rdev->mc.gtt_location = 0xFFFFFFFFUL;
3390 if (rdev->flags & RADEON_IS_IGP) {
3391 tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
3392 rdev->mc.vram_location = tmp << 16;
3394 if (rdev->flags & RADEON_IS_AGP) {
3395 r = radeon_agp_init(rdev);
3397 printk(KERN_WARNING "[drm] Disabling AGP\n");
3398 rdev->flags &= ~RADEON_IS_AGP;
3399 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
3401 rdev->mc.gtt_location = rdev->mc.agp_base;
3404 r = radeon_mc_setup(rdev);
3410 int r100_init(struct radeon_device *rdev)
3414 /* Register debugfs file specific to this group of asics */
3417 r100_vga_render_disable(rdev);
3418 /* Initialize scratch registers */
3419 radeon_scratch_init(rdev);
3420 /* Initialize surface registers */
3421 radeon_surface_init(rdev);
3422 /* TODO: disable VGA need to use VGA request */
3424 if (!radeon_get_bios(rdev)) {
3425 if (ASIC_IS_AVIVO(rdev))
3428 if (rdev->is_atom_bios) {
3429 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3432 r = radeon_combios_init(rdev);
3436 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3437 if (radeon_gpu_reset(rdev)) {
3439 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3440 RREG32(R_000E40_RBBM_STATUS),
3441 RREG32(R_0007C0_CP_STAT));
3443 /* check if cards are posted or not */
3444 if (radeon_boot_test_post_card(rdev) == false)
3446 /* Set asic errata */
3448 /* Initialize clocks */
3449 radeon_get_clock_info(rdev->ddev);
3450 /* Initialize power management */
3451 radeon_pm_init(rdev);
3452 /* Get vram informations */
3453 r100_vram_info(rdev);
3454 /* Initialize memory controller (also test AGP) */
3455 r = r100_mc_init(rdev);
3459 r = radeon_fence_driver_init(rdev);
3462 r = radeon_irq_kms_init(rdev);
3465 /* Memory manager */
3466 r = radeon_bo_init(rdev);
3469 if (rdev->flags & RADEON_IS_PCI) {
3470 r = r100_pci_gart_init(rdev);
3474 r100_set_safe_registers(rdev);
3475 rdev->accel_working = true;
3476 r = r100_startup(rdev);
3478 /* Somethings want wront with the accel init stop accel */
3479 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3484 if (rdev->flags & RADEON_IS_PCI)
3485 r100_pci_gart_fini(rdev);
3486 radeon_irq_kms_fini(rdev);
3487 rdev->accel_working = false;