drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "radeon_drm.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "r100d.h"
  37 #include "rs100d.h"
  38 #include "rv200d.h"
  39 #include "rv250d.h"
  40 #include "atom.h"
  41
  42 #include <linux/firmware.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/module.h>
  45
  46 #include "r100_reg_safe.h"
  47 #include "rn50_reg_safe.h"
  48
  49 /* Firmware Names */
  50 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  51 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  52 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  53 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  54 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  55 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  56 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  57
  58 MODULE_FIRMWARE(FIRMWARE_R100);
  59 MODULE_FIRMWARE(FIRMWARE_R200);
  60 MODULE_FIRMWARE(FIRMWARE_R300);
  61 MODULE_FIRMWARE(FIRMWARE_R420);
  62 MODULE_FIRMWARE(FIRMWARE_RS690);
  63 MODULE_FIRMWARE(FIRMWARE_RS600);
  64 MODULE_FIRMWARE(FIRMWARE_R520);
  65
  66 #include "r100_track.h"
  67
  68 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
  69 {
  70         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
  71         int i;
  72
  73         if (radeon_crtc->crtc_id == 0) {
  74                 if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
  75                         for (i = 0; i < rdev->usec_timeout; i++) {
  76                                 if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
  77                                         break;
  78                                 udelay(1);
  79                         }
  80                         for (i = 0; i < rdev->usec_timeout; i++) {
  81                                 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
  82                                         break;
  83                                 udelay(1);
  84                         }
  85                 }
  86         } else {
  87                 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) {
  88                         for (i = 0; i < rdev->usec_timeout; i++) {
  89                                 if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR))
  90                                         break;
  91                                 udelay(1);
  92                         }
  93                         for (i = 0; i < rdev->usec_timeout; i++) {
  94                                 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
  95                                         break;
  96                                 udelay(1);
  97                         }
  98                 }
  99         }
 100 }
 101
 102 /* This files gather functions specifics to:
 103  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
 104  */
 105
 106 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
 107                             struct radeon_cs_packet *pkt,
 108                             unsigned idx,
 109                             unsigned reg)
 110 {
 111         int r;
 112         u32 tile_flags = 0;
 113         u32 tmp;
 114         struct radeon_cs_reloc *reloc;
 115         u32 value;
 116
 117         r = r100_cs_packet_next_reloc(p, &reloc);
 118         if (r) {
 119                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 120                           idx, reg);
 121                 r100_cs_dump_packet(p, pkt);
 122                 return r;
 123         }
 124
 125         value = radeon_get_ib_value(p, idx);
 126         tmp = value & 0x003fffff;
 127         tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
 128
 129         if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
 130                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 131                         tile_flags |= RADEON_DST_TILE_MACRO;
 132                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
 133                         if (reg == RADEON_SRC_PITCH_OFFSET) {
 134                                 DRM_ERROR("Cannot src blit from microtiled surface\n");
 135                                 r100_cs_dump_packet(p, pkt);
 136                                 return -EINVAL;
 137                         }
 138                         tile_flags |= RADEON_DST_TILE_MICRO;
 139                 }
 140
 141                 tmp |= tile_flags;
 142                 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
 143         } else
 144                 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
 145         return 0;
 146 }
 147
 148 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
 149                              struct radeon_cs_packet *pkt,
 150                              int idx)
 151 {
 152         unsigned c, i;
 153         struct radeon_cs_reloc *reloc;
 154         struct r100_cs_track *track;
 155         int r = 0;
 156         volatile uint32_t *ib;
 157         u32 idx_value;
 158
 159         ib = p->ib.ptr;
 160         track = (struct r100_cs_track *)p->track;
 161         c = radeon_get_ib_value(p, idx++) & 0x1F;
 162         if (c > 16) {
 163             DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
 164                       pkt->opcode);
 165             r100_cs_dump_packet(p, pkt);
 166             return -EINVAL;
 167         }
 168         track->num_arrays = c;
 169         for (i = 0; i < (c - 1); i+=2, idx+=3) {
 170                 r = r100_cs_packet_next_reloc(p, &reloc);
 171                 if (r) {
 172                         DRM_ERROR("No reloc for packet3 %d\n",
 173                                   pkt->opcode);
 174                         r100_cs_dump_packet(p, pkt);
 175                         return r;
 176                 }
 177                 idx_value = radeon_get_ib_value(p, idx);
 178                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
 179
 180                 track->arrays[i + 0].esize = idx_value >> 8;
 181                 track->arrays[i + 0].robj = reloc->robj;
 182                 track->arrays[i + 0].esize &= 0x7F;
 183                 r = r100_cs_packet_next_reloc(p, &reloc);
 184                 if (r) {
 185                         DRM_ERROR("No reloc for packet3 %d\n",
 186                                   pkt->opcode);
 187                         r100_cs_dump_packet(p, pkt);
 188                         return r;
 189                 }
 190                 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
 191                 track->arrays[i + 1].robj = reloc->robj;
 192                 track->arrays[i + 1].esize = idx_value >> 24;
 193                 track->arrays[i + 1].esize &= 0x7F;
 194         }
 195         if (c & 1) {
 196                 r = r100_cs_packet_next_reloc(p, &reloc);
 197                 if (r) {
 198                         DRM_ERROR("No reloc for packet3 %d\n",
 199                                           pkt->opcode);
 200                         r100_cs_dump_packet(p, pkt);
 201                         return r;
 202                 }
 203                 idx_value = radeon_get_ib_value(p, idx);
 204                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
 205                 track->arrays[i + 0].robj = reloc->robj;
 206                 track->arrays[i + 0].esize = idx_value >> 8;
 207                 track->arrays[i + 0].esize &= 0x7F;
 208         }
 209         return r;
 210 }
 211
 212 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
 213 {
 214         /* enable the pflip int */
 215         radeon_irq_kms_pflip_irq_get(rdev, crtc);
 216 }
 217
 218 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
 219 {
 220         /* disable the pflip int */
 221         radeon_irq_kms_pflip_irq_put(rdev, crtc);
 222 }
 223
 224 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 225 {
 226         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 227         u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
 228         int i;
 229
 230         /* Lock the graphics update lock */
 231         /* update the scanout addresses */
 232         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 233
 234         /* Wait for update_pending to go high. */
 235         for (i = 0; i < rdev->usec_timeout; i++) {
 236                 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
 237                         break;
 238                 udelay(1);
 239         }
 240         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 241
 242         /* Unlock the lock, so double-buffering can take place inside vblank */
 243         tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
 244         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 245
 246         /* Return current update_pending status: */
 247         return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
 248 }
 249
 250 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
 251 {
 252         int i;
 253         rdev->pm.dynpm_can_upclock = true;
 254         rdev->pm.dynpm_can_downclock = true;
 255
 256         switch (rdev->pm.dynpm_planned_action) {
 257         case DYNPM_ACTION_MINIMUM:
 258                 rdev->pm.requested_power_state_index = 0;
 259                 rdev->pm.dynpm_can_downclock = false;
 260                 break;
 261         case DYNPM_ACTION_DOWNCLOCK:
 262                 if (rdev->pm.current_power_state_index == 0) {
 263                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 264                         rdev->pm.dynpm_can_downclock = false;
 265                 } else {
 266                         if (rdev->pm.active_crtc_count > 1) {
 267                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 268                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 269                                                 continue;
 270                                         else if (i >= rdev->pm.current_power_state_index) {
 271                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 272                                                 break;
 273                                         } else {
 274                                                 rdev->pm.requested_power_state_index = i;
 275                                                 break;
 276                                         }
 277                                 }
 278                         } else
 279                                 rdev->pm.requested_power_state_index =
 280                                         rdev->pm.current_power_state_index - 1;
 281                 }
 282                 /* don't use the power state if crtcs are active and no display flag is set */
 283                 if ((rdev->pm.active_crtc_count > 0) &&
 284                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
 285                      RADEON_PM_MODE_NO_DISPLAY)) {
 286                         rdev->pm.requested_power_state_index++;
 287                 }
 288                 break;
 289         case DYNPM_ACTION_UPCLOCK:
 290                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 291                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 292                         rdev->pm.dynpm_can_upclock = false;
 293                 } else {
 294                         if (rdev->pm.active_crtc_count > 1) {
 295                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 296                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 297                                                 continue;
 298                                         else if (i <= rdev->pm.current_power_state_index) {
 299                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 300                                                 break;
 301                                         } else {
 302                                                 rdev->pm.requested_power_state_index = i;
 303                                                 break;
 304                                         }
 305                                 }
 306                         } else
 307                                 rdev->pm.requested_power_state_index =
 308                                         rdev->pm.current_power_state_index + 1;
 309                 }
 310                 break;
 311         case DYNPM_ACTION_DEFAULT:
 312                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 313                 rdev->pm.dynpm_can_upclock = false;
 314                 break;
 315         case DYNPM_ACTION_NONE:
 316         default:
 317                 DRM_ERROR("Requested mode for not defined action\n");
 318                 return;
 319         }
 320         /* only one clock mode per power state */
 321         rdev->pm.requested_clock_mode_index = 0;
 322
 323         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 324                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 325                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 326                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 327                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 328                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 329                   pcie_lanes);
 330 }
 331
 332 void r100_pm_init_profile(struct radeon_device *rdev)
 333 {
 334         /* default */
 335         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 336         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 337         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 338         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 339         /* low sh */
 340         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 341         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 342         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 343         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 344         /* mid sh */
 345         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 346         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 347         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 348         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 349         /* high sh */
 350         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 351         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 352         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 353         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 354         /* low mh */
 355         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 356         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 357         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 358         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 359         /* mid mh */
 360         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 361         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 362         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 363         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 364         /* high mh */
 365         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 366         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 367         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 368         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 369 }
 370
 371 void r100_pm_misc(struct radeon_device *rdev)
 372 {
 373         int requested_index = rdev->pm.requested_power_state_index;
 374         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 375         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 376         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 377
 378         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 379                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 380                         tmp = RREG32(voltage->gpio.reg);
 381                         if (voltage->active_high)
 382                                 tmp |= voltage->gpio.mask;
 383                         else
 384                                 tmp &= ~(voltage->gpio.mask);
 385                         WREG32(voltage->gpio.reg, tmp);
 386                         if (voltage->delay)
 387                                 udelay(voltage->delay);
 388                 } else {
 389                         tmp = RREG32(voltage->gpio.reg);
 390                         if (voltage->active_high)
 391                                 tmp &= ~voltage->gpio.mask;
 392                         else
 393                                 tmp |= voltage->gpio.mask;
 394                         WREG32(voltage->gpio.reg, tmp);
 395                         if (voltage->delay)
 396                                 udelay(voltage->delay);
 397                 }
 398         }
 399
 400         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 401         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 402         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 403         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 404         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 405         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 406                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 407                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 408                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 409                 else
 410                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 411                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 412                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 413                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 414                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 415         } else
 416                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 417
 418         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 419                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 420                 if (voltage->delay) {
 421                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 422                         switch (voltage->delay) {
 423                         case 33:
 424                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 425                                 break;
 426                         case 66:
 427                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 428                                 break;
 429                         case 99:
 430                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 431                                 break;
 432                         case 132:
 433                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 434                                 break;
 435                         }
 436                 } else
 437                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 438         } else
 439                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 440
 441         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 442                 sclk_cntl &= ~FORCE_HDP;
 443         else
 444                 sclk_cntl |= FORCE_HDP;
 445
 446         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 447         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 448         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 449
 450         /* set pcie lanes */
 451         if ((rdev->flags & RADEON_IS_PCIE) &&
 452             !(rdev->flags & RADEON_IS_IGP) &&
 453             rdev->asic->pm.set_pcie_lanes &&
 454             (ps->pcie_lanes !=
 455              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 456                 radeon_set_pcie_lanes(rdev,
 457                                       ps->pcie_lanes);
 458                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
 459         }
 460 }
 461
 462 void r100_pm_prepare(struct radeon_device *rdev)
 463 {
 464         struct drm_device *ddev = rdev->ddev;
 465         struct drm_crtc *crtc;
 466         struct radeon_crtc *radeon_crtc;
 467         u32 tmp;
 468
 469         /* disable any active CRTCs */
 470         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 471                 radeon_crtc = to_radeon_crtc(crtc);
 472                 if (radeon_crtc->enabled) {
 473                         if (radeon_crtc->crtc_id) {
 474                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 475                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 476                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 477                         } else {
 478                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 479                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 480                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 481                         }
 482                 }
 483         }
 484 }
 485
 486 void r100_pm_finish(struct radeon_device *rdev)
 487 {
 488         struct drm_device *ddev = rdev->ddev;
 489         struct drm_crtc *crtc;
 490         struct radeon_crtc *radeon_crtc;
 491         u32 tmp;
 492
 493         /* enable any active CRTCs */
 494         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 495                 radeon_crtc = to_radeon_crtc(crtc);
 496                 if (radeon_crtc->enabled) {
 497                         if (radeon_crtc->crtc_id) {
 498                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 499                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 500                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 501                         } else {
 502                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 503                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 504                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 505                         }
 506                 }
 507         }
 508 }
 509
 510 bool r100_gui_idle(struct radeon_device *rdev)
 511 {
 512         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 513                 return false;
 514         else
 515                 return true;
 516 }
 517
 518 /* hpd for digital panel detect/disconnect */
 519 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 520 {
 521         bool connected = false;
 522
 523         switch (hpd) {
 524         case RADEON_HPD_1:
 525                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 526                         connected = true;
 527                 break;
 528         case RADEON_HPD_2:
 529                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 530                         connected = true;
 531                 break;
 532         default:
 533                 break;
 534         }
 535         return connected;
 536 }
 537
 538 void r100_hpd_set_polarity(struct radeon_device *rdev,
 539                            enum radeon_hpd_id hpd)
 540 {
 541         u32 tmp;
 542         bool connected = r100_hpd_sense(rdev, hpd);
 543
 544         switch (hpd) {
 545         case RADEON_HPD_1:
 546                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 547                 if (connected)
 548                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 549                 else
 550                         tmp |= RADEON_FP_DETECT_INT_POL;
 551                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 552                 break;
 553         case RADEON_HPD_2:
 554                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 555                 if (connected)
 556                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 557                 else
 558                         tmp |= RADEON_FP2_DETECT_INT_POL;
 559                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 560                 break;
 561         default:
 562                 break;
 563         }
 564 }
 565
 566 void r100_hpd_init(struct radeon_device *rdev)
 567 {
 568         struct drm_device *dev = rdev->ddev;
 569         struct drm_connector *connector;
 570         unsigned enable = 0;
 571
 572         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 573                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 574                 enable |= 1 << radeon_connector->hpd.hpd;
 575                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 576         }
 577         radeon_irq_kms_enable_hpd(rdev, enable);
 578 }
 579
 580 void r100_hpd_fini(struct radeon_device *rdev)
 581 {
 582         struct drm_device *dev = rdev->ddev;
 583         struct drm_connector *connector;
 584         unsigned disable = 0;
 585
 586         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 587                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 588                 disable |= 1 << radeon_connector->hpd.hpd;
 589         }
 590         radeon_irq_kms_disable_hpd(rdev, disable);
 591 }
 592
 593 /*
 594  * PCI GART
 595  */
 596 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 597 {
 598         /* TODO: can we do somethings here ? */
 599         /* It seems hw only cache one entry so we should discard this
 600          * entry otherwise if first GPU GART read hit this entry it
 601          * could end up in wrong address. */
 602 }
 603
 604 int r100_pci_gart_init(struct radeon_device *rdev)
 605 {
 606         int r;
 607
 608         if (rdev->gart.ptr) {
 609                 WARN(1, "R100 PCI GART already initialized\n");
 610                 return 0;
 611         }
 612         /* Initialize common gart structure */
 613         r = radeon_gart_init(rdev);
 614         if (r)
 615                 return r;
 616         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 617         rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 618         rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 619         return radeon_gart_table_ram_alloc(rdev);
 620 }
 621
 622 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 623 void r100_enable_bm(struct radeon_device *rdev)
 624 {
 625         uint32_t tmp;
 626         /* Enable bus mastering */
 627         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 628         WREG32(RADEON_BUS_CNTL, tmp);
 629 }
 630
 631 int r100_pci_gart_enable(struct radeon_device *rdev)
 632 {
 633         uint32_t tmp;
 634
 635         radeon_gart_restore(rdev);
 636         /* discard memory request outside of configured range */
 637         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 638         WREG32(RADEON_AIC_CNTL, tmp);
 639         /* set address range for PCI address translate */
 640         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 641         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 642         /* set PCI GART page-table base address */
 643         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 644         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 645         WREG32(RADEON_AIC_CNTL, tmp);
 646         r100_pci_gart_tlb_flush(rdev);
 647         DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
 648                  (unsigned)(rdev->mc.gtt_size >> 20),
 649                  (unsigned long long)rdev->gart.table_addr);
 650         rdev->gart.ready = true;
 651         return 0;
 652 }
 653
 654 void r100_pci_gart_disable(struct radeon_device *rdev)
 655 {
 656         uint32_t tmp;
 657
 658         /* discard memory request outside of configured range */
 659         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 660         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 661         WREG32(RADEON_AIC_LO_ADDR, 0);
 662         WREG32(RADEON_AIC_HI_ADDR, 0);
 663 }
 664
 665 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 666 {
 667         u32 *gtt = rdev->gart.ptr;
 668
 669         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 670                 return -EINVAL;
 671         }
 672         gtt[i] = cpu_to_le32(lower_32_bits(addr));
 673         return 0;
 674 }
 675
 676 void r100_pci_gart_fini(struct radeon_device *rdev)
 677 {
 678         radeon_gart_fini(rdev);
 679         r100_pci_gart_disable(rdev);
 680         radeon_gart_table_ram_free(rdev);
 681 }
 682
 683 int r100_irq_set(struct radeon_device *rdev)
 684 {
 685         uint32_t tmp = 0;
 686
 687         if (!rdev->irq.installed) {
 688                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 689                 WREG32(R_000040_GEN_INT_CNTL, 0);
 690                 return -EINVAL;
 691         }
 692         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
 693                 tmp |= RADEON_SW_INT_ENABLE;
 694         }
 695         if (rdev->irq.gui_idle) {
 696                 tmp |= RADEON_GUI_IDLE_MASK;
 697         }
 698         if (rdev->irq.crtc_vblank_int[0] ||
 699             atomic_read(&rdev->irq.pflip[0])) {
 700                 tmp |= RADEON_CRTC_VBLANK_MASK;
 701         }
 702         if (rdev->irq.crtc_vblank_int[1] ||
 703             atomic_read(&rdev->irq.pflip[1])) {
 704                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 705         }
 706         if (rdev->irq.hpd[0]) {
 707                 tmp |= RADEON_FP_DETECT_MASK;
 708         }
 709         if (rdev->irq.hpd[1]) {
 710                 tmp |= RADEON_FP2_DETECT_MASK;
 711         }
 712         WREG32(RADEON_GEN_INT_CNTL, tmp);
 713         return 0;
 714 }
 715
 716 void r100_irq_disable(struct radeon_device *rdev)
 717 {
 718         u32 tmp;
 719
 720         WREG32(R_000040_GEN_INT_CNTL, 0);
 721         /* Wait and acknowledge irq */
 722         mdelay(1);
 723         tmp = RREG32(R_000044_GEN_INT_STATUS);
 724         WREG32(R_000044_GEN_INT_STATUS, tmp);
 725 }
 726
 727 static uint32_t r100_irq_ack(struct radeon_device *rdev)
 728 {
 729         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 730         uint32_t irq_mask = RADEON_SW_INT_TEST |
 731                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 732                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 733
 734         /* the interrupt works, but the status bit is permanently asserted */
 735         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
 736                 if (!rdev->irq.gui_idle_acked)
 737                         irq_mask |= RADEON_GUI_IDLE_STAT;
 738         }
 739
 740         if (irqs) {
 741                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 742         }
 743         return irqs & irq_mask;
 744 }
 745
 746 int r100_irq_process(struct radeon_device *rdev)
 747 {
 748         uint32_t status, msi_rearm;
 749         bool queue_hotplug = false;
 750
 751         /* reset gui idle ack.  the status bit is broken */
 752         rdev->irq.gui_idle_acked = false;
 753
 754         status = r100_irq_ack(rdev);
 755         if (!status) {
 756                 return IRQ_NONE;
 757         }
 758         if (rdev->shutdown) {
 759                 return IRQ_NONE;
 760         }
 761         while (status) {
 762                 /* SW interrupt */
 763                 if (status & RADEON_SW_INT_TEST) {
 764                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
 765                 }
 766                 /* gui idle interrupt */
 767                 if (status & RADEON_GUI_IDLE_STAT) {
 768                         rdev->irq.gui_idle_acked = true;
 769                         wake_up(&rdev->irq.idle_queue);
 770                 }
 771                 /* Vertical blank interrupts */
 772                 if (status & RADEON_CRTC_VBLANK_STAT) {
 773                         if (rdev->irq.crtc_vblank_int[0]) {
 774                                 drm_handle_vblank(rdev->ddev, 0);
 775                                 rdev->pm.vblank_sync = true;
 776                                 wake_up(&rdev->irq.vblank_queue);
 777                         }
 778                         if (atomic_read(&rdev->irq.pflip[0]))
 779                                 radeon_crtc_handle_flip(rdev, 0);
 780                 }
 781                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 782                         if (rdev->irq.crtc_vblank_int[1]) {
 783                                 drm_handle_vblank(rdev->ddev, 1);
 784                                 rdev->pm.vblank_sync = true;
 785                                 wake_up(&rdev->irq.vblank_queue);
 786                         }
 787                         if (atomic_read(&rdev->irq.pflip[1]))
 788                                 radeon_crtc_handle_flip(rdev, 1);
 789                 }
 790                 if (status & RADEON_FP_DETECT_STAT) {
 791                         queue_hotplug = true;
 792                         DRM_DEBUG("HPD1\n");
 793                 }
 794                 if (status & RADEON_FP2_DETECT_STAT) {
 795                         queue_hotplug = true;
 796                         DRM_DEBUG("HPD2\n");
 797                 }
 798                 status = r100_irq_ack(rdev);
 799         }
 800         /* reset gui idle ack.  the status bit is broken */
 801         rdev->irq.gui_idle_acked = false;
 802         if (queue_hotplug)
 803                 schedule_work(&rdev->hotplug_work);
 804         if (rdev->msi_enabled) {
 805                 switch (rdev->family) {
 806                 case CHIP_RS400:
 807                 case CHIP_RS480:
 808                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 809                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 810                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 811                         break;
 812                 default:
 813                         WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
 814                         break;
 815                 }
 816         }
 817         return IRQ_HANDLED;
 818 }
 819
 820 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 821 {
 822         if (crtc == 0)
 823                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 824         else
 825                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 826 }
 827
 828 /* Who ever call radeon_fence_emit should call ring_lock and ask
 829  * for enough space (today caller are ib schedule and buffer move) */
 830 void r100_fence_ring_emit(struct radeon_device *rdev,
 831                           struct radeon_fence *fence)
 832 {
 833         struct radeon_ring *ring = &rdev->ring[fence->ring];
 834
 835         /* We have to make sure that caches are flushed before
 836          * CPU might read something from VRAM. */
 837         radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 838         radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
 839         radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 840         radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
 841         /* Wait until IDLE & CLEAN */
 842         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 843         radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 844         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 845         radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
 846                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 847         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 848         radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
 849         /* Emit fence sequence & fire IRQ */
 850         radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
 851         radeon_ring_write(ring, fence->seq);
 852         radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
 853         radeon_ring_write(ring, RADEON_SW_INT_FIRE);
 854 }
 855
 856 void r100_semaphore_ring_emit(struct radeon_device *rdev,
 857                               struct radeon_ring *ring,
 858                               struct radeon_semaphore *semaphore,
 859                               bool emit_wait)
 860 {
 861         /* Unused on older asics, since we don't have semaphores or multiple rings */
 862         BUG();
 863 }
 864
 865 int r100_copy_blit(struct radeon_device *rdev,
 866                    uint64_t src_offset,
 867                    uint64_t dst_offset,
 868                    unsigned num_gpu_pages,
 869                    struct radeon_fence **fence)
 870 {
 871         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 872         uint32_t cur_pages;
 873         uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
 874         uint32_t pitch;
 875         uint32_t stride_pixels;
 876         unsigned ndw;
 877         int num_loops;
 878         int r = 0;
 879
 880         /* radeon limited to 16k stride */
 881         stride_bytes &= 0x3fff;
 882         /* radeon pitch is /64 */
 883         pitch = stride_bytes / 64;
 884         stride_pixels = stride_bytes / 4;
 885         num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
 886
 887         /* Ask for enough room for blit + flush + fence */
 888         ndw = 64 + (10 * num_loops);
 889         r = radeon_ring_lock(rdev, ring, ndw);
 890         if (r) {
 891                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 892                 return -EINVAL;
 893         }
 894         while (num_gpu_pages > 0) {
 895                 cur_pages = num_gpu_pages;
 896                 if (cur_pages > 8191) {
 897                         cur_pages = 8191;
 898                 }
 899                 num_gpu_pages -= cur_pages;
 900
 901                 /* pages are in Y direction - height
 902                    page width in X direction - width */
 903                 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
 904                 radeon_ring_write(ring,
 905                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 906                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 907                                   RADEON_GMC_SRC_CLIPPING |
 908                                   RADEON_GMC_DST_CLIPPING |
 909                                   RADEON_GMC_BRUSH_NONE |
 910                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 911                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 912                                   RADEON_ROP3_S |
 913                                   RADEON_DP_SRC_SOURCE_MEMORY |
 914                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 915                                   RADEON_GMC_WR_MSK_DIS);
 916                 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
 917                 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
 918                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 919                 radeon_ring_write(ring, 0);
 920                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 921                 radeon_ring_write(ring, num_gpu_pages);
 922                 radeon_ring_write(ring, num_gpu_pages);
 923                 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
 924         }
 925         radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 926         radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
 927         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 928         radeon_ring_write(ring,
 929                           RADEON_WAIT_2D_IDLECLEAN |
 930                           RADEON_WAIT_HOST_IDLECLEAN |
 931                           RADEON_WAIT_DMA_GUI_IDLE);
 932         if (fence) {
 933                 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
 934         }
 935         radeon_ring_unlock_commit(rdev, ring);
 936         return r;
 937 }
 938
 939 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 940 {
 941         unsigned i;
 942         u32 tmp;
 943
 944         for (i = 0; i < rdev->usec_timeout; i++) {
 945                 tmp = RREG32(R_000E40_RBBM_STATUS);
 946                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 947                         return 0;
 948                 }
 949                 udelay(1);
 950         }
 951         return -1;
 952 }
 953
 954 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
 955 {
 956         int r;
 957
 958         r = radeon_ring_lock(rdev, ring, 2);
 959         if (r) {
 960                 return;
 961         }
 962         radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
 963         radeon_ring_write(ring,
 964                           RADEON_ISYNC_ANY2D_IDLE3D |
 965                           RADEON_ISYNC_ANY3D_IDLE2D |
 966                           RADEON_ISYNC_WAIT_IDLEGUI |
 967                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 968         radeon_ring_unlock_commit(rdev, ring);
 969 }
 970
 971
 972 /* Load the microcode for the CP */
 973 static int r100_cp_init_microcode(struct radeon_device *rdev)
 974 {
 975         struct platform_device *pdev;
 976         const char *fw_name = NULL;
 977         int err;
 978
 979         DRM_DEBUG_KMS("\n");
 980
 981         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 982         err = IS_ERR(pdev);
 983         if (err) {
 984                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 985                 return -EINVAL;
 986         }
 987         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 988             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 989             (rdev->family == CHIP_RS200)) {
 990                 DRM_INFO("Loading R100 Microcode\n");
 991                 fw_name = FIRMWARE_R100;
 992         } else if ((rdev->family == CHIP_R200) ||
 993                    (rdev->family == CHIP_RV250) ||
 994                    (rdev->family == CHIP_RV280) ||
 995                    (rdev->family == CHIP_RS300)) {
 996                 DRM_INFO("Loading R200 Microcode\n");
 997                 fw_name = FIRMWARE_R200;
 998         } else if ((rdev->family == CHIP_R300) ||
 999                    (rdev->family == CHIP_R350) ||
1000                    (rdev->family == CHIP_RV350) ||
1001                    (rdev->family == CHIP_RV380) ||
1002                    (rdev->family == CHIP_RS400) ||
1003                    (rdev->family == CHIP_RS480)) {
1004                 DRM_INFO("Loading R300 Microcode\n");
1005                 fw_name = FIRMWARE_R300;
1006         } else if ((rdev->family == CHIP_R420) ||
1007                    (rdev->family == CHIP_R423) ||
1008                    (rdev->family == CHIP_RV410)) {
1009                 DRM_INFO("Loading R400 Microcode\n");
1010                 fw_name = FIRMWARE_R420;
1011         } else if ((rdev->family == CHIP_RS690) ||
1012                    (rdev->family == CHIP_RS740)) {
1013                 DRM_INFO("Loading RS690/RS740 Microcode\n");
1014                 fw_name = FIRMWARE_RS690;
1015         } else if (rdev->family == CHIP_RS600) {
1016                 DRM_INFO("Loading RS600 Microcode\n");
1017                 fw_name = FIRMWARE_RS600;
1018         } else if ((rdev->family == CHIP_RV515) ||
1019                    (rdev->family == CHIP_R520) ||
1020                    (rdev->family == CHIP_RV530) ||
1021                    (rdev->family == CHIP_R580) ||
1022                    (rdev->family == CHIP_RV560) ||
1023                    (rdev->family == CHIP_RV570)) {
1024                 DRM_INFO("Loading R500 Microcode\n");
1025                 fw_name = FIRMWARE_R520;
1026         }
1027
1028         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1029         platform_device_unregister(pdev);
1030         if (err) {
1031                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1032                        fw_name);
1033         } else if (rdev->me_fw->size % 8) {
1034                 printk(KERN_ERR
1035                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1036                        rdev->me_fw->size, fw_name);
1037                 err = -EINVAL;
1038                 release_firmware(rdev->me_fw);
1039                 rdev->me_fw = NULL;
1040         }
1041         return err;
1042 }
1043
1044 static void r100_cp_load_microcode(struct radeon_device *rdev)
1045 {
1046         const __be32 *fw_data;
1047         int i, size;
1048
1049         if (r100_gui_wait_for_idle(rdev)) {
1050                 printk(KERN_WARNING "Failed to wait GUI idle while "
1051                        "programming pipes. Bad things might happen.\n");
1052         }
1053
1054         if (rdev->me_fw) {
1055                 size = rdev->me_fw->size / 4;
1056                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1057                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1058                 for (i = 0; i < size; i += 2) {
1059                         WREG32(RADEON_CP_ME_RAM_DATAH,
1060                                be32_to_cpup(&fw_data[i]));
1061                         WREG32(RADEON_CP_ME_RAM_DATAL,
1062                                be32_to_cpup(&fw_data[i + 1]));
1063                 }
1064         }
1065 }
1066
1067 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1068 {
1069         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1070         unsigned rb_bufsz;
1071         unsigned rb_blksz;
1072         unsigned max_fetch;
1073         unsigned pre_write_timer;
1074         unsigned pre_write_limit;
1075         unsigned indirect2_start;
1076         unsigned indirect1_start;
1077         uint32_t tmp;
1078         int r;
1079
1080         if (r100_debugfs_cp_init(rdev)) {
1081                 DRM_ERROR("Failed to register debugfs file for CP !\n");
1082         }
1083         if (!rdev->me_fw) {
1084                 r = r100_cp_init_microcode(rdev);
1085                 if (r) {
1086                         DRM_ERROR("Failed to load firmware!\n");
1087                         return r;
1088                 }
1089         }
1090
1091         /* Align ring size */
1092         rb_bufsz = drm_order(ring_size / 8);
1093         ring_size = (1 << (rb_bufsz + 1)) * 4;
1094         r100_cp_load_microcode(rdev);
1095         r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1096                              RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
1097                              0, 0x7fffff, RADEON_CP_PACKET2);
1098         if (r) {
1099                 return r;
1100         }
1101         /* Each time the cp read 1024 bytes (16 dword/quadword) update
1102          * the rptr copy in system ram */
1103         rb_blksz = 9;
1104         /* cp will read 128bytes at a time (4 dwords) */
1105         max_fetch = 1;
1106         ring->align_mask = 16 - 1;
1107         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1108         pre_write_timer = 64;
1109         /* Force CP_RB_WPTR write if written more than one time before the
1110          * delay expire
1111          */
1112         pre_write_limit = 0;
1113         /* Setup the cp cache like this (cache size is 96 dwords) :
1114          *      RING            0  to 15
1115          *      INDIRECT1       16 to 79
1116          *      INDIRECT2       80 to 95
1117          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1118          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1119          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1120          * Idea being that most of the gpu cmd will be through indirect1 buffer
1121          * so it gets the bigger cache.
1122          */
1123         indirect2_start = 80;
1124         indirect1_start = 16;
1125         /* cp setup */
1126         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1127         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1128                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1129                REG_SET(RADEON_MAX_FETCH, max_fetch));
1130 #ifdef __BIG_ENDIAN
1131         tmp |= RADEON_BUF_SWAP_32BIT;
1132 #endif
1133         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1134
1135         /* Set ring address */
1136         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1137         WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1138         /* Force read & write ptr to 0 */
1139         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1140         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1141         ring->wptr = 0;
1142         WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1143
1144         /* set the wb address whether it's enabled or not */
1145         WREG32(R_00070C_CP_RB_RPTR_ADDR,
1146                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1147         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1148
1149         if (rdev->wb.enabled)
1150                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1151         else {
1152                 tmp |= RADEON_RB_NO_UPDATE;
1153                 WREG32(R_000770_SCRATCH_UMSK, 0);
1154         }
1155
1156         WREG32(RADEON_CP_RB_CNTL, tmp);
1157         udelay(10);
1158         ring->rptr = RREG32(RADEON_CP_RB_RPTR);
1159         /* Set cp mode to bus mastering & enable cp*/
1160         WREG32(RADEON_CP_CSQ_MODE,
1161                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1162                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1163         WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1164         WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1165         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1166
1167         /* at this point everything should be setup correctly to enable master */
1168         pci_set_master(rdev->pdev);
1169
1170         radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1171         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1172         if (r) {
1173                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1174                 return r;
1175         }
1176         ring->ready = true;
1177         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1178         return 0;
1179 }
1180
1181 void r100_cp_fini(struct radeon_device *rdev)
1182 {
1183         if (r100_cp_wait_for_idle(rdev)) {
1184                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1185         }
1186         /* Disable ring */
1187         r100_cp_disable(rdev);
1188         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1189         DRM_INFO("radeon: cp finalized\n");
1190 }
1191
1192 void r100_cp_disable(struct radeon_device *rdev)
1193 {
1194         /* Disable ring */
1195         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1196         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1197         WREG32(RADEON_CP_CSQ_MODE, 0);
1198         WREG32(RADEON_CP_CSQ_CNTL, 0);
1199         WREG32(R_000770_SCRATCH_UMSK, 0);
1200         if (r100_gui_wait_for_idle(rdev)) {
1201                 printk(KERN_WARNING "Failed to wait GUI idle while "
1202                        "programming pipes. Bad things might happen.\n");
1203         }
1204 }
1205
1206 /*
1207  * CS functions
1208  */
1209 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1210                           struct radeon_cs_packet *pkt,
1211                           const unsigned *auth, unsigned n,
1212                           radeon_packet0_check_t check)
1213 {
1214         unsigned reg;
1215         unsigned i, j, m;
1216         unsigned idx;
1217         int r;
1218
1219         idx = pkt->idx + 1;
1220         reg = pkt->reg;
1221         /* Check that register fall into register range
1222          * determined by the number of entry (n) in the
1223          * safe register bitmap.
1224          */
1225         if (pkt->one_reg_wr) {
1226                 if ((reg >> 7) > n) {
1227                         return -EINVAL;
1228                 }
1229         } else {
1230                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1231                         return -EINVAL;
1232                 }
1233         }
1234         for (i = 0; i <= pkt->count; i++, idx++) {
1235                 j = (reg >> 7);
1236                 m = 1 << ((reg >> 2) & 31);
1237                 if (auth[j] & m) {
1238                         r = check(p, pkt, idx, reg);
1239                         if (r) {
1240                                 return r;
1241                         }
1242                 }
1243                 if (pkt->one_reg_wr) {
1244                         if (!(auth[j] & m)) {
1245                                 break;
1246                         }
1247                 } else {
1248                         reg += 4;
1249                 }
1250         }
1251         return 0;
1252 }
1253
1254 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1255                          struct radeon_cs_packet *pkt)
1256 {
1257         volatile uint32_t *ib;
1258         unsigned i;
1259         unsigned idx;
1260
1261         ib = p->ib.ptr;
1262         idx = pkt->idx;
1263         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1264                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1265         }
1266 }
1267
1268 /**
1269  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1270  * @parser:     parser structure holding parsing context.
1271  * @pkt:        where to store packet informations
1272  *
1273  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1274  * if packet is bigger than remaining ib size. or if packets is unknown.
1275  **/
1276 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1277                          struct radeon_cs_packet *pkt,
1278                          unsigned idx)
1279 {
1280         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1281         uint32_t header;
1282
1283         if (idx >= ib_chunk->length_dw) {
1284                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1285                           idx, ib_chunk->length_dw);
1286                 return -EINVAL;
1287         }
1288         header = radeon_get_ib_value(p, idx);
1289         pkt->idx = idx;
1290         pkt->type = CP_PACKET_GET_TYPE(header);
1291         pkt->count = CP_PACKET_GET_COUNT(header);
1292         switch (pkt->type) {
1293         case PACKET_TYPE0:
1294                 pkt->reg = CP_PACKET0_GET_REG(header);
1295                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1296                 break;
1297         case PACKET_TYPE3:
1298                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1299                 break;
1300         case PACKET_TYPE2:
1301                 pkt->count = -1;
1302                 break;
1303         default:
1304                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1305                 return -EINVAL;
1306         }
1307         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1308                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1309                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1310                 return -EINVAL;
1311         }
1312         return 0;
1313 }
1314
1315 /**
1316  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1317  * @parser:             parser structure holding parsing context.
1318  *
1319  * Userspace sends a special sequence for VLINE waits.
1320  * PACKET0 - VLINE_START_END + value
1321  * PACKET0 - WAIT_UNTIL +_value
1322  * RELOC (P3) - crtc_id in reloc.
1323  *
1324  * This function parses this and relocates the VLINE START END
1325  * and WAIT UNTIL packets to the correct crtc.
1326  * It also detects a switched off crtc and nulls out the
1327  * wait in that case.
1328  */
1329 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1330 {
1331         struct drm_mode_object *obj;
1332         struct drm_crtc *crtc;
1333         struct radeon_crtc *radeon_crtc;
1334         struct radeon_cs_packet p3reloc, waitreloc;
1335         int crtc_id;
1336         int r;
1337         uint32_t header, h_idx, reg;
1338         volatile uint32_t *ib;
1339
1340         ib = p->ib.ptr;
1341
1342         /* parse the wait until */
1343         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1344         if (r)
1345                 return r;
1346
1347         /* check its a wait until and only 1 count */
1348         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1349             waitreloc.count != 0) {
1350                 DRM_ERROR("vline wait had illegal wait until segment\n");
1351                 return -EINVAL;
1352         }
1353
1354         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1355                 DRM_ERROR("vline wait had illegal wait until\n");
1356                 return -EINVAL;
1357         }
1358
1359         /* jump over the NOP */
1360         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1361         if (r)
1362                 return r;
1363
1364         h_idx = p->idx - 2;
1365         p->idx += waitreloc.count + 2;
1366         p->idx += p3reloc.count + 2;
1367
1368         header = radeon_get_ib_value(p, h_idx);
1369         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1370         reg = CP_PACKET0_GET_REG(header);
1371         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1372         if (!obj) {
1373                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1374                 return -EINVAL;
1375         }
1376         crtc = obj_to_crtc(obj);
1377         radeon_crtc = to_radeon_crtc(crtc);
1378         crtc_id = radeon_crtc->crtc_id;
1379
1380         if (!crtc->enabled) {
1381                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1382                 ib[h_idx + 2] = PACKET2(0);
1383                 ib[h_idx + 3] = PACKET2(0);
1384         } else if (crtc_id == 1) {
1385                 switch (reg) {
1386                 case AVIVO_D1MODE_VLINE_START_END:
1387                         header &= ~R300_CP_PACKET0_REG_MASK;
1388                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1389                         break;
1390                 case RADEON_CRTC_GUI_TRIG_VLINE:
1391                         header &= ~R300_CP_PACKET0_REG_MASK;
1392                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1393                         break;
1394                 default:
1395                         DRM_ERROR("unknown crtc reloc\n");
1396                         return -EINVAL;
1397                 }
1398                 ib[h_idx] = header;
1399                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1400         }
1401
1402         return 0;
1403 }
1404
1405 /**
1406  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1407  * @parser:             parser structure holding parsing context.
1408  * @data:               pointer to relocation data
1409  * @offset_start:       starting offset
1410  * @offset_mask:        offset mask (to align start offset on)
1411  * @reloc:              reloc informations
1412  *
1413  * Check next packet is relocation packet3, do bo validation and compute
1414  * GPU offset using the provided start.
1415  **/
1416 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1417                               struct radeon_cs_reloc **cs_reloc)
1418 {
1419         struct radeon_cs_chunk *relocs_chunk;
1420         struct radeon_cs_packet p3reloc;
1421         unsigned idx;
1422         int r;
1423
1424         if (p->chunk_relocs_idx == -1) {
1425                 DRM_ERROR("No relocation chunk !\n");
1426                 return -EINVAL;
1427         }
1428         *cs_reloc = NULL;
1429         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1430         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1431         if (r) {
1432                 return r;
1433         }
1434         p->idx += p3reloc.count + 2;
1435         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1436                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1437                           p3reloc.idx);
1438                 r100_cs_dump_packet(p, &p3reloc);
1439                 return -EINVAL;
1440         }
1441         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1442         if (idx >= relocs_chunk->length_dw) {
1443                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1444                           idx, relocs_chunk->length_dw);
1445                 r100_cs_dump_packet(p, &p3reloc);
1446                 return -EINVAL;
1447         }
1448         /* FIXME: we assume reloc size is 4 dwords */
1449         *cs_reloc = p->relocs_ptr[(idx / 4)];
1450         return 0;
1451 }
1452
1453 static int r100_get_vtx_size(uint32_t vtx_fmt)
1454 {
1455         int vtx_size;
1456         vtx_size = 2;
1457         /* ordered according to bits in spec */
1458         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1459                 vtx_size++;
1460         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1461                 vtx_size += 3;
1462         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1463                 vtx_size++;
1464         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1465                 vtx_size++;
1466         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1467                 vtx_size += 3;
1468         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1469                 vtx_size++;
1470         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1471                 vtx_size++;
1472         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1473                 vtx_size += 2;
1474         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1475                 vtx_size += 2;
1476         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1477                 vtx_size++;
1478         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1479                 vtx_size += 2;
1480         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1481                 vtx_size++;
1482         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1483                 vtx_size += 2;
1484         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1485                 vtx_size++;
1486         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1487                 vtx_size++;
1488         /* blend weight */
1489         if (vtx_fmt & (0x7 << 15))
1490                 vtx_size += (vtx_fmt >> 15) & 0x7;
1491         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1492                 vtx_size += 3;
1493         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1494                 vtx_size += 2;
1495         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1496                 vtx_size++;
1497         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1498                 vtx_size++;
1499         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1500                 vtx_size++;
1501         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1502                 vtx_size++;
1503         return vtx_size;
1504 }
1505
1506 static int r100_packet0_check(struct radeon_cs_parser *p,
1507                               struct radeon_cs_packet *pkt,
1508                               unsigned idx, unsigned reg)
1509 {
1510         struct radeon_cs_reloc *reloc;
1511         struct r100_cs_track *track;
1512         volatile uint32_t *ib;
1513         uint32_t tmp;
1514         int r;
1515         int i, face;
1516         u32 tile_flags = 0;
1517         u32 idx_value;
1518
1519         ib = p->ib.ptr;
1520         track = (struct r100_cs_track *)p->track;
1521
1522         idx_value = radeon_get_ib_value(p, idx);
1523
1524         switch (reg) {
1525         case RADEON_CRTC_GUI_TRIG_VLINE:
1526                 r = r100_cs_packet_parse_vline(p);
1527                 if (r) {
1528                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1529                                   idx, reg);
1530                         r100_cs_dump_packet(p, pkt);
1531                         return r;
1532                 }
1533                 break;
1534                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1535                  * range access */
1536         case RADEON_DST_PITCH_OFFSET:
1537         case RADEON_SRC_PITCH_OFFSET:
1538                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1539                 if (r)
1540                         return r;
1541                 break;
1542         case RADEON_RB3D_DEPTHOFFSET:
1543                 r = r100_cs_packet_next_reloc(p, &reloc);
1544                 if (r) {
1545                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1546                                   idx, reg);
1547                         r100_cs_dump_packet(p, pkt);
1548                         return r;
1549                 }
1550                 track->zb.robj = reloc->robj;
1551                 track->zb.offset = idx_value;
1552                 track->zb_dirty = true;
1553                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1554                 break;
1555         case RADEON_RB3D_COLOROFFSET:
1556                 r = r100_cs_packet_next_reloc(p, &reloc);
1557                 if (r) {
1558                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1559                                   idx, reg);
1560                         r100_cs_dump_packet(p, pkt);
1561                         return r;
1562                 }
1563                 track->cb[0].robj = reloc->robj;
1564                 track->cb[0].offset = idx_value;
1565                 track->cb_dirty = true;
1566                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1567                 break;
1568         case RADEON_PP_TXOFFSET_0:
1569         case RADEON_PP_TXOFFSET_1:
1570         case RADEON_PP_TXOFFSET_2:
1571                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1572                 r = r100_cs_packet_next_reloc(p, &reloc);
1573                 if (r) {
1574                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1575                                   idx, reg);
1576                         r100_cs_dump_packet(p, pkt);
1577                         return r;
1578                 }
1579                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1580                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1581                                 tile_flags |= RADEON_TXO_MACRO_TILE;
1582                         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1583                                 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1584
1585                         tmp = idx_value & ~(0x7 << 2);
1586                         tmp |= tile_flags;
1587                         ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1588                 } else
1589                         ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1590                 track->textures[i].robj = reloc->robj;
1591                 track->tex_dirty = true;
1592                 break;
1593         case RADEON_PP_CUBIC_OFFSET_T0_0:
1594         case RADEON_PP_CUBIC_OFFSET_T0_1:
1595         case RADEON_PP_CUBIC_OFFSET_T0_2:
1596         case RADEON_PP_CUBIC_OFFSET_T0_3:
1597         case RADEON_PP_CUBIC_OFFSET_T0_4:
1598                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1599                 r = r100_cs_packet_next_reloc(p, &reloc);
1600                 if (r) {
1601                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1602                                   idx, reg);
1603                         r100_cs_dump_packet(p, pkt);
1604                         return r;
1605                 }
1606                 track->textures[0].cube_info[i].offset = idx_value;
1607                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1608                 track->textures[0].cube_info[i].robj = reloc->robj;
1609                 track->tex_dirty = true;
1610                 break;
1611         case RADEON_PP_CUBIC_OFFSET_T1_0:
1612         case RADEON_PP_CUBIC_OFFSET_T1_1:
1613         case RADEON_PP_CUBIC_OFFSET_T1_2:
1614         case RADEON_PP_CUBIC_OFFSET_T1_3:
1615         case RADEON_PP_CUBIC_OFFSET_T1_4:
1616                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1617                 r = r100_cs_packet_next_reloc(p, &reloc);
1618                 if (r) {
1619                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1620                                   idx, reg);
1621                         r100_cs_dump_packet(p, pkt);
1622                         return r;
1623                 }
1624                 track->textures[1].cube_info[i].offset = idx_value;
1625                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1626                 track->textures[1].cube_info[i].robj = reloc->robj;
1627                 track->tex_dirty = true;
1628                 break;
1629         case RADEON_PP_CUBIC_OFFSET_T2_0:
1630         case RADEON_PP_CUBIC_OFFSET_T2_1:
1631         case RADEON_PP_CUBIC_OFFSET_T2_2:
1632         case RADEON_PP_CUBIC_OFFSET_T2_3:
1633         case RADEON_PP_CUBIC_OFFSET_T2_4:
1634                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1635                 r = r100_cs_packet_next_reloc(p, &reloc);
1636                 if (r) {
1637                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1638                                   idx, reg);
1639                         r100_cs_dump_packet(p, pkt);
1640                         return r;
1641                 }
1642                 track->textures[2].cube_info[i].offset = idx_value;
1643                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1644                 track->textures[2].cube_info[i].robj = reloc->robj;
1645                 track->tex_dirty = true;
1646                 break;
1647         case RADEON_RE_WIDTH_HEIGHT:
1648                 track->maxy = ((idx_value >> 16) & 0x7FF);
1649                 track->cb_dirty = true;
1650                 track->zb_dirty = true;
1651                 break;
1652         case RADEON_RB3D_COLORPITCH:
1653                 r = r100_cs_packet_next_reloc(p, &reloc);
1654                 if (r) {
1655                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1656                                   idx, reg);
1657                         r100_cs_dump_packet(p, pkt);
1658                         return r;
1659                 }
1660                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1661                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1662                                 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1663                         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1664                                 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1665
1666                         tmp = idx_value & ~(0x7 << 16);
1667                         tmp |= tile_flags;
1668                         ib[idx] = tmp;
1669                 } else
1670                         ib[idx] = idx_value;
1671
1672                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1673                 track->cb_dirty = true;
1674                 break;
1675         case RADEON_RB3D_DEPTHPITCH:
1676                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1677                 track->zb_dirty = true;
1678                 break;
1679         case RADEON_RB3D_CNTL:
1680                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1681                 case 7:
1682                 case 8:
1683                 case 9:
1684                 case 11:
1685                 case 12:
1686                         track->cb[0].cpp = 1;
1687                         break;
1688                 case 3:
1689                 case 4:
1690                 case 15:
1691                         track->cb[0].cpp = 2;
1692                         break;
1693                 case 6:
1694                         track->cb[0].cpp = 4;
1695                         break;
1696                 default:
1697                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1698                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1699                         return -EINVAL;
1700                 }
1701                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1702                 track->cb_dirty = true;
1703                 track->zb_dirty = true;
1704                 break;
1705         case RADEON_RB3D_ZSTENCILCNTL:
1706                 switch (idx_value & 0xf) {
1707                 case 0:
1708                         track->zb.cpp = 2;
1709                         break;
1710                 case 2:
1711                 case 3:
1712                 case 4:
1713                 case 5:
1714                 case 9:
1715                 case 11:
1716                         track->zb.cpp = 4;
1717                         break;
1718                 default:
1719                         break;
1720                 }
1721                 track->zb_dirty = true;
1722                 break;
1723         case RADEON_RB3D_ZPASS_ADDR:
1724                 r = r100_cs_packet_next_reloc(p, &reloc);
1725                 if (r) {
1726                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1727                                   idx, reg);
1728                         r100_cs_dump_packet(p, pkt);
1729                         return r;
1730                 }
1731                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1732                 break;
1733         case RADEON_PP_CNTL:
1734                 {
1735                         uint32_t temp = idx_value >> 4;
1736                         for (i = 0; i < track->num_texture; i++)
1737                                 track->textures[i].enabled = !!(temp & (1 << i));
1738                         track->tex_dirty = true;
1739                 }
1740                 break;
1741         case RADEON_SE_VF_CNTL:
1742                 track->vap_vf_cntl = idx_value;
1743                 break;
1744         case RADEON_SE_VTX_FMT:
1745                 track->vtx_size = r100_get_vtx_size(idx_value);
1746                 break;
1747         case RADEON_PP_TEX_SIZE_0:
1748         case RADEON_PP_TEX_SIZE_1:
1749         case RADEON_PP_TEX_SIZE_2:
1750                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1751                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1752                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1753                 track->tex_dirty = true;
1754                 break;
1755         case RADEON_PP_TEX_PITCH_0:
1756         case RADEON_PP_TEX_PITCH_1:
1757         case RADEON_PP_TEX_PITCH_2:
1758                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1759                 track->textures[i].pitch = idx_value + 32;
1760                 track->tex_dirty = true;
1761                 break;
1762         case RADEON_PP_TXFILTER_0:
1763         case RADEON_PP_TXFILTER_1:
1764         case RADEON_PP_TXFILTER_2:
1765                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1766                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1767                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1768                 tmp = (idx_value >> 23) & 0x7;
1769                 if (tmp == 2 || tmp == 6)
1770                         track->textures[i].roundup_w = false;
1771                 tmp = (idx_value >> 27) & 0x7;
1772                 if (tmp == 2 || tmp == 6)
1773                         track->textures[i].roundup_h = false;
1774                 track->tex_dirty = true;
1775                 break;
1776         case RADEON_PP_TXFORMAT_0:
1777         case RADEON_PP_TXFORMAT_1:
1778         case RADEON_PP_TXFORMAT_2:
1779                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1780                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1781                         track->textures[i].use_pitch = 1;
1782                 } else {
1783                         track->textures[i].use_pitch = 0;
1784                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1785                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1786                 }
1787                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1788                         track->textures[i].tex_coord_type = 2;
1789                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1790                 case RADEON_TXFORMAT_I8:
1791                 case RADEON_TXFORMAT_RGB332:
1792                 case RADEON_TXFORMAT_Y8:
1793                         track->textures[i].cpp = 1;
1794                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1795                         break;
1796                 case RADEON_TXFORMAT_AI88:
1797                 case RADEON_TXFORMAT_ARGB1555:
1798                 case RADEON_TXFORMAT_RGB565:
1799                 case RADEON_TXFORMAT_ARGB4444:
1800                 case RADEON_TXFORMAT_VYUY422:
1801                 case RADEON_TXFORMAT_YVYU422:
1802                 case RADEON_TXFORMAT_SHADOW16:
1803                 case RADEON_TXFORMAT_LDUDV655:
1804                 case RADEON_TXFORMAT_DUDV88:
1805                         track->textures[i].cpp = 2;
1806                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1807                         break;
1808                 case RADEON_TXFORMAT_ARGB8888:
1809                 case RADEON_TXFORMAT_RGBA8888:
1810                 case RADEON_TXFORMAT_SHADOW32:
1811                 case RADEON_TXFORMAT_LDUDUV8888:
1812                         track->textures[i].cpp = 4;
1813                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1814                         break;
1815                 case RADEON_TXFORMAT_DXT1:
1816                         track->textures[i].cpp = 1;
1817                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1818                         break;
1819                 case RADEON_TXFORMAT_DXT23:
1820                 case RADEON_TXFORMAT_DXT45:
1821                         track->textures[i].cpp = 1;
1822                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1823                         break;
1824                 }
1825                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1826                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1827                 track->tex_dirty = true;
1828                 break;
1829         case RADEON_PP_CUBIC_FACES_0:
1830         case RADEON_PP_CUBIC_FACES_1:
1831         case RADEON_PP_CUBIC_FACES_2:
1832                 tmp = idx_value;
1833                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1834                 for (face = 0; face < 4; face++) {
1835                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1836                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1837                 }
1838                 track->tex_dirty = true;
1839                 break;
1840         default:
1841                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1842                        reg, idx);
1843                 return -EINVAL;
1844         }
1845         return 0;
1846 }
1847
1848 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1849                                          struct radeon_cs_packet *pkt,
1850                                          struct radeon_bo *robj)
1851 {
1852         unsigned idx;
1853         u32 value;
1854         idx = pkt->idx + 1;
1855         value = radeon_get_ib_value(p, idx + 2);
1856         if ((value + 1) > radeon_bo_size(robj)) {
1857                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1858                           "(need %u have %lu) !\n",
1859                           value + 1,
1860                           radeon_bo_size(robj));
1861                 return -EINVAL;
1862         }
1863         return 0;
1864 }
1865
1866 static int r100_packet3_check(struct radeon_cs_parser *p,
1867                               struct radeon_cs_packet *pkt)
1868 {
1869         struct radeon_cs_reloc *reloc;
1870         struct r100_cs_track *track;
1871         unsigned idx;
1872         volatile uint32_t *ib;
1873         int r;
1874
1875         ib = p->ib.ptr;
1876         idx = pkt->idx + 1;
1877         track = (struct r100_cs_track *)p->track;
1878         switch (pkt->opcode) {
1879         case PACKET3_3D_LOAD_VBPNTR:
1880                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1881                 if (r)
1882                         return r;
1883                 break;
1884         case PACKET3_INDX_BUFFER:
1885                 r = r100_cs_packet_next_reloc(p, &reloc);
1886                 if (r) {
1887                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1888                         r100_cs_dump_packet(p, pkt);
1889                         return r;
1890                 }
1891                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1892                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1893                 if (r) {
1894                         return r;
1895                 }
1896                 break;
1897         case 0x23:
1898                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1899                 r = r100_cs_packet_next_reloc(p, &reloc);
1900                 if (r) {
1901                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1902                         r100_cs_dump_packet(p, pkt);
1903                         return r;
1904                 }
1905                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1906                 track->num_arrays = 1;
1907                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1908
1909                 track->arrays[0].robj = reloc->robj;
1910                 track->arrays[0].esize = track->vtx_size;
1911
1912                 track->max_indx = radeon_get_ib_value(p, idx+1);
1913
1914                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1915                 track->immd_dwords = pkt->count - 1;
1916                 r = r100_cs_track_check(p->rdev, track);
1917                 if (r)
1918                         return r;
1919                 break;
1920         case PACKET3_3D_DRAW_IMMD:
1921                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1922                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1923                         return -EINVAL;
1924                 }
1925                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1926                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1927                 track->immd_dwords = pkt->count - 1;
1928                 r = r100_cs_track_check(p->rdev, track);
1929                 if (r)
1930                         return r;
1931                 break;
1932                 /* triggers drawing using in-packet vertex data */
1933         case PACKET3_3D_DRAW_IMMD_2:
1934                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1935                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1936                         return -EINVAL;
1937                 }
1938                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1939                 track->immd_dwords = pkt->count;
1940                 r = r100_cs_track_check(p->rdev, track);
1941                 if (r)
1942                         return r;
1943                 break;
1944                 /* triggers drawing using in-packet vertex data */
1945         case PACKET3_3D_DRAW_VBUF_2:
1946                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1947                 r = r100_cs_track_check(p->rdev, track);
1948                 if (r)
1949                         return r;
1950                 break;
1951                 /* triggers drawing of vertex buffers setup elsewhere */
1952         case PACKET3_3D_DRAW_INDX_2:
1953                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1954                 r = r100_cs_track_check(p->rdev, track);
1955                 if (r)
1956                         return r;
1957                 break;
1958                 /* triggers drawing using indices to vertex buffer */
1959         case PACKET3_3D_DRAW_VBUF:
1960                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1961                 r = r100_cs_track_check(p->rdev, track);
1962                 if (r)
1963                         return r;
1964                 break;
1965                 /* triggers drawing of vertex buffers setup elsewhere */
1966         case PACKET3_3D_DRAW_INDX:
1967                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1968                 r = r100_cs_track_check(p->rdev, track);
1969                 if (r)
1970                         return r;
1971                 break;
1972                 /* triggers drawing using indices to vertex buffer */
1973         case PACKET3_3D_CLEAR_HIZ:
1974         case PACKET3_3D_CLEAR_ZMASK:
1975                 if (p->rdev->hyperz_filp != p->filp)
1976                         return -EINVAL;
1977                 break;
1978         case PACKET3_NOP:
1979                 break;
1980         default:
1981                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1982                 return -EINVAL;
1983         }
1984         return 0;
1985 }
1986
1987 int r100_cs_parse(struct radeon_cs_parser *p)
1988 {
1989         struct radeon_cs_packet pkt;
1990         struct r100_cs_track *track;
1991         int r;
1992
1993         track = kzalloc(sizeof(*track), GFP_KERNEL);
1994         if (!track)
1995                 return -ENOMEM;
1996         r100_cs_track_clear(p->rdev, track);
1997         p->track = track;
1998         do {
1999                 r = r100_cs_packet_parse(p, &pkt, p->idx);
2000                 if (r) {
2001                         return r;
2002                 }
2003                 p->idx += pkt.count + 2;
2004                 switch (pkt.type) {
2005                         case PACKET_TYPE0:
2006                                 if (p->rdev->family >= CHIP_R200)
2007                                         r = r100_cs_parse_packet0(p, &pkt,
2008                                                                   p->rdev->config.r100.reg_safe_bm,
2009                                                                   p->rdev->config.r100.reg_safe_bm_size,
2010                                                                   &r200_packet0_check);
2011                                 else
2012                                         r = r100_cs_parse_packet0(p, &pkt,
2013                                                                   p->rdev->config.r100.reg_safe_bm,
2014                                                                   p->rdev->config.r100.reg_safe_bm_size,
2015                                                                   &r100_packet0_check);
2016                                 break;
2017                         case PACKET_TYPE2:
2018                                 break;
2019                         case PACKET_TYPE3:
2020                                 r = r100_packet3_check(p, &pkt);
2021                                 break;
2022                         default:
2023                                 DRM_ERROR("Unknown packet type %d !\n",
2024                                           pkt.type);
2025                                 return -EINVAL;
2026                 }
2027                 if (r) {
2028                         return r;
2029                 }
2030         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2031         return 0;
2032 }
2033
2034
2035 /*
2036  * Global GPU functions
2037  */
2038 void r100_errata(struct radeon_device *rdev)
2039 {
2040         rdev->pll_errata = 0;
2041
2042         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2043                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2044         }
2045
2046         if (rdev->family == CHIP_RV100 ||
2047             rdev->family == CHIP_RS100 ||
2048             rdev->family == CHIP_RS200) {
2049                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2050         }
2051 }
2052
2053 /* Wait for vertical sync on primary CRTC */
2054 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2055 {
2056         uint32_t crtc_gen_cntl, tmp;
2057         int i;
2058
2059         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2060         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2061             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2062                 return;
2063         }
2064         /* Clear the CRTC_VBLANK_SAVE bit */
2065         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2066         for (i = 0; i < rdev->usec_timeout; i++) {
2067                 tmp = RREG32(RADEON_CRTC_STATUS);
2068                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2069                         return;
2070                 }
2071                 DRM_UDELAY(1);
2072         }
2073 }
2074
2075 /* Wait for vertical sync on secondary CRTC */
2076 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2077 {
2078         uint32_t crtc2_gen_cntl, tmp;
2079         int i;
2080
2081         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2082         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2083             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2084                 return;
2085
2086         /* Clear the CRTC_VBLANK_SAVE bit */
2087         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2088         for (i = 0; i < rdev->usec_timeout; i++) {
2089                 tmp = RREG32(RADEON_CRTC2_STATUS);
2090                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2091                         return;
2092                 }
2093                 DRM_UDELAY(1);
2094         }
2095 }
2096
2097 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2098 {
2099         unsigned i;
2100         uint32_t tmp;
2101
2102         for (i = 0; i < rdev->usec_timeout; i++) {
2103                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2104                 if (tmp >= n) {
2105                         return 0;
2106                 }
2107                 DRM_UDELAY(1);
2108         }
2109         return -1;
2110 }
2111
2112 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2113 {
2114         unsigned i;
2115         uint32_t tmp;
2116
2117         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2118                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2119                        " Bad things might happen.\n");
2120         }
2121         for (i = 0; i < rdev->usec_timeout; i++) {
2122                 tmp = RREG32(RADEON_RBBM_STATUS);
2123                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2124                         return 0;
2125                 }
2126                 DRM_UDELAY(1);
2127         }
2128         return -1;
2129 }
2130
2131 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2132 {
2133         unsigned i;
2134         uint32_t tmp;
2135
2136         for (i = 0; i < rdev->usec_timeout; i++) {
2137                 /* read MC_STATUS */
2138                 tmp = RREG32(RADEON_MC_STATUS);
2139                 if (tmp & RADEON_MC_IDLE) {
2140                         return 0;
2141                 }
2142                 DRM_UDELAY(1);
2143         }
2144         return -1;
2145 }
2146
2147 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2148 {
2149         u32 rbbm_status;
2150
2151         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2152         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2153                 radeon_ring_lockup_update(ring);
2154                 return false;
2155         }
2156         /* force CP activities */
2157         radeon_ring_force_activity(rdev, ring);
2158         return radeon_ring_test_lockup(rdev, ring);
2159 }
2160
2161 void r100_bm_disable(struct radeon_device *rdev)
2162 {
2163         u32 tmp;
2164
2165         /* disable bus mastering */
2166         tmp = RREG32(R_000030_BUS_CNTL);
2167         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2168         mdelay(1);
2169         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2170         mdelay(1);
2171         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2172         tmp = RREG32(RADEON_BUS_CNTL);
2173         mdelay(1);
2174         pci_clear_master(rdev->pdev);
2175         mdelay(1);
2176 }
2177
2178 int r100_asic_reset(struct radeon_device *rdev)
2179 {
2180         struct r100_mc_save save;
2181         u32 status, tmp;
2182         int ret = 0;
2183
2184         status = RREG32(R_000E40_RBBM_STATUS);
2185         if (!G_000E40_GUI_ACTIVE(status)) {
2186                 return 0;
2187         }
2188         r100_mc_stop(rdev, &save);
2189         status = RREG32(R_000E40_RBBM_STATUS);
2190         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2191         /* stop CP */
2192         WREG32(RADEON_CP_CSQ_CNTL, 0);
2193         tmp = RREG32(RADEON_CP_RB_CNTL);
2194         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2195         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2196         WREG32(RADEON_CP_RB_WPTR, 0);
2197         WREG32(RADEON_CP_RB_CNTL, tmp);
2198         /* save PCI state */
2199         pci_save_state(rdev->pdev);
2200         /* disable bus mastering */
2201         r100_bm_disable(rdev);
2202         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2203                                         S_0000F0_SOFT_RESET_RE(1) |
2204                                         S_0000F0_SOFT_RESET_PP(1) |
2205                                         S_0000F0_SOFT_RESET_RB(1));
2206         RREG32(R_0000F0_RBBM_SOFT_RESET);
2207         mdelay(500);
2208         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2209         mdelay(1);
2210         status = RREG32(R_000E40_RBBM_STATUS);
2211         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2212         /* reset CP */
2213         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2214         RREG32(R_0000F0_RBBM_SOFT_RESET);
2215         mdelay(500);
2216         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2217         mdelay(1);
2218         status = RREG32(R_000E40_RBBM_STATUS);
2219         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2220         /* restore PCI & busmastering */
2221         pci_restore_state(rdev->pdev);
2222         r100_enable_bm(rdev);
2223         /* Check if GPU is idle */
2224         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2225                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2226                 dev_err(rdev->dev, "failed to reset GPU\n");
2227                 ret = -1;
2228         } else
2229                 dev_info(rdev->dev, "GPU reset succeed\n");
2230         r100_mc_resume(rdev, &save);
2231         return ret;
2232 }
2233
2234 void r100_set_common_regs(struct radeon_device *rdev)
2235 {
2236         struct drm_device *dev = rdev->ddev;
2237         bool force_dac2 = false;
2238         u32 tmp;
2239
2240         /* set these so they don't interfere with anything */
2241         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2242         WREG32(RADEON_SUBPIC_CNTL, 0);
2243         WREG32(RADEON_VIPH_CONTROL, 0);
2244         WREG32(RADEON_I2C_CNTL_1, 0);
2245         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2246         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2247         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2248
2249         /* always set up dac2 on rn50 and some rv100 as lots
2250          * of servers seem to wire it up to a VGA port but
2251          * don't report it in the bios connector
2252          * table.
2253          */
2254         switch (dev->pdev->device) {
2255                 /* RN50 */
2256         case 0x515e:
2257         case 0x5969:
2258                 force_dac2 = true;
2259                 break;
2260                 /* RV100*/
2261         case 0x5159:
2262         case 0x515a:
2263                 /* DELL triple head servers */
2264                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2265                     ((dev->pdev->subsystem_device == 0x016c) ||
2266                      (dev->pdev->subsystem_device == 0x016d) ||
2267                      (dev->pdev->subsystem_device == 0x016e) ||
2268                      (dev->pdev->subsystem_device == 0x016f) ||
2269                      (dev->pdev->subsystem_device == 0x0170) ||
2270                      (dev->pdev->subsystem_device == 0x017d) ||
2271                      (dev->pdev->subsystem_device == 0x017e) ||
2272                      (dev->pdev->subsystem_device == 0x0183) ||
2273                      (dev->pdev->subsystem_device == 0x018a) ||
2274                      (dev->pdev->subsystem_device == 0x019a)))
2275                         force_dac2 = true;
2276                 break;
2277         }
2278
2279         if (force_dac2) {
2280                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2281                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2282                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2283
2284                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2285                    enable it, even it's detected.
2286                 */
2287
2288                 /* force it to crtc0 */
2289                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2290                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2291                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2292
2293                 /* set up the TV DAC */
2294                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2295                                  RADEON_TV_DAC_STD_MASK |
2296                                  RADEON_TV_DAC_RDACPD |
2297                                  RADEON_TV_DAC_GDACPD |
2298                                  RADEON_TV_DAC_BDACPD |
2299                                  RADEON_TV_DAC_BGADJ_MASK |
2300                                  RADEON_TV_DAC_DACADJ_MASK);
2301                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2302                                 RADEON_TV_DAC_NHOLD |
2303                                 RADEON_TV_DAC_STD_PS2 |
2304                                 (0x58 << 16));
2305
2306                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2307                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2308                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2309         }
2310
2311         /* switch PM block to ACPI mode */
2312         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2313         tmp &= ~RADEON_PM_MODE_SEL;
2314         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2315
2316 }
2317
2318 /*
2319  * VRAM info
2320  */
2321 static void r100_vram_get_type(struct radeon_device *rdev)
2322 {
2323         uint32_t tmp;
2324
2325         rdev->mc.vram_is_ddr = false;
2326         if (rdev->flags & RADEON_IS_IGP)
2327                 rdev->mc.vram_is_ddr = true;
2328         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2329                 rdev->mc.vram_is_ddr = true;
2330         if ((rdev->family == CHIP_RV100) ||
2331             (rdev->family == CHIP_RS100) ||
2332             (rdev->family == CHIP_RS200)) {
2333                 tmp = RREG32(RADEON_MEM_CNTL);
2334                 if (tmp & RV100_HALF_MODE) {
2335                         rdev->mc.vram_width = 32;
2336                 } else {
2337                         rdev->mc.vram_width = 64;
2338                 }
2339                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2340                         rdev->mc.vram_width /= 4;
2341                         rdev->mc.vram_is_ddr = true;
2342                 }
2343         } else if (rdev->family <= CHIP_RV280) {
2344                 tmp = RREG32(RADEON_MEM_CNTL);
2345                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2346                         rdev->mc.vram_width = 128;
2347                 } else {
2348                         rdev->mc.vram_width = 64;
2349                 }
2350         } else {
2351                 /* newer IGPs */
2352                 rdev->mc.vram_width = 128;
2353         }
2354 }
2355
2356 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2357 {
2358         u32 aper_size;
2359         u8 byte;
2360
2361         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2362
2363         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2364          * that is has the 2nd generation multifunction PCI interface
2365          */
2366         if (rdev->family == CHIP_RV280 ||
2367             rdev->family >= CHIP_RV350) {
2368                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2369                        ~RADEON_HDP_APER_CNTL);
2370                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2371                 return aper_size * 2;
2372         }
2373
2374         /* Older cards have all sorts of funny issues to deal with. First
2375          * check if it's a multifunction card by reading the PCI config
2376          * header type... Limit those to one aperture size
2377          */
2378         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2379         if (byte & 0x80) {
2380                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2381                 DRM_INFO("Limiting VRAM to one aperture\n");
2382                 return aper_size;
2383         }
2384
2385         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2386          * have set it up. We don't write this as it's broken on some ASICs but
2387          * we expect the BIOS to have done the right thing (might be too optimistic...)
2388          */
2389         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2390                 return aper_size * 2;
2391         return aper_size;
2392 }
2393
2394 void r100_vram_init_sizes(struct radeon_device *rdev)
2395 {
2396         u64 config_aper_size;
2397
2398         /* work out accessible VRAM */
2399         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2400         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2401         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2402         /* FIXME we don't use the second aperture yet when we could use it */
2403         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2404                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2405         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2406         if (rdev->flags & RADEON_IS_IGP) {
2407                 uint32_t tom;
2408                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2409                 tom = RREG32(RADEON_NB_TOM);
2410                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2411                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2412                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2413         } else {
2414                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2415                 /* Some production boards of m6 will report 0
2416                  * if it's 8 MB
2417                  */
2418                 if (rdev->mc.real_vram_size == 0) {
2419                         rdev->mc.real_vram_size = 8192 * 1024;
2420                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2421                 }
2422                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2423                  * Novell bug 204882 + along with lots of ubuntu ones
2424                  */
2425                 if (rdev->mc.aper_size > config_aper_size)
2426                         config_aper_size = rdev->mc.aper_size;
2427
2428                 if (config_aper_size > rdev->mc.real_vram_size)
2429                         rdev->mc.mc_vram_size = config_aper_size;
2430                 else
2431                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2432         }
2433 }
2434
2435 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2436 {
2437         uint32_t temp;
2438
2439         temp = RREG32(RADEON_CONFIG_CNTL);
2440         if (state == false) {
2441                 temp &= ~RADEON_CFG_VGA_RAM_EN;
2442                 temp |= RADEON_CFG_VGA_IO_DIS;
2443         } else {
2444                 temp &= ~RADEON_CFG_VGA_IO_DIS;
2445         }
2446         WREG32(RADEON_CONFIG_CNTL, temp);
2447 }
2448
2449 void r100_mc_init(struct radeon_device *rdev)
2450 {
2451         u64 base;
2452
2453         r100_vram_get_type(rdev);
2454         r100_vram_init_sizes(rdev);
2455         base = rdev->mc.aper_base;
2456         if (rdev->flags & RADEON_IS_IGP)
2457                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2458         radeon_vram_location(rdev, &rdev->mc, base);
2459         rdev->mc.gtt_base_align = 0;
2460         if (!(rdev->flags & RADEON_IS_AGP))
2461                 radeon_gtt_location(rdev, &rdev->mc);
2462         radeon_update_bandwidth_info(rdev);
2463 }
2464
2465
2466 /*
2467  * Indirect registers accessor
2468  */
2469 void r100_pll_errata_after_index(struct radeon_device *rdev)
2470 {
2471         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2472                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2473                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2474         }
2475 }
2476
2477 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2478 {
2479         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2480          * or the chip could hang on a subsequent access
2481          */
2482         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2483                 mdelay(5);
2484         }
2485
2486         /* This function is required to workaround a hardware bug in some (all?)
2487          * revisions of the R300.  This workaround should be called after every
2488          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2489          * may not be correct.
2490          */
2491         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2492                 uint32_t save, tmp;
2493
2494                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2495                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2496                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2497                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2498                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2499         }
2500 }
2501
2502 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2503 {
2504         uint32_t data;
2505
2506         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2507         r100_pll_errata_after_index(rdev);
2508         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2509         r100_pll_errata_after_data(rdev);
2510         return data;
2511 }
2512
2513 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2514 {
2515         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2516         r100_pll_errata_after_index(rdev);
2517         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2518         r100_pll_errata_after_data(rdev);
2519 }
2520
2521 void r100_set_safe_registers(struct radeon_device *rdev)
2522 {
2523         if (ASIC_IS_RN50(rdev)) {
2524                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2525                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2526         } else if (rdev->family < CHIP_R200) {
2527                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2528                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2529         } else {
2530                 r200_set_safe_registers(rdev);
2531         }
2532 }
2533
2534 /*
2535  * Debugfs info
2536  */
2537 #if defined(CONFIG_DEBUG_FS)
2538 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2539 {
2540         struct drm_info_node *node = (struct drm_info_node *) m->private;
2541         struct drm_device *dev = node->minor->dev;
2542         struct radeon_device *rdev = dev->dev_private;
2543         uint32_t reg, value;
2544         unsigned i;
2545
2546         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2547         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2548         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2549         for (i = 0; i < 64; i++) {
2550                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2551                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2552                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2553                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2554                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2555         }
2556         return 0;
2557 }
2558
2559 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2560 {
2561         struct drm_info_node *node = (struct drm_info_node *) m->private;
2562         struct drm_device *dev = node->minor->dev;
2563         struct radeon_device *rdev = dev->dev_private;
2564         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2565         uint32_t rdp, wdp;
2566         unsigned count, i, j;
2567
2568         radeon_ring_free_size(rdev, ring);
2569         rdp = RREG32(RADEON_CP_RB_RPTR);
2570         wdp = RREG32(RADEON_CP_RB_WPTR);
2571         count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2572         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2573         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2574         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2575         seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2576         seq_printf(m, "%u dwords in ring\n", count);
2577         for (j = 0; j <= count; j++) {
2578                 i = (rdp + j) & ring->ptr_mask;
2579                 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2580         }
2581         return 0;
2582 }
2583
2584
2585 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2586 {
2587         struct drm_info_node *node = (struct drm_info_node *) m->private;
2588         struct drm_device *dev = node->minor->dev;
2589         struct radeon_device *rdev = dev->dev_private;
2590         uint32_t csq_stat, csq2_stat, tmp;
2591         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2592         unsigned i;
2593
2594         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2595         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2596         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2597         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2598         r_rptr = (csq_stat >> 0) & 0x3ff;
2599         r_wptr = (csq_stat >> 10) & 0x3ff;
2600         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2601         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2602         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2603         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2604         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2605         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2606         seq_printf(m, "Ring rptr %u\n", r_rptr);
2607         seq_printf(m, "Ring wptr %u\n", r_wptr);
2608         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2609         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2610         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2611         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2612         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2613          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2614         seq_printf(m, "Ring fifo:\n");
2615         for (i = 0; i < 256; i++) {
2616                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2617                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2618                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2619         }
2620         seq_printf(m, "Indirect1 fifo:\n");
2621         for (i = 256; i <= 512; i++) {
2622                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2623                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2624                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2625         }
2626         seq_printf(m, "Indirect2 fifo:\n");
2627         for (i = 640; i < ib1_wptr; i++) {
2628                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2629                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2630                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2631         }
2632         return 0;
2633 }
2634
2635 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2636 {
2637         struct drm_info_node *node = (struct drm_info_node *) m->private;
2638         struct drm_device *dev = node->minor->dev;
2639         struct radeon_device *rdev = dev->dev_private;
2640         uint32_t tmp;
2641
2642         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2643         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2644         tmp = RREG32(RADEON_MC_FB_LOCATION);
2645         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2646         tmp = RREG32(RADEON_BUS_CNTL);
2647         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2648         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2649         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2650         tmp = RREG32(RADEON_AGP_BASE);
2651         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2652         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2653         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2654         tmp = RREG32(0x01D0);
2655         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2656         tmp = RREG32(RADEON_AIC_LO_ADDR);
2657         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2658         tmp = RREG32(RADEON_AIC_HI_ADDR);
2659         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2660         tmp = RREG32(0x01E4);
2661         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2662         return 0;
2663 }
2664
2665 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2666         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2667 };
2668
2669 static struct drm_info_list r100_debugfs_cp_list[] = {
2670         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2671         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2672 };
2673
2674 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2675         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2676 };
2677 #endif
2678
2679 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2680 {
2681 #if defined(CONFIG_DEBUG_FS)
2682         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2683 #else
2684         return 0;
2685 #endif
2686 }
2687
2688 int r100_debugfs_cp_init(struct radeon_device *rdev)
2689 {
2690 #if defined(CONFIG_DEBUG_FS)
2691         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2692 #else
2693         return 0;
2694 #endif
2695 }
2696
2697 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2698 {
2699 #if defined(CONFIG_DEBUG_FS)
2700         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2701 #else
2702         return 0;
2703 #endif
2704 }
2705
2706 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2707                          uint32_t tiling_flags, uint32_t pitch,
2708                          uint32_t offset, uint32_t obj_size)
2709 {
2710         int surf_index = reg * 16;
2711         int flags = 0;
2712
2713         if (rdev->family <= CHIP_RS200) {
2714                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2715                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2716                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2717                 if (tiling_flags & RADEON_TILING_MACRO)
2718                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2719         } else if (rdev->family <= CHIP_RV280) {
2720                 if (tiling_flags & (RADEON_TILING_MACRO))
2721                         flags |= R200_SURF_TILE_COLOR_MACRO;
2722                 if (tiling_flags & RADEON_TILING_MICRO)
2723                         flags |= R200_SURF_TILE_COLOR_MICRO;
2724         } else {
2725                 if (tiling_flags & RADEON_TILING_MACRO)
2726                         flags |= R300_SURF_TILE_MACRO;
2727                 if (tiling_flags & RADEON_TILING_MICRO)
2728                         flags |= R300_SURF_TILE_MICRO;
2729         }
2730
2731         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2732                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2733         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2734                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2735
2736         /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2737         if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2738                 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2739                         if (ASIC_IS_RN50(rdev))
2740                                 pitch /= 16;
2741         }
2742
2743         /* r100/r200 divide by 16 */
2744         if (rdev->family < CHIP_R300)
2745                 flags |= pitch / 16;
2746         else
2747                 flags |= pitch / 8;
2748
2749
2750         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2751         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2752         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2753         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2754         return 0;
2755 }
2756
2757 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2758 {
2759         int surf_index = reg * 16;
2760         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2761 }
2762
2763 void r100_bandwidth_update(struct radeon_device *rdev)
2764 {
2765         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2766         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2767         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2768         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2769         fixed20_12 memtcas_ff[8] = {
2770                 dfixed_init(1),
2771                 dfixed_init(2),
2772                 dfixed_init(3),
2773                 dfixed_init(0),
2774                 dfixed_init_half(1),
2775                 dfixed_init_half(2),
2776                 dfixed_init(0),
2777         };
2778         fixed20_12 memtcas_rs480_ff[8] = {
2779                 dfixed_init(0),
2780                 dfixed_init(1),
2781                 dfixed_init(2),
2782                 dfixed_init(3),
2783                 dfixed_init(0),
2784                 dfixed_init_half(1),
2785                 dfixed_init_half(2),
2786                 dfixed_init_half(3),
2787         };
2788         fixed20_12 memtcas2_ff[8] = {
2789                 dfixed_init(0),
2790                 dfixed_init(1),
2791                 dfixed_init(2),
2792                 dfixed_init(3),
2793                 dfixed_init(4),
2794                 dfixed_init(5),
2795                 dfixed_init(6),
2796                 dfixed_init(7),
2797         };
2798         fixed20_12 memtrbs[8] = {
2799                 dfixed_init(1),
2800                 dfixed_init_half(1),
2801                 dfixed_init(2),
2802                 dfixed_init_half(2),
2803                 dfixed_init(3),
2804                 dfixed_init_half(3),
2805                 dfixed_init(4),
2806                 dfixed_init_half(4)
2807         };
2808         fixed20_12 memtrbs_r4xx[8] = {
2809                 dfixed_init(4),
2810                 dfixed_init(5),
2811                 dfixed_init(6),
2812                 dfixed_init(7),
2813                 dfixed_init(8),
2814                 dfixed_init(9),
2815                 dfixed_init(10),
2816                 dfixed_init(11)
2817         };
2818         fixed20_12 min_mem_eff;
2819         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2820         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2821         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2822                 disp_drain_rate2, read_return_rate;
2823         fixed20_12 time_disp1_drop_priority;
2824         int c;
2825         int cur_size = 16;       /* in octawords */
2826         int critical_point = 0, critical_point2;
2827 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2828         int stop_req, max_stop_req;
2829         struct drm_display_mode *mode1 = NULL;
2830         struct drm_display_mode *mode2 = NULL;
2831         uint32_t pixel_bytes1 = 0;
2832         uint32_t pixel_bytes2 = 0;
2833
2834         radeon_update_display_priority(rdev);
2835
2836         if (rdev->mode_info.crtcs[0]->base.enabled) {
2837                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2838                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2839         }
2840         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2841                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2842                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2843                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2844                 }
2845         }
2846
2847         min_mem_eff.full = dfixed_const_8(0);
2848         /* get modes */
2849         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2850                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2851                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2852                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2853                 /* check crtc enables */
2854                 if (mode2)
2855                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2856                 if (mode1)
2857                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2858                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2859         }
2860
2861         /*
2862          * determine is there is enough bw for current mode
2863          */
2864         sclk_ff = rdev->pm.sclk;
2865         mclk_ff = rdev->pm.mclk;
2866
2867         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2868         temp_ff.full = dfixed_const(temp);
2869         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2870
2871         pix_clk.full = 0;
2872         pix_clk2.full = 0;
2873         peak_disp_bw.full = 0;
2874         if (mode1) {
2875                 temp_ff.full = dfixed_const(1000);
2876                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2877                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2878                 temp_ff.full = dfixed_const(pixel_bytes1);
2879                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2880         }
2881         if (mode2) {
2882                 temp_ff.full = dfixed_const(1000);
2883                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2884                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2885                 temp_ff.full = dfixed_const(pixel_bytes2);
2886                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2887         }
2888
2889         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2890         if (peak_disp_bw.full >= mem_bw.full) {
2891                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2892                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2893         }
2894
2895         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2896         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2897         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2898                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2899                 mem_trp  = ((temp & 0x3)) + 1;
2900                 mem_tras = ((temp & 0x70) >> 4) + 1;
2901         } else if (rdev->family == CHIP_R300 ||
2902                    rdev->family == CHIP_R350) { /* r300, r350 */
2903                 mem_trcd = (temp & 0x7) + 1;
2904                 mem_trp = ((temp >> 8) & 0x7) + 1;
2905                 mem_tras = ((temp >> 11) & 0xf) + 4;
2906         } else if (rdev->family == CHIP_RV350 ||
2907                    rdev->family <= CHIP_RV380) {
2908                 /* rv3x0 */
2909                 mem_trcd = (temp & 0x7) + 3;
2910                 mem_trp = ((temp >> 8) & 0x7) + 3;
2911                 mem_tras = ((temp >> 11) & 0xf) + 6;
2912         } else if (rdev->family == CHIP_R420 ||
2913                    rdev->family == CHIP_R423 ||
2914                    rdev->family == CHIP_RV410) {
2915                 /* r4xx */
2916                 mem_trcd = (temp & 0xf) + 3;
2917                 if (mem_trcd > 15)
2918                         mem_trcd = 15;
2919                 mem_trp = ((temp >> 8) & 0xf) + 3;
2920                 if (mem_trp > 15)
2921                         mem_trp = 15;
2922                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2923                 if (mem_tras > 31)
2924                         mem_tras = 31;
2925         } else { /* RV200, R200 */
2926                 mem_trcd = (temp & 0x7) + 1;
2927                 mem_trp = ((temp >> 8) & 0x7) + 1;
2928                 mem_tras = ((temp >> 12) & 0xf) + 4;
2929         }
2930         /* convert to FF */
2931         trcd_ff.full = dfixed_const(mem_trcd);
2932         trp_ff.full = dfixed_const(mem_trp);
2933         tras_ff.full = dfixed_const(mem_tras);
2934
2935         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2936         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2937         data = (temp & (7 << 20)) >> 20;
2938         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2939                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2940                         tcas_ff = memtcas_rs480_ff[data];
2941                 else
2942                         tcas_ff = memtcas_ff[data];
2943         } else
2944                 tcas_ff = memtcas2_ff[data];
2945
2946         if (rdev->family == CHIP_RS400 ||
2947             rdev->family == CHIP_RS480) {
2948                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2949                 data = (temp >> 23) & 0x7;
2950                 if (data < 5)
2951                         tcas_ff.full += dfixed_const(data);
2952         }
2953
2954         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2955                 /* on the R300, Tcas is included in Trbs.
2956                  */
2957                 temp = RREG32(RADEON_MEM_CNTL);
2958                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2959                 if (data == 1) {
2960                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2961                                 temp = RREG32(R300_MC_IND_INDEX);
2962                                 temp &= ~R300_MC_IND_ADDR_MASK;
2963                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2964                                 WREG32(R300_MC_IND_INDEX, temp);
2965                                 temp = RREG32(R300_MC_IND_DATA);
2966                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2967                         } else {
2968                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2969                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2970                         }
2971                 } else {
2972                         temp = RREG32(R300_MC_READ_CNTL_AB);
2973                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2974                 }
2975                 if (rdev->family == CHIP_RV410 ||
2976                     rdev->family == CHIP_R420 ||
2977                     rdev->family == CHIP_R423)
2978                         trbs_ff = memtrbs_r4xx[data];
2979                 else
2980                         trbs_ff = memtrbs[data];
2981                 tcas_ff.full += trbs_ff.full;
2982         }
2983
2984         sclk_eff_ff.full = sclk_ff.full;
2985
2986         if (rdev->flags & RADEON_IS_AGP) {
2987                 fixed20_12 agpmode_ff;
2988                 agpmode_ff.full = dfixed_const(radeon_agpmode);
2989                 temp_ff.full = dfixed_const_666(16);
2990                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
2991         }
2992         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2993
2994         if (ASIC_IS_R300(rdev)) {
2995                 sclk_delay_ff.full = dfixed_const(250);
2996         } else {
2997                 if ((rdev->family == CHIP_RV100) ||
2998                     rdev->flags & RADEON_IS_IGP) {
2999                         if (rdev->mc.vram_is_ddr)
3000                                 sclk_delay_ff.full = dfixed_const(41);
3001                         else
3002                                 sclk_delay_ff.full = dfixed_const(33);
3003                 } else {
3004                         if (rdev->mc.vram_width == 128)
3005                                 sclk_delay_ff.full = dfixed_const(57);
3006                         else
3007                                 sclk_delay_ff.full = dfixed_const(41);
3008                 }
3009         }
3010
3011         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3012
3013         if (rdev->mc.vram_is_ddr) {
3014                 if (rdev->mc.vram_width == 32) {
3015                         k1.full = dfixed_const(40);
3016                         c  = 3;
3017                 } else {
3018                         k1.full = dfixed_const(20);
3019                         c  = 1;
3020                 }
3021         } else {
3022                 k1.full = dfixed_const(40);
3023                 c  = 3;
3024         }
3025
3026         temp_ff.full = dfixed_const(2);
3027         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3028         temp_ff.full = dfixed_const(c);
3029         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3030         temp_ff.full = dfixed_const(4);
3031         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3032         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3033         mc_latency_mclk.full += k1.full;
3034
3035         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3036         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3037
3038         /*
3039           HW cursor time assuming worst case of full size colour cursor.
3040         */
3041         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3042         temp_ff.full += trcd_ff.full;
3043         if (temp_ff.full < tras_ff.full)
3044                 temp_ff.full = tras_ff.full;
3045         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3046
3047         temp_ff.full = dfixed_const(cur_size);
3048         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3049         /*
3050           Find the total latency for the display data.
3051         */
3052         disp_latency_overhead.full = dfixed_const(8);
3053         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3054         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3055         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3056
3057         if (mc_latency_mclk.full > mc_latency_sclk.full)
3058                 disp_latency.full = mc_latency_mclk.full;
3059         else
3060                 disp_latency.full = mc_latency_sclk.full;
3061
3062         /* setup Max GRPH_STOP_REQ default value */
3063         if (ASIC_IS_RV100(rdev))
3064                 max_stop_req = 0x5c;
3065         else
3066                 max_stop_req = 0x7c;
3067
3068         if (mode1) {
3069                 /*  CRTC1
3070                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3071                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3072                 */
3073                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3074
3075                 if (stop_req > max_stop_req)
3076                         stop_req = max_stop_req;
3077
3078                 /*
3079                   Find the drain rate of the display buffer.
3080                 */
3081                 temp_ff.full = dfixed_const((16/pixel_bytes1));
3082                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3083
3084                 /*
3085                   Find the critical point of the display buffer.
3086                 */
3087                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3088                 crit_point_ff.full += dfixed_const_half(0);
3089
3090                 critical_point = dfixed_trunc(crit_point_ff);
3091
3092                 if (rdev->disp_priority == 2) {
3093                         critical_point = 0;
3094                 }
3095
3096                 /*
3097                   The critical point should never be above max_stop_req-4.  Setting
3098                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3099                 */
3100                 if (max_stop_req - critical_point < 4)
3101                         critical_point = 0;
3102
3103                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3104                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3105                         critical_point = 0x10;
3106                 }
3107
3108                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3109                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3110                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3111                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3112                 if ((rdev->family == CHIP_R350) &&
3113                     (stop_req > 0x15)) {
3114                         stop_req -= 0x10;
3115                 }
3116                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3117                 temp |= RADEON_GRPH_BUFFER_SIZE;
3118                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3119                           RADEON_GRPH_CRITICAL_AT_SOF |
3120                           RADEON_GRPH_STOP_CNTL);
3121                 /*
3122                   Write the result into the register.
3123                 */
3124                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3125                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3126
3127 #if 0
3128                 if ((rdev->family == CHIP_RS400) ||
3129                     (rdev->family == CHIP_RS480)) {
3130                         /* attempt to program RS400 disp regs correctly ??? */
3131                         temp = RREG32(RS400_DISP1_REG_CNTL);
3132                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3133                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3134                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3135                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3136                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3137                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3138                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3139                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3140                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3141                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3142                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3143                 }
3144 #endif
3145
3146                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3147                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3148                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3149         }
3150
3151         if (mode2) {
3152                 u32 grph2_cntl;
3153                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3154
3155                 if (stop_req > max_stop_req)
3156                         stop_req = max_stop_req;
3157
3158                 /*
3159                   Find the drain rate of the display buffer.
3160                 */
3161                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3162                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3163
3164                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3165                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3166                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3167                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3168                 if ((rdev->family == CHIP_R350) &&
3169                     (stop_req > 0x15)) {
3170                         stop_req -= 0x10;
3171                 }
3172                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3173                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3174                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3175                           RADEON_GRPH_CRITICAL_AT_SOF |
3176                           RADEON_GRPH_STOP_CNTL);
3177
3178                 if ((rdev->family == CHIP_RS100) ||
3179                     (rdev->family == CHIP_RS200))
3180                         critical_point2 = 0;
3181                 else {
3182                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3183                         temp_ff.full = dfixed_const(temp);
3184                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3185                         if (sclk_ff.full < temp_ff.full)
3186                                 temp_ff.full = sclk_ff.full;
3187
3188                         read_return_rate.full = temp_ff.full;
3189
3190                         if (mode1) {
3191                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3192                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3193                         } else {
3194                                 time_disp1_drop_priority.full = 0;
3195                         }
3196                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3197                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3198                         crit_point_ff.full += dfixed_const_half(0);
3199
3200                         critical_point2 = dfixed_trunc(crit_point_ff);
3201
3202                         if (rdev->disp_priority == 2) {
3203                                 critical_point2 = 0;
3204                         }
3205
3206                         if (max_stop_req - critical_point2 < 4)
3207                                 critical_point2 = 0;
3208
3209                 }
3210
3211                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3212                         /* some R300 cards have problem with this set to 0 */
3213                         critical_point2 = 0x10;
3214                 }
3215
3216                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3217                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3218
3219                 if ((rdev->family == CHIP_RS400) ||
3220                     (rdev->family == CHIP_RS480)) {
3221 #if 0
3222                         /* attempt to program RS400 disp2 regs correctly ??? */
3223                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3224                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3225                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3226                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3227                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3228                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3229                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3230                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3231                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3232                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3233                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3234                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3235 #endif
3236                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3237                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3238                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3239                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3240                 }
3241
3242                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3243                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3244         }
3245 }
3246
3247 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3248 {
3249         DRM_ERROR("pitch                      %d\n", t->pitch);
3250         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
3251         DRM_ERROR("width                      %d\n", t->width);
3252         DRM_ERROR("width_11                   %d\n", t->width_11);
3253         DRM_ERROR("height                     %d\n", t->height);
3254         DRM_ERROR("height_11                  %d\n", t->height_11);
3255         DRM_ERROR("num levels                 %d\n", t->num_levels);
3256         DRM_ERROR("depth                      %d\n", t->txdepth);
3257         DRM_ERROR("bpp                        %d\n", t->cpp);
3258         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
3259         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
3260         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3261         DRM_ERROR("compress format            %d\n", t->compress_format);
3262 }
3263
3264 static int r100_track_compress_size(int compress_format, int w, int h)
3265 {
3266         int block_width, block_height, block_bytes;
3267         int wblocks, hblocks;
3268         int min_wblocks;
3269         int sz;
3270
3271         block_width = 4;
3272         block_height = 4;
3273
3274         switch (compress_format) {
3275         case R100_TRACK_COMP_DXT1:
3276                 block_bytes = 8;
3277                 min_wblocks = 4;
3278                 break;
3279         default:
3280         case R100_TRACK_COMP_DXT35:
3281                 block_bytes = 16;
3282                 min_wblocks = 2;
3283                 break;
3284         }
3285
3286         hblocks = (h + block_height - 1) / block_height;
3287         wblocks = (w + block_width - 1) / block_width;
3288         if (wblocks < min_wblocks)
3289                 wblocks = min_wblocks;
3290         sz = wblocks * hblocks * block_bytes;
3291         return sz;
3292 }
3293
3294 static int r100_cs_track_cube(struct radeon_device *rdev,
3295                               struct r100_cs_track *track, unsigned idx)
3296 {
3297         unsigned face, w, h;
3298         struct radeon_bo *cube_robj;
3299         unsigned long size;
3300         unsigned compress_format = track->textures[idx].compress_format;
3301
3302         for (face = 0; face < 5; face++) {
3303                 cube_robj = track->textures[idx].cube_info[face].robj;
3304                 w = track->textures[idx].cube_info[face].width;
3305                 h = track->textures[idx].cube_info[face].height;
3306
3307                 if (compress_format) {
3308                         size = r100_track_compress_size(compress_format, w, h);
3309                 } else
3310                         size = w * h;
3311                 size *= track->textures[idx].cpp;
3312
3313                 size += track->textures[idx].cube_info[face].offset;
3314
3315                 if (size > radeon_bo_size(cube_robj)) {
3316                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3317                                   size, radeon_bo_size(cube_robj));
3318                         r100_cs_track_texture_print(&track->textures[idx]);
3319                         return -1;
3320                 }
3321         }
3322         return 0;
3323 }
3324
3325 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3326                                        struct r100_cs_track *track)
3327 {
3328         struct radeon_bo *robj;
3329         unsigned long size;
3330         unsigned u, i, w, h, d;
3331         int ret;
3332
3333         for (u = 0; u < track->num_texture; u++) {
3334                 if (!track->textures[u].enabled)
3335                         continue;
3336                 if (track->textures[u].lookup_disable)
3337                         continue;
3338                 robj = track->textures[u].robj;
3339                 if (robj == NULL) {
3340                         DRM_ERROR("No texture bound to unit %u\n", u);
3341                         return -EINVAL;
3342                 }
3343                 size = 0;
3344                 for (i = 0; i <= track->textures[u].num_levels; i++) {
3345                         if (track->textures[u].use_pitch) {
3346                                 if (rdev->family < CHIP_R300)
3347                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3348                                 else
3349                                         w = track->textures[u].pitch / (1 << i);
3350                         } else {
3351                                 w = track->textures[u].width;
3352                                 if (rdev->family >= CHIP_RV515)
3353                                         w |= track->textures[u].width_11;
3354                                 w = w / (1 << i);
3355                                 if (track->textures[u].roundup_w)
3356                                         w = roundup_pow_of_two(w);
3357                         }
3358                         h = track->textures[u].height;
3359                         if (rdev->family >= CHIP_RV515)
3360                                 h |= track->textures[u].height_11;
3361                         h = h / (1 << i);
3362                         if (track->textures[u].roundup_h)
3363                                 h = roundup_pow_of_two(h);
3364                         if (track->textures[u].tex_coord_type == 1) {
3365                                 d = (1 << track->textures[u].txdepth) / (1 << i);
3366                                 if (!d)
3367                                         d = 1;
3368                         } else {
3369                                 d = 1;
3370                         }
3371                         if (track->textures[u].compress_format) {
3372
3373                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3374                                 /* compressed textures are block based */
3375                         } else
3376                                 size += w * h * d;
3377                 }
3378                 size *= track->textures[u].cpp;
3379
3380                 switch (track->textures[u].tex_coord_type) {
3381                 case 0:
3382                 case 1:
3383                         break;
3384                 case 2:
3385                         if (track->separate_cube) {
3386                                 ret = r100_cs_track_cube(rdev, track, u);
3387                                 if (ret)
3388                                         return ret;
3389                         } else
3390                                 size *= 6;
3391                         break;
3392                 default:
3393                         DRM_ERROR("Invalid texture coordinate type %u for unit "
3394                                   "%u\n", track->textures[u].tex_coord_type, u);
3395                         return -EINVAL;
3396                 }
3397                 if (size > radeon_bo_size(robj)) {
3398                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3399                                   "%lu\n", u, size, radeon_bo_size(robj));
3400                         r100_cs_track_texture_print(&track->textures[u]);
3401                         return -EINVAL;
3402                 }
3403         }
3404         return 0;
3405 }
3406
3407 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3408 {
3409         unsigned i;
3410         unsigned long size;
3411         unsigned prim_walk;
3412         unsigned nverts;
3413         unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
3414
3415         if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
3416             !track->blend_read_enable)
3417                 num_cb = 0;
3418
3419         for (i = 0; i < num_cb; i++) {
3420                 if (track->cb[i].robj == NULL) {
3421                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3422                         return -EINVAL;
3423                 }
3424                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3425                 size += track->cb[i].offset;
3426                 if (size > radeon_bo_size(track->cb[i].robj)) {
3427                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
3428                                   "(need %lu have %lu) !\n", i, size,
3429                                   radeon_bo_size(track->cb[i].robj));
3430                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3431                                   i, track->cb[i].pitch, track->cb[i].cpp,
3432                                   track->cb[i].offset, track->maxy);
3433                         return -EINVAL;
3434                 }
3435         }
3436         track->cb_dirty = false;
3437
3438         if (track->zb_dirty && track->z_enabled) {
3439                 if (track->zb.robj == NULL) {
3440                         DRM_ERROR("[drm] No buffer for z buffer !\n");
3441                         return -EINVAL;
3442                 }
3443                 size = track->zb.pitch * track->zb.cpp * track->maxy;
3444                 size += track->zb.offset;
3445                 if (size > radeon_bo_size(track->zb.robj)) {
3446                         DRM_ERROR("[drm] Buffer too small for z buffer "
3447                                   "(need %lu have %lu) !\n", size,
3448                                   radeon_bo_size(track->zb.robj));
3449                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3450                                   track->zb.pitch, track->zb.cpp,
3451                                   track->zb.offset, track->maxy);
3452                         return -EINVAL;
3453                 }
3454         }
3455         track->zb_dirty = false;
3456
3457         if (track->aa_dirty && track->aaresolve) {
3458                 if (track->aa.robj == NULL) {
3459                         DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3460                         return -EINVAL;
3461                 }
3462                 /* I believe the format comes from colorbuffer0. */
3463                 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3464                 size += track->aa.offset;
3465                 if (size > radeon_bo_size(track->aa.robj)) {
3466                         DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3467                                   "(need %lu have %lu) !\n", i, size,
3468                                   radeon_bo_size(track->aa.robj));
3469                         DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3470                                   i, track->aa.pitch, track->cb[0].cpp,
3471                                   track->aa.offset, track->maxy);
3472                         return -EINVAL;
3473                 }
3474         }
3475         track->aa_dirty = false;
3476
3477         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3478         if (track->vap_vf_cntl & (1 << 14)) {
3479                 nverts = track->vap_alt_nverts;
3480         } else {
3481                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3482         }
3483         switch (prim_walk) {
3484         case 1:
3485                 for (i = 0; i < track->num_arrays; i++) {
3486                         size = track->arrays[i].esize * track->max_indx * 4;
3487                         if (track->arrays[i].robj == NULL) {
3488                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3489                                           "bound\n", prim_walk, i);
3490                                 return -EINVAL;
3491                         }
3492                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3493                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3494                                         "need %lu dwords have %lu dwords\n",
3495                                         prim_walk, i, size >> 2,
3496                                         radeon_bo_size(track->arrays[i].robj)
3497                                         >> 2);
3498                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3499                                 return -EINVAL;
3500                         }
3501                 }
3502                 break;
3503         case 2:
3504                 for (i = 0; i < track->num_arrays; i++) {
3505                         size = track->arrays[i].esize * (nverts - 1) * 4;
3506                         if (track->arrays[i].robj == NULL) {
3507                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3508                                           "bound\n", prim_walk, i);
3509                                 return -EINVAL;
3510                         }
3511                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3512                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3513                                         "need %lu dwords have %lu dwords\n",
3514                                         prim_walk, i, size >> 2,
3515                                         radeon_bo_size(track->arrays[i].robj)
3516                                         >> 2);
3517                                 return -EINVAL;
3518                         }
3519                 }
3520                 break;
3521         case 3:
3522                 size = track->vtx_size * nverts;
3523                 if (size != track->immd_dwords) {
3524                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3525                                   track->immd_dwords, size);
3526                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3527                                   nverts, track->vtx_size);
3528                         return -EINVAL;
3529                 }
3530                 break;
3531         default:
3532                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3533                           prim_walk);
3534                 return -EINVAL;
3535         }
3536
3537         if (track->tex_dirty) {
3538                 track->tex_dirty = false;
3539                 return r100_cs_track_texture_check(rdev, track);
3540         }
3541         return 0;
3542 }
3543
3544 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3545 {
3546         unsigned i, face;
3547
3548         track->cb_dirty = true;
3549         track->zb_dirty = true;
3550         track->tex_dirty = true;
3551         track->aa_dirty = true;
3552
3553         if (rdev->family < CHIP_R300) {
3554                 track->num_cb = 1;
3555                 if (rdev->family <= CHIP_RS200)
3556                         track->num_texture = 3;
3557                 else
3558                         track->num_texture = 6;
3559                 track->maxy = 2048;
3560                 track->separate_cube = 1;
3561         } else {
3562                 track->num_cb = 4;
3563                 track->num_texture = 16;
3564                 track->maxy = 4096;
3565                 track->separate_cube = 0;
3566                 track->aaresolve = false;
3567                 track->aa.robj = NULL;
3568         }
3569
3570         for (i = 0; i < track->num_cb; i++) {
3571                 track->cb[i].robj = NULL;
3572                 track->cb[i].pitch = 8192;
3573                 track->cb[i].cpp = 16;
3574                 track->cb[i].offset = 0;
3575         }
3576         track->z_enabled = true;
3577         track->zb.robj = NULL;
3578         track->zb.pitch = 8192;
3579         track->zb.cpp = 4;
3580         track->zb.offset = 0;
3581         track->vtx_size = 0x7F;
3582         track->immd_dwords = 0xFFFFFFFFUL;
3583         track->num_arrays = 11;
3584         track->max_indx = 0x00FFFFFFUL;
3585         for (i = 0; i < track->num_arrays; i++) {
3586                 track->arrays[i].robj = NULL;
3587                 track->arrays[i].esize = 0x7F;
3588         }
3589         for (i = 0; i < track->num_texture; i++) {
3590                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3591                 track->textures[i].pitch = 16536;
3592                 track->textures[i].width = 16536;
3593                 track->textures[i].height = 16536;
3594                 track->textures[i].width_11 = 1 << 11;
3595                 track->textures[i].height_11 = 1 << 11;
3596                 track->textures[i].num_levels = 12;
3597                 if (rdev->family <= CHIP_RS200) {
3598                         track->textures[i].tex_coord_type = 0;
3599                         track->textures[i].txdepth = 0;
3600                 } else {
3601                         track->textures[i].txdepth = 16;
3602                         track->textures[i].tex_coord_type = 1;
3603                 }
3604                 track->textures[i].cpp = 64;
3605                 track->textures[i].robj = NULL;
3606                 /* CS IB emission code makes sure texture unit are disabled */
3607                 track->textures[i].enabled = false;
3608                 track->textures[i].lookup_disable = false;
3609                 track->textures[i].roundup_w = true;
3610                 track->textures[i].roundup_h = true;
3611                 if (track->separate_cube)
3612                         for (face = 0; face < 5; face++) {
3613                                 track->textures[i].cube_info[face].robj = NULL;
3614                                 track->textures[i].cube_info[face].width = 16536;
3615                                 track->textures[i].cube_info[face].height = 16536;
3616                                 track->textures[i].cube_info[face].offset = 0;
3617                         }
3618         }
3619 }
3620
3621 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3622 {
3623         uint32_t scratch;
3624         uint32_t tmp = 0;
3625         unsigned i;
3626         int r;
3627
3628         r = radeon_scratch_get(rdev, &scratch);
3629         if (r) {
3630                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3631                 return r;
3632         }
3633         WREG32(scratch, 0xCAFEDEAD);
3634         r = radeon_ring_lock(rdev, ring, 2);
3635         if (r) {
3636                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3637                 radeon_scratch_free(rdev, scratch);
3638                 return r;
3639         }
3640         radeon_ring_write(ring, PACKET0(scratch, 0));
3641         radeon_ring_write(ring, 0xDEADBEEF);
3642         radeon_ring_unlock_commit(rdev, ring);
3643         for (i = 0; i < rdev->usec_timeout; i++) {
3644                 tmp = RREG32(scratch);
3645                 if (tmp == 0xDEADBEEF) {
3646                         break;
3647                 }
3648                 DRM_UDELAY(1);
3649         }
3650         if (i < rdev->usec_timeout) {
3651                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3652         } else {
3653                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3654                           scratch, tmp);
3655                 r = -EINVAL;
3656         }
3657         radeon_scratch_free(rdev, scratch);
3658         return r;
3659 }
3660
3661 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3662 {
3663         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3664
3665         radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3666         radeon_ring_write(ring, ib->gpu_addr);
3667         radeon_ring_write(ring, ib->length_dw);
3668 }
3669
3670 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3671 {
3672         struct radeon_ib ib;
3673         uint32_t scratch;
3674         uint32_t tmp = 0;
3675         unsigned i;
3676         int r;
3677
3678         r = radeon_scratch_get(rdev, &scratch);
3679         if (r) {
3680                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3681                 return r;
3682         }
3683         WREG32(scratch, 0xCAFEDEAD);
3684         r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, 256);
3685         if (r) {
3686                 return r;
3687         }
3688         ib.ptr[0] = PACKET0(scratch, 0);
3689         ib.ptr[1] = 0xDEADBEEF;
3690         ib.ptr[2] = PACKET2(0);
3691         ib.ptr[3] = PACKET2(0);
3692         ib.ptr[4] = PACKET2(0);
3693         ib.ptr[5] = PACKET2(0);
3694         ib.ptr[6] = PACKET2(0);
3695         ib.ptr[7] = PACKET2(0);
3696         ib.length_dw = 8;
3697         r = radeon_ib_schedule(rdev, &ib);
3698         if (r) {
3699                 radeon_scratch_free(rdev, scratch);
3700                 radeon_ib_free(rdev, &ib);
3701                 return r;
3702         }
3703         r = radeon_fence_wait(ib.fence, false);
3704         if (r) {
3705                 return r;
3706         }
3707         for (i = 0; i < rdev->usec_timeout; i++) {
3708                 tmp = RREG32(scratch);
3709                 if (tmp == 0xDEADBEEF) {
3710                         break;
3711                 }
3712                 DRM_UDELAY(1);
3713         }
3714         if (i < rdev->usec_timeout) {
3715                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3716         } else {
3717                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3718                           scratch, tmp);
3719                 r = -EINVAL;
3720         }
3721         radeon_scratch_free(rdev, scratch);
3722         radeon_ib_free(rdev, &ib);
3723         return r;
3724 }
3725
3726 void r100_ib_fini(struct radeon_device *rdev)
3727 {
3728         radeon_ib_pool_suspend(rdev);
3729         radeon_ib_pool_fini(rdev);
3730 }
3731
3732 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3733 {
3734         /* Shutdown CP we shouldn't need to do that but better be safe than
3735          * sorry
3736          */
3737         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3738         WREG32(R_000740_CP_CSQ_CNTL, 0);
3739
3740         /* Save few CRTC registers */
3741         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3742         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3743         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3744         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3745         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3746                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3747                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3748         }
3749
3750         /* Disable VGA aperture access */
3751         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3752         /* Disable cursor, overlay, crtc */
3753         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3754         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3755                                         S_000054_CRTC_DISPLAY_DIS(1));
3756         WREG32(R_000050_CRTC_GEN_CNTL,
3757                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3758                         S_000050_CRTC_DISP_REQ_EN_B(1));
3759         WREG32(R_000420_OV0_SCALE_CNTL,
3760                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3761         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3762         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3763                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3764                                                 S_000360_CUR2_LOCK(1));
3765                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3766                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3767                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3768                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3769                 WREG32(R_000360_CUR2_OFFSET,
3770                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3771         }
3772 }
3773
3774 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3775 {
3776         /* Update base address for crtc */
3777         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3778         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3779                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3780         }
3781         /* Restore CRTC registers */
3782         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3783         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3784         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3785         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3786                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3787         }
3788 }
3789
3790 void r100_vga_render_disable(struct radeon_device *rdev)
3791 {
3792         u32 tmp;
3793
3794         tmp = RREG8(R_0003C2_GENMO_WT);
3795         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3796 }
3797
3798 static void r100_debugfs(struct radeon_device *rdev)
3799 {
3800         int r;
3801
3802         r = r100_debugfs_mc_info_init(rdev);
3803         if (r)
3804                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3805 }
3806
3807 static void r100_mc_program(struct radeon_device *rdev)
3808 {
3809         struct r100_mc_save save;
3810
3811         /* Stops all mc clients */
3812         r100_mc_stop(rdev, &save);
3813         if (rdev->flags & RADEON_IS_AGP) {
3814                 WREG32(R_00014C_MC_AGP_LOCATION,
3815                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3816                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3817                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3818                 if (rdev->family > CHIP_RV200)
3819                         WREG32(R_00015C_AGP_BASE_2,
3820                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3821         } else {
3822                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3823                 WREG32(R_000170_AGP_BASE, 0);
3824                 if (rdev->family > CHIP_RV200)
3825                         WREG32(R_00015C_AGP_BASE_2, 0);
3826         }
3827         /* Wait for mc idle */
3828         if (r100_mc_wait_for_idle(rdev))
3829                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3830         /* Program MC, should be a 32bits limited address space */
3831         WREG32(R_000148_MC_FB_LOCATION,
3832                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3833                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3834         r100_mc_resume(rdev, &save);
3835 }
3836
3837 void r100_clock_startup(struct radeon_device *rdev)
3838 {
3839         u32 tmp;
3840
3841         if (radeon_dynclks != -1 && radeon_dynclks)
3842                 radeon_legacy_set_clock_gating(rdev, 1);
3843         /* We need to force on some of the block */
3844         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3845         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3846         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3847                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3848         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3849 }
3850
3851 static int r100_startup(struct radeon_device *rdev)
3852 {
3853         int r;
3854
3855         /* set common regs */
3856         r100_set_common_regs(rdev);
3857         /* program mc */
3858         r100_mc_program(rdev);
3859         /* Resume clock */
3860         r100_clock_startup(rdev);
3861         /* Initialize GART (initialize after TTM so we can allocate
3862          * memory through TTM but finalize after TTM) */
3863         r100_enable_bm(rdev);
3864         if (rdev->flags & RADEON_IS_PCI) {
3865                 r = r100_pci_gart_enable(rdev);
3866                 if (r)
3867                         return r;
3868         }
3869
3870         /* allocate wb buffer */
3871         r = radeon_wb_init(rdev);
3872         if (r)
3873                 return r;
3874
3875         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3876         if (r) {
3877                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3878                 return r;
3879         }
3880
3881         /* Enable IRQ */
3882         r100_irq_set(rdev);
3883         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3884         /* 1M ring buffer */
3885         r = r100_cp_init(rdev, 1024 * 1024);
3886         if (r) {
3887                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3888                 return r;
3889         }
3890
3891         r = radeon_ib_pool_start(rdev);
3892         if (r)
3893                 return r;
3894
3895         r = radeon_ib_ring_tests(rdev);
3896         if (r)
3897                 return r;
3898
3899         return 0;
3900 }
3901
3902 int r100_resume(struct radeon_device *rdev)
3903 {
3904         int r;
3905
3906         /* Make sur GART are not working */
3907         if (rdev->flags & RADEON_IS_PCI)
3908                 r100_pci_gart_disable(rdev);
3909         /* Resume clock before doing reset */
3910         r100_clock_startup(rdev);
3911         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3912         if (radeon_asic_reset(rdev)) {
3913                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3914                         RREG32(R_000E40_RBBM_STATUS),
3915                         RREG32(R_0007C0_CP_STAT));
3916         }
3917         /* post */
3918         radeon_combios_asic_init(rdev->ddev);
3919         /* Resume clock after posting */
3920         r100_clock_startup(rdev);
3921         /* Initialize surface registers */
3922         radeon_surface_init(rdev);
3923
3924         rdev->accel_working = true;
3925         r = r100_startup(rdev);
3926         if (r) {
3927                 rdev->accel_working = false;
3928         }
3929         return r;
3930 }
3931
3932 int r100_suspend(struct radeon_device *rdev)
3933 {
3934         radeon_ib_pool_suspend(rdev);
3935         r100_cp_disable(rdev);
3936         radeon_wb_disable(rdev);
3937         r100_irq_disable(rdev);
3938         if (rdev->flags & RADEON_IS_PCI)
3939                 r100_pci_gart_disable(rdev);
3940         return 0;
3941 }
3942
3943 void r100_fini(struct radeon_device *rdev)
3944 {
3945         r100_cp_fini(rdev);
3946         radeon_wb_fini(rdev);
3947         r100_ib_fini(rdev);
3948         radeon_gem_fini(rdev);
3949         if (rdev->flags & RADEON_IS_PCI)
3950                 r100_pci_gart_fini(rdev);
3951         radeon_agp_fini(rdev);
3952         radeon_irq_kms_fini(rdev);
3953         radeon_fence_driver_fini(rdev);
3954         radeon_bo_fini(rdev);
3955         radeon_atombios_fini(rdev);
3956         kfree(rdev->bios);
3957         rdev->bios = NULL;
3958 }
3959
3960 /*
3961  * Due to how kexec works, it can leave the hw fully initialised when it
3962  * boots the new kernel. However doing our init sequence with the CP and
3963  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3964  * do some quick sanity checks and restore sane values to avoid this
3965  * problem.
3966  */
3967 void r100_restore_sanity(struct radeon_device *rdev)
3968 {
3969         u32 tmp;
3970
3971         tmp = RREG32(RADEON_CP_CSQ_CNTL);
3972         if (tmp) {
3973                 WREG32(RADEON_CP_CSQ_CNTL, 0);
3974         }
3975         tmp = RREG32(RADEON_CP_RB_CNTL);
3976         if (tmp) {
3977                 WREG32(RADEON_CP_RB_CNTL, 0);
3978         }
3979         tmp = RREG32(RADEON_SCRATCH_UMSK);
3980         if (tmp) {
3981                 WREG32(RADEON_SCRATCH_UMSK, 0);
3982         }
3983 }
3984
3985 int r100_init(struct radeon_device *rdev)
3986 {
3987         int r;
3988
3989         /* Register debugfs file specific to this group of asics */
3990         r100_debugfs(rdev);
3991         /* Disable VGA */
3992         r100_vga_render_disable(rdev);
3993         /* Initialize scratch registers */
3994         radeon_scratch_init(rdev);
3995         /* Initialize surface registers */
3996         radeon_surface_init(rdev);
3997         /* sanity check some register to avoid hangs like after kexec */
3998         r100_restore_sanity(rdev);
3999         /* TODO: disable VGA need to use VGA request */
4000         /* BIOS*/
4001         if (!radeon_get_bios(rdev)) {
4002                 if (ASIC_IS_AVIVO(rdev))
4003                         return -EINVAL;
4004         }
4005         if (rdev->is_atom_bios) {
4006                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4007                 return -EINVAL;
4008         } else {
4009                 r = radeon_combios_init(rdev);
4010                 if (r)
4011                         return r;
4012         }
4013         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4014         if (radeon_asic_reset(rdev)) {
4015                 dev_warn(rdev->dev,
4016                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4017                         RREG32(R_000E40_RBBM_STATUS),
4018                         RREG32(R_0007C0_CP_STAT));
4019         }
4020         /* check if cards are posted or not */
4021         if (radeon_boot_test_post_card(rdev) == false)
4022                 return -EINVAL;
4023         /* Set asic errata */
4024         r100_errata(rdev);
4025         /* Initialize clocks */
4026         radeon_get_clock_info(rdev->ddev);
4027         /* initialize AGP */
4028         if (rdev->flags & RADEON_IS_AGP) {
4029                 r = radeon_agp_init(rdev);
4030                 if (r) {
4031                         radeon_agp_disable(rdev);
4032                 }
4033         }
4034         /* initialize VRAM */
4035         r100_mc_init(rdev);
4036         /* Fence driver */
4037         r = radeon_fence_driver_init(rdev);
4038         if (r)
4039                 return r;
4040         r = radeon_irq_kms_init(rdev);
4041         if (r)
4042                 return r;
4043         /* Memory manager */
4044         r = radeon_bo_init(rdev);
4045         if (r)
4046                 return r;
4047         if (rdev->flags & RADEON_IS_PCI) {
4048                 r = r100_pci_gart_init(rdev);
4049                 if (r)
4050                         return r;
4051         }
4052         r100_set_safe_registers(rdev);
4053
4054         r = radeon_ib_pool_init(rdev);
4055         rdev->accel_working = true;
4056         if (r) {
4057                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
4058                 rdev->accel_working = false;
4059         }
4060
4061         r = r100_startup(rdev);
4062         if (r) {
4063                 /* Somethings want wront with the accel init stop accel */
4064                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4065                 r100_cp_fini(rdev);
4066                 radeon_wb_fini(rdev);
4067                 r100_ib_fini(rdev);
4068                 radeon_irq_kms_fini(rdev);
4069                 if (rdev->flags & RADEON_IS_PCI)
4070                         r100_pci_gart_fini(rdev);
4071                 rdev->accel_working = false;
4072         }
4073         return 0;
4074 }
4075
4076 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4077 {
4078         if (reg < rdev->rmmio_size)
4079                 return readl(((void __iomem *)rdev->rmmio) + reg);
4080         else {
4081                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4082                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4083         }
4084 }
4085
4086 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4087 {
4088         if (reg < rdev->rmmio_size)
4089                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4090         else {
4091                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4092                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4093         }
4094 }
4095
4096 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4097 {
4098         if (reg < rdev->rio_mem_size)
4099                 return ioread32(rdev->rio_mem + reg);
4100         else {
4101                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4102                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4103         }
4104 }
4105
4106 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4107 {
4108         if (reg < rdev->rio_mem_size)
4109                 iowrite32(v, rdev->rio_mem + reg);
4110         else {
4111                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4112                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4113         }
4114 }