2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
30 #include "radeon_asic.h"
31 #include <drm/radeon_drm.h>
35 #include "cayman_blit_shaders.h"
37 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
38 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
39 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
40 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
41 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
42 extern void evergreen_mc_program(struct radeon_device *rdev);
43 extern void evergreen_irq_suspend(struct radeon_device *rdev);
44 extern int evergreen_mc_init(struct radeon_device *rdev);
45 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
46 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
47 extern void si_rlc_fini(struct radeon_device *rdev);
48 extern int si_rlc_init(struct radeon_device *rdev);
50 #define EVERGREEN_PFP_UCODE_SIZE 1120
51 #define EVERGREEN_PM4_UCODE_SIZE 1376
52 #define EVERGREEN_RLC_UCODE_SIZE 768
53 #define BTC_MC_UCODE_SIZE 6024
55 #define CAYMAN_PFP_UCODE_SIZE 2176
56 #define CAYMAN_PM4_UCODE_SIZE 2176
57 #define CAYMAN_RLC_UCODE_SIZE 1024
58 #define CAYMAN_MC_UCODE_SIZE 6037
60 #define ARUBA_RLC_UCODE_SIZE 1536
63 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
64 MODULE_FIRMWARE("radeon/BARTS_me.bin");
65 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
66 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
67 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
68 MODULE_FIRMWARE("radeon/TURKS_me.bin");
69 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
70 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
71 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
72 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
73 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
74 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
75 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
76 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
77 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
78 MODULE_FIRMWARE("radeon/ARUBA_me.bin");
79 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
81 #define BTC_IO_MC_REGS_SIZE 29
83 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
84 {0x00000077, 0xff010100},
85 {0x00000078, 0x00000000},
86 {0x00000079, 0x00001434},
87 {0x0000007a, 0xcc08ec08},
88 {0x0000007b, 0x00040000},
89 {0x0000007c, 0x000080c0},
90 {0x0000007d, 0x09000000},
91 {0x0000007e, 0x00210404},
92 {0x00000081, 0x08a8e800},
93 {0x00000082, 0x00030444},
94 {0x00000083, 0x00000000},
95 {0x00000085, 0x00000001},
96 {0x00000086, 0x00000002},
97 {0x00000087, 0x48490000},
98 {0x00000088, 0x20244647},
99 {0x00000089, 0x00000005},
100 {0x0000008b, 0x66030000},
101 {0x0000008c, 0x00006603},
102 {0x0000008d, 0x00000100},
103 {0x0000008f, 0x00001c0a},
104 {0x00000090, 0xff000001},
105 {0x00000094, 0x00101101},
106 {0x00000095, 0x00000fff},
107 {0x00000096, 0x00116fff},
108 {0x00000097, 0x60010000},
109 {0x00000098, 0x10010000},
110 {0x00000099, 0x00006000},
111 {0x0000009a, 0x00001000},
112 {0x0000009f, 0x00946a00}
115 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
116 {0x00000077, 0xff010100},
117 {0x00000078, 0x00000000},
118 {0x00000079, 0x00001434},
119 {0x0000007a, 0xcc08ec08},
120 {0x0000007b, 0x00040000},
121 {0x0000007c, 0x000080c0},
122 {0x0000007d, 0x09000000},
123 {0x0000007e, 0x00210404},
124 {0x00000081, 0x08a8e800},
125 {0x00000082, 0x00030444},
126 {0x00000083, 0x00000000},
127 {0x00000085, 0x00000001},
128 {0x00000086, 0x00000002},
129 {0x00000087, 0x48490000},
130 {0x00000088, 0x20244647},
131 {0x00000089, 0x00000005},
132 {0x0000008b, 0x66030000},
133 {0x0000008c, 0x00006603},
134 {0x0000008d, 0x00000100},
135 {0x0000008f, 0x00001c0a},
136 {0x00000090, 0xff000001},
137 {0x00000094, 0x00101101},
138 {0x00000095, 0x00000fff},
139 {0x00000096, 0x00116fff},
140 {0x00000097, 0x60010000},
141 {0x00000098, 0x10010000},
142 {0x00000099, 0x00006000},
143 {0x0000009a, 0x00001000},
144 {0x0000009f, 0x00936a00}
147 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
148 {0x00000077, 0xff010100},
149 {0x00000078, 0x00000000},
150 {0x00000079, 0x00001434},
151 {0x0000007a, 0xcc08ec08},
152 {0x0000007b, 0x00040000},
153 {0x0000007c, 0x000080c0},
154 {0x0000007d, 0x09000000},
155 {0x0000007e, 0x00210404},
156 {0x00000081, 0x08a8e800},
157 {0x00000082, 0x00030444},
158 {0x00000083, 0x00000000},
159 {0x00000085, 0x00000001},
160 {0x00000086, 0x00000002},
161 {0x00000087, 0x48490000},
162 {0x00000088, 0x20244647},
163 {0x00000089, 0x00000005},
164 {0x0000008b, 0x66030000},
165 {0x0000008c, 0x00006603},
166 {0x0000008d, 0x00000100},
167 {0x0000008f, 0x00001c0a},
168 {0x00000090, 0xff000001},
169 {0x00000094, 0x00101101},
170 {0x00000095, 0x00000fff},
171 {0x00000096, 0x00116fff},
172 {0x00000097, 0x60010000},
173 {0x00000098, 0x10010000},
174 {0x00000099, 0x00006000},
175 {0x0000009a, 0x00001000},
176 {0x0000009f, 0x00916a00}
179 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
180 {0x00000077, 0xff010100},
181 {0x00000078, 0x00000000},
182 {0x00000079, 0x00001434},
183 {0x0000007a, 0xcc08ec08},
184 {0x0000007b, 0x00040000},
185 {0x0000007c, 0x000080c0},
186 {0x0000007d, 0x09000000},
187 {0x0000007e, 0x00210404},
188 {0x00000081, 0x08a8e800},
189 {0x00000082, 0x00030444},
190 {0x00000083, 0x00000000},
191 {0x00000085, 0x00000001},
192 {0x00000086, 0x00000002},
193 {0x00000087, 0x48490000},
194 {0x00000088, 0x20244647},
195 {0x00000089, 0x00000005},
196 {0x0000008b, 0x66030000},
197 {0x0000008c, 0x00006603},
198 {0x0000008d, 0x00000100},
199 {0x0000008f, 0x00001c0a},
200 {0x00000090, 0xff000001},
201 {0x00000094, 0x00101101},
202 {0x00000095, 0x00000fff},
203 {0x00000096, 0x00116fff},
204 {0x00000097, 0x60010000},
205 {0x00000098, 0x10010000},
206 {0x00000099, 0x00006000},
207 {0x0000009a, 0x00001000},
208 {0x0000009f, 0x00976b00}
211 int ni_mc_load_microcode(struct radeon_device *rdev)
213 const __be32 *fw_data;
214 u32 mem_type, running, blackout = 0;
216 int i, ucode_size, regs_size;
221 switch (rdev->family) {
223 io_mc_regs = (u32 *)&barts_io_mc_regs;
224 ucode_size = BTC_MC_UCODE_SIZE;
225 regs_size = BTC_IO_MC_REGS_SIZE;
228 io_mc_regs = (u32 *)&turks_io_mc_regs;
229 ucode_size = BTC_MC_UCODE_SIZE;
230 regs_size = BTC_IO_MC_REGS_SIZE;
234 io_mc_regs = (u32 *)&caicos_io_mc_regs;
235 ucode_size = BTC_MC_UCODE_SIZE;
236 regs_size = BTC_IO_MC_REGS_SIZE;
239 io_mc_regs = (u32 *)&cayman_io_mc_regs;
240 ucode_size = CAYMAN_MC_UCODE_SIZE;
241 regs_size = BTC_IO_MC_REGS_SIZE;
245 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
246 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
248 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
250 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
251 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
254 /* reset the engine and set to writable */
255 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
256 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
258 /* load mc io regs */
259 for (i = 0; i < regs_size; i++) {
260 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
261 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
263 /* load the MC ucode */
264 fw_data = (const __be32 *)rdev->mc_fw->data;
265 for (i = 0; i < ucode_size; i++)
266 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
268 /* put the engine back into the active state */
269 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
270 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
271 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
273 /* wait for training to complete */
274 for (i = 0; i < rdev->usec_timeout; i++) {
275 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
281 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
287 int ni_init_microcode(struct radeon_device *rdev)
289 struct platform_device *pdev;
290 const char *chip_name;
291 const char *rlc_chip_name;
292 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
298 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
301 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
305 switch (rdev->family) {
308 rlc_chip_name = "BTC";
309 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
310 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
311 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
312 mc_req_size = BTC_MC_UCODE_SIZE * 4;
316 rlc_chip_name = "BTC";
317 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
318 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
319 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
320 mc_req_size = BTC_MC_UCODE_SIZE * 4;
323 chip_name = "CAICOS";
324 rlc_chip_name = "BTC";
325 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
326 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
327 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
328 mc_req_size = BTC_MC_UCODE_SIZE * 4;
331 chip_name = "CAYMAN";
332 rlc_chip_name = "CAYMAN";
333 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
334 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
335 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
336 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
340 rlc_chip_name = "ARUBA";
341 /* pfp/me same size as CAYMAN */
342 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
343 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
344 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
350 DRM_INFO("Loading %s Microcode\n", chip_name);
352 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
353 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
356 if (rdev->pfp_fw->size != pfp_req_size) {
358 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
359 rdev->pfp_fw->size, fw_name);
364 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
365 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
368 if (rdev->me_fw->size != me_req_size) {
370 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
371 rdev->me_fw->size, fw_name);
375 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
376 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
379 if (rdev->rlc_fw->size != rlc_req_size) {
381 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
382 rdev->rlc_fw->size, fw_name);
386 /* no MC ucode on TN */
387 if (!(rdev->flags & RADEON_IS_IGP)) {
388 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
389 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
392 if (rdev->mc_fw->size != mc_req_size) {
394 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
395 rdev->mc_fw->size, fw_name);
400 platform_device_unregister(pdev);
405 "ni_cp: Failed to load firmware \"%s\"\n",
407 release_firmware(rdev->pfp_fw);
409 release_firmware(rdev->me_fw);
411 release_firmware(rdev->rlc_fw);
413 release_firmware(rdev->mc_fw);
422 static void cayman_gpu_init(struct radeon_device *rdev)
424 u32 gb_addr_config = 0;
425 u32 mc_shared_chmap, mc_arb_ramcfg;
426 u32 cgts_tcc_disable;
429 u32 cgts_sm_ctrl_reg;
430 u32 hdp_host_path_cntl;
432 u32 disabled_rb_mask;
435 switch (rdev->family) {
437 rdev->config.cayman.max_shader_engines = 2;
438 rdev->config.cayman.max_pipes_per_simd = 4;
439 rdev->config.cayman.max_tile_pipes = 8;
440 rdev->config.cayman.max_simds_per_se = 12;
441 rdev->config.cayman.max_backends_per_se = 4;
442 rdev->config.cayman.max_texture_channel_caches = 8;
443 rdev->config.cayman.max_gprs = 256;
444 rdev->config.cayman.max_threads = 256;
445 rdev->config.cayman.max_gs_threads = 32;
446 rdev->config.cayman.max_stack_entries = 512;
447 rdev->config.cayman.sx_num_of_sets = 8;
448 rdev->config.cayman.sx_max_export_size = 256;
449 rdev->config.cayman.sx_max_export_pos_size = 64;
450 rdev->config.cayman.sx_max_export_smx_size = 192;
451 rdev->config.cayman.max_hw_contexts = 8;
452 rdev->config.cayman.sq_num_cf_insts = 2;
454 rdev->config.cayman.sc_prim_fifo_size = 0x100;
455 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
456 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
457 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
461 rdev->config.cayman.max_shader_engines = 1;
462 rdev->config.cayman.max_pipes_per_simd = 4;
463 rdev->config.cayman.max_tile_pipes = 2;
464 if ((rdev->pdev->device == 0x9900) ||
465 (rdev->pdev->device == 0x9901) ||
466 (rdev->pdev->device == 0x9905) ||
467 (rdev->pdev->device == 0x9906) ||
468 (rdev->pdev->device == 0x9907) ||
469 (rdev->pdev->device == 0x9908) ||
470 (rdev->pdev->device == 0x9909) ||
471 (rdev->pdev->device == 0x9910) ||
472 (rdev->pdev->device == 0x9917)) {
473 rdev->config.cayman.max_simds_per_se = 6;
474 rdev->config.cayman.max_backends_per_se = 2;
475 } else if ((rdev->pdev->device == 0x9903) ||
476 (rdev->pdev->device == 0x9904) ||
477 (rdev->pdev->device == 0x990A) ||
478 (rdev->pdev->device == 0x9913) ||
479 (rdev->pdev->device == 0x9918)) {
480 rdev->config.cayman.max_simds_per_se = 4;
481 rdev->config.cayman.max_backends_per_se = 2;
482 } else if ((rdev->pdev->device == 0x9919) ||
483 (rdev->pdev->device == 0x9990) ||
484 (rdev->pdev->device == 0x9991) ||
485 (rdev->pdev->device == 0x9994) ||
486 (rdev->pdev->device == 0x99A0)) {
487 rdev->config.cayman.max_simds_per_se = 3;
488 rdev->config.cayman.max_backends_per_se = 1;
490 rdev->config.cayman.max_simds_per_se = 2;
491 rdev->config.cayman.max_backends_per_se = 1;
493 rdev->config.cayman.max_texture_channel_caches = 2;
494 rdev->config.cayman.max_gprs = 256;
495 rdev->config.cayman.max_threads = 256;
496 rdev->config.cayman.max_gs_threads = 32;
497 rdev->config.cayman.max_stack_entries = 512;
498 rdev->config.cayman.sx_num_of_sets = 8;
499 rdev->config.cayman.sx_max_export_size = 256;
500 rdev->config.cayman.sx_max_export_pos_size = 64;
501 rdev->config.cayman.sx_max_export_smx_size = 192;
502 rdev->config.cayman.max_hw_contexts = 8;
503 rdev->config.cayman.sq_num_cf_insts = 2;
505 rdev->config.cayman.sc_prim_fifo_size = 0x40;
506 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
507 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
508 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
513 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
514 WREG32((0x2c14 + j), 0x00000000);
515 WREG32((0x2c18 + j), 0x00000000);
516 WREG32((0x2c1c + j), 0x00000000);
517 WREG32((0x2c20 + j), 0x00000000);
518 WREG32((0x2c24 + j), 0x00000000);
521 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
523 evergreen_fix_pci_max_read_req_size(rdev);
525 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
526 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
528 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
529 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
530 if (rdev->config.cayman.mem_row_size_in_kb > 4)
531 rdev->config.cayman.mem_row_size_in_kb = 4;
532 /* XXX use MC settings? */
533 rdev->config.cayman.shader_engine_tile_size = 32;
534 rdev->config.cayman.num_gpus = 1;
535 rdev->config.cayman.multi_gpu_tile_size = 64;
537 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
538 rdev->config.cayman.num_tile_pipes = (1 << tmp);
539 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
540 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
541 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
542 rdev->config.cayman.num_shader_engines = tmp + 1;
543 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
544 rdev->config.cayman.num_gpus = tmp + 1;
545 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
546 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
547 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
548 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
551 /* setup tiling info dword. gb_addr_config is not adequate since it does
552 * not have bank info, so create a custom tiling dword.
555 * bits 11:8 group_size
556 * bits 15:12 row_size
558 rdev->config.cayman.tile_config = 0;
559 switch (rdev->config.cayman.num_tile_pipes) {
562 rdev->config.cayman.tile_config |= (0 << 0);
565 rdev->config.cayman.tile_config |= (1 << 0);
568 rdev->config.cayman.tile_config |= (2 << 0);
571 rdev->config.cayman.tile_config |= (3 << 0);
575 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
576 if (rdev->flags & RADEON_IS_IGP)
577 rdev->config.cayman.tile_config |= 1 << 4;
579 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
580 case 0: /* four banks */
581 rdev->config.cayman.tile_config |= 0 << 4;
583 case 1: /* eight banks */
584 rdev->config.cayman.tile_config |= 1 << 4;
586 case 2: /* sixteen banks */
588 rdev->config.cayman.tile_config |= 2 << 4;
592 rdev->config.cayman.tile_config |=
593 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
594 rdev->config.cayman.tile_config |=
595 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
598 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
599 u32 rb_disable_bitmap;
601 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
602 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
603 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
605 tmp |= rb_disable_bitmap;
607 /* enabled rb are just the one not disabled :) */
608 disabled_rb_mask = tmp;
610 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
611 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
613 WREG32(GB_ADDR_CONFIG, gb_addr_config);
614 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
615 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
616 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
617 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
619 tmp = gb_addr_config & NUM_PIPES_MASK;
620 tmp = r6xx_remap_render_backend(rdev, tmp,
621 rdev->config.cayman.max_backends_per_se *
622 rdev->config.cayman.max_shader_engines,
623 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
624 WREG32(GB_BACKEND_MAP, tmp);
626 cgts_tcc_disable = 0xffff0000;
627 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
628 cgts_tcc_disable &= ~(1 << (16 + i));
629 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
630 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
631 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
632 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
634 /* reprogram the shader complex */
635 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
636 for (i = 0; i < 16; i++)
637 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
638 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
640 /* set HW defaults for 3D engine */
641 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
643 sx_debug_1 = RREG32(SX_DEBUG_1);
644 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
645 WREG32(SX_DEBUG_1, sx_debug_1);
647 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
648 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
649 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
650 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
652 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
654 /* need to be explicitly zero-ed */
655 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
656 WREG32(SQ_LSTMP_RING_BASE, 0);
657 WREG32(SQ_HSTMP_RING_BASE, 0);
658 WREG32(SQ_ESTMP_RING_BASE, 0);
659 WREG32(SQ_GSTMP_RING_BASE, 0);
660 WREG32(SQ_VSTMP_RING_BASE, 0);
661 WREG32(SQ_PSTMP_RING_BASE, 0);
663 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
665 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
666 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
667 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
669 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
670 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
671 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
674 WREG32(VGT_NUM_INSTANCES, 1);
676 WREG32(CP_PERFMON_CNTL, 0);
678 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
679 FETCH_FIFO_HIWATER(0x4) |
680 DONE_FIFO_HIWATER(0xe0) |
681 ALU_UPDATE_FIFO_HIWATER(0x8)));
683 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
684 WREG32(SQ_CONFIG, (VC_ENABLE |
689 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
691 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
692 FORCE_EOV_MAX_REZ_CNT(255)));
694 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
695 AUTO_INVLD_EN(ES_AND_GS_AUTO));
697 WREG32(VGT_GS_VERTEX_REUSE, 16);
698 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
700 WREG32(CB_PERF_CTR0_SEL_0, 0);
701 WREG32(CB_PERF_CTR0_SEL_1, 0);
702 WREG32(CB_PERF_CTR1_SEL_0, 0);
703 WREG32(CB_PERF_CTR1_SEL_1, 0);
704 WREG32(CB_PERF_CTR2_SEL_0, 0);
705 WREG32(CB_PERF_CTR2_SEL_1, 0);
706 WREG32(CB_PERF_CTR3_SEL_0, 0);
707 WREG32(CB_PERF_CTR3_SEL_1, 0);
709 tmp = RREG32(HDP_MISC_CNTL);
710 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
711 WREG32(HDP_MISC_CNTL, tmp);
713 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
714 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
716 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
724 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
726 /* flush hdp cache */
727 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
729 /* bits 0-7 are the VM contexts0-7 */
730 WREG32(VM_INVALIDATE_REQUEST, 1);
733 static int cayman_pcie_gart_enable(struct radeon_device *rdev)
737 if (rdev->gart.robj == NULL) {
738 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
741 r = radeon_gart_table_vram_pin(rdev);
744 radeon_gart_restore(rdev);
745 /* Setup TLB control */
746 WREG32(MC_VM_MX_L1_TLB_CNTL,
749 ENABLE_L1_FRAGMENT_PROCESSING |
750 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
751 ENABLE_ADVANCED_DRIVER_MODEL |
752 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
754 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
755 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
756 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
757 EFFECTIVE_L2_QUEUE_SIZE(7) |
758 CONTEXT1_IDENTITY_ACCESS_MODE(1));
759 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
760 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
761 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
763 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
764 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
765 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
766 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
767 (u32)(rdev->dummy_page.addr >> 12));
768 WREG32(VM_CONTEXT0_CNTL2, 0);
769 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
770 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
776 /* empty context1-7 */
777 /* Assign the pt base to something valid for now; the pts used for
778 * the VMs are determined by the application and setup and assigned
779 * on the fly in the vm part of radeon_gart.c
781 for (i = 1; i < 8; i++) {
782 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
783 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
784 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
785 rdev->gart.table_addr >> 12);
788 /* enable context1-7 */
789 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
790 (u32)(rdev->dummy_page.addr >> 12));
791 WREG32(VM_CONTEXT1_CNTL2, 4);
792 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
793 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
794 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
795 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
796 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
797 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
798 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
799 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
800 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
801 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
802 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
803 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
804 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
806 cayman_pcie_gart_tlb_flush(rdev);
807 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
808 (unsigned)(rdev->mc.gtt_size >> 20),
809 (unsigned long long)rdev->gart.table_addr);
810 rdev->gart.ready = true;
814 static void cayman_pcie_gart_disable(struct radeon_device *rdev)
816 /* Disable all tables */
817 WREG32(VM_CONTEXT0_CNTL, 0);
818 WREG32(VM_CONTEXT1_CNTL, 0);
819 /* Setup TLB control */
820 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
821 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
822 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
824 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
825 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
826 EFFECTIVE_L2_QUEUE_SIZE(7) |
827 CONTEXT1_IDENTITY_ACCESS_MODE(1));
828 WREG32(VM_L2_CNTL2, 0);
829 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
830 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
831 radeon_gart_table_vram_unpin(rdev);
834 static void cayman_pcie_gart_fini(struct radeon_device *rdev)
836 cayman_pcie_gart_disable(rdev);
837 radeon_gart_table_vram_free(rdev);
838 radeon_gart_fini(rdev);
841 void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
842 int ring, u32 cp_int_cntl)
844 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
846 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
847 WREG32(CP_INT_CNTL, cp_int_cntl);
853 void cayman_fence_ring_emit(struct radeon_device *rdev,
854 struct radeon_fence *fence)
856 struct radeon_ring *ring = &rdev->ring[fence->ring];
857 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
859 /* flush read cache over gart for this vmid */
860 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
861 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
862 radeon_ring_write(ring, 0);
863 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
864 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
865 radeon_ring_write(ring, 0xFFFFFFFF);
866 radeon_ring_write(ring, 0);
867 radeon_ring_write(ring, 10); /* poll interval */
868 /* EVENT_WRITE_EOP - flush caches, send int */
869 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
870 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
871 radeon_ring_write(ring, addr & 0xffffffff);
872 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
873 radeon_ring_write(ring, fence->seq);
874 radeon_ring_write(ring, 0);
877 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
879 struct radeon_ring *ring = &rdev->ring[ib->ring];
881 /* set to DX10/11 mode */
882 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
883 radeon_ring_write(ring, 1);
885 if (ring->rptr_save_reg) {
886 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
887 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
888 radeon_ring_write(ring, ((ring->rptr_save_reg -
889 PACKET3_SET_CONFIG_REG_START) >> 2));
890 radeon_ring_write(ring, next_rptr);
893 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
894 radeon_ring_write(ring,
898 (ib->gpu_addr & 0xFFFFFFFC));
899 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
900 radeon_ring_write(ring, ib->length_dw |
901 (ib->vm ? (ib->vm->id << 24) : 0));
903 /* flush read cache over gart for this vmid */
904 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
905 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
906 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
907 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
908 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
909 radeon_ring_write(ring, 0xFFFFFFFF);
910 radeon_ring_write(ring, 0);
911 radeon_ring_write(ring, 10); /* poll interval */
914 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
917 WREG32(CP_ME_CNTL, 0);
919 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
920 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
921 WREG32(SCRATCH_UMSK, 0);
922 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
926 static int cayman_cp_load_microcode(struct radeon_device *rdev)
928 const __be32 *fw_data;
931 if (!rdev->me_fw || !rdev->pfp_fw)
934 cayman_cp_enable(rdev, false);
936 fw_data = (const __be32 *)rdev->pfp_fw->data;
937 WREG32(CP_PFP_UCODE_ADDR, 0);
938 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
939 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
940 WREG32(CP_PFP_UCODE_ADDR, 0);
942 fw_data = (const __be32 *)rdev->me_fw->data;
943 WREG32(CP_ME_RAM_WADDR, 0);
944 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
945 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
947 WREG32(CP_PFP_UCODE_ADDR, 0);
948 WREG32(CP_ME_RAM_WADDR, 0);
949 WREG32(CP_ME_RAM_RADDR, 0);
953 static int cayman_cp_start(struct radeon_device *rdev)
955 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
958 r = radeon_ring_lock(rdev, ring, 7);
960 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
963 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
964 radeon_ring_write(ring, 0x1);
965 radeon_ring_write(ring, 0x0);
966 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
967 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
968 radeon_ring_write(ring, 0);
969 radeon_ring_write(ring, 0);
970 radeon_ring_unlock_commit(rdev, ring);
972 cayman_cp_enable(rdev, true);
974 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
976 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
980 /* setup clear context state */
981 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
982 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
984 for (i = 0; i < cayman_default_size; i++)
985 radeon_ring_write(ring, cayman_default_state[i]);
987 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
988 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
990 /* set clear context state */
991 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
992 radeon_ring_write(ring, 0);
994 /* SQ_VTX_BASE_VTX_LOC */
995 radeon_ring_write(ring, 0xc0026f00);
996 radeon_ring_write(ring, 0x00000000);
997 radeon_ring_write(ring, 0x00000000);
998 radeon_ring_write(ring, 0x00000000);
1001 radeon_ring_write(ring, 0xc0036f00);
1002 radeon_ring_write(ring, 0x00000bc4);
1003 radeon_ring_write(ring, 0xffffffff);
1004 radeon_ring_write(ring, 0xffffffff);
1005 radeon_ring_write(ring, 0xffffffff);
1007 radeon_ring_write(ring, 0xc0026900);
1008 radeon_ring_write(ring, 0x00000316);
1009 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1010 radeon_ring_write(ring, 0x00000010); /* */
1012 radeon_ring_unlock_commit(rdev, ring);
1014 /* XXX init other rings */
1019 static void cayman_cp_fini(struct radeon_device *rdev)
1021 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1022 cayman_cp_enable(rdev, false);
1023 radeon_ring_fini(rdev, ring);
1024 radeon_scratch_free(rdev, ring->rptr_save_reg);
1027 static int cayman_cp_resume(struct radeon_device *rdev)
1029 static const int ridx[] = {
1030 RADEON_RING_TYPE_GFX_INDEX,
1031 CAYMAN_RING_TYPE_CP1_INDEX,
1032 CAYMAN_RING_TYPE_CP2_INDEX
1034 static const unsigned cp_rb_cntl[] = {
1039 static const unsigned cp_rb_rptr_addr[] = {
1044 static const unsigned cp_rb_rptr_addr_hi[] = {
1045 CP_RB0_RPTR_ADDR_HI,
1046 CP_RB1_RPTR_ADDR_HI,
1049 static const unsigned cp_rb_base[] = {
1054 struct radeon_ring *ring;
1057 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1058 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1064 RREG32(GRBM_SOFT_RESET);
1066 WREG32(GRBM_SOFT_RESET, 0);
1067 RREG32(GRBM_SOFT_RESET);
1069 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1070 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1072 /* Set the write pointer delay */
1073 WREG32(CP_RB_WPTR_DELAY, 0);
1075 WREG32(CP_DEBUG, (1 << 27));
1077 /* set the wb address whether it's enabled or not */
1078 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1079 WREG32(SCRATCH_UMSK, 0xff);
1081 for (i = 0; i < 3; ++i) {
1085 /* Set ring buffer size */
1086 ring = &rdev->ring[ridx[i]];
1087 rb_cntl = drm_order(ring->ring_size / 8);
1088 rb_cntl |= drm_order(RADEON_GPU_PAGE_SIZE/8) << 8;
1090 rb_cntl |= BUF_SWAP_32BIT;
1092 WREG32(cp_rb_cntl[i], rb_cntl);
1094 /* set the wb address whether it's enabled or not */
1095 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1096 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1097 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1100 /* set the rb base addr, this causes an internal reset of ALL rings */
1101 for (i = 0; i < 3; ++i) {
1102 ring = &rdev->ring[ridx[i]];
1103 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1106 for (i = 0; i < 3; ++i) {
1107 /* Initialize the ring buffer's read and write pointers */
1108 ring = &rdev->ring[ridx[i]];
1109 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
1111 ring->rptr = ring->wptr = 0;
1112 WREG32(ring->rptr_reg, ring->rptr);
1113 WREG32(ring->wptr_reg, ring->wptr);
1116 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1119 /* start the rings */
1120 cayman_cp_start(rdev);
1121 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1122 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1123 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1124 /* this only test cp0 */
1125 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1127 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1128 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1129 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1138 * Starting with R600, the GPU has an asynchronous
1139 * DMA engine. The programming model is very similar
1140 * to the 3D engine (ring buffer, IBs, etc.), but the
1141 * DMA controller has it's own packet format that is
1142 * different form the PM4 format used by the 3D engine.
1143 * It supports copying data, writing embedded data,
1144 * solid fills, and a number of other things. It also
1145 * has support for tiling/detiling of buffers.
1146 * Cayman and newer support two asynchronous DMA engines.
1149 * cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine
1151 * @rdev: radeon_device pointer
1152 * @ib: IB object to schedule
1154 * Schedule an IB in the DMA ring (cayman-SI).
1156 void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
1157 struct radeon_ib *ib)
1159 struct radeon_ring *ring = &rdev->ring[ib->ring];
1161 if (rdev->wb.enabled) {
1162 u32 next_rptr = ring->wptr + 4;
1163 while ((next_rptr & 7) != 5)
1166 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
1167 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1168 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
1169 radeon_ring_write(ring, next_rptr);
1172 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
1173 * Pad as necessary with NOPs.
1175 while ((ring->wptr & 7) != 5)
1176 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1177 radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, ib->vm ? ib->vm->id : 0, 0));
1178 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
1179 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
1184 * cayman_dma_stop - stop the async dma engines
1186 * @rdev: radeon_device pointer
1188 * Stop the async dma engines (cayman-SI).
1190 void cayman_dma_stop(struct radeon_device *rdev)
1194 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1197 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1198 rb_cntl &= ~DMA_RB_ENABLE;
1199 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);
1202 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1203 rb_cntl &= ~DMA_RB_ENABLE;
1204 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);
1206 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
1207 rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
1211 * cayman_dma_resume - setup and start the async dma engines
1213 * @rdev: radeon_device pointer
1215 * Set up the DMA ring buffers and enable them. (cayman-SI).
1216 * Returns 0 for success, error for failure.
1218 int cayman_dma_resume(struct radeon_device *rdev)
1220 struct radeon_ring *ring;
1221 u32 rb_cntl, dma_cntl, ib_cntl;
1223 u32 reg_offset, wb_offset;
1227 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
1228 RREG32(SRBM_SOFT_RESET);
1230 WREG32(SRBM_SOFT_RESET, 0);
1232 for (i = 0; i < 2; i++) {
1234 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1235 reg_offset = DMA0_REGISTER_OFFSET;
1236 wb_offset = R600_WB_DMA_RPTR_OFFSET;
1238 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1239 reg_offset = DMA1_REGISTER_OFFSET;
1240 wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;
1243 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
1244 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
1246 /* Set ring buffer size in dwords */
1247 rb_bufsz = drm_order(ring->ring_size / 4);
1248 rb_cntl = rb_bufsz << 1;
1250 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
1252 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);
1254 /* Initialize the ring buffer's read and write pointers */
1255 WREG32(DMA_RB_RPTR + reg_offset, 0);
1256 WREG32(DMA_RB_WPTR + reg_offset, 0);
1258 /* set the wb address whether it's enabled or not */
1259 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,
1260 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF);
1261 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,
1262 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
1264 if (rdev->wb.enabled)
1265 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
1267 WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);
1269 /* enable DMA IBs */
1270 ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE;
1272 ib_cntl |= DMA_IB_SWAP_ENABLE;
1274 WREG32(DMA_IB_CNTL + reg_offset, ib_cntl);
1276 dma_cntl = RREG32(DMA_CNTL + reg_offset);
1277 dma_cntl &= ~CTXEMPTY_INT_ENABLE;
1278 WREG32(DMA_CNTL + reg_offset, dma_cntl);
1281 WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);
1283 ring->rptr = RREG32(DMA_RB_RPTR + reg_offset) >> 2;
1285 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);
1289 r = radeon_ring_test(rdev, ring->idx, ring);
1291 ring->ready = false;
1296 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1302 * cayman_dma_fini - tear down the async dma engines
1304 * @rdev: radeon_device pointer
1306 * Stop the async dma engines and free the rings (cayman-SI).
1308 void cayman_dma_fini(struct radeon_device *rdev)
1310 cayman_dma_stop(rdev);
1311 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
1312 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
1315 static u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
1321 tmp = RREG32(GRBM_STATUS);
1322 if (tmp & (PA_BUSY | SC_BUSY |
1324 TA_BUSY | VGT_BUSY |
1326 GDS_BUSY | SPI_BUSY |
1327 IA_BUSY | IA_BUSY_NO_DMA))
1328 reset_mask |= RADEON_RESET_GFX;
1330 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1331 CP_BUSY | CP_COHERENCY_BUSY))
1332 reset_mask |= RADEON_RESET_CP;
1334 if (tmp & GRBM_EE_BUSY)
1335 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1337 /* DMA_STATUS_REG 0 */
1338 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1339 if (!(tmp & DMA_IDLE))
1340 reset_mask |= RADEON_RESET_DMA;
1342 /* DMA_STATUS_REG 1 */
1343 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1344 if (!(tmp & DMA_IDLE))
1345 reset_mask |= RADEON_RESET_DMA1;
1348 tmp = RREG32(SRBM_STATUS2);
1350 reset_mask |= RADEON_RESET_DMA;
1352 if (tmp & DMA1_BUSY)
1353 reset_mask |= RADEON_RESET_DMA1;
1356 tmp = RREG32(SRBM_STATUS);
1357 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1358 reset_mask |= RADEON_RESET_RLC;
1361 reset_mask |= RADEON_RESET_IH;
1364 reset_mask |= RADEON_RESET_SEM;
1366 if (tmp & GRBM_RQ_PENDING)
1367 reset_mask |= RADEON_RESET_GRBM;
1370 reset_mask |= RADEON_RESET_VMC;
1372 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1373 MCC_BUSY | MCD_BUSY))
1374 reset_mask |= RADEON_RESET_MC;
1376 if (evergreen_is_display_hung(rdev))
1377 reset_mask |= RADEON_RESET_DISPLAY;
1380 tmp = RREG32(VM_L2_STATUS);
1382 reset_mask |= RADEON_RESET_VMC;
1384 /* Skip MC reset as it's mostly likely not hung, just busy */
1385 if (reset_mask & RADEON_RESET_MC) {
1386 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1387 reset_mask &= ~RADEON_RESET_MC;
1393 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1395 struct evergreen_mc_save save;
1396 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1399 if (reset_mask == 0)
1402 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1404 evergreen_print_gpu_status_regs(rdev);
1405 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1407 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1409 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1411 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1414 /* Disable CP parsing/prefetching */
1415 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1417 if (reset_mask & RADEON_RESET_DMA) {
1419 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1420 tmp &= ~DMA_RB_ENABLE;
1421 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1424 if (reset_mask & RADEON_RESET_DMA1) {
1426 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1427 tmp &= ~DMA_RB_ENABLE;
1428 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1433 evergreen_mc_stop(rdev, &save);
1434 if (evergreen_mc_wait_for_idle(rdev)) {
1435 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1438 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1439 grbm_soft_reset = SOFT_RESET_CB |
1453 if (reset_mask & RADEON_RESET_CP) {
1454 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1456 srbm_soft_reset |= SOFT_RESET_GRBM;
1459 if (reset_mask & RADEON_RESET_DMA)
1460 srbm_soft_reset |= SOFT_RESET_DMA;
1462 if (reset_mask & RADEON_RESET_DMA1)
1463 srbm_soft_reset |= SOFT_RESET_DMA1;
1465 if (reset_mask & RADEON_RESET_DISPLAY)
1466 srbm_soft_reset |= SOFT_RESET_DC;
1468 if (reset_mask & RADEON_RESET_RLC)
1469 srbm_soft_reset |= SOFT_RESET_RLC;
1471 if (reset_mask & RADEON_RESET_SEM)
1472 srbm_soft_reset |= SOFT_RESET_SEM;
1474 if (reset_mask & RADEON_RESET_IH)
1475 srbm_soft_reset |= SOFT_RESET_IH;
1477 if (reset_mask & RADEON_RESET_GRBM)
1478 srbm_soft_reset |= SOFT_RESET_GRBM;
1480 if (reset_mask & RADEON_RESET_VMC)
1481 srbm_soft_reset |= SOFT_RESET_VMC;
1483 if (!(rdev->flags & RADEON_IS_IGP)) {
1484 if (reset_mask & RADEON_RESET_MC)
1485 srbm_soft_reset |= SOFT_RESET_MC;
1488 if (grbm_soft_reset) {
1489 tmp = RREG32(GRBM_SOFT_RESET);
1490 tmp |= grbm_soft_reset;
1491 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1492 WREG32(GRBM_SOFT_RESET, tmp);
1493 tmp = RREG32(GRBM_SOFT_RESET);
1497 tmp &= ~grbm_soft_reset;
1498 WREG32(GRBM_SOFT_RESET, tmp);
1499 tmp = RREG32(GRBM_SOFT_RESET);
1502 if (srbm_soft_reset) {
1503 tmp = RREG32(SRBM_SOFT_RESET);
1504 tmp |= srbm_soft_reset;
1505 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1506 WREG32(SRBM_SOFT_RESET, tmp);
1507 tmp = RREG32(SRBM_SOFT_RESET);
1511 tmp &= ~srbm_soft_reset;
1512 WREG32(SRBM_SOFT_RESET, tmp);
1513 tmp = RREG32(SRBM_SOFT_RESET);
1516 /* Wait a little for things to settle down */
1519 evergreen_mc_resume(rdev, &save);
1522 evergreen_print_gpu_status_regs(rdev);
1525 int cayman_asic_reset(struct radeon_device *rdev)
1529 reset_mask = cayman_gpu_check_soft_reset(rdev);
1532 r600_set_bios_scratch_engine_hung(rdev, true);
1534 cayman_gpu_soft_reset(rdev, reset_mask);
1536 reset_mask = cayman_gpu_check_soft_reset(rdev);
1539 r600_set_bios_scratch_engine_hung(rdev, false);
1545 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1547 * @rdev: radeon_device pointer
1548 * @ring: radeon_ring structure holding ring information
1550 * Check if the GFX engine is locked up.
1551 * Returns true if the engine appears to be locked up, false if not.
1553 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1555 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1557 if (!(reset_mask & (RADEON_RESET_GFX |
1558 RADEON_RESET_COMPUTE |
1559 RADEON_RESET_CP))) {
1560 radeon_ring_lockup_update(ring);
1563 /* force CP activities */
1564 radeon_ring_force_activity(rdev, ring);
1565 return radeon_ring_test_lockup(rdev, ring);
1569 * cayman_dma_is_lockup - Check if the DMA engine is locked up
1571 * @rdev: radeon_device pointer
1572 * @ring: radeon_ring structure holding ring information
1574 * Check if the async DMA engine is locked up.
1575 * Returns true if the engine appears to be locked up, false if not.
1577 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1579 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1582 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
1583 mask = RADEON_RESET_DMA;
1585 mask = RADEON_RESET_DMA1;
1587 if (!(reset_mask & mask)) {
1588 radeon_ring_lockup_update(ring);
1591 /* force ring activities */
1592 radeon_ring_force_activity(rdev, ring);
1593 return radeon_ring_test_lockup(rdev, ring);
1596 static int cayman_startup(struct radeon_device *rdev)
1598 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1601 /* enable pcie gen2 link */
1602 evergreen_pcie_gen2_enable(rdev);
1604 if (rdev->flags & RADEON_IS_IGP) {
1605 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1606 r = ni_init_microcode(rdev);
1608 DRM_ERROR("Failed to load firmware!\n");
1613 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1614 r = ni_init_microcode(rdev);
1616 DRM_ERROR("Failed to load firmware!\n");
1621 r = ni_mc_load_microcode(rdev);
1623 DRM_ERROR("Failed to load MC firmware!\n");
1628 r = r600_vram_scratch_init(rdev);
1632 evergreen_mc_program(rdev);
1633 r = cayman_pcie_gart_enable(rdev);
1636 cayman_gpu_init(rdev);
1638 r = evergreen_blit_init(rdev);
1640 r600_blit_fini(rdev);
1641 rdev->asic->copy.copy = NULL;
1642 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1645 /* allocate rlc buffers */
1646 if (rdev->flags & RADEON_IS_IGP) {
1647 r = si_rlc_init(rdev);
1649 DRM_ERROR("Failed to init rlc BOs!\n");
1654 /* allocate wb buffer */
1655 r = radeon_wb_init(rdev);
1659 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1661 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1665 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1667 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1671 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1673 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1677 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1679 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1683 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
1685 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1690 r = r600_irq_init(rdev);
1692 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1693 radeon_irq_kms_fini(rdev);
1696 evergreen_irq_set(rdev);
1698 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1699 CP_RB0_RPTR, CP_RB0_WPTR,
1700 0, 0xfffff, RADEON_CP_PACKET2);
1704 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1705 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1706 DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
1707 DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
1708 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1712 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1713 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
1714 DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
1715 DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
1716 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1720 r = cayman_cp_load_microcode(rdev);
1723 r = cayman_cp_resume(rdev);
1727 r = cayman_dma_resume(rdev);
1731 r = radeon_ib_pool_init(rdev);
1733 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1737 r = radeon_vm_manager_init(rdev);
1739 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
1743 r = r600_audio_init(rdev);
1750 int cayman_resume(struct radeon_device *rdev)
1754 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1755 * posting will perform necessary task to bring back GPU into good
1759 atom_asic_init(rdev->mode_info.atom_context);
1761 rdev->accel_working = true;
1762 r = cayman_startup(rdev);
1764 DRM_ERROR("cayman startup failed on resume\n");
1765 rdev->accel_working = false;
1771 int cayman_suspend(struct radeon_device *rdev)
1773 r600_audio_fini(rdev);
1774 cayman_cp_enable(rdev, false);
1775 cayman_dma_stop(rdev);
1776 evergreen_irq_suspend(rdev);
1777 radeon_wb_disable(rdev);
1778 cayman_pcie_gart_disable(rdev);
1782 /* Plan is to move initialization in that function and use
1783 * helper function so that radeon_device_init pretty much
1784 * do nothing more than calling asic specific function. This
1785 * should also allow to remove a bunch of callback function
1788 int cayman_init(struct radeon_device *rdev)
1790 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1794 if (!radeon_get_bios(rdev)) {
1795 if (ASIC_IS_AVIVO(rdev))
1798 /* Must be an ATOMBIOS */
1799 if (!rdev->is_atom_bios) {
1800 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1803 r = radeon_atombios_init(rdev);
1807 /* Post card if necessary */
1808 if (!radeon_card_posted(rdev)) {
1810 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1813 DRM_INFO("GPU not posted. posting now...\n");
1814 atom_asic_init(rdev->mode_info.atom_context);
1816 /* Initialize scratch registers */
1817 r600_scratch_init(rdev);
1818 /* Initialize surface registers */
1819 radeon_surface_init(rdev);
1820 /* Initialize clocks */
1821 radeon_get_clock_info(rdev->ddev);
1823 r = radeon_fence_driver_init(rdev);
1826 /* initialize memory controller */
1827 r = evergreen_mc_init(rdev);
1830 /* Memory manager */
1831 r = radeon_bo_init(rdev);
1835 r = radeon_irq_kms_init(rdev);
1839 ring->ring_obj = NULL;
1840 r600_ring_init(rdev, ring, 1024 * 1024);
1842 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1843 ring->ring_obj = NULL;
1844 r600_ring_init(rdev, ring, 64 * 1024);
1846 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1847 ring->ring_obj = NULL;
1848 r600_ring_init(rdev, ring, 64 * 1024);
1850 rdev->ih.ring_obj = NULL;
1851 r600_ih_ring_init(rdev, 64 * 1024);
1853 r = r600_pcie_gart_init(rdev);
1857 rdev->accel_working = true;
1858 r = cayman_startup(rdev);
1860 dev_err(rdev->dev, "disabling GPU acceleration\n");
1861 cayman_cp_fini(rdev);
1862 cayman_dma_fini(rdev);
1863 r600_irq_fini(rdev);
1864 if (rdev->flags & RADEON_IS_IGP)
1866 radeon_wb_fini(rdev);
1867 radeon_ib_pool_fini(rdev);
1868 radeon_vm_manager_fini(rdev);
1869 radeon_irq_kms_fini(rdev);
1870 cayman_pcie_gart_fini(rdev);
1871 rdev->accel_working = false;
1874 /* Don't start up if the MC ucode is missing.
1875 * The default clocks and voltages before the MC ucode
1876 * is loaded are not suffient for advanced operations.
1878 * We can skip this check for TN, because there is no MC
1881 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
1882 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1889 void cayman_fini(struct radeon_device *rdev)
1891 r600_blit_fini(rdev);
1892 cayman_cp_fini(rdev);
1893 cayman_dma_fini(rdev);
1894 r600_irq_fini(rdev);
1895 if (rdev->flags & RADEON_IS_IGP)
1897 radeon_wb_fini(rdev);
1898 radeon_vm_manager_fini(rdev);
1899 radeon_ib_pool_fini(rdev);
1900 radeon_irq_kms_fini(rdev);
1901 cayman_pcie_gart_fini(rdev);
1902 r600_vram_scratch_fini(rdev);
1903 radeon_gem_fini(rdev);
1904 radeon_fence_driver_fini(rdev);
1905 radeon_bo_fini(rdev);
1906 radeon_atombios_fini(rdev);
1914 int cayman_vm_init(struct radeon_device *rdev)
1917 rdev->vm_manager.nvm = 8;
1918 /* base offset of vram pages */
1919 if (rdev->flags & RADEON_IS_IGP) {
1920 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
1922 rdev->vm_manager.vram_base_offset = tmp;
1924 rdev->vm_manager.vram_base_offset = 0;
1928 void cayman_vm_fini(struct radeon_device *rdev)
1932 #define R600_ENTRY_VALID (1 << 0)
1933 #define R600_PTE_SYSTEM (1 << 1)
1934 #define R600_PTE_SNOOPED (1 << 2)
1935 #define R600_PTE_READABLE (1 << 5)
1936 #define R600_PTE_WRITEABLE (1 << 6)
1938 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags)
1940 uint32_t r600_flags = 0;
1941 r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_ENTRY_VALID : 0;
1942 r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
1943 r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
1944 if (flags & RADEON_VM_PAGE_SYSTEM) {
1945 r600_flags |= R600_PTE_SYSTEM;
1946 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
1952 * cayman_vm_set_page - update the page tables using the CP
1954 * @rdev: radeon_device pointer
1955 * @ib: indirect buffer to fill with commands
1956 * @pe: addr of the page entry
1957 * @addr: dst addr to write into pe
1958 * @count: number of page entries to update
1959 * @incr: increase next addr by incr bytes
1960 * @flags: access flags
1962 * Update the page tables using the CP (cayman/TN).
1964 void cayman_vm_set_page(struct radeon_device *rdev,
1965 struct radeon_ib *ib,
1967 uint64_t addr, unsigned count,
1968 uint32_t incr, uint32_t flags)
1970 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
1974 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
1976 ndw = 1 + count * 2;
1980 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_ME_WRITE, ndw);
1981 ib->ptr[ib->length_dw++] = pe;
1982 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
1983 for (; ndw > 1; ndw -= 2, --count, pe += 8) {
1984 if (flags & RADEON_VM_PAGE_SYSTEM) {
1985 value = radeon_vm_map_gart(rdev, addr);
1986 value &= 0xFFFFFFFFFFFFF000ULL;
1987 } else if (flags & RADEON_VM_PAGE_VALID) {
1993 value |= r600_flags;
1994 ib->ptr[ib->length_dw++] = value;
1995 ib->ptr[ib->length_dw++] = upper_32_bits(value);
2004 /* for non-physically contiguous pages (system) */
2005 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw);
2006 ib->ptr[ib->length_dw++] = pe;
2007 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
2008 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
2009 if (flags & RADEON_VM_PAGE_SYSTEM) {
2010 value = radeon_vm_map_gart(rdev, addr);
2011 value &= 0xFFFFFFFFFFFFF000ULL;
2012 } else if (flags & RADEON_VM_PAGE_VALID) {
2018 value |= r600_flags;
2019 ib->ptr[ib->length_dw++] = value;
2020 ib->ptr[ib->length_dw++] = upper_32_bits(value);
2023 while (ib->length_dw & 0x7)
2024 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
2029 * cayman_vm_flush - vm flush using the CP
2031 * @rdev: radeon_device pointer
2033 * Update the page table base and flush the VM TLB
2034 * using the CP (cayman-si).
2036 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
2038 struct radeon_ring *ring = &rdev->ring[ridx];
2043 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
2044 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
2046 /* flush hdp cache */
2047 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2048 radeon_ring_write(ring, 0x1);
2050 /* bits 0-7 are the VM contexts0-7 */
2051 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
2052 radeon_ring_write(ring, 1 << vm->id);
2054 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2055 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2056 radeon_ring_write(ring, 0x0);
2059 void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
2061 struct radeon_ring *ring = &rdev->ring[ridx];
2066 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2067 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
2068 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
2070 /* flush hdp cache */
2071 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2072 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
2073 radeon_ring_write(ring, 1);
2075 /* bits 0-7 are the VM contexts0-7 */
2076 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2077 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
2078 radeon_ring_write(ring, 1 << vm->id);