2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Christian König
27 #include <linux/hdmi.h>
29 #include <drm/radeon_drm.h>
31 #include "radeon_asic.h"
32 #include "evergreend.h"
35 extern void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder);
36 extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder);
37 extern void dce6_afmt_select_pin(struct drm_encoder *encoder);
38 extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
39 struct drm_display_mode *mode);
41 /* enable the audio stream */
42 static void dce4_audio_enable(struct radeon_device *rdev,
43 struct r600_audio_pin *pin,
46 u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
54 tmp |= PIN0_AUDIO_ENABLED;
56 tmp |= PIN1_AUDIO_ENABLED;
58 tmp |= PIN2_AUDIO_ENABLED;
60 tmp |= PIN3_AUDIO_ENABLED;
62 tmp &= ~(AUDIO_ENABLED |
69 WREG32(AZ_HOT_PLUG_CONTROL, tmp);
73 * update the N and CTS parameters for a given pixel clock rate
75 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
77 struct drm_device *dev = encoder->dev;
78 struct radeon_device *rdev = dev->dev_private;
79 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
80 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
81 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
82 uint32_t offset = dig->afmt->offset;
84 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
85 WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
87 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
88 WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
90 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
91 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
94 static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
95 struct drm_display_mode *mode)
97 struct radeon_device *rdev = encoder->dev->dev_private;
98 struct drm_connector *connector;
99 struct radeon_connector *radeon_connector = NULL;
102 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
103 if (connector->encoder == encoder) {
104 radeon_connector = to_radeon_connector(connector);
109 if (!radeon_connector) {
110 DRM_ERROR("Couldn't find encoder's connector\n");
114 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
115 if (connector->latency_present[1])
116 tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
117 AUDIO_LIPSYNC(connector->audio_latency[1]);
119 tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
121 if (connector->latency_present[0])
122 tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
123 AUDIO_LIPSYNC(connector->audio_latency[0]);
125 tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
127 WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
130 static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
132 struct radeon_device *rdev = encoder->dev->dev_private;
133 struct drm_connector *connector;
134 struct radeon_connector *radeon_connector = NULL;
139 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
140 if (connector->encoder == encoder) {
141 radeon_connector = to_radeon_connector(connector);
146 if (!radeon_connector) {
147 DRM_ERROR("Couldn't find encoder's connector\n");
151 sad_count = drm_edid_to_speaker_allocation(radeon_connector_edid(connector), &sadb);
153 DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
157 /* program the speaker allocation */
158 tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
159 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
161 tmp |= HDMI_CONNECTION;
163 tmp |= SPEAKER_ALLOCATION(sadb[0]);
165 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
166 WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
171 static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder)
173 struct radeon_device *rdev = encoder->dev->dev_private;
174 struct drm_connector *connector;
175 struct radeon_connector *radeon_connector = NULL;
176 struct cea_sad *sads;
179 static const u16 eld_reg_to_type[][2] = {
180 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
181 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
182 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
183 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
184 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
185 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
186 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
187 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
188 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
189 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
190 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
191 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
194 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
195 if (connector->encoder == encoder) {
196 radeon_connector = to_radeon_connector(connector);
201 if (!radeon_connector) {
202 DRM_ERROR("Couldn't find encoder's connector\n");
206 sad_count = drm_edid_to_sad(radeon_connector_edid(connector), &sads);
207 if (sad_count <= 0) {
208 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
213 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
216 int max_channels = -1;
219 for (j = 0; j < sad_count; j++) {
220 struct cea_sad *sad = &sads[j];
222 if (sad->format == eld_reg_to_type[i][1]) {
223 if (sad->channels > max_channels) {
224 value = MAX_CHANNELS(sad->channels) |
225 DESCRIPTOR_BYTE_2(sad->byte2) |
226 SUPPORTED_FREQUENCIES(sad->freq);
227 max_channels = sad->channels;
230 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
231 stereo_freqs |= sad->freq;
237 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
239 WREG32(eld_reg_to_type[i][0], value);
246 * build a HDMI Video Info Frame
248 static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
249 void *buffer, size_t size)
251 struct drm_device *dev = encoder->dev;
252 struct radeon_device *rdev = dev->dev_private;
253 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
254 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
255 uint32_t offset = dig->afmt->offset;
256 uint8_t *frame = buffer + 3;
257 uint8_t *header = buffer;
259 WREG32(AFMT_AVI_INFO0 + offset,
260 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
261 WREG32(AFMT_AVI_INFO1 + offset,
262 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
263 WREG32(AFMT_AVI_INFO2 + offset,
264 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
265 WREG32(AFMT_AVI_INFO3 + offset,
266 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
269 static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)
271 struct drm_device *dev = encoder->dev;
272 struct radeon_device *rdev = dev->dev_private;
273 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
274 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
275 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
276 u32 base_rate = 24000;
277 u32 max_ratio = clock / base_rate;
279 u32 dto_modulo = clock;
283 if (!dig || !dig->afmt)
286 if (ASIC_IS_DCE6(rdev)) {
287 dto_phase = 24 * 1000;
289 if (max_ratio >= 8) {
290 dto_phase = 192 * 1000;
292 } else if (max_ratio >= 4) {
293 dto_phase = 96 * 1000;
295 } else if (max_ratio >= 2) {
296 dto_phase = 48 * 1000;
299 dto_phase = 24 * 1000;
302 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
303 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
304 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
307 /* XXX two dtos; generally use dto0 for hdmi */
308 /* Express [24MHz / target pixel clock] as an exact rational
309 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
310 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
312 WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
313 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
314 WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
319 * update the info frames with the data from the current display mode
321 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
323 struct drm_device *dev = encoder->dev;
324 struct radeon_device *rdev = dev->dev_private;
325 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
326 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
327 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
328 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
329 struct hdmi_avi_infoframe frame;
335 if (!dig || !dig->afmt)
338 /* Silent, r600_hdmi_enable will raise WARN for us */
339 if (!dig->afmt->enabled)
341 offset = dig->afmt->offset;
343 /* hdmi deep color mode general control packets setup, if bpc > 8 */
345 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
346 bpc = radeon_crtc->bpc;
349 /* disable audio prior to setting up hw */
350 if (ASIC_IS_DCE6(rdev)) {
351 dig->afmt->pin = dce6_audio_get_pin(rdev);
352 dce6_audio_enable(rdev, dig->afmt->pin, 0);
354 dig->afmt->pin = r600_audio_get_pin(rdev);
355 dce4_audio_enable(rdev, dig->afmt->pin, 0);
358 evergreen_audio_set_dto(encoder, mode->clock);
360 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
361 HDMI_NULL_SEND); /* send null packets when required */
363 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
365 val = RREG32(HDMI_CONTROL + offset);
366 val &= ~HDMI_DEEP_COLOR_ENABLE;
367 val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;
375 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
376 connector->name, bpc);
379 val |= HDMI_DEEP_COLOR_ENABLE;
380 val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);
381 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
385 val |= HDMI_DEEP_COLOR_ENABLE;
386 val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);
387 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
392 WREG32(HDMI_CONTROL + offset, val);
394 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
395 HDMI_NULL_SEND | /* send null packets when required */
396 HDMI_GC_SEND | /* send general control packets */
397 HDMI_GC_CONT); /* send general control packets every frame */
399 WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
400 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
401 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
403 WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
404 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
406 WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
407 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
409 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
411 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
412 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
413 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
415 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
416 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
418 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
421 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
422 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
424 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
425 HDMI_ACR_SOURCE | /* select SW CTS value */
426 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
428 evergreen_hdmi_update_ACR(encoder, mode->clock);
430 WREG32(AFMT_60958_0 + offset,
431 AFMT_60958_CS_CHANNEL_NUMBER_L(1));
433 WREG32(AFMT_60958_1 + offset,
434 AFMT_60958_CS_CHANNEL_NUMBER_R(2));
436 WREG32(AFMT_60958_2 + offset,
437 AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
438 AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
439 AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
440 AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
441 AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
442 AFMT_60958_CS_CHANNEL_NUMBER_7(8));
444 if (ASIC_IS_DCE6(rdev)) {
445 dce6_afmt_write_speaker_allocation(encoder);
447 dce4_afmt_write_speaker_allocation(encoder);
450 WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
451 AFMT_AUDIO_CHANNEL_ENABLE(0xff));
453 /* fglrx sets 0x40 in 0x5f80 here */
455 if (ASIC_IS_DCE6(rdev)) {
456 dce6_afmt_select_pin(encoder);
457 dce6_afmt_write_sad_regs(encoder);
458 dce6_afmt_write_latency_fields(encoder, mode);
460 evergreen_hdmi_write_sad_regs(encoder);
461 dce4_afmt_write_latency_fields(encoder, mode);
464 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
466 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
470 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
472 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
476 evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
478 WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
479 HDMI_AVI_INFO_SEND | /* enable AVI info frames */
480 HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
482 WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
483 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
484 ~HDMI_AVI_INFO_LINE_MASK);
486 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
487 AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
489 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
490 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
491 WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
492 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
493 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
495 /* enable audio after to setting up hw */
496 if (ASIC_IS_DCE6(rdev))
497 dce6_audio_enable(rdev, dig->afmt->pin, 1);
499 dce4_audio_enable(rdev, dig->afmt->pin, 0xf);
502 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
504 struct drm_device *dev = encoder->dev;
505 struct radeon_device *rdev = dev->dev_private;
506 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
507 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
509 if (!dig || !dig->afmt)
512 /* Silent, r600_hdmi_enable will raise WARN for us */
513 if (enable && dig->afmt->enabled)
515 if (!enable && !dig->afmt->enabled)
518 if (!enable && dig->afmt->pin) {
519 if (ASIC_IS_DCE6(rdev))
520 dce6_audio_enable(rdev, dig->afmt->pin, 0);
522 dce4_audio_enable(rdev, dig->afmt->pin, 0);
523 dig->afmt->pin = NULL;
526 dig->afmt->enabled = enable;
528 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
529 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);