2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
30 #include "radeon_audio.h"
32 #include <linux/backlight.h>
34 extern int atom_debug;
37 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
42 if (rdev->family >= CHIP_R600)
43 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
45 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
47 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
48 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
50 return backlight_level;
54 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
59 if (rdev->family >= CHIP_R600)
60 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
62 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
64 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
65 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
66 ATOM_S2_CURRENT_BL_LEVEL_MASK);
68 if (rdev->family >= CHIP_R600)
69 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
71 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
75 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
77 struct drm_device *dev = radeon_encoder->base.dev;
78 struct radeon_device *rdev = dev->dev_private;
80 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
83 return radeon_atom_get_backlight_level_from_reg(rdev);
87 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
89 struct drm_encoder *encoder = &radeon_encoder->base;
90 struct drm_device *dev = radeon_encoder->base.dev;
91 struct radeon_device *rdev = dev->dev_private;
92 struct radeon_encoder_atom_dig *dig;
93 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
96 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
99 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
100 radeon_encoder->enc_priv) {
101 dig = radeon_encoder->enc_priv;
102 dig->backlight_level = level;
103 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
105 switch (radeon_encoder->encoder_id) {
106 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
107 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
108 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
109 if (dig->backlight_level == 0) {
110 args.ucAction = ATOM_LCD_BLOFF;
111 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
113 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
114 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
115 args.ucAction = ATOM_LCD_BLON;
116 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
120 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
123 if (dig->backlight_level == 0)
124 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
127 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
136 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
138 static u8 radeon_atom_bl_level(struct backlight_device *bd)
142 /* Convert brightness to hardware level */
143 if (bd->props.brightness < 0)
145 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
146 level = RADEON_MAX_BL_LEVEL;
148 level = bd->props.brightness;
153 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
155 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
156 struct radeon_encoder *radeon_encoder = pdata->encoder;
158 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
163 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
165 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
166 struct radeon_encoder *radeon_encoder = pdata->encoder;
167 struct drm_device *dev = radeon_encoder->base.dev;
168 struct radeon_device *rdev = dev->dev_private;
170 return radeon_atom_get_backlight_level_from_reg(rdev);
173 static const struct backlight_ops radeon_atom_backlight_ops = {
174 .get_brightness = radeon_atom_backlight_get_brightness,
175 .update_status = radeon_atom_backlight_update_status,
178 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
179 struct drm_connector *drm_connector)
181 struct drm_device *dev = radeon_encoder->base.dev;
182 struct radeon_device *rdev = dev->dev_private;
183 struct backlight_device *bd;
184 struct backlight_properties props;
185 struct radeon_backlight_privdata *pdata;
186 struct radeon_encoder_atom_dig *dig;
189 /* Mac laptops with multiple GPUs use the gmux driver for backlight
190 * so don't register a backlight device
192 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
193 (rdev->pdev->device == 0x6741))
196 if (!radeon_encoder->enc_priv)
199 if (!rdev->is_atom_bios)
202 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
205 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
207 DRM_ERROR("Memory allocation failed\n");
211 memset(&props, 0, sizeof(props));
212 props.max_brightness = RADEON_MAX_BL_LEVEL;
213 props.type = BACKLIGHT_RAW;
214 snprintf(bl_name, sizeof(bl_name),
215 "radeon_bl%d", dev->primary->index);
216 bd = backlight_device_register(bl_name, drm_connector->kdev,
217 pdata, &radeon_atom_backlight_ops, &props);
219 DRM_ERROR("Backlight registration failed\n");
223 pdata->encoder = radeon_encoder;
225 dig = radeon_encoder->enc_priv;
228 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
229 /* Set a reasonable default here if the level is 0 otherwise
230 * fbdev will attempt to turn the backlight on after console
231 * unblanking and it will try and restore 0 which turns the backlight
234 if (bd->props.brightness == 0)
235 bd->props.brightness = RADEON_MAX_BL_LEVEL;
236 bd->props.power = FB_BLANK_UNBLANK;
237 backlight_update_status(bd);
239 DRM_INFO("radeon atom DIG backlight initialized\n");
240 rdev->mode_info.bl_encoder = radeon_encoder;
249 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
251 struct drm_device *dev = radeon_encoder->base.dev;
252 struct radeon_device *rdev = dev->dev_private;
253 struct backlight_device *bd = NULL;
254 struct radeon_encoder_atom_dig *dig;
256 if (!radeon_encoder->enc_priv)
259 if (!rdev->is_atom_bios)
262 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
265 dig = radeon_encoder->enc_priv;
270 struct radeon_legacy_backlight_privdata *pdata;
272 pdata = bl_get_data(bd);
273 backlight_device_unregister(bd);
276 DRM_INFO("radeon atom LVDS backlight unloaded\n");
280 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
282 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
286 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
292 /* evil but including atombios.h is much worse */
293 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
294 struct drm_display_mode *mode);
296 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
297 const struct drm_display_mode *mode,
298 struct drm_display_mode *adjusted_mode)
300 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
301 struct drm_device *dev = encoder->dev;
302 struct radeon_device *rdev = dev->dev_private;
304 /* set the active encoder to connector routing */
305 radeon_encoder_set_active_device(encoder);
306 drm_mode_set_crtcinfo(adjusted_mode, 0);
309 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
310 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
311 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
313 /* vertical FP must be at least 1 */
314 if (mode->crtc_vsync_start == mode->crtc_vdisplay)
315 adjusted_mode->crtc_vsync_start++;
317 /* get the native mode for scaling */
318 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
319 radeon_panel_mode_fixup(encoder, adjusted_mode);
320 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
321 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
323 if (tv_dac->tv_std == TV_STD_NTSC ||
324 tv_dac->tv_std == TV_STD_NTSC_J ||
325 tv_dac->tv_std == TV_STD_PAL_M)
326 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
328 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
330 } else if (radeon_encoder->rmx_type != RMX_OFF) {
331 radeon_panel_mode_fixup(encoder, adjusted_mode);
334 if (ASIC_IS_DCE3(rdev) &&
335 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
336 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
337 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
338 radeon_dp_set_link_config(connector, adjusted_mode);
345 atombios_dac_setup(struct drm_encoder *encoder, int action)
347 struct drm_device *dev = encoder->dev;
348 struct radeon_device *rdev = dev->dev_private;
349 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
350 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
352 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
354 memset(&args, 0, sizeof(args));
356 switch (radeon_encoder->encoder_id) {
357 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
358 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
359 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
361 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
362 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
363 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
367 args.ucAction = action;
369 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
370 args.ucDacStandard = ATOM_DAC1_PS2;
371 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
372 args.ucDacStandard = ATOM_DAC1_CV;
374 switch (dac_info->tv_std) {
377 case TV_STD_SCART_PAL:
380 args.ucDacStandard = ATOM_DAC1_PAL;
386 args.ucDacStandard = ATOM_DAC1_NTSC;
390 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
392 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
397 atombios_tv_setup(struct drm_encoder *encoder, int action)
399 struct drm_device *dev = encoder->dev;
400 struct radeon_device *rdev = dev->dev_private;
401 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
402 TV_ENCODER_CONTROL_PS_ALLOCATION args;
404 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
406 memset(&args, 0, sizeof(args));
408 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
410 args.sTVEncoder.ucAction = action;
412 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
413 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
415 switch (dac_info->tv_std) {
417 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
420 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
423 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
426 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
429 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
431 case TV_STD_SCART_PAL:
432 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
435 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
438 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
441 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
446 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
448 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
452 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
457 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
458 bpc = radeon_crtc->bpc;
463 return PANEL_BPC_UNDEFINE;
465 return PANEL_6BIT_PER_COLOR;
468 return PANEL_8BIT_PER_COLOR;
470 return PANEL_10BIT_PER_COLOR;
472 return PANEL_12BIT_PER_COLOR;
474 return PANEL_16BIT_PER_COLOR;
478 union dvo_encoder_control {
479 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
480 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
481 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
482 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
486 atombios_dvo_setup(struct drm_encoder *encoder, int action)
488 struct drm_device *dev = encoder->dev;
489 struct radeon_device *rdev = dev->dev_private;
490 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
491 union dvo_encoder_control args;
492 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
495 memset(&args, 0, sizeof(args));
497 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
500 /* some R4xx chips have the wrong frev */
501 if (rdev->family <= CHIP_RV410)
509 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
511 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
512 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
514 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
518 args.dvo.sDVOEncoder.ucAction = action;
519 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
520 /* DFP1, CRT1, TV1 depending on the type of port */
521 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
523 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
524 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
528 args.dvo_v3.ucAction = action;
529 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
530 args.dvo_v3.ucDVOConfig = 0; /* XXX */
534 args.dvo_v4.ucAction = action;
535 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
536 args.dvo_v4.ucDVOConfig = 0; /* XXX */
537 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
540 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
545 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
549 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
552 union lvds_encoder_control {
553 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
554 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
558 atombios_digital_setup(struct drm_encoder *encoder, int action)
560 struct drm_device *dev = encoder->dev;
561 struct radeon_device *rdev = dev->dev_private;
562 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
563 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
564 union lvds_encoder_control args;
566 int hdmi_detected = 0;
572 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
575 memset(&args, 0, sizeof(args));
577 switch (radeon_encoder->encoder_id) {
578 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
579 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
581 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
582 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
583 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
585 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
586 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
587 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
589 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
593 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
602 args.v1.ucAction = action;
604 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
605 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
606 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
607 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
608 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
609 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
610 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
613 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
614 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
615 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
616 /*if (pScrn->rgbBits == 8) */
617 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
623 args.v2.ucAction = action;
625 if (dig->coherent_mode)
626 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
629 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
630 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
631 args.v2.ucTruncate = 0;
632 args.v2.ucSpatial = 0;
633 args.v2.ucTemporal = 0;
635 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
636 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
637 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
638 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
639 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
640 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
641 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
643 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
644 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
645 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
646 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
647 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
648 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
652 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
653 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
654 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
658 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
663 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
667 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
671 atombios_get_encoder_mode(struct drm_encoder *encoder)
673 struct drm_device *dev = encoder->dev;
674 struct radeon_device *rdev = dev->dev_private;
675 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
676 struct drm_connector *connector;
677 struct radeon_connector *radeon_connector;
678 struct radeon_connector_atom_dig *dig_connector;
679 struct radeon_encoder_atom_dig *dig_enc;
681 if (radeon_encoder_is_digital(encoder)) {
682 dig_enc = radeon_encoder->enc_priv;
683 if (dig_enc->active_mst_links)
684 return ATOM_ENCODER_MODE_DP_MST;
686 if (radeon_encoder->is_mst_encoder || radeon_encoder->offset)
687 return ATOM_ENCODER_MODE_DP_MST;
688 /* dp bridges are always DP */
689 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
690 return ATOM_ENCODER_MODE_DP;
692 /* DVO is always DVO */
693 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
694 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
695 return ATOM_ENCODER_MODE_DVO;
697 connector = radeon_get_connector_for_encoder(encoder);
698 /* if we don't have an active device yet, just use one of
699 * the connectors tied to the encoder.
702 connector = radeon_get_connector_for_encoder_init(encoder);
703 radeon_connector = to_radeon_connector(connector);
705 switch (connector->connector_type) {
706 case DRM_MODE_CONNECTOR_DVII:
707 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
708 if (radeon_audio != 0) {
709 if (radeon_connector->use_digital &&
710 (radeon_connector->audio == RADEON_AUDIO_ENABLE))
711 return ATOM_ENCODER_MODE_HDMI;
712 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
713 (radeon_connector->audio == RADEON_AUDIO_AUTO))
714 return ATOM_ENCODER_MODE_HDMI;
715 else if (radeon_connector->use_digital)
716 return ATOM_ENCODER_MODE_DVI;
718 return ATOM_ENCODER_MODE_CRT;
719 } else if (radeon_connector->use_digital) {
720 return ATOM_ENCODER_MODE_DVI;
722 return ATOM_ENCODER_MODE_CRT;
725 case DRM_MODE_CONNECTOR_DVID:
726 case DRM_MODE_CONNECTOR_HDMIA:
728 if (radeon_audio != 0) {
729 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
730 return ATOM_ENCODER_MODE_HDMI;
731 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
732 (radeon_connector->audio == RADEON_AUDIO_AUTO))
733 return ATOM_ENCODER_MODE_HDMI;
735 return ATOM_ENCODER_MODE_DVI;
737 return ATOM_ENCODER_MODE_DVI;
740 case DRM_MODE_CONNECTOR_LVDS:
741 return ATOM_ENCODER_MODE_LVDS;
743 case DRM_MODE_CONNECTOR_DisplayPort:
744 dig_connector = radeon_connector->con_priv;
745 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
746 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
747 if (radeon_audio != 0 &&
748 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
749 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
750 return ATOM_ENCODER_MODE_DP_AUDIO;
751 return ATOM_ENCODER_MODE_DP;
752 } else if (radeon_audio != 0) {
753 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
754 return ATOM_ENCODER_MODE_HDMI;
755 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
756 (radeon_connector->audio == RADEON_AUDIO_AUTO))
757 return ATOM_ENCODER_MODE_HDMI;
759 return ATOM_ENCODER_MODE_DVI;
761 return ATOM_ENCODER_MODE_DVI;
764 case DRM_MODE_CONNECTOR_eDP:
765 if (radeon_audio != 0 &&
766 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
767 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
768 return ATOM_ENCODER_MODE_DP_AUDIO;
769 return ATOM_ENCODER_MODE_DP;
770 case DRM_MODE_CONNECTOR_DVIA:
771 case DRM_MODE_CONNECTOR_VGA:
772 return ATOM_ENCODER_MODE_CRT;
774 case DRM_MODE_CONNECTOR_Composite:
775 case DRM_MODE_CONNECTOR_SVIDEO:
776 case DRM_MODE_CONNECTOR_9PinDIN:
778 return ATOM_ENCODER_MODE_TV;
779 /*return ATOM_ENCODER_MODE_CV;*/
785 * DIG Encoder/Transmitter Setup
788 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
789 * Supports up to 3 digital outputs
790 * - 2 DIG encoder blocks.
791 * DIG1 can drive UNIPHY link A or link B
792 * DIG2 can drive UNIPHY link B or LVTMA
795 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
796 * Supports up to 5 digital outputs
797 * - 2 DIG encoder blocks.
798 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
801 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
802 * Supports up to 6 digital outputs
803 * - 6 DIG encoder blocks.
804 * - DIG to PHY mapping is hardcoded
805 * DIG1 drives UNIPHY0 link A, A+B
806 * DIG2 drives UNIPHY0 link B
807 * DIG3 drives UNIPHY1 link A, A+B
808 * DIG4 drives UNIPHY1 link B
809 * DIG5 drives UNIPHY2 link A, A+B
810 * DIG6 drives UNIPHY2 link B
813 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
814 * Supports up to 6 digital outputs
815 * - 2 DIG encoder blocks.
817 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
819 * DIG1 drives UNIPHY0/1/2 link A
820 * DIG2 drives UNIPHY0/1/2 link B
823 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
825 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
826 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
827 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
828 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
831 union dig_encoder_control {
832 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
833 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
834 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
835 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
839 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
841 struct drm_device *dev = encoder->dev;
842 struct radeon_device *rdev = dev->dev_private;
843 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
844 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
845 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
846 union dig_encoder_control args;
850 int dp_lane_count = 0;
851 int hpd_id = RADEON_HPD_NONE;
854 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
855 struct radeon_connector_atom_dig *dig_connector =
856 radeon_connector->con_priv;
858 dp_clock = dig_connector->dp_clock;
859 dp_lane_count = dig_connector->dp_lane_count;
860 hpd_id = radeon_connector->hpd.hpd;
863 /* no dig encoder assigned */
864 if (dig->dig_encoder == -1)
867 memset(&args, 0, sizeof(args));
869 if (ASIC_IS_DCE4(rdev))
870 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
872 if (dig->dig_encoder)
873 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
875 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
878 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
885 args.v1.ucAction = action;
886 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
887 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
888 args.v3.ucPanelMode = panel_mode;
890 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
892 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
893 args.v1.ucLaneNum = dp_lane_count;
894 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
895 args.v1.ucLaneNum = 8;
897 args.v1.ucLaneNum = 4;
899 switch (radeon_encoder->encoder_id) {
900 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
901 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
903 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
904 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
905 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
907 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
908 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
912 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
914 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
916 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
917 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
922 args.v3.ucAction = action;
923 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
924 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
925 args.v3.ucPanelMode = panel_mode;
927 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
929 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
930 args.v3.ucLaneNum = dp_lane_count;
931 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
932 args.v3.ucLaneNum = 8;
934 args.v3.ucLaneNum = 4;
936 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
937 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
938 if (enc_override != -1)
939 args.v3.acConfig.ucDigSel = enc_override;
941 args.v3.acConfig.ucDigSel = dig->dig_encoder;
942 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
945 args.v4.ucAction = action;
946 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
947 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
948 args.v4.ucPanelMode = panel_mode;
950 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
952 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
953 args.v4.ucLaneNum = dp_lane_count;
954 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
955 args.v4.ucLaneNum = 8;
957 args.v4.ucLaneNum = 4;
959 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
960 if (dp_clock == 540000)
961 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
962 else if (dp_clock == 324000)
963 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
964 else if (dp_clock == 270000)
965 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
967 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
970 if (enc_override != -1)
971 args.v4.acConfig.ucDigSel = enc_override;
973 args.v4.acConfig.ucDigSel = dig->dig_encoder;
974 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
975 if (hpd_id == RADEON_HPD_NONE)
976 args.v4.ucHPD_ID = 0;
978 args.v4.ucHPD_ID = hpd_id + 1;
981 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
986 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
990 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
995 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
997 atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
1000 union dig_transmitter_control {
1001 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
1002 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
1003 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
1004 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
1005 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
1009 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
1011 struct drm_device *dev = encoder->dev;
1012 struct radeon_device *rdev = dev->dev_private;
1013 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1014 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1015 struct drm_connector *connector;
1016 union dig_transmitter_control args;
1022 int dp_lane_count = 0;
1023 int connector_object_id = 0;
1024 int igp_lane_info = 0;
1025 int dig_encoder = dig->dig_encoder;
1026 int hpd_id = RADEON_HPD_NONE;
1028 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1029 connector = radeon_get_connector_for_encoder_init(encoder);
1030 /* just needed to avoid bailing in the encoder check. the encoder
1031 * isn't used for init
1035 connector = radeon_get_connector_for_encoder(encoder);
1038 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1039 struct radeon_connector_atom_dig *dig_connector =
1040 radeon_connector->con_priv;
1042 hpd_id = radeon_connector->hpd.hpd;
1043 dp_clock = dig_connector->dp_clock;
1044 dp_lane_count = dig_connector->dp_lane_count;
1045 connector_object_id =
1046 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1047 igp_lane_info = dig_connector->igp_lane_info;
1050 if (encoder->crtc) {
1051 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1052 pll_id = radeon_crtc->pll_id;
1055 /* no dig encoder assigned */
1056 if (dig_encoder == -1)
1059 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1062 memset(&args, 0, sizeof(args));
1064 switch (radeon_encoder->encoder_id) {
1065 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1066 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1068 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1069 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1070 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1071 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1072 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1074 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1075 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1079 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1086 args.v1.ucAction = action;
1087 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1088 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1089 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1090 args.v1.asMode.ucLaneSel = lane_num;
1091 args.v1.asMode.ucLaneSet = lane_set;
1094 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1095 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1096 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1098 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1101 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1104 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1106 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1108 if ((rdev->flags & RADEON_IS_IGP) &&
1109 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1111 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1112 if (igp_lane_info & 0x1)
1113 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1114 else if (igp_lane_info & 0x2)
1115 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1116 else if (igp_lane_info & 0x4)
1117 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1118 else if (igp_lane_info & 0x8)
1119 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1121 if (igp_lane_info & 0x3)
1122 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1123 else if (igp_lane_info & 0xc)
1124 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1129 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1131 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1134 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1135 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1136 if (dig->coherent_mode)
1137 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1138 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1139 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1143 args.v2.ucAction = action;
1144 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1145 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1146 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1147 args.v2.asMode.ucLaneSel = lane_num;
1148 args.v2.asMode.ucLaneSet = lane_set;
1151 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1152 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1153 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1155 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1158 args.v2.acConfig.ucEncoderSel = dig_encoder;
1160 args.v2.acConfig.ucLinkSel = 1;
1162 switch (radeon_encoder->encoder_id) {
1163 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1164 args.v2.acConfig.ucTransmitterSel = 0;
1166 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1167 args.v2.acConfig.ucTransmitterSel = 1;
1169 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1170 args.v2.acConfig.ucTransmitterSel = 2;
1175 args.v2.acConfig.fCoherentMode = 1;
1176 args.v2.acConfig.fDPConnector = 1;
1177 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1178 if (dig->coherent_mode)
1179 args.v2.acConfig.fCoherentMode = 1;
1180 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1181 args.v2.acConfig.fDualLinkConnector = 1;
1185 args.v3.ucAction = action;
1186 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1187 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1188 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1189 args.v3.asMode.ucLaneSel = lane_num;
1190 args.v3.asMode.ucLaneSet = lane_set;
1193 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1194 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1195 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1197 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1201 args.v3.ucLaneNum = dp_lane_count;
1202 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1203 args.v3.ucLaneNum = 8;
1205 args.v3.ucLaneNum = 4;
1208 args.v3.acConfig.ucLinkSel = 1;
1209 if (dig_encoder & 1)
1210 args.v3.acConfig.ucEncoderSel = 1;
1212 /* Select the PLL for the PHY
1213 * DP PHY should be clocked from external src if there is
1216 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1217 if (is_dp && rdev->clock.dp_extclk)
1218 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1220 args.v3.acConfig.ucRefClkSource = pll_id;
1222 switch (radeon_encoder->encoder_id) {
1223 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1224 args.v3.acConfig.ucTransmitterSel = 0;
1226 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1227 args.v3.acConfig.ucTransmitterSel = 1;
1229 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1230 args.v3.acConfig.ucTransmitterSel = 2;
1235 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1236 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1237 if (dig->coherent_mode)
1238 args.v3.acConfig.fCoherentMode = 1;
1239 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1240 args.v3.acConfig.fDualLinkConnector = 1;
1244 args.v4.ucAction = action;
1245 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1246 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1247 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1248 args.v4.asMode.ucLaneSel = lane_num;
1249 args.v4.asMode.ucLaneSet = lane_set;
1252 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1253 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1254 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1256 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1260 args.v4.ucLaneNum = dp_lane_count;
1261 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1262 args.v4.ucLaneNum = 8;
1264 args.v4.ucLaneNum = 4;
1267 args.v4.acConfig.ucLinkSel = 1;
1268 if (dig_encoder & 1)
1269 args.v4.acConfig.ucEncoderSel = 1;
1271 /* Select the PLL for the PHY
1272 * DP PHY should be clocked from external src if there is
1275 /* On DCE5 DCPLL usually generates the DP ref clock */
1277 if (rdev->clock.dp_extclk)
1278 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1280 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1282 args.v4.acConfig.ucRefClkSource = pll_id;
1284 switch (radeon_encoder->encoder_id) {
1285 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1286 args.v4.acConfig.ucTransmitterSel = 0;
1288 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1289 args.v4.acConfig.ucTransmitterSel = 1;
1291 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1292 args.v4.acConfig.ucTransmitterSel = 2;
1297 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1298 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1299 if (dig->coherent_mode)
1300 args.v4.acConfig.fCoherentMode = 1;
1301 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1302 args.v4.acConfig.fDualLinkConnector = 1;
1306 args.v5.ucAction = action;
1308 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1310 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1312 switch (radeon_encoder->encoder_id) {
1313 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1315 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1317 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1319 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1321 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1323 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1325 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1327 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1329 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1331 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1332 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1336 args.v5.ucLaneNum = dp_lane_count;
1337 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1338 args.v5.ucLaneNum = 8;
1340 args.v5.ucLaneNum = 4;
1341 args.v5.ucConnObjId = connector_object_id;
1342 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1344 if (is_dp && rdev->clock.dp_extclk)
1345 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1347 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1350 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1351 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1352 if (dig->coherent_mode)
1353 args.v5.asConfig.ucCoherentMode = 1;
1355 if (hpd_id == RADEON_HPD_NONE)
1356 args.v5.asConfig.ucHPDSel = 0;
1358 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1359 args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1360 args.v5.ucDPLaneSet = lane_set;
1363 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1368 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1372 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1376 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1378 atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1382 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1384 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1385 struct drm_device *dev = radeon_connector->base.dev;
1386 struct radeon_device *rdev = dev->dev_private;
1387 union dig_transmitter_control args;
1388 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1391 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1394 if (!ASIC_IS_DCE4(rdev))
1397 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1398 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1401 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1404 memset(&args, 0, sizeof(args));
1406 args.v1.ucAction = action;
1408 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1410 /* wait for the panel to power up */
1411 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1414 for (i = 0; i < 300; i++) {
1415 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1425 union external_encoder_control {
1426 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1427 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1431 atombios_external_encoder_setup(struct drm_encoder *encoder,
1432 struct drm_encoder *ext_encoder,
1435 struct drm_device *dev = encoder->dev;
1436 struct radeon_device *rdev = dev->dev_private;
1437 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1438 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1439 union external_encoder_control args;
1440 struct drm_connector *connector;
1441 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1444 int dp_lane_count = 0;
1445 int connector_object_id = 0;
1446 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1448 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1449 connector = radeon_get_connector_for_encoder_init(encoder);
1451 connector = radeon_get_connector_for_encoder(encoder);
1454 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1455 struct radeon_connector_atom_dig *dig_connector =
1456 radeon_connector->con_priv;
1458 dp_clock = dig_connector->dp_clock;
1459 dp_lane_count = dig_connector->dp_lane_count;
1460 connector_object_id =
1461 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1464 memset(&args, 0, sizeof(args));
1466 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1471 /* no params on frev 1 */
1477 args.v1.sDigEncoder.ucAction = action;
1478 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1479 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1481 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1482 if (dp_clock == 270000)
1483 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1484 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1485 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1486 args.v1.sDigEncoder.ucLaneNum = 8;
1488 args.v1.sDigEncoder.ucLaneNum = 4;
1491 args.v3.sExtEncoder.ucAction = action;
1492 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1493 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1495 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1496 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1498 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1499 if (dp_clock == 270000)
1500 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1501 else if (dp_clock == 540000)
1502 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1503 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1504 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1505 args.v3.sExtEncoder.ucLaneNum = 8;
1507 args.v3.sExtEncoder.ucLaneNum = 4;
1509 case GRAPH_OBJECT_ENUM_ID1:
1510 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1512 case GRAPH_OBJECT_ENUM_ID2:
1513 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1515 case GRAPH_OBJECT_ENUM_ID3:
1516 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1519 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1522 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1527 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1530 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1534 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1536 struct drm_device *dev = encoder->dev;
1537 struct radeon_device *rdev = dev->dev_private;
1538 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1539 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1540 ENABLE_YUV_PS_ALLOCATION args;
1541 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1544 memset(&args, 0, sizeof(args));
1546 if (rdev->family >= CHIP_R600)
1547 reg = R600_BIOS_3_SCRATCH;
1549 reg = RADEON_BIOS_3_SCRATCH;
1551 /* XXX: fix up scratch reg handling */
1553 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1554 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1555 (radeon_crtc->crtc_id << 18)));
1556 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1557 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1562 args.ucEnable = ATOM_ENABLE;
1563 args.ucCRTC = radeon_crtc->crtc_id;
1565 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1571 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1573 struct drm_device *dev = encoder->dev;
1574 struct radeon_device *rdev = dev->dev_private;
1575 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1576 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1579 memset(&args, 0, sizeof(args));
1581 switch (radeon_encoder->encoder_id) {
1582 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1583 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1584 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1586 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1587 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1588 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1589 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1591 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1592 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1594 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1595 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1596 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1598 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1600 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1601 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1602 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1603 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1604 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1605 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1607 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1609 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1610 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1611 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1612 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1613 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1614 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1616 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1623 case DRM_MODE_DPMS_ON:
1624 args.ucAction = ATOM_ENABLE;
1625 /* workaround for DVOOutputControl on some RS690 systems */
1626 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1627 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1628 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1629 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1630 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1632 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1633 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1634 if (rdev->mode_info.bl_encoder) {
1635 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1637 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1639 args.ucAction = ATOM_LCD_BLON;
1640 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1644 case DRM_MODE_DPMS_STANDBY:
1645 case DRM_MODE_DPMS_SUSPEND:
1646 case DRM_MODE_DPMS_OFF:
1647 args.ucAction = ATOM_DISABLE;
1648 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1649 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1650 args.ucAction = ATOM_LCD_BLOFF;
1651 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1658 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1660 struct drm_device *dev = encoder->dev;
1661 struct radeon_device *rdev = dev->dev_private;
1662 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1663 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1664 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1665 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1666 struct radeon_connector *radeon_connector = NULL;
1667 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1668 bool travis_quirk = false;
1671 radeon_connector = to_radeon_connector(connector);
1672 radeon_dig_connector = radeon_connector->con_priv;
1673 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1674 ENCODER_OBJECT_ID_TRAVIS) &&
1675 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1676 !ASIC_IS_DCE5(rdev))
1677 travis_quirk = true;
1681 case DRM_MODE_DPMS_ON:
1682 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1684 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1686 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1688 /* setup and enable the encoder */
1689 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1690 atombios_dig_encoder_setup(encoder,
1691 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1694 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1695 atombios_external_encoder_setup(encoder, ext_encoder,
1696 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1698 } else if (ASIC_IS_DCE4(rdev)) {
1699 /* setup and enable the encoder */
1700 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1702 /* setup and enable the encoder and transmitter */
1703 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1704 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1706 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1707 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1708 atombios_set_edp_panel_power(connector,
1709 ATOM_TRANSMITTER_ACTION_POWER_ON);
1710 radeon_dig_connector->edp_on = true;
1713 /* enable the transmitter */
1714 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1715 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1716 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1717 radeon_dp_link_train(encoder, connector);
1718 if (ASIC_IS_DCE4(rdev))
1719 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1721 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1722 if (rdev->mode_info.bl_encoder)
1723 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1725 atombios_dig_transmitter_setup(encoder,
1726 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1729 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1731 case DRM_MODE_DPMS_STANDBY:
1732 case DRM_MODE_DPMS_SUSPEND:
1733 case DRM_MODE_DPMS_OFF:
1735 /* don't power off encoders with active MST links */
1736 if (dig->active_mst_links)
1739 if (ASIC_IS_DCE4(rdev)) {
1740 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1741 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1744 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1745 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1746 atombios_dig_transmitter_setup(encoder,
1747 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1749 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1750 connector && !travis_quirk)
1751 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1752 if (ASIC_IS_DCE4(rdev)) {
1753 /* disable the transmitter */
1754 atombios_dig_transmitter_setup(encoder,
1755 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1757 /* disable the encoder and transmitter */
1758 atombios_dig_transmitter_setup(encoder,
1759 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1760 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1762 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1764 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1765 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1766 atombios_set_edp_panel_power(connector,
1767 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1768 radeon_dig_connector->edp_on = false;
1776 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1778 struct drm_device *dev = encoder->dev;
1779 struct radeon_device *rdev = dev->dev_private;
1780 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1781 int encoder_mode = atombios_get_encoder_mode(encoder);
1783 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1784 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1785 radeon_encoder->active_device);
1787 if ((radeon_audio != 0) &&
1788 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1789 ENCODER_MODE_IS_DP(encoder_mode)))
1790 radeon_audio_dpms(encoder, mode);
1792 switch (radeon_encoder->encoder_id) {
1793 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1794 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1795 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1796 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1797 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1798 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1799 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1800 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1801 radeon_atom_encoder_dpms_avivo(encoder, mode);
1803 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1804 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1805 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1806 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1807 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1808 radeon_atom_encoder_dpms_dig(encoder, mode);
1810 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1811 if (ASIC_IS_DCE5(rdev)) {
1813 case DRM_MODE_DPMS_ON:
1814 atombios_dvo_setup(encoder, ATOM_ENABLE);
1816 case DRM_MODE_DPMS_STANDBY:
1817 case DRM_MODE_DPMS_SUSPEND:
1818 case DRM_MODE_DPMS_OFF:
1819 atombios_dvo_setup(encoder, ATOM_DISABLE);
1822 } else if (ASIC_IS_DCE3(rdev))
1823 radeon_atom_encoder_dpms_dig(encoder, mode);
1825 radeon_atom_encoder_dpms_avivo(encoder, mode);
1827 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1828 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1829 if (ASIC_IS_DCE5(rdev)) {
1831 case DRM_MODE_DPMS_ON:
1832 atombios_dac_setup(encoder, ATOM_ENABLE);
1834 case DRM_MODE_DPMS_STANDBY:
1835 case DRM_MODE_DPMS_SUSPEND:
1836 case DRM_MODE_DPMS_OFF:
1837 atombios_dac_setup(encoder, ATOM_DISABLE);
1841 radeon_atom_encoder_dpms_avivo(encoder, mode);
1847 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1851 union crtc_source_param {
1852 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1853 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1857 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1859 struct drm_device *dev = encoder->dev;
1860 struct radeon_device *rdev = dev->dev_private;
1861 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1862 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1863 union crtc_source_param args;
1864 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1866 struct radeon_encoder_atom_dig *dig;
1868 memset(&args, 0, sizeof(args));
1870 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1878 if (ASIC_IS_AVIVO(rdev))
1879 args.v1.ucCRTC = radeon_crtc->crtc_id;
1881 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1882 args.v1.ucCRTC = radeon_crtc->crtc_id;
1884 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1887 switch (radeon_encoder->encoder_id) {
1888 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1889 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1890 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1892 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1893 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1894 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1895 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1897 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1899 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1900 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1901 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1902 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1904 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1905 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1906 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1907 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1908 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1909 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1911 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1913 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1914 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1915 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1916 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1917 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1918 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1920 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1925 args.v2.ucCRTC = radeon_crtc->crtc_id;
1926 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1927 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1929 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1930 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1931 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1932 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1934 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1935 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1936 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1938 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1940 switch (radeon_encoder->encoder_id) {
1941 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1942 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1943 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1944 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1945 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1946 dig = radeon_encoder->enc_priv;
1947 switch (dig->dig_encoder) {
1949 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1952 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1955 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1958 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1961 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1964 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1967 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1971 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1972 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1974 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1975 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1976 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1977 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1978 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1980 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1982 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1983 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1984 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1985 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1986 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1988 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1995 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1999 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2001 /* update scratch regs with new routing */
2002 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
2006 atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe)
2008 struct drm_device *dev = encoder->dev;
2009 struct radeon_device *rdev = dev->dev_private;
2010 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2011 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
2013 union crtc_source_param args;
2015 memset(&args, 0, sizeof(args));
2017 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2020 if (frev != 1 && crev != 2)
2021 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev);
2023 args.v2.ucCRTC = radeon_crtc->crtc_id;
2024 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST;
2028 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
2031 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
2034 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
2037 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
2040 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
2043 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
2046 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
2049 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2053 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
2054 struct drm_display_mode *mode)
2056 struct drm_device *dev = encoder->dev;
2057 struct radeon_device *rdev = dev->dev_private;
2058 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2059 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2061 /* Funky macbooks */
2062 if ((dev->pdev->device == 0x71C5) &&
2063 (dev->pdev->subsystem_vendor == 0x106b) &&
2064 (dev->pdev->subsystem_device == 0x0080)) {
2065 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2066 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2068 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2069 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2071 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2075 /* set scaler clears this on some chips */
2076 if (ASIC_IS_AVIVO(rdev) &&
2077 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2078 if (ASIC_IS_DCE8(rdev)) {
2079 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2080 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2083 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2084 } else if (ASIC_IS_DCE4(rdev)) {
2085 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2086 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2087 EVERGREEN_INTERLEAVE_EN);
2089 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2091 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2092 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2093 AVIVO_D1MODE_INTERLEAVE_EN);
2095 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2100 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2104 rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2107 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
2109 struct drm_device *dev = encoder->dev;
2110 struct radeon_device *rdev = dev->dev_private;
2111 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2112 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2113 struct drm_encoder *test_encoder;
2114 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2115 uint32_t dig_enc_in_use = 0;
2122 if (ASIC_IS_DCE6(rdev)) {
2124 switch (radeon_encoder->encoder_id) {
2125 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2131 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2137 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2143 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2148 } else if (ASIC_IS_DCE4(rdev)) {
2150 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2151 /* ontario follows DCE4 */
2152 if (rdev->family == CHIP_PALM) {
2158 /* llano follows DCE3.2 */
2159 enc_idx = radeon_crtc->crtc_id;
2161 switch (radeon_encoder->encoder_id) {
2162 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2168 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2174 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2185 /* on DCE32 and encoder can driver any block so just crtc id */
2186 if (ASIC_IS_DCE32(rdev)) {
2187 enc_idx = radeon_crtc->crtc_id;
2191 /* on DCE3 - LVTMA can only be driven by DIGB */
2192 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2193 struct radeon_encoder *radeon_test_encoder;
2195 if (encoder == test_encoder)
2198 if (!radeon_encoder_is_digital(test_encoder))
2201 radeon_test_encoder = to_radeon_encoder(test_encoder);
2202 dig = radeon_test_encoder->enc_priv;
2204 if (dig->dig_encoder >= 0)
2205 dig_enc_in_use |= (1 << dig->dig_encoder);
2208 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2209 if (dig_enc_in_use & 0x2)
2210 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2213 if (!(dig_enc_in_use & 1))
2218 if (enc_idx == -1) {
2219 DRM_ERROR("Got encoder index incorrect - returning 0\n");
2222 if (rdev->mode_info.active_encoders & (1 << enc_idx)) {
2223 DRM_ERROR("chosen encoder in use %d\n", enc_idx);
2225 rdev->mode_info.active_encoders |= (1 << enc_idx);
2229 /* This only needs to be called once at startup */
2231 radeon_atom_encoder_init(struct radeon_device *rdev)
2233 struct drm_device *dev = rdev->ddev;
2234 struct drm_encoder *encoder;
2236 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2237 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2238 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2240 switch (radeon_encoder->encoder_id) {
2241 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2242 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2243 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2244 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2245 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2246 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2252 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2253 atombios_external_encoder_setup(encoder, ext_encoder,
2254 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2259 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2260 struct drm_display_mode *mode,
2261 struct drm_display_mode *adjusted_mode)
2263 struct drm_device *dev = encoder->dev;
2264 struct radeon_device *rdev = dev->dev_private;
2265 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2266 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2269 radeon_encoder->pixel_clock = adjusted_mode->clock;
2271 /* need to call this here rather than in prepare() since we need some crtc info */
2272 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2274 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2275 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2276 atombios_yuv_setup(encoder, true);
2278 atombios_yuv_setup(encoder, false);
2281 switch (radeon_encoder->encoder_id) {
2282 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2283 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2284 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2285 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2286 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2288 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2289 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2290 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2291 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2292 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2293 /* handled in dpms */
2295 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2296 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2297 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2298 atombios_dvo_setup(encoder, ATOM_ENABLE);
2300 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2301 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2302 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2303 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2304 atombios_dac_setup(encoder, ATOM_ENABLE);
2305 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2306 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2307 atombios_tv_setup(encoder, ATOM_ENABLE);
2309 atombios_tv_setup(encoder, ATOM_DISABLE);
2314 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2316 encoder_mode = atombios_get_encoder_mode(encoder);
2317 if (connector && (radeon_audio != 0) &&
2318 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2319 ENCODER_MODE_IS_DP(encoder_mode)))
2320 radeon_audio_mode_set(encoder, adjusted_mode);
2324 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2326 struct drm_device *dev = encoder->dev;
2327 struct radeon_device *rdev = dev->dev_private;
2328 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2329 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2331 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2332 ATOM_DEVICE_CV_SUPPORT |
2333 ATOM_DEVICE_CRT_SUPPORT)) {
2334 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2335 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2338 memset(&args, 0, sizeof(args));
2340 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2343 args.sDacload.ucMisc = 0;
2345 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2346 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2347 args.sDacload.ucDacType = ATOM_DAC_A;
2349 args.sDacload.ucDacType = ATOM_DAC_B;
2351 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2352 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2353 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2354 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2355 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2356 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2358 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2359 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2360 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2362 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2365 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2372 static enum drm_connector_status
2373 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2375 struct drm_device *dev = encoder->dev;
2376 struct radeon_device *rdev = dev->dev_private;
2377 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2378 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2379 uint32_t bios_0_scratch;
2381 if (!atombios_dac_load_detect(encoder, connector)) {
2382 DRM_DEBUG_KMS("detect returned false \n");
2383 return connector_status_unknown;
2386 if (rdev->family >= CHIP_R600)
2387 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2389 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2391 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2392 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2393 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2394 return connector_status_connected;
2396 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2397 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2398 return connector_status_connected;
2400 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2401 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2402 return connector_status_connected;
2404 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2405 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2406 return connector_status_connected; /* CTV */
2407 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2408 return connector_status_connected; /* STV */
2410 return connector_status_disconnected;
2413 static enum drm_connector_status
2414 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2416 struct drm_device *dev = encoder->dev;
2417 struct radeon_device *rdev = dev->dev_private;
2418 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2419 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2420 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2423 if (!ASIC_IS_DCE4(rdev))
2424 return connector_status_unknown;
2427 return connector_status_unknown;
2429 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2430 return connector_status_unknown;
2432 /* load detect on the dp bridge */
2433 atombios_external_encoder_setup(encoder, ext_encoder,
2434 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2436 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2438 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2439 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2440 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2441 return connector_status_connected;
2443 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2444 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2445 return connector_status_connected;
2447 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2448 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2449 return connector_status_connected;
2451 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2452 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2453 return connector_status_connected; /* CTV */
2454 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2455 return connector_status_connected; /* STV */
2457 return connector_status_disconnected;
2461 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2463 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2466 /* ddc_setup on the dp bridge */
2467 atombios_external_encoder_setup(encoder, ext_encoder,
2468 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2472 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2474 struct radeon_device *rdev = encoder->dev->dev_private;
2475 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2476 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2478 if ((radeon_encoder->active_device &
2479 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2480 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2481 ENCODER_OBJECT_ID_NONE)) {
2482 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2484 if (dig->dig_encoder >= 0)
2485 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2486 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
2487 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2488 if (rdev->family >= CHIP_R600)
2489 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2491 /* RS600/690/740 have only 1 afmt block */
2492 dig->afmt = rdev->mode_info.afmt[0];
2497 radeon_atom_output_lock(encoder, true);
2500 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2502 /* select the clock/data port if it uses a router */
2503 if (radeon_connector->router.cd_valid)
2504 radeon_router_select_cd_port(radeon_connector);
2506 /* turn eDP panel on for mode set */
2507 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2508 atombios_set_edp_panel_power(connector,
2509 ATOM_TRANSMITTER_ACTION_POWER_ON);
2512 /* this is needed for the pll/ss setup to work correctly in some cases */
2513 atombios_set_encoder_crtc_source(encoder);
2514 /* set up the FMT blocks */
2515 if (ASIC_IS_DCE8(rdev))
2516 dce8_program_fmt(encoder);
2517 else if (ASIC_IS_DCE4(rdev))
2518 dce4_program_fmt(encoder);
2519 else if (ASIC_IS_DCE3(rdev))
2520 dce3_program_fmt(encoder);
2521 else if (ASIC_IS_AVIVO(rdev))
2522 avivo_program_fmt(encoder);
2525 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2527 /* need to call this here as we need the crtc set up */
2528 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2529 radeon_atom_output_lock(encoder, false);
2532 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2534 struct drm_device *dev = encoder->dev;
2535 struct radeon_device *rdev = dev->dev_private;
2536 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2537 struct radeon_encoder_atom_dig *dig;
2539 /* check for pre-DCE3 cards with shared encoders;
2540 * can't really use the links individually, so don't disable
2541 * the encoder if it's in use by another connector
2543 if (!ASIC_IS_DCE3(rdev)) {
2544 struct drm_encoder *other_encoder;
2545 struct radeon_encoder *other_radeon_encoder;
2547 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2548 other_radeon_encoder = to_radeon_encoder(other_encoder);
2549 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2550 drm_helper_encoder_in_use(other_encoder))
2555 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2557 switch (radeon_encoder->encoder_id) {
2558 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2559 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2560 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2561 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2562 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2564 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2565 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2566 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2567 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2568 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2569 /* handled in dpms */
2571 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2572 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2573 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2574 atombios_dvo_setup(encoder, ATOM_DISABLE);
2576 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2577 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2578 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2579 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2580 atombios_dac_setup(encoder, ATOM_DISABLE);
2581 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2582 atombios_tv_setup(encoder, ATOM_DISABLE);
2587 if (radeon_encoder_is_digital(encoder)) {
2588 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2589 if (rdev->asic->display.hdmi_enable)
2590 radeon_hdmi_enable(rdev, encoder, false);
2592 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) {
2593 dig = radeon_encoder->enc_priv;
2594 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2595 dig->dig_encoder = -1;
2596 radeon_encoder->active_device = 0;
2599 radeon_encoder->active_device = 0;
2602 /* these are handled by the primary encoders */
2603 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2608 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2614 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2615 struct drm_display_mode *mode,
2616 struct drm_display_mode *adjusted_mode)
2621 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2627 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2632 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2633 .dpms = radeon_atom_ext_dpms,
2634 .prepare = radeon_atom_ext_prepare,
2635 .mode_set = radeon_atom_ext_mode_set,
2636 .commit = radeon_atom_ext_commit,
2637 .disable = radeon_atom_ext_disable,
2638 /* no detect for TMDS/LVDS yet */
2641 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2642 .dpms = radeon_atom_encoder_dpms,
2643 .mode_fixup = radeon_atom_mode_fixup,
2644 .prepare = radeon_atom_encoder_prepare,
2645 .mode_set = radeon_atom_encoder_mode_set,
2646 .commit = radeon_atom_encoder_commit,
2647 .disable = radeon_atom_encoder_disable,
2648 .detect = radeon_atom_dig_detect,
2651 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2652 .dpms = radeon_atom_encoder_dpms,
2653 .mode_fixup = radeon_atom_mode_fixup,
2654 .prepare = radeon_atom_encoder_prepare,
2655 .mode_set = radeon_atom_encoder_mode_set,
2656 .commit = radeon_atom_encoder_commit,
2657 .detect = radeon_atom_dac_detect,
2660 void radeon_enc_destroy(struct drm_encoder *encoder)
2662 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2663 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2664 radeon_atom_backlight_exit(radeon_encoder);
2665 kfree(radeon_encoder->enc_priv);
2666 drm_encoder_cleanup(encoder);
2667 kfree(radeon_encoder);
2670 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2671 .destroy = radeon_enc_destroy,
2674 static struct radeon_encoder_atom_dac *
2675 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2677 struct drm_device *dev = radeon_encoder->base.dev;
2678 struct radeon_device *rdev = dev->dev_private;
2679 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2684 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2688 static struct radeon_encoder_atom_dig *
2689 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2691 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2692 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2697 /* coherent mode by default */
2698 dig->coherent_mode = true;
2699 dig->dig_encoder = -1;
2701 if (encoder_enum == 2)
2710 radeon_add_atom_encoder(struct drm_device *dev,
2711 uint32_t encoder_enum,
2712 uint32_t supported_device,
2715 struct radeon_device *rdev = dev->dev_private;
2716 struct drm_encoder *encoder;
2717 struct radeon_encoder *radeon_encoder;
2719 /* see if we already added it */
2720 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2721 radeon_encoder = to_radeon_encoder(encoder);
2722 if (radeon_encoder->encoder_enum == encoder_enum) {
2723 radeon_encoder->devices |= supported_device;
2730 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2731 if (!radeon_encoder)
2734 encoder = &radeon_encoder->base;
2735 switch (rdev->num_crtc) {
2737 encoder->possible_crtcs = 0x1;
2741 encoder->possible_crtcs = 0x3;
2744 encoder->possible_crtcs = 0xf;
2747 encoder->possible_crtcs = 0x3f;
2751 radeon_encoder->enc_priv = NULL;
2753 radeon_encoder->encoder_enum = encoder_enum;
2754 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2755 radeon_encoder->devices = supported_device;
2756 radeon_encoder->rmx_type = RMX_OFF;
2757 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2758 radeon_encoder->is_ext_encoder = false;
2759 radeon_encoder->caps = caps;
2761 switch (radeon_encoder->encoder_id) {
2762 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2763 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2764 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2765 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2766 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2767 radeon_encoder->rmx_type = RMX_FULL;
2768 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2769 DRM_MODE_ENCODER_LVDS, NULL);
2770 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2772 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2773 DRM_MODE_ENCODER_TMDS, NULL);
2774 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2776 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2778 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2779 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2780 DRM_MODE_ENCODER_DAC, NULL);
2781 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2782 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2784 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2785 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2786 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2787 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2788 DRM_MODE_ENCODER_TVDAC, NULL);
2789 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2790 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2792 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2793 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2794 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2795 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2796 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2797 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2798 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2799 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2800 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2801 radeon_encoder->rmx_type = RMX_FULL;
2802 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2803 DRM_MODE_ENCODER_LVDS, NULL);
2804 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2805 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2806 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2807 DRM_MODE_ENCODER_DAC, NULL);
2808 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2810 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2811 DRM_MODE_ENCODER_TMDS, NULL);
2812 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2814 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2816 case ENCODER_OBJECT_ID_SI170B:
2817 case ENCODER_OBJECT_ID_CH7303:
2818 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2819 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2820 case ENCODER_OBJECT_ID_TITFP513:
2821 case ENCODER_OBJECT_ID_VT1623:
2822 case ENCODER_OBJECT_ID_HDMI_SI1930:
2823 case ENCODER_OBJECT_ID_TRAVIS:
2824 case ENCODER_OBJECT_ID_NUTMEG:
2825 /* these are handled by the primary encoders */
2826 radeon_encoder->is_ext_encoder = true;
2827 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2828 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2829 DRM_MODE_ENCODER_LVDS, NULL);
2830 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2831 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2832 DRM_MODE_ENCODER_DAC, NULL);
2834 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2835 DRM_MODE_ENCODER_TMDS, NULL);
2836 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);