2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon_fixed.h"
32 #include "atom-bits.h"
34 static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
45 memset(&args, 0, sizeof(args));
47 args.usOverscanRight = 0;
48 args.usOverscanLeft = 0;
49 args.usOverscanBottom = 0;
50 args.usOverscanTop = 0;
51 args.ucCRTC = radeon_crtc->crtc_id;
53 switch (radeon_crtc->rmx_type) {
55 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
56 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
57 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
58 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
59 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
63 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
66 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
67 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
69 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
70 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
72 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
76 args.usOverscanRight = 0;
77 args.usOverscanLeft = 0;
78 args.usOverscanBottom = 0;
79 args.usOverscanTop = 0;
80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
85 static void atombios_scaler_setup(struct drm_crtc *crtc)
87 struct drm_device *dev = crtc->dev;
88 struct radeon_device *rdev = dev->dev_private;
89 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
90 ENABLE_SCALER_PS_ALLOCATION args;
91 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
93 /* fixme - fill in enc_priv for atom dac */
94 enum radeon_tv_std tv_std = TV_STD_NTSC;
95 bool is_tv = false, is_cv = false;
96 struct drm_encoder *encoder;
98 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
101 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
103 if (encoder->crtc == crtc) {
104 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
105 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
106 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
107 tv_std = tv_dac->tv_std;
113 memset(&args, 0, sizeof(args));
115 args.ucScaler = radeon_crtc->crtc_id;
121 args.ucTVStandard = ATOM_TV_NTSC;
124 args.ucTVStandard = ATOM_TV_PAL;
127 args.ucTVStandard = ATOM_TV_PALM;
130 args.ucTVStandard = ATOM_TV_PAL60;
133 args.ucTVStandard = ATOM_TV_NTSCJ;
135 case TV_STD_SCART_PAL:
136 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
139 args.ucTVStandard = ATOM_TV_SECAM;
142 args.ucTVStandard = ATOM_TV_PALCN;
145 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
147 args.ucTVStandard = ATOM_TV_CV;
148 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
150 switch (radeon_crtc->rmx_type) {
152 args.ucEnable = ATOM_SCALER_EXPANSION;
155 args.ucEnable = ATOM_SCALER_CENTER;
158 args.ucEnable = ATOM_SCALER_EXPANSION;
161 if (ASIC_IS_AVIVO(rdev))
162 args.ucEnable = ATOM_SCALER_DISABLE;
164 args.ucEnable = ATOM_SCALER_CENTER;
168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
170 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
171 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
175 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
177 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
178 struct drm_device *dev = crtc->dev;
179 struct radeon_device *rdev = dev->dev_private;
181 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
182 ENABLE_CRTC_PS_ALLOCATION args;
184 memset(&args, 0, sizeof(args));
186 args.ucCRTC = radeon_crtc->crtc_id;
187 args.ucEnable = lock;
189 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
192 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
194 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
195 struct drm_device *dev = crtc->dev;
196 struct radeon_device *rdev = dev->dev_private;
197 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
198 ENABLE_CRTC_PS_ALLOCATION args;
200 memset(&args, 0, sizeof(args));
202 args.ucCRTC = radeon_crtc->crtc_id;
203 args.ucEnable = state;
205 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
208 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
210 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
211 struct drm_device *dev = crtc->dev;
212 struct radeon_device *rdev = dev->dev_private;
213 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
214 ENABLE_CRTC_PS_ALLOCATION args;
216 memset(&args, 0, sizeof(args));
218 args.ucCRTC = radeon_crtc->crtc_id;
219 args.ucEnable = state;
221 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
224 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227 struct drm_device *dev = crtc->dev;
228 struct radeon_device *rdev = dev->dev_private;
229 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
230 BLANK_CRTC_PS_ALLOCATION args;
232 memset(&args, 0, sizeof(args));
234 args.ucCRTC = radeon_crtc->crtc_id;
235 args.ucBlanking = state;
237 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
240 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
242 struct drm_device *dev = crtc->dev;
243 struct radeon_device *rdev = dev->dev_private;
244 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
247 case DRM_MODE_DPMS_ON:
248 atombios_enable_crtc(crtc, ATOM_ENABLE);
249 if (ASIC_IS_DCE3(rdev))
250 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
251 atombios_blank_crtc(crtc, ATOM_DISABLE);
252 /* XXX re-enable when interrupt support is added */
253 if (!ASIC_IS_DCE4(rdev))
254 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
255 radeon_crtc_load_lut(crtc);
257 case DRM_MODE_DPMS_STANDBY:
258 case DRM_MODE_DPMS_SUSPEND:
259 case DRM_MODE_DPMS_OFF:
260 /* XXX re-enable when interrupt support is added */
261 if (!ASIC_IS_DCE4(rdev))
262 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
263 atombios_blank_crtc(crtc, ATOM_ENABLE);
264 if (ASIC_IS_DCE3(rdev))
265 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
266 atombios_enable_crtc(crtc, ATOM_DISABLE);
272 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
273 struct drm_display_mode *mode)
275 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
276 struct drm_device *dev = crtc->dev;
277 struct radeon_device *rdev = dev->dev_private;
278 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
279 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
282 memset(&args, 0, sizeof(args));
283 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
284 args.usH_Blanking_Time =
285 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
286 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
287 args.usV_Blanking_Time =
288 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
289 args.usH_SyncOffset =
290 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
292 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
293 args.usV_SyncOffset =
294 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
296 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
297 /*args.ucH_Border = mode->hborder;*/
298 /*args.ucV_Border = mode->vborder;*/
300 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
301 misc |= ATOM_VSYNC_POLARITY;
302 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
303 misc |= ATOM_HSYNC_POLARITY;
304 if (mode->flags & DRM_MODE_FLAG_CSYNC)
305 misc |= ATOM_COMPOSITESYNC;
306 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
307 misc |= ATOM_INTERLACE;
308 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
309 misc |= ATOM_DOUBLE_CLOCK_MODE;
311 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
312 args.ucCRTC = radeon_crtc->crtc_id;
314 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
317 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
318 struct drm_display_mode *mode)
320 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
321 struct drm_device *dev = crtc->dev;
322 struct radeon_device *rdev = dev->dev_private;
323 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
324 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
327 memset(&args, 0, sizeof(args));
328 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
329 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
330 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
332 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
333 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
334 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
335 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
337 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
339 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
340 misc |= ATOM_VSYNC_POLARITY;
341 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
342 misc |= ATOM_HSYNC_POLARITY;
343 if (mode->flags & DRM_MODE_FLAG_CSYNC)
344 misc |= ATOM_COMPOSITESYNC;
345 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
346 misc |= ATOM_INTERLACE;
347 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
348 misc |= ATOM_DOUBLE_CLOCK_MODE;
350 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
351 args.ucCRTC = radeon_crtc->crtc_id;
353 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
356 static void atombios_disable_ss(struct drm_crtc *crtc)
358 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
359 struct drm_device *dev = crtc->dev;
360 struct radeon_device *rdev = dev->dev_private;
363 if (ASIC_IS_DCE4(rdev)) {
364 switch (radeon_crtc->pll_id) {
366 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
367 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
368 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
371 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
372 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
373 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
376 case ATOM_PPLL_INVALID:
379 } else if (ASIC_IS_AVIVO(rdev)) {
380 switch (radeon_crtc->pll_id) {
382 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
384 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
387 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
389 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
392 case ATOM_PPLL_INVALID:
399 union atom_enable_ss {
400 ENABLE_LVDS_SS_PARAMETERS legacy;
401 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
404 static void atombios_enable_ss(struct drm_crtc *crtc)
406 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
407 struct drm_device *dev = crtc->dev;
408 struct radeon_device *rdev = dev->dev_private;
409 struct drm_encoder *encoder = NULL;
410 struct radeon_encoder *radeon_encoder = NULL;
411 struct radeon_encoder_atom_dig *dig = NULL;
412 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
413 union atom_enable_ss args;
414 uint16_t percentage = 0;
415 uint8_t type = 0, step = 0, delay = 0, range = 0;
417 /* XXX add ss support for DCE4 */
418 if (ASIC_IS_DCE4(rdev))
421 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
422 if (encoder->crtc == crtc) {
423 radeon_encoder = to_radeon_encoder(encoder);
424 /* only enable spread spectrum on LVDS */
425 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
426 dig = radeon_encoder->enc_priv;
427 if (dig && dig->ss) {
428 percentage = dig->ss->percentage;
429 type = dig->ss->type;
430 step = dig->ss->step;
431 delay = dig->ss->delay;
432 range = dig->ss->range;
444 memset(&args, 0, sizeof(args));
445 if (ASIC_IS_AVIVO(rdev)) {
446 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
447 args.v1.ucSpreadSpectrumType = type;
448 args.v1.ucSpreadSpectrumStep = step;
449 args.v1.ucSpreadSpectrumDelay = delay;
450 args.v1.ucSpreadSpectrumRange = range;
451 args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
452 args.v1.ucEnable = ATOM_ENABLE;
454 args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
455 args.legacy.ucSpreadSpectrumType = type;
456 args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
457 args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
458 args.legacy.ucEnable = ATOM_ENABLE;
460 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
463 union adjust_pixel_clock {
464 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
465 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
468 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
469 struct drm_display_mode *mode,
470 struct radeon_pll *pll)
472 struct drm_device *dev = crtc->dev;
473 struct radeon_device *rdev = dev->dev_private;
474 struct drm_encoder *encoder = NULL;
475 struct radeon_encoder *radeon_encoder = NULL;
476 u32 adjusted_clock = mode->clock;
477 int encoder_mode = 0;
479 /* reset the pll flags */
482 /* select the PLL algo */
483 if (ASIC_IS_AVIVO(rdev)) {
484 if (radeon_new_pll == 0)
485 pll->algo = PLL_ALGO_LEGACY;
487 pll->algo = PLL_ALGO_NEW;
489 if (radeon_new_pll == 1)
490 pll->algo = PLL_ALGO_NEW;
492 pll->algo = PLL_ALGO_LEGACY;
495 if (ASIC_IS_AVIVO(rdev)) {
496 if ((rdev->family == CHIP_RS600) ||
497 (rdev->family == CHIP_RS690) ||
498 (rdev->family == CHIP_RS740))
499 pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
500 RADEON_PLL_PREFER_CLOSEST_LOWER);
502 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
503 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
505 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
507 pll->flags |= RADEON_PLL_LEGACY;
509 if (mode->clock > 200000) /* range limits??? */
510 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
512 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
516 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
517 if (encoder->crtc == crtc) {
518 radeon_encoder = to_radeon_encoder(encoder);
519 encoder_mode = atombios_get_encoder_mode(encoder);
520 if (ASIC_IS_AVIVO(rdev)) {
521 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
522 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
523 adjusted_clock = mode->clock * 2;
524 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
525 pll->algo = PLL_ALGO_LEGACY;
526 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
529 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
530 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
531 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
532 pll->flags |= RADEON_PLL_USE_REF_DIV;
538 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
539 * accordingly based on the encoder/transmitter to work around
540 * special hw requirements.
542 if (ASIC_IS_DCE3(rdev)) {
543 union adjust_pixel_clock args;
547 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
548 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
550 return adjusted_clock;
552 memset(&args, 0, sizeof(args));
559 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
560 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
561 args.v1.ucEncodeMode = encoder_mode;
563 atom_execute_table(rdev->mode_info.atom_context,
564 index, (uint32_t *)&args);
565 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
568 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
569 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
570 args.v3.sInput.ucEncodeMode = encoder_mode;
571 args.v3.sInput.ucDispPllConfig = 0;
572 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
573 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
575 if (encoder_mode == ATOM_ENCODER_MODE_DP)
576 args.v3.sInput.ucDispPllConfig |=
577 DISPPLL_CONFIG_COHERENT_MODE;
579 if (dig->coherent_mode)
580 args.v3.sInput.ucDispPllConfig |=
581 DISPPLL_CONFIG_COHERENT_MODE;
582 if (mode->clock > 165000)
583 args.v3.sInput.ucDispPllConfig |=
584 DISPPLL_CONFIG_DUAL_LINK;
586 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
587 /* may want to enable SS on DP/eDP eventually */
588 /*args.v3.sInput.ucDispPllConfig |=
589 DISPPLL_CONFIG_SS_ENABLE;*/
590 if (encoder_mode == ATOM_ENCODER_MODE_DP)
591 args.v3.sInput.ucDispPllConfig |=
592 DISPPLL_CONFIG_COHERENT_MODE;
594 if (mode->clock > 165000)
595 args.v3.sInput.ucDispPllConfig |=
596 DISPPLL_CONFIG_DUAL_LINK;
599 atom_execute_table(rdev->mode_info.atom_context,
600 index, (uint32_t *)&args);
601 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
602 if (args.v3.sOutput.ucRefDiv) {
603 pll->flags |= RADEON_PLL_USE_REF_DIV;
604 pll->reference_div = args.v3.sOutput.ucRefDiv;
606 if (args.v3.sOutput.ucPostDiv) {
607 pll->flags |= RADEON_PLL_USE_POST_DIV;
608 pll->post_div = args.v3.sOutput.ucPostDiv;
612 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
613 return adjusted_clock;
617 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
618 return adjusted_clock;
621 return adjusted_clock;
624 union set_pixel_clock {
625 SET_PIXEL_CLOCK_PS_ALLOCATION base;
626 PIXEL_CLOCK_PARAMETERS v1;
627 PIXEL_CLOCK_PARAMETERS_V2 v2;
628 PIXEL_CLOCK_PARAMETERS_V3 v3;
629 PIXEL_CLOCK_PARAMETERS_V5 v5;
632 static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
634 struct drm_device *dev = crtc->dev;
635 struct radeon_device *rdev = dev->dev_private;
638 union set_pixel_clock args;
640 memset(&args, 0, sizeof(args));
642 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
643 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
651 /* if the default dcpll clock is specified,
652 * SetPixelClock provides the dividers
654 args.v5.ucCRTC = ATOM_CRTC_INVALID;
655 args.v5.usPixelClock = rdev->clock.default_dispclk;
656 args.v5.ucPpll = ATOM_DCPLL;
659 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
664 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
667 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
670 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
672 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
673 struct drm_device *dev = crtc->dev;
674 struct radeon_device *rdev = dev->dev_private;
675 struct drm_encoder *encoder = NULL;
676 struct radeon_encoder *radeon_encoder = NULL;
679 union set_pixel_clock args;
680 u32 pll_clock = mode->clock;
681 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
682 struct radeon_pll *pll;
684 int encoder_mode = 0;
686 memset(&args, 0, sizeof(args));
688 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
689 if (encoder->crtc == crtc) {
690 radeon_encoder = to_radeon_encoder(encoder);
691 encoder_mode = atombios_get_encoder_mode(encoder);
699 switch (radeon_crtc->pll_id) {
701 pll = &rdev->clock.p1pll;
704 pll = &rdev->clock.p2pll;
707 case ATOM_PPLL_INVALID:
708 pll = &rdev->clock.dcpll;
712 /* adjust pixel clock as needed */
713 adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
715 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
716 &ref_div, &post_div);
718 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
719 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
727 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
728 args.v1.usRefDiv = cpu_to_le16(ref_div);
729 args.v1.usFbDiv = cpu_to_le16(fb_div);
730 args.v1.ucFracFbDiv = frac_fb_div;
731 args.v1.ucPostDiv = post_div;
732 args.v1.ucPpll = radeon_crtc->pll_id;
733 args.v1.ucCRTC = radeon_crtc->crtc_id;
734 args.v1.ucRefDivSrc = 1;
737 args.v2.usPixelClock = cpu_to_le16(mode->clock / 10);
738 args.v2.usRefDiv = cpu_to_le16(ref_div);
739 args.v2.usFbDiv = cpu_to_le16(fb_div);
740 args.v2.ucFracFbDiv = frac_fb_div;
741 args.v2.ucPostDiv = post_div;
742 args.v2.ucPpll = radeon_crtc->pll_id;
743 args.v2.ucCRTC = radeon_crtc->crtc_id;
744 args.v2.ucRefDivSrc = 1;
747 args.v3.usPixelClock = cpu_to_le16(mode->clock / 10);
748 args.v3.usRefDiv = cpu_to_le16(ref_div);
749 args.v3.usFbDiv = cpu_to_le16(fb_div);
750 args.v3.ucFracFbDiv = frac_fb_div;
751 args.v3.ucPostDiv = post_div;
752 args.v3.ucPpll = radeon_crtc->pll_id;
753 args.v3.ucMiscInfo = (radeon_crtc->pll_id << 2);
754 args.v3.ucTransmitterId = radeon_encoder->encoder_id;
755 args.v3.ucEncoderMode = encoder_mode;
758 args.v5.ucCRTC = radeon_crtc->crtc_id;
759 args.v5.usPixelClock = cpu_to_le16(mode->clock / 10);
760 args.v5.ucRefDiv = ref_div;
761 args.v5.usFbDiv = cpu_to_le16(fb_div);
762 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
763 args.v5.ucPostDiv = post_div;
764 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
765 args.v5.ucTransmitterID = radeon_encoder->encoder_id;
766 args.v5.ucEncoderMode = encoder_mode;
767 args.v5.ucPpll = radeon_crtc->pll_id;
770 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
775 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
779 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
782 static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
783 struct drm_framebuffer *old_fb)
785 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
786 struct drm_device *dev = crtc->dev;
787 struct radeon_device *rdev = dev->dev_private;
788 struct radeon_framebuffer *radeon_fb;
789 struct drm_gem_object *obj;
790 struct radeon_bo *rbo;
791 uint64_t fb_location;
792 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
797 DRM_DEBUG("No FB bound\n");
801 radeon_fb = to_radeon_framebuffer(crtc->fb);
803 /* Pin framebuffer & get tilling informations */
804 obj = radeon_fb->obj;
805 rbo = obj->driver_private;
806 r = radeon_bo_reserve(rbo, false);
807 if (unlikely(r != 0))
809 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
810 if (unlikely(r != 0)) {
811 radeon_bo_unreserve(rbo);
814 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
815 radeon_bo_unreserve(rbo);
817 switch (crtc->fb->bits_per_pixel) {
819 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
820 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
823 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
824 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
827 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
828 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
832 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
833 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
836 DRM_ERROR("Unsupported screen depth %d\n",
837 crtc->fb->bits_per_pixel);
841 switch (radeon_crtc->crtc_id) {
843 WREG32(AVIVO_D1VGA_CONTROL, 0);
846 WREG32(AVIVO_D2VGA_CONTROL, 0);
849 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
852 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
855 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
858 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
864 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
865 upper_32_bits(fb_location));
866 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
867 upper_32_bits(fb_location));
868 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
869 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
870 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
871 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
872 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
874 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
875 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
876 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
877 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
878 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
879 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
881 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
882 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
883 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
885 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
886 crtc->mode.vdisplay);
889 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
891 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
892 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
894 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
895 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
896 EVERGREEN_INTERLEAVE_EN);
898 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
900 if (old_fb && old_fb != crtc->fb) {
901 radeon_fb = to_radeon_framebuffer(old_fb);
902 rbo = radeon_fb->obj->driver_private;
903 r = radeon_bo_reserve(rbo, false);
904 if (unlikely(r != 0))
906 radeon_bo_unpin(rbo);
907 radeon_bo_unreserve(rbo);
910 /* Bytes per pixel may have changed */
911 radeon_bandwidth_update(rdev);
916 static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
917 struct drm_framebuffer *old_fb)
919 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
920 struct drm_device *dev = crtc->dev;
921 struct radeon_device *rdev = dev->dev_private;
922 struct radeon_framebuffer *radeon_fb;
923 struct drm_gem_object *obj;
924 struct radeon_bo *rbo;
925 uint64_t fb_location;
926 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
931 DRM_DEBUG("No FB bound\n");
935 radeon_fb = to_radeon_framebuffer(crtc->fb);
937 /* Pin framebuffer & get tilling informations */
938 obj = radeon_fb->obj;
939 rbo = obj->driver_private;
940 r = radeon_bo_reserve(rbo, false);
941 if (unlikely(r != 0))
943 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
944 if (unlikely(r != 0)) {
945 radeon_bo_unreserve(rbo);
948 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
949 radeon_bo_unreserve(rbo);
951 switch (crtc->fb->bits_per_pixel) {
954 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
955 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
959 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
960 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
964 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
965 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
970 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
971 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
974 DRM_ERROR("Unsupported screen depth %d\n",
975 crtc->fb->bits_per_pixel);
979 if (tiling_flags & RADEON_TILING_MACRO)
980 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
982 if (tiling_flags & RADEON_TILING_MICRO)
983 fb_format |= AVIVO_D1GRPH_TILED;
985 if (radeon_crtc->crtc_id == 0)
986 WREG32(AVIVO_D1VGA_CONTROL, 0);
988 WREG32(AVIVO_D2VGA_CONTROL, 0);
990 if (rdev->family >= CHIP_RV770) {
991 if (radeon_crtc->crtc_id) {
992 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
993 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
995 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
996 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
999 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1001 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1002 radeon_crtc->crtc_offset, (u32) fb_location);
1003 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1005 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1006 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1007 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1008 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1009 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
1010 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
1012 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
1013 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1014 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1016 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1017 crtc->mode.vdisplay);
1020 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1022 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1023 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1025 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1026 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1027 AVIVO_D1MODE_INTERLEAVE_EN);
1029 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1031 if (old_fb && old_fb != crtc->fb) {
1032 radeon_fb = to_radeon_framebuffer(old_fb);
1033 rbo = radeon_fb->obj->driver_private;
1034 r = radeon_bo_reserve(rbo, false);
1035 if (unlikely(r != 0))
1037 radeon_bo_unpin(rbo);
1038 radeon_bo_unreserve(rbo);
1041 /* Bytes per pixel may have changed */
1042 radeon_bandwidth_update(rdev);
1047 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1048 struct drm_framebuffer *old_fb)
1050 struct drm_device *dev = crtc->dev;
1051 struct radeon_device *rdev = dev->dev_private;
1053 if (ASIC_IS_DCE4(rdev))
1054 return evergreen_crtc_set_base(crtc, x, y, old_fb);
1055 else if (ASIC_IS_AVIVO(rdev))
1056 return avivo_crtc_set_base(crtc, x, y, old_fb);
1058 return radeon_crtc_set_base(crtc, x, y, old_fb);
1061 /* properly set additional regs when using atombios */
1062 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1064 struct drm_device *dev = crtc->dev;
1065 struct radeon_device *rdev = dev->dev_private;
1066 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1067 u32 disp_merge_cntl;
1069 switch (radeon_crtc->crtc_id) {
1071 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1072 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1073 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1076 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1077 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1078 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1079 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1080 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1085 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1087 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1088 struct drm_device *dev = crtc->dev;
1089 struct radeon_device *rdev = dev->dev_private;
1090 struct drm_encoder *test_encoder;
1091 struct drm_crtc *test_crtc;
1092 uint32_t pll_in_use = 0;
1094 if (ASIC_IS_DCE4(rdev)) {
1095 /* if crtc is driving DP and we have an ext clock, use that */
1096 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1097 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1098 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1099 if (rdev->clock.dp_extclk)
1100 return ATOM_PPLL_INVALID;
1105 /* otherwise, pick one of the plls */
1106 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1107 struct radeon_crtc *radeon_test_crtc;
1109 if (crtc == test_crtc)
1112 radeon_test_crtc = to_radeon_crtc(test_crtc);
1113 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1114 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1115 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1117 if (!(pll_in_use & 1))
1121 return radeon_crtc->crtc_id;
1125 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1126 struct drm_display_mode *mode,
1127 struct drm_display_mode *adjusted_mode,
1128 int x, int y, struct drm_framebuffer *old_fb)
1130 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1131 struct drm_device *dev = crtc->dev;
1132 struct radeon_device *rdev = dev->dev_private;
1134 /* TODO color tiling */
1136 atombios_disable_ss(crtc);
1137 /* always set DCPLL */
1138 if (ASIC_IS_DCE4(rdev))
1139 atombios_crtc_set_dcpll(crtc);
1140 atombios_crtc_set_pll(crtc, adjusted_mode);
1141 atombios_enable_ss(crtc);
1143 if (ASIC_IS_DCE4(rdev))
1144 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1145 else if (ASIC_IS_AVIVO(rdev))
1146 atombios_crtc_set_timing(crtc, adjusted_mode);
1148 atombios_crtc_set_timing(crtc, adjusted_mode);
1149 if (radeon_crtc->crtc_id == 0)
1150 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1151 radeon_legacy_atom_fixup(crtc);
1153 atombios_crtc_set_base(crtc, x, y, old_fb);
1154 atombios_overscan_setup(crtc, mode, adjusted_mode);
1155 atombios_scaler_setup(crtc);
1159 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1160 struct drm_display_mode *mode,
1161 struct drm_display_mode *adjusted_mode)
1163 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1168 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1170 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1173 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1175 atombios_lock_crtc(crtc, ATOM_ENABLE);
1176 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1179 static void atombios_crtc_commit(struct drm_crtc *crtc)
1181 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1182 atombios_lock_crtc(crtc, ATOM_DISABLE);
1185 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1186 .dpms = atombios_crtc_dpms,
1187 .mode_fixup = atombios_crtc_mode_fixup,
1188 .mode_set = atombios_crtc_mode_set,
1189 .mode_set_base = atombios_crtc_set_base,
1190 .prepare = atombios_crtc_prepare,
1191 .commit = atombios_crtc_commit,
1192 .load_lut = radeon_crtc_load_lut,
1195 void radeon_atombios_init_crtc(struct drm_device *dev,
1196 struct radeon_crtc *radeon_crtc)
1198 struct radeon_device *rdev = dev->dev_private;
1200 if (ASIC_IS_DCE4(rdev)) {
1201 switch (radeon_crtc->crtc_id) {
1204 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1207 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1210 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1213 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1216 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1219 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1223 if (radeon_crtc->crtc_id == 1)
1224 radeon_crtc->crtc_offset =
1225 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1227 radeon_crtc->crtc_offset = 0;
1229 radeon_crtc->pll_id = -1;
1230 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);