2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/backlight.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_panel.h>
36 #include <video/display_timing.h>
37 #include <video/videomode.h>
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
42 const struct display_timing *timings;
43 unsigned int num_timings;
48 * @width: width (in millimeters) of the panel's active display area
49 * @height: height (in millimeters) of the panel's active display area
57 * @prepare: the time (in milliseconds) that it takes for the panel to
58 * become ready and start receiving video data
59 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
60 * Plug Detect isn't used.
61 * @enable: the time (in milliseconds) that it takes for the panel to
62 * display the first valid frame after starting to receive
64 * @disable: the time (in milliseconds) that it takes for the panel to
65 * turn the display off (no content is visible)
66 * @unprepare: the time (in milliseconds) that it takes for the panel
67 * to power itself down completely
71 unsigned int hpd_absent_delay;
74 unsigned int unprepare;
82 struct drm_panel base;
87 const struct panel_desc *desc;
89 struct backlight_device *backlight;
90 struct regulator *supply;
91 struct i2c_adapter *ddc;
93 struct gpio_desc *enable_gpio;
96 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
98 return container_of(panel, struct panel_simple, base);
101 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
103 struct drm_connector *connector = panel->base.connector;
104 struct drm_device *drm = panel->base.drm;
105 struct drm_display_mode *mode;
106 unsigned int i, num = 0;
111 for (i = 0; i < panel->desc->num_timings; i++) {
112 const struct display_timing *dt = &panel->desc->timings[i];
115 videomode_from_timing(dt, &vm);
116 mode = drm_mode_create(drm);
118 dev_err(drm->dev, "failed to add mode %ux%u\n",
119 dt->hactive.typ, dt->vactive.typ);
123 drm_display_mode_from_videomode(&vm, mode);
125 mode->type |= DRM_MODE_TYPE_DRIVER;
127 if (panel->desc->num_timings == 1)
128 mode->type |= DRM_MODE_TYPE_PREFERRED;
130 drm_mode_probed_add(connector, mode);
134 for (i = 0; i < panel->desc->num_modes; i++) {
135 const struct drm_display_mode *m = &panel->desc->modes[i];
137 mode = drm_mode_duplicate(drm, m);
139 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
140 m->hdisplay, m->vdisplay, m->vrefresh);
144 mode->type |= DRM_MODE_TYPE_DRIVER;
146 if (panel->desc->num_modes == 1)
147 mode->type |= DRM_MODE_TYPE_PREFERRED;
149 drm_mode_set_name(mode);
151 drm_mode_probed_add(connector, mode);
155 connector->display_info.bpc = panel->desc->bpc;
156 connector->display_info.width_mm = panel->desc->size.width;
157 connector->display_info.height_mm = panel->desc->size.height;
158 if (panel->desc->bus_format)
159 drm_display_info_set_bus_formats(&connector->display_info,
160 &panel->desc->bus_format, 1);
161 connector->display_info.bus_flags = panel->desc->bus_flags;
166 static int panel_simple_disable(struct drm_panel *panel)
168 struct panel_simple *p = to_panel_simple(panel);
174 p->backlight->props.power = FB_BLANK_POWERDOWN;
175 p->backlight->props.state |= BL_CORE_FBBLANK;
176 backlight_update_status(p->backlight);
179 if (p->desc->delay.disable)
180 msleep(p->desc->delay.disable);
187 static int panel_simple_unprepare(struct drm_panel *panel)
189 struct panel_simple *p = to_panel_simple(panel);
194 gpiod_set_value_cansleep(p->enable_gpio, 0);
196 regulator_disable(p->supply);
198 if (p->desc->delay.unprepare)
199 msleep(p->desc->delay.unprepare);
206 static int panel_simple_prepare(struct drm_panel *panel)
208 struct panel_simple *p = to_panel_simple(panel);
215 err = regulator_enable(p->supply);
217 dev_err(panel->dev, "failed to enable supply: %d\n", err);
221 gpiod_set_value_cansleep(p->enable_gpio, 1);
223 delay = p->desc->delay.prepare;
225 delay += p->desc->delay.hpd_absent_delay;
234 static int panel_simple_enable(struct drm_panel *panel)
236 struct panel_simple *p = to_panel_simple(panel);
241 if (p->desc->delay.enable)
242 msleep(p->desc->delay.enable);
245 p->backlight->props.state &= ~BL_CORE_FBBLANK;
246 p->backlight->props.power = FB_BLANK_UNBLANK;
247 backlight_update_status(p->backlight);
255 static int panel_simple_get_modes(struct drm_panel *panel)
257 struct panel_simple *p = to_panel_simple(panel);
260 /* probe EDID if a DDC bus is available */
262 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
263 drm_connector_update_edid_property(panel->connector, edid);
265 num += drm_add_edid_modes(panel->connector, edid);
270 /* add hard-coded panel modes */
271 num += panel_simple_get_fixed_modes(p);
276 static int panel_simple_get_timings(struct drm_panel *panel,
277 unsigned int num_timings,
278 struct display_timing *timings)
280 struct panel_simple *p = to_panel_simple(panel);
283 if (p->desc->num_timings < num_timings)
284 num_timings = p->desc->num_timings;
287 for (i = 0; i < num_timings; i++)
288 timings[i] = p->desc->timings[i];
290 return p->desc->num_timings;
293 static const struct drm_panel_funcs panel_simple_funcs = {
294 .disable = panel_simple_disable,
295 .unprepare = panel_simple_unprepare,
296 .prepare = panel_simple_prepare,
297 .enable = panel_simple_enable,
298 .get_modes = panel_simple_get_modes,
299 .get_timings = panel_simple_get_timings,
302 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
304 struct device_node *backlight, *ddc;
305 struct panel_simple *panel;
308 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
312 panel->enabled = false;
313 panel->prepared = false;
316 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
318 panel->supply = devm_regulator_get(dev, "power");
319 if (IS_ERR(panel->supply))
320 return PTR_ERR(panel->supply);
322 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
324 if (IS_ERR(panel->enable_gpio)) {
325 err = PTR_ERR(panel->enable_gpio);
326 if (err != -EPROBE_DEFER)
327 dev_err(dev, "failed to request GPIO: %d\n", err);
331 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
333 panel->backlight = of_find_backlight_by_node(backlight);
334 of_node_put(backlight);
336 if (!panel->backlight)
337 return -EPROBE_DEFER;
340 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
342 panel->ddc = of_find_i2c_adapter_by_node(ddc);
351 drm_panel_init(&panel->base);
352 panel->base.dev = dev;
353 panel->base.funcs = &panel_simple_funcs;
355 err = drm_panel_add(&panel->base);
359 dev_set_drvdata(dev, panel);
365 put_device(&panel->ddc->dev);
367 if (panel->backlight)
368 put_device(&panel->backlight->dev);
373 static int panel_simple_remove(struct device *dev)
375 struct panel_simple *panel = dev_get_drvdata(dev);
377 drm_panel_remove(&panel->base);
379 panel_simple_disable(&panel->base);
380 panel_simple_unprepare(&panel->base);
383 put_device(&panel->ddc->dev);
385 if (panel->backlight)
386 put_device(&panel->backlight->dev);
391 static void panel_simple_shutdown(struct device *dev)
393 struct panel_simple *panel = dev_get_drvdata(dev);
395 panel_simple_disable(&panel->base);
396 panel_simple_unprepare(&panel->base);
399 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
402 .hsync_start = 480 + 2,
403 .hsync_end = 480 + 2 + 41,
404 .htotal = 480 + 2 + 41 + 2,
406 .vsync_start = 272 + 2,
407 .vsync_end = 272 + 2 + 10,
408 .vtotal = 272 + 2 + 10 + 2,
410 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
413 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
414 .modes = &ire_am_480272h3tmqw_t01h_mode,
421 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
424 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
427 .hsync_start = 800 + 0,
428 .hsync_end = 800 + 0 + 255,
429 .htotal = 800 + 0 + 255 + 0,
431 .vsync_start = 480 + 2,
432 .vsync_end = 480 + 2 + 45,
433 .vtotal = 480 + 2 + 45 + 0,
435 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
438 static const struct panel_desc ampire_am800480r3tmqwa1h = {
439 .modes = &ire_am800480r3tmqwa1h_mode,
446 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
449 static const struct drm_display_mode auo_b101aw03_mode = {
452 .hsync_start = 1024 + 156,
453 .hsync_end = 1024 + 156 + 8,
454 .htotal = 1024 + 156 + 8 + 156,
456 .vsync_start = 600 + 16,
457 .vsync_end = 600 + 16 + 6,
458 .vtotal = 600 + 16 + 6 + 16,
462 static const struct panel_desc auo_b101aw03 = {
463 .modes = &auo_b101aw03_mode,
472 static const struct drm_display_mode auo_b101ean01_mode = {
475 .hsync_start = 1280 + 119,
476 .hsync_end = 1280 + 119 + 32,
477 .htotal = 1280 + 119 + 32 + 21,
479 .vsync_start = 800 + 4,
480 .vsync_end = 800 + 4 + 20,
481 .vtotal = 800 + 4 + 20 + 8,
485 static const struct panel_desc auo_b101ean01 = {
486 .modes = &auo_b101ean01_mode,
495 static const struct drm_display_mode auo_b101xtn01_mode = {
498 .hsync_start = 1366 + 20,
499 .hsync_end = 1366 + 20 + 70,
500 .htotal = 1366 + 20 + 70,
502 .vsync_start = 768 + 14,
503 .vsync_end = 768 + 14 + 42,
504 .vtotal = 768 + 14 + 42,
506 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
509 static const struct panel_desc auo_b101xtn01 = {
510 .modes = &auo_b101xtn01_mode,
519 static const struct drm_display_mode auo_b116xw03_mode = {
522 .hsync_start = 1366 + 40,
523 .hsync_end = 1366 + 40 + 40,
524 .htotal = 1366 + 40 + 40 + 32,
526 .vsync_start = 768 + 10,
527 .vsync_end = 768 + 10 + 12,
528 .vtotal = 768 + 10 + 12 + 6,
532 static const struct panel_desc auo_b116xw03 = {
533 .modes = &auo_b116xw03_mode,
542 static const struct drm_display_mode auo_b133xtn01_mode = {
545 .hsync_start = 1366 + 48,
546 .hsync_end = 1366 + 48 + 32,
547 .htotal = 1366 + 48 + 32 + 20,
549 .vsync_start = 768 + 3,
550 .vsync_end = 768 + 3 + 6,
551 .vtotal = 768 + 3 + 6 + 13,
555 static const struct panel_desc auo_b133xtn01 = {
556 .modes = &auo_b133xtn01_mode,
565 static const struct drm_display_mode auo_b133htn01_mode = {
568 .hsync_start = 1920 + 172,
569 .hsync_end = 1920 + 172 + 80,
570 .htotal = 1920 + 172 + 80 + 60,
572 .vsync_start = 1080 + 25,
573 .vsync_end = 1080 + 25 + 10,
574 .vtotal = 1080 + 25 + 10 + 10,
578 static const struct panel_desc auo_b133htn01 = {
579 .modes = &auo_b133htn01_mode,
593 static const struct display_timing auo_g070vvn01_timings = {
594 .pixelclock = { 33300000, 34209000, 45000000 },
595 .hactive = { 800, 800, 800 },
596 .hfront_porch = { 20, 40, 200 },
597 .hback_porch = { 87, 40, 1 },
598 .hsync_len = { 1, 48, 87 },
599 .vactive = { 480, 480, 480 },
600 .vfront_porch = { 5, 13, 200 },
601 .vback_porch = { 31, 31, 29 },
602 .vsync_len = { 1, 1, 3 },
605 static const struct panel_desc auo_g070vvn01 = {
606 .timings = &auo_g070vvn01_timings,
621 static const struct drm_display_mode auo_g104sn02_mode = {
624 .hsync_start = 800 + 40,
625 .hsync_end = 800 + 40 + 216,
626 .htotal = 800 + 40 + 216 + 128,
628 .vsync_start = 600 + 10,
629 .vsync_end = 600 + 10 + 35,
630 .vtotal = 600 + 10 + 35 + 2,
634 static const struct panel_desc auo_g104sn02 = {
635 .modes = &auo_g104sn02_mode,
644 static const struct display_timing auo_g133han01_timings = {
645 .pixelclock = { 134000000, 141200000, 149000000 },
646 .hactive = { 1920, 1920, 1920 },
647 .hfront_porch = { 39, 58, 77 },
648 .hback_porch = { 59, 88, 117 },
649 .hsync_len = { 28, 42, 56 },
650 .vactive = { 1080, 1080, 1080 },
651 .vfront_porch = { 3, 8, 11 },
652 .vback_porch = { 5, 14, 19 },
653 .vsync_len = { 4, 14, 19 },
656 static const struct panel_desc auo_g133han01 = {
657 .timings = &auo_g133han01_timings,
670 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
673 static const struct display_timing auo_g185han01_timings = {
674 .pixelclock = { 120000000, 144000000, 175000000 },
675 .hactive = { 1920, 1920, 1920 },
676 .hfront_porch = { 18, 60, 74 },
677 .hback_porch = { 12, 44, 54 },
678 .hsync_len = { 10, 24, 32 },
679 .vactive = { 1080, 1080, 1080 },
680 .vfront_porch = { 6, 10, 40 },
681 .vback_porch = { 2, 5, 20 },
682 .vsync_len = { 2, 5, 20 },
685 static const struct panel_desc auo_g185han01 = {
686 .timings = &auo_g185han01_timings,
699 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
702 static const struct display_timing auo_p320hvn03_timings = {
703 .pixelclock = { 106000000, 148500000, 164000000 },
704 .hactive = { 1920, 1920, 1920 },
705 .hfront_porch = { 25, 50, 130 },
706 .hback_porch = { 25, 50, 130 },
707 .hsync_len = { 20, 40, 105 },
708 .vactive = { 1080, 1080, 1080 },
709 .vfront_porch = { 8, 17, 150 },
710 .vback_porch = { 8, 17, 150 },
711 .vsync_len = { 4, 11, 100 },
714 static const struct panel_desc auo_p320hvn03 = {
715 .timings = &auo_p320hvn03_timings,
727 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
730 static const struct drm_display_mode auo_t215hvn01_mode = {
733 .hsync_start = 1920 + 88,
734 .hsync_end = 1920 + 88 + 44,
735 .htotal = 1920 + 88 + 44 + 148,
737 .vsync_start = 1080 + 4,
738 .vsync_end = 1080 + 4 + 5,
739 .vtotal = 1080 + 4 + 5 + 36,
743 static const struct panel_desc auo_t215hvn01 = {
744 .modes = &auo_t215hvn01_mode,
757 static const struct drm_display_mode avic_tm070ddh03_mode = {
760 .hsync_start = 1024 + 160,
761 .hsync_end = 1024 + 160 + 4,
762 .htotal = 1024 + 160 + 4 + 156,
764 .vsync_start = 600 + 17,
765 .vsync_end = 600 + 17 + 1,
766 .vtotal = 600 + 17 + 1 + 17,
770 static const struct panel_desc avic_tm070ddh03 = {
771 .modes = &avic_tm070ddh03_mode,
785 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
788 .hsync_start = 800 + 40,
789 .hsync_end = 800 + 40 + 48,
790 .htotal = 800 + 40 + 48 + 40,
792 .vsync_start = 480 + 13,
793 .vsync_end = 480 + 13 + 3,
794 .vtotal = 480 + 13 + 3 + 29,
797 static const struct panel_desc bananapi_s070wv20_ct16 = {
798 .modes = &bananapi_s070wv20_ct16_mode,
807 static const struct drm_display_mode boe_hv070wsa_mode = {
810 .hsync_start = 1024 + 30,
811 .hsync_end = 1024 + 30 + 30,
812 .htotal = 1024 + 30 + 30 + 30,
814 .vsync_start = 600 + 10,
815 .vsync_end = 600 + 10 + 10,
816 .vtotal = 600 + 10 + 10 + 10,
820 static const struct panel_desc boe_hv070wsa = {
821 .modes = &boe_hv070wsa_mode,
829 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
833 .hsync_start = 1280 + 48,
834 .hsync_end = 1280 + 48 + 32,
835 .htotal = 1280 + 48 + 32 + 80,
837 .vsync_start = 800 + 3,
838 .vsync_end = 800 + 3 + 5,
839 .vtotal = 800 + 3 + 5 + 24,
845 .hsync_start = 1280 + 48,
846 .hsync_end = 1280 + 48 + 32,
847 .htotal = 1280 + 48 + 32 + 80,
849 .vsync_start = 800 + 3,
850 .vsync_end = 800 + 3 + 5,
851 .vtotal = 800 + 3 + 5 + 24,
856 static const struct panel_desc boe_nv101wxmn51 = {
857 .modes = boe_nv101wxmn51_modes,
858 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
871 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
874 .hsync_start = 480 + 5,
875 .hsync_end = 480 + 5 + 5,
876 .htotal = 480 + 5 + 5 + 40,
878 .vsync_start = 272 + 8,
879 .vsync_end = 272 + 8 + 8,
880 .vtotal = 272 + 8 + 8 + 8,
882 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
885 static const struct panel_desc cdtech_s043wq26h_ct7 = {
886 .modes = &cdtech_s043wq26h_ct7_mode,
893 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
896 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
899 .hsync_start = 800 + 40,
900 .hsync_end = 800 + 40 + 40,
901 .htotal = 800 + 40 + 40 + 48,
903 .vsync_start = 480 + 29,
904 .vsync_end = 480 + 29 + 13,
905 .vtotal = 480 + 29 + 13 + 3,
907 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
910 static const struct panel_desc cdtech_s070wv95_ct16 = {
911 .modes = &cdtech_s070wv95_ct16_mode,
920 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
923 .hsync_start = 800 + 49,
924 .hsync_end = 800 + 49 + 33,
925 .htotal = 800 + 49 + 33 + 17,
927 .vsync_start = 1280 + 1,
928 .vsync_end = 1280 + 1 + 7,
929 .vtotal = 1280 + 1 + 7 + 15,
931 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
934 static const struct panel_desc chunghwa_claa070wp03xg = {
935 .modes = &chunghwa_claa070wp03xg_mode,
944 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
947 .hsync_start = 1366 + 58,
948 .hsync_end = 1366 + 58 + 58,
949 .htotal = 1366 + 58 + 58 + 58,
951 .vsync_start = 768 + 4,
952 .vsync_end = 768 + 4 + 4,
953 .vtotal = 768 + 4 + 4 + 4,
957 static const struct panel_desc chunghwa_claa101wa01a = {
958 .modes = &chunghwa_claa101wa01a_mode,
967 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
970 .hsync_start = 1366 + 48,
971 .hsync_end = 1366 + 48 + 32,
972 .htotal = 1366 + 48 + 32 + 20,
974 .vsync_start = 768 + 16,
975 .vsync_end = 768 + 16 + 8,
976 .vtotal = 768 + 16 + 8 + 16,
980 static const struct panel_desc chunghwa_claa101wb01 = {
981 .modes = &chunghwa_claa101wb01_mode,
990 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
993 .hsync_start = 800 + 40,
994 .hsync_end = 800 + 40 + 128,
995 .htotal = 800 + 40 + 128 + 88,
997 .vsync_start = 480 + 10,
998 .vsync_end = 480 + 10 + 2,
999 .vtotal = 480 + 10 + 2 + 33,
1001 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1004 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1005 .modes = &dataimage_scf0700c48ggu18_mode,
1012 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1013 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1016 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1017 .pixelclock = { 45000000, 51200000, 57000000 },
1018 .hactive = { 1024, 1024, 1024 },
1019 .hfront_porch = { 100, 106, 113 },
1020 .hback_porch = { 100, 106, 113 },
1021 .hsync_len = { 100, 108, 114 },
1022 .vactive = { 600, 600, 600 },
1023 .vfront_porch = { 8, 11, 15 },
1024 .vback_porch = { 8, 11, 15 },
1025 .vsync_len = { 9, 13, 15 },
1026 .flags = DISPLAY_FLAGS_DE_HIGH,
1029 static const struct panel_desc dlc_dlc0700yzg_1 = {
1030 .timings = &dlc_dlc0700yzg_1_timing,
1042 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1045 static const struct display_timing dlc_dlc1010gig_timing = {
1046 .pixelclock = { 68900000, 71100000, 73400000 },
1047 .hactive = { 1280, 1280, 1280 },
1048 .hfront_porch = { 43, 53, 63 },
1049 .hback_porch = { 43, 53, 63 },
1050 .hsync_len = { 44, 54, 64 },
1051 .vactive = { 800, 800, 800 },
1052 .vfront_porch = { 5, 8, 11 },
1053 .vback_porch = { 5, 8, 11 },
1054 .vsync_len = { 5, 7, 11 },
1055 .flags = DISPLAY_FLAGS_DE_HIGH,
1058 static const struct panel_desc dlc_dlc1010gig = {
1059 .timings = &dlc_dlc1010gig_timing,
1072 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1075 static const struct drm_display_mode edt_et057090dhu_mode = {
1078 .hsync_start = 640 + 16,
1079 .hsync_end = 640 + 16 + 30,
1080 .htotal = 640 + 16 + 30 + 114,
1082 .vsync_start = 480 + 10,
1083 .vsync_end = 480 + 10 + 3,
1084 .vtotal = 480 + 10 + 3 + 32,
1086 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1089 static const struct panel_desc edt_et057090dhu = {
1090 .modes = &edt_et057090dhu_mode,
1097 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1098 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1101 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1104 .hsync_start = 800 + 40,
1105 .hsync_end = 800 + 40 + 128,
1106 .htotal = 800 + 40 + 128 + 88,
1108 .vsync_start = 480 + 10,
1109 .vsync_end = 480 + 10 + 2,
1110 .vtotal = 480 + 10 + 2 + 33,
1112 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1115 static const struct panel_desc edt_etm0700g0dh6 = {
1116 .modes = &edt_etm0700g0dh6_mode,
1123 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1124 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1127 static const struct panel_desc edt_etm0700g0bdh6 = {
1128 .modes = &edt_etm0700g0dh6_mode,
1135 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1136 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1139 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1142 .hsync_start = 800 + 168,
1143 .hsync_end = 800 + 168 + 64,
1144 .htotal = 800 + 168 + 64 + 88,
1146 .vsync_start = 480 + 37,
1147 .vsync_end = 480 + 37 + 2,
1148 .vtotal = 480 + 37 + 2 + 8,
1152 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1153 .modes = &foxlink_fl500wvr00_a0t_mode,
1160 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1163 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1166 .hsync_start = 480 + 5,
1167 .hsync_end = 480 + 5 + 1,
1168 .htotal = 480 + 5 + 1 + 40,
1170 .vsync_start = 272 + 8,
1171 .vsync_end = 272 + 8 + 1,
1172 .vtotal = 272 + 8 + 1 + 8,
1176 static const struct panel_desc giantplus_gpg482739qs5 = {
1177 .modes = &giantplus_gpg482739qs5_mode,
1184 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1187 static const struct display_timing hannstar_hsd070pww1_timing = {
1188 .pixelclock = { 64300000, 71100000, 82000000 },
1189 .hactive = { 1280, 1280, 1280 },
1190 .hfront_porch = { 1, 1, 10 },
1191 .hback_porch = { 1, 1, 10 },
1193 * According to the data sheet, the minimum horizontal blanking interval
1194 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1195 * minimum working horizontal blanking interval to be 60 clocks.
1197 .hsync_len = { 58, 158, 661 },
1198 .vactive = { 800, 800, 800 },
1199 .vfront_porch = { 1, 1, 10 },
1200 .vback_porch = { 1, 1, 10 },
1201 .vsync_len = { 1, 21, 203 },
1202 .flags = DISPLAY_FLAGS_DE_HIGH,
1205 static const struct panel_desc hannstar_hsd070pww1 = {
1206 .timings = &hannstar_hsd070pww1_timing,
1213 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1216 static const struct display_timing hannstar_hsd100pxn1_timing = {
1217 .pixelclock = { 55000000, 65000000, 75000000 },
1218 .hactive = { 1024, 1024, 1024 },
1219 .hfront_porch = { 40, 40, 40 },
1220 .hback_porch = { 220, 220, 220 },
1221 .hsync_len = { 20, 60, 100 },
1222 .vactive = { 768, 768, 768 },
1223 .vfront_porch = { 7, 7, 7 },
1224 .vback_porch = { 21, 21, 21 },
1225 .vsync_len = { 10, 10, 10 },
1226 .flags = DISPLAY_FLAGS_DE_HIGH,
1229 static const struct panel_desc hannstar_hsd100pxn1 = {
1230 .timings = &hannstar_hsd100pxn1_timing,
1237 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1240 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1243 .hsync_start = 800 + 85,
1244 .hsync_end = 800 + 85 + 86,
1245 .htotal = 800 + 85 + 86 + 85,
1247 .vsync_start = 480 + 16,
1248 .vsync_end = 480 + 16 + 13,
1249 .vtotal = 480 + 16 + 13 + 16,
1253 static const struct panel_desc hitachi_tx23d38vm0caa = {
1254 .modes = &hitachi_tx23d38vm0caa_mode,
1267 static const struct drm_display_mode innolux_at043tn24_mode = {
1270 .hsync_start = 480 + 2,
1271 .hsync_end = 480 + 2 + 41,
1272 .htotal = 480 + 2 + 41 + 2,
1274 .vsync_start = 272 + 2,
1275 .vsync_end = 272 + 2 + 10,
1276 .vtotal = 272 + 2 + 10 + 2,
1278 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1281 static const struct panel_desc innolux_at043tn24 = {
1282 .modes = &innolux_at043tn24_mode,
1289 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1290 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1293 static const struct drm_display_mode innolux_at070tn92_mode = {
1296 .hsync_start = 800 + 210,
1297 .hsync_end = 800 + 210 + 20,
1298 .htotal = 800 + 210 + 20 + 46,
1300 .vsync_start = 480 + 22,
1301 .vsync_end = 480 + 22 + 10,
1302 .vtotal = 480 + 22 + 23 + 10,
1306 static const struct panel_desc innolux_at070tn92 = {
1307 .modes = &innolux_at070tn92_mode,
1313 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1316 static const struct display_timing innolux_g070y2_l01_timing = {
1317 .pixelclock = { 28000000, 29500000, 32000000 },
1318 .hactive = { 800, 800, 800 },
1319 .hfront_porch = { 61, 91, 141 },
1320 .hback_porch = { 60, 90, 140 },
1321 .hsync_len = { 12, 12, 12 },
1322 .vactive = { 480, 480, 480 },
1323 .vfront_porch = { 4, 9, 30 },
1324 .vback_porch = { 4, 8, 28 },
1325 .vsync_len = { 2, 2, 2 },
1326 .flags = DISPLAY_FLAGS_DE_HIGH,
1329 static const struct panel_desc innolux_g070y2_l01 = {
1330 .timings = &innolux_g070y2_l01_timing,
1343 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1346 static const struct display_timing innolux_g101ice_l01_timing = {
1347 .pixelclock = { 60400000, 71100000, 74700000 },
1348 .hactive = { 1280, 1280, 1280 },
1349 .hfront_porch = { 41, 80, 100 },
1350 .hback_porch = { 40, 79, 99 },
1351 .hsync_len = { 1, 1, 1 },
1352 .vactive = { 800, 800, 800 },
1353 .vfront_porch = { 5, 11, 14 },
1354 .vback_porch = { 4, 11, 14 },
1355 .vsync_len = { 1, 1, 1 },
1356 .flags = DISPLAY_FLAGS_DE_HIGH,
1359 static const struct panel_desc innolux_g101ice_l01 = {
1360 .timings = &innolux_g101ice_l01_timing,
1371 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1374 static const struct display_timing innolux_g121i1_l01_timing = {
1375 .pixelclock = { 67450000, 71000000, 74550000 },
1376 .hactive = { 1280, 1280, 1280 },
1377 .hfront_porch = { 40, 80, 160 },
1378 .hback_porch = { 39, 79, 159 },
1379 .hsync_len = { 1, 1, 1 },
1380 .vactive = { 800, 800, 800 },
1381 .vfront_porch = { 5, 11, 100 },
1382 .vback_porch = { 4, 11, 99 },
1383 .vsync_len = { 1, 1, 1 },
1386 static const struct panel_desc innolux_g121i1_l01 = {
1387 .timings = &innolux_g121i1_l01_timing,
1398 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1401 static const struct drm_display_mode innolux_g121x1_l03_mode = {
1404 .hsync_start = 1024 + 0,
1405 .hsync_end = 1024 + 1,
1406 .htotal = 1024 + 0 + 1 + 320,
1408 .vsync_start = 768 + 38,
1409 .vsync_end = 768 + 38 + 1,
1410 .vtotal = 768 + 38 + 1 + 0,
1412 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1415 static const struct panel_desc innolux_g121x1_l03 = {
1416 .modes = &innolux_g121x1_l03_mode,
1430 static const struct drm_display_mode innolux_n116bge_mode = {
1433 .hsync_start = 1366 + 136,
1434 .hsync_end = 1366 + 136 + 30,
1435 .htotal = 1366 + 136 + 30 + 60,
1437 .vsync_start = 768 + 8,
1438 .vsync_end = 768 + 8 + 12,
1439 .vtotal = 768 + 8 + 12 + 12,
1441 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1444 static const struct panel_desc innolux_n116bge = {
1445 .modes = &innolux_n116bge_mode,
1454 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1457 .hsync_start = 1366 + 16,
1458 .hsync_end = 1366 + 16 + 34,
1459 .htotal = 1366 + 16 + 34 + 50,
1461 .vsync_start = 768 + 2,
1462 .vsync_end = 768 + 2 + 6,
1463 .vtotal = 768 + 2 + 6 + 12,
1467 static const struct panel_desc innolux_n156bge_l21 = {
1468 .modes = &innolux_n156bge_l21_mode,
1477 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
1480 .hsync_start = 2160 + 48,
1481 .hsync_end = 2160 + 48 + 32,
1482 .htotal = 2160 + 48 + 32 + 80,
1484 .vsync_start = 1440 + 3,
1485 .vsync_end = 1440 + 3 + 10,
1486 .vtotal = 1440 + 3 + 10 + 27,
1488 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1491 static const struct panel_desc innolux_p120zdg_bf1 = {
1492 .modes = &innolux_p120zdg_bf1_mode,
1500 .hpd_absent_delay = 200,
1505 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1508 .hsync_start = 1024 + 128,
1509 .hsync_end = 1024 + 128 + 64,
1510 .htotal = 1024 + 128 + 64 + 128,
1512 .vsync_start = 600 + 16,
1513 .vsync_end = 600 + 16 + 4,
1514 .vtotal = 600 + 16 + 4 + 16,
1518 static const struct panel_desc innolux_zj070na_01p = {
1519 .modes = &innolux_zj070na_01p_mode,
1528 static const struct display_timing koe_tx31d200vm0baa_timing = {
1529 .pixelclock = { 39600000, 43200000, 48000000 },
1530 .hactive = { 1280, 1280, 1280 },
1531 .hfront_porch = { 16, 36, 56 },
1532 .hback_porch = { 16, 36, 56 },
1533 .hsync_len = { 8, 8, 8 },
1534 .vactive = { 480, 480, 480 },
1535 .vfront_porch = { 6, 21, 33 },
1536 .vback_porch = { 6, 21, 33 },
1537 .vsync_len = { 8, 8, 8 },
1538 .flags = DISPLAY_FLAGS_DE_HIGH,
1541 static const struct panel_desc koe_tx31d200vm0baa = {
1542 .timings = &koe_tx31d200vm0baa_timing,
1549 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1552 static const struct display_timing kyo_tcg121xglp_timing = {
1553 .pixelclock = { 52000000, 65000000, 71000000 },
1554 .hactive = { 1024, 1024, 1024 },
1555 .hfront_porch = { 2, 2, 2 },
1556 .hback_porch = { 2, 2, 2 },
1557 .hsync_len = { 86, 124, 244 },
1558 .vactive = { 768, 768, 768 },
1559 .vfront_porch = { 2, 2, 2 },
1560 .vback_porch = { 2, 2, 2 },
1561 .vsync_len = { 6, 34, 73 },
1562 .flags = DISPLAY_FLAGS_DE_HIGH,
1565 static const struct panel_desc kyo_tcg121xglp = {
1566 .timings = &kyo_tcg121xglp_timing,
1573 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1576 static const struct drm_display_mode lg_lb070wv8_mode = {
1579 .hsync_start = 800 + 88,
1580 .hsync_end = 800 + 88 + 80,
1581 .htotal = 800 + 88 + 80 + 88,
1583 .vsync_start = 480 + 10,
1584 .vsync_end = 480 + 10 + 25,
1585 .vtotal = 480 + 10 + 25 + 10,
1589 static const struct panel_desc lg_lb070wv8 = {
1590 .modes = &lg_lb070wv8_mode,
1597 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1600 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1603 .hsync_start = 1536 + 12,
1604 .hsync_end = 1536 + 12 + 16,
1605 .htotal = 1536 + 12 + 16 + 48,
1607 .vsync_start = 2048 + 8,
1608 .vsync_end = 2048 + 8 + 4,
1609 .vtotal = 2048 + 8 + 4 + 8,
1611 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1614 static const struct panel_desc lg_lp079qx1_sp0v = {
1615 .modes = &lg_lp079qx1_sp0v_mode,
1623 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1626 .hsync_start = 2048 + 150,
1627 .hsync_end = 2048 + 150 + 5,
1628 .htotal = 2048 + 150 + 5 + 5,
1630 .vsync_start = 1536 + 3,
1631 .vsync_end = 1536 + 3 + 1,
1632 .vtotal = 1536 + 3 + 1 + 9,
1636 static const struct panel_desc lg_lp097qx1_spa1 = {
1637 .modes = &lg_lp097qx1_spa1_mode,
1645 static const struct drm_display_mode lg_lp120up1_mode = {
1648 .hsync_start = 1920 + 40,
1649 .hsync_end = 1920 + 40 + 40,
1650 .htotal = 1920 + 40 + 40+ 80,
1652 .vsync_start = 1280 + 4,
1653 .vsync_end = 1280 + 4 + 4,
1654 .vtotal = 1280 + 4 + 4 + 12,
1658 static const struct panel_desc lg_lp120up1 = {
1659 .modes = &lg_lp120up1_mode,
1668 static const struct drm_display_mode lg_lp129qe_mode = {
1671 .hsync_start = 2560 + 48,
1672 .hsync_end = 2560 + 48 + 32,
1673 .htotal = 2560 + 48 + 32 + 80,
1675 .vsync_start = 1700 + 3,
1676 .vsync_end = 1700 + 3 + 10,
1677 .vtotal = 1700 + 3 + 10 + 36,
1681 static const struct panel_desc lg_lp129qe = {
1682 .modes = &lg_lp129qe_mode,
1691 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
1694 .hsync_start = 800 + 0,
1695 .hsync_end = 800 + 1,
1696 .htotal = 800 + 0 + 1 + 160,
1698 .vsync_start = 480 + 0,
1699 .vsync_end = 480 + 48 + 1,
1700 .vtotal = 480 + 48 + 1 + 0,
1702 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1705 static const struct panel_desc mitsubishi_aa070mc01 = {
1706 .modes = &mitsubishi_aa070mc01_mode,
1719 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1720 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1723 static const struct display_timing nec_nl12880bc20_05_timing = {
1724 .pixelclock = { 67000000, 71000000, 75000000 },
1725 .hactive = { 1280, 1280, 1280 },
1726 .hfront_porch = { 2, 30, 30 },
1727 .hback_porch = { 6, 100, 100 },
1728 .hsync_len = { 2, 30, 30 },
1729 .vactive = { 800, 800, 800 },
1730 .vfront_porch = { 5, 5, 5 },
1731 .vback_porch = { 11, 11, 11 },
1732 .vsync_len = { 7, 7, 7 },
1735 static const struct panel_desc nec_nl12880bc20_05 = {
1736 .timings = &nec_nl12880bc20_05_timing,
1747 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1750 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1753 .hsync_start = 480 + 2,
1754 .hsync_end = 480 + 2 + 41,
1755 .htotal = 480 + 2 + 41 + 2,
1757 .vsync_start = 272 + 2,
1758 .vsync_end = 272 + 2 + 4,
1759 .vtotal = 272 + 2 + 4 + 2,
1761 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1764 static const struct panel_desc nec_nl4827hc19_05b = {
1765 .modes = &nec_nl4827hc19_05b_mode,
1772 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1773 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1776 static const struct drm_display_mode netron_dy_e231732_mode = {
1779 .hsync_start = 1024 + 160,
1780 .hsync_end = 1024 + 160 + 70,
1781 .htotal = 1024 + 160 + 70 + 90,
1783 .vsync_start = 600 + 127,
1784 .vsync_end = 600 + 127 + 20,
1785 .vtotal = 600 + 127 + 20 + 3,
1789 static const struct panel_desc netron_dy_e231732 = {
1790 .modes = &netron_dy_e231732_mode,
1796 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1799 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
1802 .hsync_start = 480 + 2,
1803 .hsync_end = 480 + 2 + 41,
1804 .htotal = 480 + 2 + 41 + 2,
1806 .vsync_start = 272 + 2,
1807 .vsync_end = 272 + 2 + 10,
1808 .vtotal = 272 + 2 + 10 + 2,
1810 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1813 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
1814 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
1821 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1822 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
1823 DRM_BUS_FLAG_SYNC_POSEDGE,
1826 static const struct display_timing nlt_nl192108ac18_02d_timing = {
1827 .pixelclock = { 130000000, 148350000, 163000000 },
1828 .hactive = { 1920, 1920, 1920 },
1829 .hfront_porch = { 80, 100, 100 },
1830 .hback_porch = { 100, 120, 120 },
1831 .hsync_len = { 50, 60, 60 },
1832 .vactive = { 1080, 1080, 1080 },
1833 .vfront_porch = { 12, 30, 30 },
1834 .vback_porch = { 4, 10, 10 },
1835 .vsync_len = { 4, 5, 5 },
1838 static const struct panel_desc nlt_nl192108ac18_02d = {
1839 .timings = &nlt_nl192108ac18_02d_timing,
1849 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1852 static const struct drm_display_mode nvd_9128_mode = {
1855 .hsync_start = 800 + 130,
1856 .hsync_end = 800 + 130 + 98,
1857 .htotal = 800 + 0 + 130 + 98,
1859 .vsync_start = 480 + 10,
1860 .vsync_end = 480 + 10 + 50,
1861 .vtotal = 480 + 0 + 10 + 50,
1864 static const struct panel_desc nvd_9128 = {
1865 .modes = &nvd_9128_mode,
1872 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1875 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1876 .pixelclock = { 30000000, 30000000, 40000000 },
1877 .hactive = { 800, 800, 800 },
1878 .hfront_porch = { 40, 40, 40 },
1879 .hback_porch = { 40, 40, 40 },
1880 .hsync_len = { 1, 48, 48 },
1881 .vactive = { 480, 480, 480 },
1882 .vfront_porch = { 13, 13, 13 },
1883 .vback_porch = { 29, 29, 29 },
1884 .vsync_len = { 3, 3, 3 },
1885 .flags = DISPLAY_FLAGS_DE_HIGH,
1888 static const struct panel_desc okaya_rs800480t_7x0gp = {
1889 .timings = &okaya_rs800480t_7x0gp_timing,
1902 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1905 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
1908 .hsync_start = 480 + 5,
1909 .hsync_end = 480 + 5 + 30,
1910 .htotal = 480 + 5 + 30 + 10,
1912 .vsync_start = 272 + 8,
1913 .vsync_end = 272 + 8 + 5,
1914 .vtotal = 272 + 8 + 5 + 3,
1918 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1919 .modes = &olimex_lcd_olinuxino_43ts_mode,
1925 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1929 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1930 * pixel clocks, but this is the timing that was being used in the Adafruit
1931 * installation instructions.
1933 static const struct drm_display_mode ontat_yx700wv03_mode = {
1944 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1949 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1951 static const struct panel_desc ontat_yx700wv03 = {
1952 .modes = &ontat_yx700wv03_mode,
1959 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1962 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1965 .hsync_start = 480 + 10,
1966 .hsync_end = 480 + 10 + 10,
1967 .htotal = 480 + 10 + 10 + 15,
1969 .vsync_start = 800 + 3,
1970 .vsync_end = 800 + 3 + 3,
1971 .vtotal = 800 + 3 + 3 + 3,
1975 static const struct panel_desc ortustech_com43h4m85ulc = {
1976 .modes = &ortustech_com43h4m85ulc_mode,
1983 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1984 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1987 static const struct drm_display_mode qd43003c0_40_mode = {
1990 .hsync_start = 480 + 8,
1991 .hsync_end = 480 + 8 + 4,
1992 .htotal = 480 + 8 + 4 + 39,
1994 .vsync_start = 272 + 4,
1995 .vsync_end = 272 + 4 + 10,
1996 .vtotal = 272 + 4 + 10 + 2,
2000 static const struct panel_desc qd43003c0_40 = {
2001 .modes = &qd43003c0_40_mode,
2008 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2011 static const struct display_timing rocktech_rk070er9427_timing = {
2012 .pixelclock = { 26400000, 33300000, 46800000 },
2013 .hactive = { 800, 800, 800 },
2014 .hfront_porch = { 16, 210, 354 },
2015 .hback_porch = { 46, 46, 46 },
2016 .hsync_len = { 1, 1, 1 },
2017 .vactive = { 480, 480, 480 },
2018 .vfront_porch = { 7, 22, 147 },
2019 .vback_porch = { 23, 23, 23 },
2020 .vsync_len = { 1, 1, 1 },
2021 .flags = DISPLAY_FLAGS_DE_HIGH,
2024 static const struct panel_desc rocktech_rk070er9427 = {
2025 .timings = &rocktech_rk070er9427_timing,
2038 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2041 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
2044 .hsync_start = 2560 + 48,
2045 .hsync_end = 2560 + 48 + 32,
2046 .htotal = 2560 + 48 + 32 + 80,
2048 .vsync_start = 1600 + 2,
2049 .vsync_end = 1600 + 2 + 5,
2050 .vtotal = 1600 + 2 + 5 + 57,
2054 static const struct panel_desc samsung_lsn122dl01_c01 = {
2055 .modes = &samsung_lsn122dl01_c01_mode,
2063 static const struct drm_display_mode samsung_ltn101nt05_mode = {
2066 .hsync_start = 1024 + 24,
2067 .hsync_end = 1024 + 24 + 136,
2068 .htotal = 1024 + 24 + 136 + 160,
2070 .vsync_start = 600 + 3,
2071 .vsync_end = 600 + 3 + 6,
2072 .vtotal = 600 + 3 + 6 + 61,
2076 static const struct panel_desc samsung_ltn101nt05 = {
2077 .modes = &samsung_ltn101nt05_mode,
2086 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
2089 .hsync_start = 1366 + 64,
2090 .hsync_end = 1366 + 64 + 48,
2091 .htotal = 1366 + 64 + 48 + 128,
2093 .vsync_start = 768 + 2,
2094 .vsync_end = 768 + 2 + 5,
2095 .vtotal = 768 + 2 + 5 + 17,
2099 static const struct panel_desc samsung_ltn140at29_301 = {
2100 .modes = &samsung_ltn140at29_301_mode,
2109 static const struct drm_display_mode sharp_lq035q7db03_mode = {
2112 .hsync_start = 240 + 16,
2113 .hsync_end = 240 + 16 + 7,
2114 .htotal = 240 + 16 + 7 + 5,
2116 .vsync_start = 320 + 9,
2117 .vsync_end = 320 + 9 + 1,
2118 .vtotal = 320 + 9 + 1 + 7,
2122 static const struct panel_desc sharp_lq035q7db03 = {
2123 .modes = &sharp_lq035q7db03_mode,
2130 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2133 static const struct display_timing sharp_lq101k1ly04_timing = {
2134 .pixelclock = { 60000000, 65000000, 80000000 },
2135 .hactive = { 1280, 1280, 1280 },
2136 .hfront_porch = { 20, 20, 20 },
2137 .hback_porch = { 20, 20, 20 },
2138 .hsync_len = { 10, 10, 10 },
2139 .vactive = { 800, 800, 800 },
2140 .vfront_porch = { 4, 4, 4 },
2141 .vback_porch = { 4, 4, 4 },
2142 .vsync_len = { 4, 4, 4 },
2143 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2146 static const struct panel_desc sharp_lq101k1ly04 = {
2147 .timings = &sharp_lq101k1ly04_timing,
2154 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
2157 static const struct display_timing sharp_lq123p1jx31_timing = {
2158 .pixelclock = { 252750000, 252750000, 266604720 },
2159 .hactive = { 2400, 2400, 2400 },
2160 .hfront_porch = { 48, 48, 48 },
2161 .hback_porch = { 80, 80, 84 },
2162 .hsync_len = { 32, 32, 32 },
2163 .vactive = { 1600, 1600, 1600 },
2164 .vfront_porch = { 3, 3, 3 },
2165 .vback_porch = { 33, 33, 120 },
2166 .vsync_len = { 10, 10, 10 },
2167 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2170 static const struct panel_desc sharp_lq123p1jx31 = {
2171 .timings = &sharp_lq123p1jx31_timing,
2185 static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2188 .hsync_start = 1024 + 168,
2189 .hsync_end = 1024 + 168 + 64,
2190 .htotal = 1024 + 168 + 64 + 88,
2192 .vsync_start = 768 + 37,
2193 .vsync_end = 768 + 37 + 2,
2194 .vtotal = 768 + 37 + 2 + 8,
2198 static const struct panel_desc sharp_lq150x1lg11 = {
2199 .modes = &sharp_lq150x1lg11_mode,
2206 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2209 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
2212 .hsync_start = 800 + 1,
2213 .hsync_end = 800 + 1 + 64,
2214 .htotal = 800 + 1 + 64 + 64,
2216 .vsync_start = 480 + 1,
2217 .vsync_end = 480 + 1 + 23,
2218 .vtotal = 480 + 1 + 23 + 22,
2222 static const struct panel_desc shelly_sca07010_bfn_lnn = {
2223 .modes = &shelly_sca07010_bfn_lnn_mode,
2229 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2232 static const struct drm_display_mode starry_kr122ea0sra_mode = {
2235 .hsync_start = 1920 + 16,
2236 .hsync_end = 1920 + 16 + 16,
2237 .htotal = 1920 + 16 + 16 + 32,
2239 .vsync_start = 1200 + 15,
2240 .vsync_end = 1200 + 15 + 2,
2241 .vtotal = 1200 + 15 + 2 + 18,
2243 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2246 static const struct panel_desc starry_kr122ea0sra = {
2247 .modes = &starry_kr122ea0sra_mode,
2254 .prepare = 10 + 200,
2256 .unprepare = 10 + 500,
2260 static const struct display_timing tianma_tm070jdhg30_timing = {
2261 .pixelclock = { 62600000, 68200000, 78100000 },
2262 .hactive = { 1280, 1280, 1280 },
2263 .hfront_porch = { 15, 64, 159 },
2264 .hback_porch = { 5, 5, 5 },
2265 .hsync_len = { 1, 1, 256 },
2266 .vactive = { 800, 800, 800 },
2267 .vfront_porch = { 3, 40, 99 },
2268 .vback_porch = { 2, 2, 2 },
2269 .vsync_len = { 1, 1, 128 },
2270 .flags = DISPLAY_FLAGS_DE_HIGH,
2273 static const struct panel_desc tianma_tm070jdhg30 = {
2274 .timings = &tianma_tm070jdhg30_timing,
2281 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2284 static const struct display_timing tianma_tm070rvhg71_timing = {
2285 .pixelclock = { 27700000, 29200000, 39600000 },
2286 .hactive = { 800, 800, 800 },
2287 .hfront_porch = { 12, 40, 212 },
2288 .hback_porch = { 88, 88, 88 },
2289 .hsync_len = { 1, 1, 40 },
2290 .vactive = { 480, 480, 480 },
2291 .vfront_porch = { 1, 13, 88 },
2292 .vback_porch = { 32, 32, 32 },
2293 .vsync_len = { 1, 1, 3 },
2294 .flags = DISPLAY_FLAGS_DE_HIGH,
2297 static const struct panel_desc tianma_tm070rvhg71 = {
2298 .timings = &tianma_tm070rvhg71_timing,
2305 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2308 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
2311 .hsync_start = 1280 + 192,
2312 .hsync_end = 1280 + 192 + 128,
2313 .htotal = 1280 + 192 + 128 + 64,
2315 .vsync_start = 768 + 20,
2316 .vsync_end = 768 + 20 + 7,
2317 .vtotal = 768 + 20 + 7 + 3,
2321 static const struct panel_desc toshiba_lt089ac29000 = {
2322 .modes = &toshiba_lt089ac29000_mode,
2328 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2329 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
2332 static const struct drm_display_mode tpk_f07a_0102_mode = {
2335 .hsync_start = 800 + 40,
2336 .hsync_end = 800 + 40 + 128,
2337 .htotal = 800 + 40 + 128 + 88,
2339 .vsync_start = 480 + 10,
2340 .vsync_end = 480 + 10 + 2,
2341 .vtotal = 480 + 10 + 2 + 33,
2345 static const struct panel_desc tpk_f07a_0102 = {
2346 .modes = &tpk_f07a_0102_mode,
2352 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
2355 static const struct drm_display_mode tpk_f10a_0102_mode = {
2358 .hsync_start = 1024 + 176,
2359 .hsync_end = 1024 + 176 + 5,
2360 .htotal = 1024 + 176 + 5 + 88,
2362 .vsync_start = 600 + 20,
2363 .vsync_end = 600 + 20 + 5,
2364 .vtotal = 600 + 20 + 5 + 25,
2368 static const struct panel_desc tpk_f10a_0102 = {
2369 .modes = &tpk_f10a_0102_mode,
2377 static const struct display_timing urt_umsh_8596md_timing = {
2378 .pixelclock = { 33260000, 33260000, 33260000 },
2379 .hactive = { 800, 800, 800 },
2380 .hfront_porch = { 41, 41, 41 },
2381 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
2382 .hsync_len = { 71, 128, 128 },
2383 .vactive = { 480, 480, 480 },
2384 .vfront_porch = { 10, 10, 10 },
2385 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
2386 .vsync_len = { 2, 2, 2 },
2387 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2388 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2391 static const struct panel_desc urt_umsh_8596md_lvds = {
2392 .timings = &urt_umsh_8596md_timing,
2399 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2402 static const struct panel_desc urt_umsh_8596md_parallel = {
2403 .timings = &urt_umsh_8596md_timing,
2410 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2413 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
2416 .hsync_start = 320 + 20,
2417 .hsync_end = 320 + 20 + 30,
2418 .htotal = 320 + 20 + 30 + 38,
2420 .vsync_start = 240 + 4,
2421 .vsync_end = 240 + 4 + 3,
2422 .vtotal = 240 + 4 + 3 + 15,
2424 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2427 static const struct panel_desc winstar_wf35ltiacd = {
2428 .modes = &winstar_wf35ltiacd_mode,
2435 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2438 static const struct drm_display_mode arm_rtsm_mode[] = {
2442 .hsync_start = 1024 + 24,
2443 .hsync_end = 1024 + 24 + 136,
2444 .htotal = 1024 + 24 + 136 + 160,
2446 .vsync_start = 768 + 3,
2447 .vsync_end = 768 + 3 + 6,
2448 .vtotal = 768 + 3 + 6 + 29,
2450 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2454 static const struct panel_desc arm_rtsm = {
2455 .modes = arm_rtsm_mode,
2462 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2465 static const struct of_device_id platform_of_match[] = {
2467 .compatible = "ampire,am-480272h3tmqw-t01h",
2468 .data = &ire_am_480272h3tmqw_t01h,
2470 .compatible = "ampire,am800480r3tmqwa1h",
2471 .data = &ire_am800480r3tmqwa1h,
2473 .compatible = "arm,rtsm-display",
2476 .compatible = "auo,b101aw03",
2477 .data = &auo_b101aw03,
2479 .compatible = "auo,b101ean01",
2480 .data = &auo_b101ean01,
2482 .compatible = "auo,b101xtn01",
2483 .data = &auo_b101xtn01,
2485 .compatible = "auo,b116xw03",
2486 .data = &auo_b116xw03,
2488 .compatible = "auo,b133htn01",
2489 .data = &auo_b133htn01,
2491 .compatible = "auo,b133xtn01",
2492 .data = &auo_b133xtn01,
2494 .compatible = "auo,g070vvn01",
2495 .data = &auo_g070vvn01,
2497 .compatible = "auo,g104sn02",
2498 .data = &auo_g104sn02,
2500 .compatible = "auo,g133han01",
2501 .data = &auo_g133han01,
2503 .compatible = "auo,g185han01",
2504 .data = &auo_g185han01,
2506 .compatible = "auo,p320hvn03",
2507 .data = &auo_p320hvn03,
2509 .compatible = "auo,t215hvn01",
2510 .data = &auo_t215hvn01,
2512 .compatible = "avic,tm070ddh03",
2513 .data = &avic_tm070ddh03,
2515 .compatible = "bananapi,s070wv20-ct16",
2516 .data = &bananapi_s070wv20_ct16,
2518 .compatible = "boe,hv070wsa-100",
2519 .data = &boe_hv070wsa
2521 .compatible = "boe,nv101wxmn51",
2522 .data = &boe_nv101wxmn51,
2524 .compatible = "cdtech,s043wq26h-ct7",
2525 .data = &cdtech_s043wq26h_ct7,
2527 .compatible = "cdtech,s070wv95-ct16",
2528 .data = &cdtech_s070wv95_ct16,
2530 .compatible = "chunghwa,claa070wp03xg",
2531 .data = &chunghwa_claa070wp03xg,
2533 .compatible = "chunghwa,claa101wa01a",
2534 .data = &chunghwa_claa101wa01a
2536 .compatible = "chunghwa,claa101wb01",
2537 .data = &chunghwa_claa101wb01
2539 .compatible = "dataimage,scf0700c48ggu18",
2540 .data = &dataimage_scf0700c48ggu18,
2542 .compatible = "dlc,dlc0700yzg-1",
2543 .data = &dlc_dlc0700yzg_1,
2545 .compatible = "dlc,dlc1010gig",
2546 .data = &dlc_dlc1010gig,
2548 .compatible = "edt,et057090dhu",
2549 .data = &edt_et057090dhu,
2551 .compatible = "edt,et070080dh6",
2552 .data = &edt_etm0700g0dh6,
2554 .compatible = "edt,etm0700g0dh6",
2555 .data = &edt_etm0700g0dh6,
2557 .compatible = "edt,etm0700g0bdh6",
2558 .data = &edt_etm0700g0bdh6,
2560 .compatible = "edt,etm0700g0edh6",
2561 .data = &edt_etm0700g0bdh6,
2563 .compatible = "foxlink,fl500wvr00-a0t",
2564 .data = &foxlink_fl500wvr00_a0t,
2566 .compatible = "giantplus,gpg482739qs5",
2567 .data = &giantplus_gpg482739qs5
2569 .compatible = "hannstar,hsd070pww1",
2570 .data = &hannstar_hsd070pww1,
2572 .compatible = "hannstar,hsd100pxn1",
2573 .data = &hannstar_hsd100pxn1,
2575 .compatible = "hit,tx23d38vm0caa",
2576 .data = &hitachi_tx23d38vm0caa
2578 .compatible = "innolux,at043tn24",
2579 .data = &innolux_at043tn24,
2581 .compatible = "innolux,at070tn92",
2582 .data = &innolux_at070tn92,
2584 .compatible = "innolux,g070y2-l01",
2585 .data = &innolux_g070y2_l01,
2587 .compatible = "innolux,g101ice-l01",
2588 .data = &innolux_g101ice_l01
2590 .compatible = "innolux,g121i1-l01",
2591 .data = &innolux_g121i1_l01
2593 .compatible = "innolux,g121x1-l03",
2594 .data = &innolux_g121x1_l03,
2596 .compatible = "innolux,n116bge",
2597 .data = &innolux_n116bge,
2599 .compatible = "innolux,n156bge-l21",
2600 .data = &innolux_n156bge_l21,
2602 .compatible = "innolux,p120zdg-bf1",
2603 .data = &innolux_p120zdg_bf1,
2605 .compatible = "innolux,zj070na-01p",
2606 .data = &innolux_zj070na_01p,
2608 .compatible = "koe,tx31d200vm0baa",
2609 .data = &koe_tx31d200vm0baa,
2611 .compatible = "kyo,tcg121xglp",
2612 .data = &kyo_tcg121xglp,
2614 .compatible = "lg,lb070wv8",
2615 .data = &lg_lb070wv8,
2617 .compatible = "lg,lp079qx1-sp0v",
2618 .data = &lg_lp079qx1_sp0v,
2620 .compatible = "lg,lp097qx1-spa1",
2621 .data = &lg_lp097qx1_spa1,
2623 .compatible = "lg,lp120up1",
2624 .data = &lg_lp120up1,
2626 .compatible = "lg,lp129qe",
2627 .data = &lg_lp129qe,
2629 .compatible = "mitsubishi,aa070mc01-ca1",
2630 .data = &mitsubishi_aa070mc01,
2632 .compatible = "nec,nl12880bc20-05",
2633 .data = &nec_nl12880bc20_05,
2635 .compatible = "nec,nl4827hc19-05b",
2636 .data = &nec_nl4827hc19_05b,
2638 .compatible = "netron-dy,e231732",
2639 .data = &netron_dy_e231732,
2641 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
2642 .data = &newhaven_nhd_43_480272ef_atxl,
2644 .compatible = "nlt,nl192108ac18-02d",
2645 .data = &nlt_nl192108ac18_02d,
2647 .compatible = "nvd,9128",
2650 .compatible = "okaya,rs800480t-7x0gp",
2651 .data = &okaya_rs800480t_7x0gp,
2653 .compatible = "olimex,lcd-olinuxino-43-ts",
2654 .data = &olimex_lcd_olinuxino_43ts,
2656 .compatible = "ontat,yx700wv03",
2657 .data = &ontat_yx700wv03,
2659 .compatible = "ortustech,com43h4m85ulc",
2660 .data = &ortustech_com43h4m85ulc,
2662 .compatible = "qiaodian,qd43003c0-40",
2663 .data = &qd43003c0_40,
2665 .compatible = "rocktech,rk070er9427",
2666 .data = &rocktech_rk070er9427,
2668 .compatible = "samsung,lsn122dl01-c01",
2669 .data = &samsung_lsn122dl01_c01,
2671 .compatible = "samsung,ltn101nt05",
2672 .data = &samsung_ltn101nt05,
2674 .compatible = "samsung,ltn140at29-301",
2675 .data = &samsung_ltn140at29_301,
2677 .compatible = "sharp,lq035q7db03",
2678 .data = &sharp_lq035q7db03,
2680 .compatible = "sharp,lq101k1ly04",
2681 .data = &sharp_lq101k1ly04,
2683 .compatible = "sharp,lq123p1jx31",
2684 .data = &sharp_lq123p1jx31,
2686 .compatible = "sharp,lq150x1lg11",
2687 .data = &sharp_lq150x1lg11,
2689 .compatible = "shelly,sca07010-bfn-lnn",
2690 .data = &shelly_sca07010_bfn_lnn,
2692 .compatible = "starry,kr122ea0sra",
2693 .data = &starry_kr122ea0sra,
2695 .compatible = "tianma,tm070jdhg30",
2696 .data = &tianma_tm070jdhg30,
2698 .compatible = "tianma,tm070rvhg71",
2699 .data = &tianma_tm070rvhg71,
2701 .compatible = "toshiba,lt089ac29000",
2702 .data = &toshiba_lt089ac29000,
2704 .compatible = "tpk,f07a-0102",
2705 .data = &tpk_f07a_0102,
2707 .compatible = "tpk,f10a-0102",
2708 .data = &tpk_f10a_0102,
2710 .compatible = "urt,umsh-8596md-t",
2711 .data = &urt_umsh_8596md_parallel,
2713 .compatible = "urt,umsh-8596md-1t",
2714 .data = &urt_umsh_8596md_parallel,
2716 .compatible = "urt,umsh-8596md-7t",
2717 .data = &urt_umsh_8596md_parallel,
2719 .compatible = "urt,umsh-8596md-11t",
2720 .data = &urt_umsh_8596md_lvds,
2722 .compatible = "urt,umsh-8596md-19t",
2723 .data = &urt_umsh_8596md_lvds,
2725 .compatible = "urt,umsh-8596md-20t",
2726 .data = &urt_umsh_8596md_parallel,
2728 .compatible = "winstar,wf35ltiacd",
2729 .data = &winstar_wf35ltiacd,
2734 MODULE_DEVICE_TABLE(of, platform_of_match);
2736 static int panel_simple_platform_probe(struct platform_device *pdev)
2738 const struct of_device_id *id;
2740 id = of_match_node(platform_of_match, pdev->dev.of_node);
2744 return panel_simple_probe(&pdev->dev, id->data);
2747 static int panel_simple_platform_remove(struct platform_device *pdev)
2749 return panel_simple_remove(&pdev->dev);
2752 static void panel_simple_platform_shutdown(struct platform_device *pdev)
2754 panel_simple_shutdown(&pdev->dev);
2757 static struct platform_driver panel_simple_platform_driver = {
2759 .name = "panel-simple",
2760 .of_match_table = platform_of_match,
2762 .probe = panel_simple_platform_probe,
2763 .remove = panel_simple_platform_remove,
2764 .shutdown = panel_simple_platform_shutdown,
2767 struct panel_desc_dsi {
2768 struct panel_desc desc;
2770 unsigned long flags;
2771 enum mipi_dsi_pixel_format format;
2775 static const struct drm_display_mode auo_b080uan01_mode = {
2778 .hsync_start = 1200 + 62,
2779 .hsync_end = 1200 + 62 + 4,
2780 .htotal = 1200 + 62 + 4 + 62,
2782 .vsync_start = 1920 + 9,
2783 .vsync_end = 1920 + 9 + 2,
2784 .vtotal = 1920 + 9 + 2 + 8,
2788 static const struct panel_desc_dsi auo_b080uan01 = {
2790 .modes = &auo_b080uan01_mode,
2798 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
2799 .format = MIPI_DSI_FMT_RGB888,
2803 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
2806 .hsync_start = 1200 + 120,
2807 .hsync_end = 1200 + 120 + 20,
2808 .htotal = 1200 + 120 + 20 + 21,
2810 .vsync_start = 1920 + 21,
2811 .vsync_end = 1920 + 21 + 3,
2812 .vtotal = 1920 + 21 + 3 + 18,
2814 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2817 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
2819 .modes = &boe_tv080wum_nl0_mode,
2826 .flags = MIPI_DSI_MODE_VIDEO |
2827 MIPI_DSI_MODE_VIDEO_BURST |
2828 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
2829 .format = MIPI_DSI_FMT_RGB888,
2833 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
2836 .hsync_start = 800 + 32,
2837 .hsync_end = 800 + 32 + 1,
2838 .htotal = 800 + 32 + 1 + 57,
2840 .vsync_start = 1280 + 28,
2841 .vsync_end = 1280 + 28 + 1,
2842 .vtotal = 1280 + 28 + 1 + 14,
2846 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
2848 .modes = &lg_ld070wx3_sl01_mode,
2856 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
2857 .format = MIPI_DSI_FMT_RGB888,
2861 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
2864 .hsync_start = 720 + 12,
2865 .hsync_end = 720 + 12 + 4,
2866 .htotal = 720 + 12 + 4 + 112,
2868 .vsync_start = 1280 + 8,
2869 .vsync_end = 1280 + 8 + 4,
2870 .vtotal = 1280 + 8 + 4 + 12,
2874 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
2876 .modes = &lg_lh500wx1_sd03_mode,
2884 .flags = MIPI_DSI_MODE_VIDEO,
2885 .format = MIPI_DSI_FMT_RGB888,
2889 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
2892 .hsync_start = 1920 + 154,
2893 .hsync_end = 1920 + 154 + 16,
2894 .htotal = 1920 + 154 + 16 + 32,
2896 .vsync_start = 1200 + 17,
2897 .vsync_end = 1200 + 17 + 2,
2898 .vtotal = 1200 + 17 + 2 + 16,
2902 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
2904 .modes = &panasonic_vvx10f004b00_mode,
2912 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
2913 MIPI_DSI_CLOCK_NON_CONTINUOUS,
2914 .format = MIPI_DSI_FMT_RGB888,
2918 static const struct of_device_id dsi_of_match[] = {
2920 .compatible = "auo,b080uan01",
2921 .data = &auo_b080uan01
2923 .compatible = "boe,tv080wum-nl0",
2924 .data = &boe_tv080wum_nl0
2926 .compatible = "lg,ld070wx3-sl01",
2927 .data = &lg_ld070wx3_sl01
2929 .compatible = "lg,lh500wx1-sd03",
2930 .data = &lg_lh500wx1_sd03
2932 .compatible = "panasonic,vvx10f004b00",
2933 .data = &panasonic_vvx10f004b00
2938 MODULE_DEVICE_TABLE(of, dsi_of_match);
2940 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
2942 const struct panel_desc_dsi *desc;
2943 const struct of_device_id *id;
2946 id = of_match_node(dsi_of_match, dsi->dev.of_node);
2952 err = panel_simple_probe(&dsi->dev, &desc->desc);
2956 dsi->mode_flags = desc->flags;
2957 dsi->format = desc->format;
2958 dsi->lanes = desc->lanes;
2960 return mipi_dsi_attach(dsi);
2963 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
2967 err = mipi_dsi_detach(dsi);
2969 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
2971 return panel_simple_remove(&dsi->dev);
2974 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
2976 panel_simple_shutdown(&dsi->dev);
2979 static struct mipi_dsi_driver panel_simple_dsi_driver = {
2981 .name = "panel-simple-dsi",
2982 .of_match_table = dsi_of_match,
2984 .probe = panel_simple_dsi_probe,
2985 .remove = panel_simple_dsi_remove,
2986 .shutdown = panel_simple_dsi_shutdown,
2989 static int __init panel_simple_init(void)
2993 err = platform_driver_register(&panel_simple_platform_driver);
2997 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2998 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
3005 module_init(panel_simple_init);
3007 static void __exit panel_simple_exit(void)
3009 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
3010 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
3012 platform_driver_unregister(&panel_simple_platform_driver);
3014 module_exit(panel_simple_exit);
3016 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
3017 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
3018 MODULE_LICENSE("GPL and additional rights");