drivers/gpu/drm/omapdrm/omap_crtc.c

   1 /*
   2  * drivers/gpu/drm/omapdrm/omap_crtc.c
   3  *
   4  * Copyright (C) 2011 Texas Instruments
   5  * Author: Rob Clark <rob@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <drm/drm_atomic.h>
  21 #include <drm/drm_atomic_helper.h>
  22 #include <drm/drm_crtc.h>
  23 #include <drm/drm_crtc_helper.h>
  24 #include <drm/drm_mode.h>
  25 #include <drm/drm_plane_helper.h>
  26
  27 #include "omap_drv.h"
  28
  29 #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
  30
  31 struct omap_crtc {
  32         struct drm_crtc base;
  33
  34         const char *name;
  35         enum omap_channel channel;
  36
  37         struct videomode vm;
  38
  39         struct omap_drm_irq vblank_irq;
  40         struct omap_drm_irq error_irq;
  41
  42         bool ignore_digit_sync_lost;
  43
  44         bool pending;
  45         wait_queue_head_t pending_wait;
  46 };
  47
  48 /* -----------------------------------------------------------------------------
  49  * Helper Functions
  50  */
  51
  52 uint32_t pipe2vbl(struct drm_crtc *crtc)
  53 {
  54         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  55
  56         return dispc_mgr_get_vsync_irq(omap_crtc->channel);
  57 }
  58
  59 struct videomode *omap_crtc_timings(struct drm_crtc *crtc)
  60 {
  61         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  62         return &omap_crtc->vm;
  63 }
  64
  65 enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
  66 {
  67         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  68         return omap_crtc->channel;
  69 }
  70
  71 int omap_crtc_wait_pending(struct drm_crtc *crtc)
  72 {
  73         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  74
  75         /*
  76          * Timeout is set to a "sufficiently" high value, which should cover
  77          * a single frame refresh even on slower displays.
  78          */
  79         return wait_event_timeout(omap_crtc->pending_wait,
  80                                   !omap_crtc->pending,
  81                                   msecs_to_jiffies(250));
  82 }
  83
  84 /* -----------------------------------------------------------------------------
  85  * DSS Manager Functions
  86  */
  87
  88 /*
  89  * Manager-ops, callbacks from output when they need to configure
  90  * the upstream part of the video pipe.
  91  *
  92  * Most of these we can ignore until we add support for command-mode
  93  * panels.. for video-mode the crtc-helpers already do an adequate
  94  * job of sequencing the setup of the video pipe in the proper order
  95  */
  96
  97 /* ovl-mgr-id -> crtc */
  98 static struct omap_crtc *omap_crtcs[8];
  99 static struct omap_dss_device *omap_crtc_output[8];
 100
 101 /* we can probably ignore these until we support command-mode panels: */
 102 static int omap_crtc_dss_connect(enum omap_channel channel,
 103                 struct omap_dss_device *dst)
 104 {
 105         if (omap_crtc_output[channel])
 106                 return -EINVAL;
 107
 108         if ((dispc_mgr_get_supported_outputs(channel) & dst->id) == 0)
 109                 return -EINVAL;
 110
 111         omap_crtc_output[channel] = dst;
 112         dst->dispc_channel_connected = true;
 113
 114         return 0;
 115 }
 116
 117 static void omap_crtc_dss_disconnect(enum omap_channel channel,
 118                 struct omap_dss_device *dst)
 119 {
 120         omap_crtc_output[channel] = NULL;
 121         dst->dispc_channel_connected = false;
 122 }
 123
 124 static void omap_crtc_dss_start_update(enum omap_channel channel)
 125 {
 126 }
 127
 128 /* Called only from the encoder enable/disable and suspend/resume handlers. */
 129 static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
 130 {
 131         struct drm_device *dev = crtc->dev;
 132         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 133         enum omap_channel channel = omap_crtc->channel;
 134         struct omap_irq_wait *wait;
 135         u32 framedone_irq, vsync_irq;
 136         int ret;
 137
 138         if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) {
 139                 dispc_mgr_enable(channel, enable);
 140                 return;
 141         }
 142
 143         if (dispc_mgr_is_enabled(channel) == enable)
 144                 return;
 145
 146         if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
 147                 /*
 148                  * Digit output produces some sync lost interrupts during the
 149                  * first frame when enabling, so we need to ignore those.
 150                  */
 151                 omap_crtc->ignore_digit_sync_lost = true;
 152         }
 153
 154         framedone_irq = dispc_mgr_get_framedone_irq(channel);
 155         vsync_irq = dispc_mgr_get_vsync_irq(channel);
 156
 157         if (enable) {
 158                 wait = omap_irq_wait_init(dev, vsync_irq, 1);
 159         } else {
 160                 /*
 161                  * When we disable the digit output, we need to wait for
 162                  * FRAMEDONE to know that DISPC has finished with the output.
 163                  *
 164                  * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
 165                  * that case we need to use vsync interrupt, and wait for both
 166                  * even and odd frames.
 167                  */
 168
 169                 if (framedone_irq)
 170                         wait = omap_irq_wait_init(dev, framedone_irq, 1);
 171                 else
 172                         wait = omap_irq_wait_init(dev, vsync_irq, 2);
 173         }
 174
 175         dispc_mgr_enable(channel, enable);
 176
 177         ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
 178         if (ret) {
 179                 dev_err(dev->dev, "%s: timeout waiting for %s\n",
 180                                 omap_crtc->name, enable ? "enable" : "disable");
 181         }
 182
 183         if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
 184                 omap_crtc->ignore_digit_sync_lost = false;
 185                 /* make sure the irq handler sees the value above */
 186                 mb();
 187         }
 188 }
 189
 190
 191 static int omap_crtc_dss_enable(enum omap_channel channel)
 192 {
 193         struct omap_crtc *omap_crtc = omap_crtcs[channel];
 194         struct omap_overlay_manager_info info;
 195
 196         memset(&info, 0, sizeof(info));
 197         info.default_color = 0x00000000;
 198         info.trans_key = 0x00000000;
 199         info.trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
 200         info.trans_enabled = false;
 201
 202         dispc_mgr_setup(omap_crtc->channel, &info);
 203         dispc_mgr_set_timings(omap_crtc->channel,
 204                         &omap_crtc->vm);
 205         omap_crtc_set_enabled(&omap_crtc->base, true);
 206
 207         return 0;
 208 }
 209
 210 static void omap_crtc_dss_disable(enum omap_channel channel)
 211 {
 212         struct omap_crtc *omap_crtc = omap_crtcs[channel];
 213
 214         omap_crtc_set_enabled(&omap_crtc->base, false);
 215 }
 216
 217 static void omap_crtc_dss_set_timings(enum omap_channel channel,
 218                 const struct videomode *vm)
 219 {
 220         struct omap_crtc *omap_crtc = omap_crtcs[channel];
 221         DBG("%s", omap_crtc->name);
 222         omap_crtc->vm = *vm;
 223 }
 224
 225 static void omap_crtc_dss_set_lcd_config(enum omap_channel channel,
 226                 const struct dss_lcd_mgr_config *config)
 227 {
 228         struct omap_crtc *omap_crtc = omap_crtcs[channel];
 229         DBG("%s", omap_crtc->name);
 230         dispc_mgr_set_lcd_config(omap_crtc->channel, config);
 231 }
 232
 233 static int omap_crtc_dss_register_framedone(
 234                 enum omap_channel channel,
 235                 void (*handler)(void *), void *data)
 236 {
 237         return 0;
 238 }
 239
 240 static void omap_crtc_dss_unregister_framedone(
 241                 enum omap_channel channel,
 242                 void (*handler)(void *), void *data)
 243 {
 244 }
 245
 246 static const struct dss_mgr_ops mgr_ops = {
 247         .connect = omap_crtc_dss_connect,
 248         .disconnect = omap_crtc_dss_disconnect,
 249         .start_update = omap_crtc_dss_start_update,
 250         .enable = omap_crtc_dss_enable,
 251         .disable = omap_crtc_dss_disable,
 252         .set_timings = omap_crtc_dss_set_timings,
 253         .set_lcd_config = omap_crtc_dss_set_lcd_config,
 254         .register_framedone_handler = omap_crtc_dss_register_framedone,
 255         .unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
 256 };
 257
 258 /* -----------------------------------------------------------------------------
 259  * Setup, Flush and Page Flip
 260  */
 261
 262 static void omap_crtc_complete_page_flip(struct drm_crtc *crtc)
 263 {
 264         struct drm_pending_vblank_event *event;
 265         struct drm_device *dev = crtc->dev;
 266         unsigned long flags;
 267
 268         event = crtc->state->event;
 269
 270         if (!event)
 271                 return;
 272
 273         spin_lock_irqsave(&dev->event_lock, flags);
 274         drm_crtc_send_vblank_event(crtc, event);
 275         spin_unlock_irqrestore(&dev->event_lock, flags);
 276 }
 277
 278 static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
 279 {
 280         struct omap_crtc *omap_crtc =
 281                         container_of(irq, struct omap_crtc, error_irq);
 282
 283         if (omap_crtc->ignore_digit_sync_lost) {
 284                 irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
 285                 if (!irqstatus)
 286                         return;
 287         }
 288
 289         DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
 290 }
 291
 292 static void omap_crtc_vblank_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
 293 {
 294         struct omap_crtc *omap_crtc =
 295                         container_of(irq, struct omap_crtc, vblank_irq);
 296         struct drm_device *dev = omap_crtc->base.dev;
 297
 298         if (dispc_mgr_go_busy(omap_crtc->channel))
 299                 return;
 300
 301         DBG("%s: apply done", omap_crtc->name);
 302
 303         __omap_irq_unregister(dev, &omap_crtc->vblank_irq);
 304
 305         rmb();
 306         WARN_ON(!omap_crtc->pending);
 307         omap_crtc->pending = false;
 308         wmb();
 309
 310         /* wake up userspace */
 311         omap_crtc_complete_page_flip(&omap_crtc->base);
 312
 313         /* wake up omap_atomic_complete */
 314         wake_up(&omap_crtc->pending_wait);
 315 }
 316
 317 /* -----------------------------------------------------------------------------
 318  * CRTC Functions
 319  */
 320
 321 static void omap_crtc_destroy(struct drm_crtc *crtc)
 322 {
 323         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 324
 325         DBG("%s", omap_crtc->name);
 326
 327         WARN_ON(omap_crtc->vblank_irq.registered);
 328         omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
 329
 330         drm_crtc_cleanup(crtc);
 331
 332         kfree(omap_crtc);
 333 }
 334
 335 static void omap_crtc_enable(struct drm_crtc *crtc)
 336 {
 337         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 338
 339         DBG("%s", omap_crtc->name);
 340
 341         rmb();
 342         WARN_ON(omap_crtc->pending);
 343         omap_crtc->pending = true;
 344         wmb();
 345
 346         omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
 347
 348         drm_crtc_vblank_on(crtc);
 349 }
 350
 351 static void omap_crtc_disable(struct drm_crtc *crtc)
 352 {
 353         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 354
 355         DBG("%s", omap_crtc->name);
 356
 357         drm_crtc_vblank_off(crtc);
 358 }
 359
 360 static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
 361 {
 362         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 363         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 364
 365         DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
 366             omap_crtc->name, mode->base.id, mode->name,
 367             mode->vrefresh, mode->clock,
 368             mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
 369             mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal,
 370             mode->type, mode->flags);
 371
 372         drm_display_mode_to_videomode(mode, &omap_crtc->vm);
 373         omap_crtc->vm.flags |= DISPLAY_FLAGS_DE_HIGH |
 374                                DISPLAY_FLAGS_PIXDATA_POSEDGE |
 375                                DISPLAY_FLAGS_SYNC_NEGEDGE;
 376 }
 377
 378 static int omap_crtc_atomic_check(struct drm_crtc *crtc,
 379                                 struct drm_crtc_state *state)
 380 {
 381         if (state->color_mgmt_changed && state->gamma_lut) {
 382                 uint length = state->gamma_lut->length /
 383                         sizeof(struct drm_color_lut);
 384
 385                 if (length < 2)
 386                         return -EINVAL;
 387         }
 388
 389         return 0;
 390 }
 391
 392 static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
 393                                   struct drm_crtc_state *old_crtc_state)
 394 {
 395 }
 396
 397 static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
 398                                   struct drm_crtc_state *old_crtc_state)
 399 {
 400         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 401
 402         WARN_ON(omap_crtc->vblank_irq.registered);
 403
 404         if (crtc->state->color_mgmt_changed) {
 405                 struct drm_color_lut *lut = NULL;
 406                 uint length = 0;
 407
 408                 if (crtc->state->gamma_lut) {
 409                         lut = (struct drm_color_lut *)
 410                                 crtc->state->gamma_lut->data;
 411                         length = crtc->state->gamma_lut->length /
 412                                 sizeof(*lut);
 413                 }
 414                 dispc_mgr_set_gamma(omap_crtc->channel, lut, length);
 415         }
 416
 417         if (dispc_mgr_is_enabled(omap_crtc->channel)) {
 418
 419                 DBG("%s: GO", omap_crtc->name);
 420
 421                 rmb();
 422                 WARN_ON(omap_crtc->pending);
 423                 omap_crtc->pending = true;
 424                 wmb();
 425
 426                 dispc_mgr_go(omap_crtc->channel);
 427                 omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
 428         }
 429 }
 430
 431 static bool omap_crtc_is_plane_prop(struct drm_crtc *crtc,
 432         struct drm_property *property)
 433 {
 434         struct drm_device *dev = crtc->dev;
 435         struct omap_drm_private *priv = dev->dev_private;
 436
 437         return property == priv->zorder_prop ||
 438                 property == crtc->primary->rotation_property;
 439 }
 440
 441 static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
 442                                          struct drm_crtc_state *state,
 443                                          struct drm_property *property,
 444                                          uint64_t val)
 445 {
 446         if (omap_crtc_is_plane_prop(crtc, property)) {
 447                 struct drm_plane_state *plane_state;
 448                 struct drm_plane *plane = crtc->primary;
 449
 450                 /*
 451                  * Delegate property set to the primary plane. Get the plane
 452                  * state and set the property directly.
 453                  */
 454
 455                 plane_state = drm_atomic_get_plane_state(state->state, plane);
 456                 if (IS_ERR(plane_state))
 457                         return PTR_ERR(plane_state);
 458
 459                 return drm_atomic_plane_set_property(plane, plane_state,
 460                                 property, val);
 461         }
 462
 463         return -EINVAL;
 464 }
 465
 466 static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
 467                                          const struct drm_crtc_state *state,
 468                                          struct drm_property *property,
 469                                          uint64_t *val)
 470 {
 471         if (omap_crtc_is_plane_prop(crtc, property)) {
 472                 /*
 473                  * Delegate property get to the primary plane. The
 474                  * drm_atomic_plane_get_property() function isn't exported, but
 475                  * can be called through drm_object_property_get_value() as that
 476                  * will call drm_atomic_get_property() for atomic drivers.
 477                  */
 478                 return drm_object_property_get_value(&crtc->primary->base,
 479                                 property, val);
 480         }
 481
 482         return -EINVAL;
 483 }
 484
 485 static const struct drm_crtc_funcs omap_crtc_funcs = {
 486         .reset = drm_atomic_helper_crtc_reset,
 487         .set_config = drm_atomic_helper_set_config,
 488         .destroy = omap_crtc_destroy,
 489         .page_flip = drm_atomic_helper_page_flip,
 490         .gamma_set = drm_atomic_helper_legacy_gamma_set,
 491         .set_property = drm_atomic_helper_crtc_set_property,
 492         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 493         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 494         .atomic_set_property = omap_crtc_atomic_set_property,
 495         .atomic_get_property = omap_crtc_atomic_get_property,
 496 };
 497
 498 static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
 499         .mode_set_nofb = omap_crtc_mode_set_nofb,
 500         .disable = omap_crtc_disable,
 501         .enable = omap_crtc_enable,
 502         .atomic_check = omap_crtc_atomic_check,
 503         .atomic_begin = omap_crtc_atomic_begin,
 504         .atomic_flush = omap_crtc_atomic_flush,
 505 };
 506
 507 /* -----------------------------------------------------------------------------
 508  * Init and Cleanup
 509  */
 510
 511 static const char *channel_names[] = {
 512         [OMAP_DSS_CHANNEL_LCD] = "lcd",
 513         [OMAP_DSS_CHANNEL_DIGIT] = "tv",
 514         [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
 515         [OMAP_DSS_CHANNEL_LCD3] = "lcd3",
 516 };
 517
 518 void omap_crtc_pre_init(void)
 519 {
 520         dss_install_mgr_ops(&mgr_ops);
 521 }
 522
 523 void omap_crtc_pre_uninit(void)
 524 {
 525         dss_uninstall_mgr_ops();
 526 }
 527
 528 /* initialize crtc */
 529 struct drm_crtc *omap_crtc_init(struct drm_device *dev,
 530                 struct drm_plane *plane, enum omap_channel channel, int id)
 531 {
 532         struct drm_crtc *crtc = NULL;
 533         struct omap_crtc *omap_crtc;
 534         int ret;
 535
 536         DBG("%s", channel_names[channel]);
 537
 538         omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
 539         if (!omap_crtc)
 540                 return NULL;
 541
 542         crtc = &omap_crtc->base;
 543
 544         init_waitqueue_head(&omap_crtc->pending_wait);
 545
 546         omap_crtc->channel = channel;
 547         omap_crtc->name = channel_names[channel];
 548
 549         omap_crtc->vblank_irq.irqmask = pipe2vbl(crtc);
 550         omap_crtc->vblank_irq.irq = omap_crtc_vblank_irq;
 551
 552         omap_crtc->error_irq.irqmask =
 553                         dispc_mgr_get_sync_lost_irq(channel);
 554         omap_crtc->error_irq.irq = omap_crtc_error_irq;
 555         omap_irq_register(dev, &omap_crtc->error_irq);
 556
 557         ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
 558                                         &omap_crtc_funcs, NULL);
 559         if (ret < 0) {
 560                 kfree(omap_crtc);
 561                 return NULL;
 562         }
 563
 564         drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
 565
 566         /* The dispc API adapts to what ever size, but the HW supports
 567          * 256 element gamma table for LCDs and 1024 element table for
 568          * OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma
 569          * tables so lets use that. Size of HW gamma table can be
 570          * extracted with dispc_mgr_gamma_size(). If it returns 0
 571          * gamma table is not supprted.
 572          */
 573         if (dispc_mgr_gamma_size(channel)) {
 574                 uint gamma_lut_size = 256;
 575
 576                 drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size);
 577                 drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);
 578         }
 579
 580         omap_plane_install_properties(crtc->primary, &crtc->base);
 581
 582         omap_crtcs[channel] = omap_crtc;
 583
 584         return crtc;
 585 }