2 * linux/drivers/video/omap2/dss/dss.h
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
26 #include <linux/interrupt.h>
34 #ifdef DSS_SUBSYS_NAME
35 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
37 #define pr_fmt(fmt) fmt
40 #define DSSDBG(format, ...) \
41 pr_debug(format, ## __VA_ARGS__)
43 #ifdef DSS_SUBSYS_NAME
44 #define DSSERR(format, ...) \
45 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
48 #define DSSERR(format, ...) \
49 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
52 #ifdef DSS_SUBSYS_NAME
53 #define DSSINFO(format, ...) \
54 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
57 #define DSSINFO(format, ...) \
58 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
61 #ifdef DSS_SUBSYS_NAME
62 #define DSSWARN(format, ...) \
63 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
66 #define DSSWARN(format, ...) \
67 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
70 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
71 number. For example 7:0 */
72 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
73 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
74 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
75 #define FLD_MOD(orig, val, start, end) \
76 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
78 enum dss_io_pad_mode {
79 DSS_IO_PAD_MODE_RESET,
81 DSS_IO_PAD_MODE_BYPASS,
84 enum dss_hdmi_venc_clk_source_select {
89 enum dss_dsi_content_type {
91 DSS_DSI_CONTENT_GENERIC,
94 enum dss_writeback_channel {
115 #define DSS_PLL_MAX_HSDIVS 4
118 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
119 * Type-B PLLs: clkout[0] refers to m2.
121 struct dss_pll_clock_info {
122 /* rates that we get with dividers below */
124 unsigned long clkdco;
125 unsigned long clkout[DSS_PLL_MAX_HSDIVS];
131 u16 mX[DSS_PLL_MAX_HSDIVS];
136 int (*enable)(struct dss_pll *pll);
137 void (*disable)(struct dss_pll *pll);
138 int (*set_config)(struct dss_pll *pll,
139 const struct dss_pll_clock_info *cinfo);
148 unsigned long fint_min, fint_max;
149 unsigned long clkdco_min, clkdco_low, clkdco_max;
153 u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
166 struct regulator *regulator;
170 const struct dss_pll_hw *hw;
172 const struct dss_pll_ops *ops;
174 struct dss_pll_clock_info cinfo;
177 struct dispc_clock_info {
178 /* rates that we get with dividers below */
187 struct dss_lcd_mgr_config {
188 enum dss_io_pad_mode io_pad_mode;
193 struct dispc_clock_info clock_info;
195 int video_port_width;
197 int lcden_sig_polarity;
201 struct platform_device;
204 struct platform_device *dss_get_core_pdev(void);
205 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
206 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
207 int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
208 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
210 static inline bool dss_mgr_is_lcd(enum omap_channel id)
212 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
213 id == OMAP_DSS_CHANNEL_LCD3)
220 int dss_init_platform_driver(void) __init;
221 void dss_uninit_platform_driver(void);
223 int dss_runtime_get(void);
224 void dss_runtime_put(void);
226 unsigned long dss_get_dispc_clk_rate(void);
227 int dss_dpi_select_source(int port, enum omap_channel channel);
228 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
229 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
230 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
231 void dss_dump_clocks(struct seq_file *s);
234 struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
235 struct regulator *regulator);
236 void dss_video_pll_uninit(struct dss_pll *pll);
239 struct device_node *dss_of_port_get_parent_device(struct device_node *port);
240 u32 dss_of_port_get_port_number(struct device_node *port);
242 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
243 void dss_debug_dump_clocks(struct seq_file *s);
246 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable);
247 void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id,
248 enum omap_channel channel);
250 void dss_sdi_init(int datapairs);
251 int dss_sdi_enable(void);
252 void dss_sdi_disable(void);
254 void dss_select_dsi_clk_source(int dsi_module,
255 enum omap_dss_clk_source clk_src);
256 void dss_select_lcd_clk_source(enum omap_channel channel,
257 enum omap_dss_clk_source clk_src);
258 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
259 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
260 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
262 void dss_set_venc_output(enum omap_dss_venc_type type);
263 void dss_set_dac_pwrdn_bgz(bool enable);
265 int dss_set_fck_rate(unsigned long rate);
267 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
268 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
269 dss_div_calc_func func, void *data);
272 int sdi_init_platform_driver(void) __init;
273 void sdi_uninit_platform_driver(void);
275 #ifdef CONFIG_OMAP2_DSS_SDI
276 int sdi_init_port(struct platform_device *pdev, struct device_node *port);
277 void sdi_uninit_port(struct device_node *port);
279 static inline int sdi_init_port(struct platform_device *pdev,
280 struct device_node *port)
284 static inline void sdi_uninit_port(struct device_node *port)
291 #ifdef CONFIG_OMAP2_DSS_DSI
294 struct file_operations;
296 int dsi_init_platform_driver(void) __init;
297 void dsi_uninit_platform_driver(void);
299 void dsi_dump_clocks(struct seq_file *s);
301 void dsi_irq_handler(void);
302 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
305 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
307 WARN(1, "%s: DSI not compiled in, returning pixel_size as 0\n",
314 int dpi_init_platform_driver(void) __init;
315 void dpi_uninit_platform_driver(void);
317 #ifdef CONFIG_OMAP2_DSS_DPI
318 int dpi_init_port(struct platform_device *pdev, struct device_node *port);
319 void dpi_uninit_port(struct device_node *port);
321 static inline int dpi_init_port(struct platform_device *pdev,
322 struct device_node *port)
326 static inline void dpi_uninit_port(struct device_node *port)
332 int dispc_init_platform_driver(void) __init;
333 void dispc_uninit_platform_driver(void);
334 void dispc_dump_clocks(struct seq_file *s);
336 void dispc_enable_sidle(void);
337 void dispc_disable_sidle(void);
339 void dispc_lcd_enable_signal(bool enable);
340 void dispc_pck_free_enable(bool enable);
341 void dispc_enable_fifomerge(bool enable);
342 void dispc_enable_gamma_table(bool enable);
344 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
345 unsigned long pck, void *data);
346 bool dispc_div_calc(unsigned long dispc,
347 unsigned long pck_min, unsigned long pck_max,
348 dispc_div_calc_func func, void *data);
350 bool dispc_mgr_timings_ok(enum omap_channel channel,
351 const struct omap_video_timings *timings);
352 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
353 struct dispc_clock_info *cinfo);
356 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
357 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
358 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
361 void dispc_mgr_set_clock_div(enum omap_channel channel,
362 const struct dispc_clock_info *cinfo);
363 int dispc_mgr_get_clock_div(enum omap_channel channel,
364 struct dispc_clock_info *cinfo);
365 void dispc_set_tv_pclk(unsigned long pclk);
367 u32 dispc_wb_get_framedone_irq(void);
368 bool dispc_wb_go_busy(void);
369 void dispc_wb_go(void);
370 void dispc_wb_enable(bool enable);
371 bool dispc_wb_is_enabled(void);
372 void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
373 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
374 bool mem_to_mem, const struct omap_video_timings *timings);
377 int venc_init_platform_driver(void) __init;
378 void venc_uninit_platform_driver(void);
381 int hdmi4_init_platform_driver(void) __init;
382 void hdmi4_uninit_platform_driver(void);
384 int hdmi5_init_platform_driver(void) __init;
385 void hdmi5_uninit_platform_driver(void);
388 int rfbi_init_platform_driver(void) __init;
389 void rfbi_uninit_platform_driver(void);
392 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
393 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
396 for (b = 0; b < 32; ++b) {
397 if (irqstatus & (1 << b))
404 typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
405 unsigned long clkdco, void *data);
406 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
409 int dss_pll_register(struct dss_pll *pll);
410 void dss_pll_unregister(struct dss_pll *pll);
411 struct dss_pll *dss_pll_find(const char *name);
412 int dss_pll_enable(struct dss_pll *pll);
413 void dss_pll_disable(struct dss_pll *pll);
414 int dss_pll_set_config(struct dss_pll *pll,
415 const struct dss_pll_clock_info *cinfo);
417 bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco,
418 unsigned long out_min, unsigned long out_max,
419 dss_hsdiv_calc_func func, void *data);
420 bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin,
421 unsigned long pll_min, unsigned long pll_max,
422 dss_pll_calc_func func, void *data);
423 int dss_pll_write_config_type_a(struct dss_pll *pll,
424 const struct dss_pll_clock_info *cinfo);
425 int dss_pll_write_config_type_b(struct dss_pll *pll,
426 const struct dss_pll_clock_info *cinfo);
427 int dss_pll_wait_reset_done(struct dss_pll *pll);