drivers/gpu/drm/omapdrm/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/export.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/jiffies.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/delay.h>
  34 #include <linux/workqueue.h>
  35 #include <linux/hardirq.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/pm_runtime.h>
  38 #include <linux/sizes.h>
  39 #include <linux/mfd/syscon.h>
  40 #include <linux/regmap.h>
  41 #include <linux/of.h>
  42 #include <linux/component.h>
  43
  44 #include <video/omapdss.h>
  45
  46 #include "dss.h"
  47 #include "dss_features.h"
  48 #include "dispc.h"
  49
  50 /* DISPC */
  51 #define DISPC_SZ_REGS                   SZ_4K
  52
  53 enum omap_burst_size {
  54         BURST_SIZE_X2 = 0,
  55         BURST_SIZE_X4 = 1,
  56         BURST_SIZE_X8 = 2,
  57 };
  58
  59 #define REG_GET(idx, start, end) \
  60         FLD_GET(dispc_read_reg(idx), start, end)
  61
  62 #define REG_FLD_MOD(idx, val, start, end)                               \
  63         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  64
  65 struct dispc_features {
  66         u8 sw_start;
  67         u8 fp_start;
  68         u8 bp_start;
  69         u16 sw_max;
  70         u16 vp_max;
  71         u16 hp_max;
  72         u8 mgr_width_start;
  73         u8 mgr_height_start;
  74         u16 mgr_width_max;
  75         u16 mgr_height_max;
  76         unsigned long max_lcd_pclk;
  77         unsigned long max_tv_pclk;
  78         int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
  79                 const struct omap_video_timings *mgr_timings,
  80                 u16 width, u16 height, u16 out_width, u16 out_height,
  81                 enum omap_color_mode color_mode, bool *five_taps,
  82                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
  83                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
  84         unsigned long (*calc_core_clk) (unsigned long pclk,
  85                 u16 width, u16 height, u16 out_width, u16 out_height,
  86                 bool mem_to_mem);
  87         u8 num_fifos;
  88
  89         /* swap GFX & WB fifos */
  90         bool gfx_fifo_workaround:1;
  91
  92         /* no DISPC_IRQ_FRAMEDONETV on this SoC */
  93         bool no_framedone_tv:1;
  94
  95         /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
  96         bool mstandby_workaround:1;
  97
  98         bool set_max_preload:1;
  99
 100         /* PIXEL_INC is not added to the last pixel of a line */
 101         bool last_pixel_inc_missing:1;
 102
 103         /* POL_FREQ has ALIGN bit */
 104         bool supports_sync_align:1;
 105
 106         bool has_writeback:1;
 107
 108         bool supports_double_pixel:1;
 109
 110         /*
 111          * Field order for VENC is different than HDMI. We should handle this in
 112          * some intelligent manner, but as the SoCs have either HDMI or VENC,
 113          * never both, we can just use this flag for now.
 114          */
 115         bool reverse_ilace_field_order:1;
 116 };
 117
 118 #define DISPC_MAX_NR_FIFOS 5
 119
 120 static struct {
 121         struct platform_device *pdev;
 122         void __iomem    *base;
 123
 124         int irq;
 125         irq_handler_t user_handler;
 126         void *user_data;
 127
 128         unsigned long core_clk_rate;
 129         unsigned long tv_pclk_rate;
 130
 131         u32 fifo_size[DISPC_MAX_NR_FIFOS];
 132         /* maps which plane is using a fifo. fifo-id -> plane-id */
 133         int fifo_assignment[DISPC_MAX_NR_FIFOS];
 134
 135         bool            ctx_valid;
 136         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 137
 138         const struct dispc_features *feat;
 139
 140         bool is_enabled;
 141
 142         struct regmap *syscon_pol;
 143         u32 syscon_pol_offset;
 144
 145         /* DISPC_CONTROL & DISPC_CONFIG lock*/
 146         spinlock_t control_lock;
 147 } dispc;
 148
 149 enum omap_color_component {
 150         /* used for all color formats for OMAP3 and earlier
 151          * and for RGB and Y color component on OMAP4
 152          */
 153         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 154         /* used for UV component for
 155          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 156          * color formats on OMAP4
 157          */
 158         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 159 };
 160
 161 enum mgr_reg_fields {
 162         DISPC_MGR_FLD_ENABLE,
 163         DISPC_MGR_FLD_STNTFT,
 164         DISPC_MGR_FLD_GO,
 165         DISPC_MGR_FLD_TFTDATALINES,
 166         DISPC_MGR_FLD_STALLMODE,
 167         DISPC_MGR_FLD_TCKENABLE,
 168         DISPC_MGR_FLD_TCKSELECTION,
 169         DISPC_MGR_FLD_CPR,
 170         DISPC_MGR_FLD_FIFOHANDCHECK,
 171         /* used to maintain a count of the above fields */
 172         DISPC_MGR_FLD_NUM,
 173 };
 174
 175 struct dispc_reg_field {
 176         u16 reg;
 177         u8 high;
 178         u8 low;
 179 };
 180
 181 static const struct {
 182         const char *name;
 183         u32 vsync_irq;
 184         u32 framedone_irq;
 185         u32 sync_lost_irq;
 186         struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
 187 } mgr_desc[] = {
 188         [OMAP_DSS_CHANNEL_LCD] = {
 189                 .name           = "LCD",
 190                 .vsync_irq      = DISPC_IRQ_VSYNC,
 191                 .framedone_irq  = DISPC_IRQ_FRAMEDONE,
 192                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST,
 193                 .reg_desc       = {
 194                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  0,  0 },
 195                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL,  3,  3 },
 196                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  5,  5 },
 197                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL,  9,  8 },
 198                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL, 11, 11 },
 199                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  10, 10 },
 200                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  11, 11 },
 201                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG,  15, 15 },
 202                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 203                 },
 204         },
 205         [OMAP_DSS_CHANNEL_DIGIT] = {
 206                 .name           = "DIGIT",
 207                 .vsync_irq      = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
 208                 .framedone_irq  = DISPC_IRQ_FRAMEDONETV,
 209                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST_DIGIT,
 210                 .reg_desc       = {
 211                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  1,  1 },
 212                         [DISPC_MGR_FLD_STNTFT]          = { },
 213                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  6,  6 },
 214                         [DISPC_MGR_FLD_TFTDATALINES]    = { },
 215                         [DISPC_MGR_FLD_STALLMODE]       = { },
 216                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  12, 12 },
 217                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  13, 13 },
 218                         [DISPC_MGR_FLD_CPR]             = { },
 219                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 220                 },
 221         },
 222         [OMAP_DSS_CHANNEL_LCD2] = {
 223                 .name           = "LCD2",
 224                 .vsync_irq      = DISPC_IRQ_VSYNC2,
 225                 .framedone_irq  = DISPC_IRQ_FRAMEDONE2,
 226                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST2,
 227                 .reg_desc       = {
 228                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL2,  0,  0 },
 229                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL2,  3,  3 },
 230                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL2,  5,  5 },
 231                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL2,  9,  8 },
 232                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL2, 11, 11 },
 233                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG2,  10, 10 },
 234                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG2,  11, 11 },
 235                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG2,  15, 15 },
 236                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG2,  16, 16 },
 237                 },
 238         },
 239         [OMAP_DSS_CHANNEL_LCD3] = {
 240                 .name           = "LCD3",
 241                 .vsync_irq      = DISPC_IRQ_VSYNC3,
 242                 .framedone_irq  = DISPC_IRQ_FRAMEDONE3,
 243                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST3,
 244                 .reg_desc       = {
 245                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL3,  0,  0 },
 246                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL3,  3,  3 },
 247                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL3,  5,  5 },
 248                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL3,  9,  8 },
 249                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL3, 11, 11 },
 250                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG3,  10, 10 },
 251                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG3,  11, 11 },
 252                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG3,  15, 15 },
 253                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG3,  16, 16 },
 254                 },
 255         },
 256 };
 257
 258 struct color_conv_coef {
 259         int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
 260         int full_range;
 261 };
 262
 263 static unsigned long dispc_fclk_rate(void);
 264 static unsigned long dispc_core_clk_rate(void);
 265 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
 266 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
 267
 268 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
 269 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
 270
 271 static inline void dispc_write_reg(const u16 idx, u32 val)
 272 {
 273         __raw_writel(val, dispc.base + idx);
 274 }
 275
 276 static inline u32 dispc_read_reg(const u16 idx)
 277 {
 278         return __raw_readl(dispc.base + idx);
 279 }
 280
 281 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
 282 {
 283         const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 284         return REG_GET(rfld.reg, rfld.high, rfld.low);
 285 }
 286
 287 static void mgr_fld_write(enum omap_channel channel,
 288                                         enum mgr_reg_fields regfld, int val) {
 289         const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 290         const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
 291         unsigned long flags;
 292
 293         if (need_lock)
 294                 spin_lock_irqsave(&dispc.control_lock, flags);
 295
 296         REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
 297
 298         if (need_lock)
 299                 spin_unlock_irqrestore(&dispc.control_lock, flags);
 300 }
 301
 302 #define SR(reg) \
 303         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 304 #define RR(reg) \
 305         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 306
 307 static void dispc_save_context(void)
 308 {
 309         int i, j;
 310
 311         DSSDBG("dispc_save_context\n");
 312
 313         SR(IRQENABLE);
 314         SR(CONTROL);
 315         SR(CONFIG);
 316         SR(LINE_NUMBER);
 317         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 318                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 319                 SR(GLOBAL_ALPHA);
 320         if (dss_has_feature(FEAT_MGR_LCD2)) {
 321                 SR(CONTROL2);
 322                 SR(CONFIG2);
 323         }
 324         if (dss_has_feature(FEAT_MGR_LCD3)) {
 325                 SR(CONTROL3);
 326                 SR(CONFIG3);
 327         }
 328
 329         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 330                 SR(DEFAULT_COLOR(i));
 331                 SR(TRANS_COLOR(i));
 332                 SR(SIZE_MGR(i));
 333                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 334                         continue;
 335                 SR(TIMING_H(i));
 336                 SR(TIMING_V(i));
 337                 SR(POL_FREQ(i));
 338                 SR(DIVISORo(i));
 339
 340                 SR(DATA_CYCLE1(i));
 341                 SR(DATA_CYCLE2(i));
 342                 SR(DATA_CYCLE3(i));
 343
 344                 if (dss_has_feature(FEAT_CPR)) {
 345                         SR(CPR_COEF_R(i));
 346                         SR(CPR_COEF_G(i));
 347                         SR(CPR_COEF_B(i));
 348                 }
 349         }
 350
 351         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 352                 SR(OVL_BA0(i));
 353                 SR(OVL_BA1(i));
 354                 SR(OVL_POSITION(i));
 355                 SR(OVL_SIZE(i));
 356                 SR(OVL_ATTRIBUTES(i));
 357                 SR(OVL_FIFO_THRESHOLD(i));
 358                 SR(OVL_ROW_INC(i));
 359                 SR(OVL_PIXEL_INC(i));
 360                 if (dss_has_feature(FEAT_PRELOAD))
 361                         SR(OVL_PRELOAD(i));
 362                 if (i == OMAP_DSS_GFX) {
 363                         SR(OVL_WINDOW_SKIP(i));
 364                         SR(OVL_TABLE_BA(i));
 365                         continue;
 366                 }
 367                 SR(OVL_FIR(i));
 368                 SR(OVL_PICTURE_SIZE(i));
 369                 SR(OVL_ACCU0(i));
 370                 SR(OVL_ACCU1(i));
 371
 372                 for (j = 0; j < 8; j++)
 373                         SR(OVL_FIR_COEF_H(i, j));
 374
 375                 for (j = 0; j < 8; j++)
 376                         SR(OVL_FIR_COEF_HV(i, j));
 377
 378                 for (j = 0; j < 5; j++)
 379                         SR(OVL_CONV_COEF(i, j));
 380
 381                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 382                         for (j = 0; j < 8; j++)
 383                                 SR(OVL_FIR_COEF_V(i, j));
 384                 }
 385
 386                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 387                         SR(OVL_BA0_UV(i));
 388                         SR(OVL_BA1_UV(i));
 389                         SR(OVL_FIR2(i));
 390                         SR(OVL_ACCU2_0(i));
 391                         SR(OVL_ACCU2_1(i));
 392
 393                         for (j = 0; j < 8; j++)
 394                                 SR(OVL_FIR_COEF_H2(i, j));
 395
 396                         for (j = 0; j < 8; j++)
 397                                 SR(OVL_FIR_COEF_HV2(i, j));
 398
 399                         for (j = 0; j < 8; j++)
 400                                 SR(OVL_FIR_COEF_V2(i, j));
 401                 }
 402                 if (dss_has_feature(FEAT_ATTR2))
 403                         SR(OVL_ATTRIBUTES2(i));
 404         }
 405
 406         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 407                 SR(DIVISOR);
 408
 409         dispc.ctx_valid = true;
 410
 411         DSSDBG("context saved\n");
 412 }
 413
 414 static void dispc_restore_context(void)
 415 {
 416         int i, j;
 417
 418         DSSDBG("dispc_restore_context\n");
 419
 420         if (!dispc.ctx_valid)
 421                 return;
 422
 423         /*RR(IRQENABLE);*/
 424         /*RR(CONTROL);*/
 425         RR(CONFIG);
 426         RR(LINE_NUMBER);
 427         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 428                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 429                 RR(GLOBAL_ALPHA);
 430         if (dss_has_feature(FEAT_MGR_LCD2))
 431                 RR(CONFIG2);
 432         if (dss_has_feature(FEAT_MGR_LCD3))
 433                 RR(CONFIG3);
 434
 435         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 436                 RR(DEFAULT_COLOR(i));
 437                 RR(TRANS_COLOR(i));
 438                 RR(SIZE_MGR(i));
 439                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 440                         continue;
 441                 RR(TIMING_H(i));
 442                 RR(TIMING_V(i));
 443                 RR(POL_FREQ(i));
 444                 RR(DIVISORo(i));
 445
 446                 RR(DATA_CYCLE1(i));
 447                 RR(DATA_CYCLE2(i));
 448                 RR(DATA_CYCLE3(i));
 449
 450                 if (dss_has_feature(FEAT_CPR)) {
 451                         RR(CPR_COEF_R(i));
 452                         RR(CPR_COEF_G(i));
 453                         RR(CPR_COEF_B(i));
 454                 }
 455         }
 456
 457         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 458                 RR(OVL_BA0(i));
 459                 RR(OVL_BA1(i));
 460                 RR(OVL_POSITION(i));
 461                 RR(OVL_SIZE(i));
 462                 RR(OVL_ATTRIBUTES(i));
 463                 RR(OVL_FIFO_THRESHOLD(i));
 464                 RR(OVL_ROW_INC(i));
 465                 RR(OVL_PIXEL_INC(i));
 466                 if (dss_has_feature(FEAT_PRELOAD))
 467                         RR(OVL_PRELOAD(i));
 468                 if (i == OMAP_DSS_GFX) {
 469                         RR(OVL_WINDOW_SKIP(i));
 470                         RR(OVL_TABLE_BA(i));
 471                         continue;
 472                 }
 473                 RR(OVL_FIR(i));
 474                 RR(OVL_PICTURE_SIZE(i));
 475                 RR(OVL_ACCU0(i));
 476                 RR(OVL_ACCU1(i));
 477
 478                 for (j = 0; j < 8; j++)
 479                         RR(OVL_FIR_COEF_H(i, j));
 480
 481                 for (j = 0; j < 8; j++)
 482                         RR(OVL_FIR_COEF_HV(i, j));
 483
 484                 for (j = 0; j < 5; j++)
 485                         RR(OVL_CONV_COEF(i, j));
 486
 487                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 488                         for (j = 0; j < 8; j++)
 489                                 RR(OVL_FIR_COEF_V(i, j));
 490                 }
 491
 492                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 493                         RR(OVL_BA0_UV(i));
 494                         RR(OVL_BA1_UV(i));
 495                         RR(OVL_FIR2(i));
 496                         RR(OVL_ACCU2_0(i));
 497                         RR(OVL_ACCU2_1(i));
 498
 499                         for (j = 0; j < 8; j++)
 500                                 RR(OVL_FIR_COEF_H2(i, j));
 501
 502                         for (j = 0; j < 8; j++)
 503                                 RR(OVL_FIR_COEF_HV2(i, j));
 504
 505                         for (j = 0; j < 8; j++)
 506                                 RR(OVL_FIR_COEF_V2(i, j));
 507                 }
 508                 if (dss_has_feature(FEAT_ATTR2))
 509                         RR(OVL_ATTRIBUTES2(i));
 510         }
 511
 512         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 513                 RR(DIVISOR);
 514
 515         /* enable last, because LCD & DIGIT enable are here */
 516         RR(CONTROL);
 517         if (dss_has_feature(FEAT_MGR_LCD2))
 518                 RR(CONTROL2);
 519         if (dss_has_feature(FEAT_MGR_LCD3))
 520                 RR(CONTROL3);
 521         /* clear spurious SYNC_LOST_DIGIT interrupts */
 522         dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
 523
 524         /*
 525          * enable last so IRQs won't trigger before
 526          * the context is fully restored
 527          */
 528         RR(IRQENABLE);
 529
 530         DSSDBG("context restored\n");
 531 }
 532
 533 #undef SR
 534 #undef RR
 535
 536 int dispc_runtime_get(void)
 537 {
 538         int r;
 539
 540         DSSDBG("dispc_runtime_get\n");
 541
 542         r = pm_runtime_get_sync(&dispc.pdev->dev);
 543         WARN_ON(r < 0);
 544         return r < 0 ? r : 0;
 545 }
 546 EXPORT_SYMBOL(dispc_runtime_get);
 547
 548 void dispc_runtime_put(void)
 549 {
 550         int r;
 551
 552         DSSDBG("dispc_runtime_put\n");
 553
 554         r = pm_runtime_put_sync(&dispc.pdev->dev);
 555         WARN_ON(r < 0 && r != -ENOSYS);
 556 }
 557 EXPORT_SYMBOL(dispc_runtime_put);
 558
 559 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
 560 {
 561         return mgr_desc[channel].vsync_irq;
 562 }
 563 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
 564
 565 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
 566 {
 567         if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
 568                 return 0;
 569
 570         return mgr_desc[channel].framedone_irq;
 571 }
 572 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
 573
 574 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
 575 {
 576         return mgr_desc[channel].sync_lost_irq;
 577 }
 578 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
 579
 580 u32 dispc_wb_get_framedone_irq(void)
 581 {
 582         return DISPC_IRQ_FRAMEDONEWB;
 583 }
 584
 585 bool dispc_mgr_go_busy(enum omap_channel channel)
 586 {
 587         return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
 588 }
 589 EXPORT_SYMBOL(dispc_mgr_go_busy);
 590
 591 void dispc_mgr_go(enum omap_channel channel)
 592 {
 593         WARN_ON(!dispc_mgr_is_enabled(channel));
 594         WARN_ON(dispc_mgr_go_busy(channel));
 595
 596         DSSDBG("GO %s\n", mgr_desc[channel].name);
 597
 598         mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
 599 }
 600 EXPORT_SYMBOL(dispc_mgr_go);
 601
 602 bool dispc_wb_go_busy(void)
 603 {
 604         return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 605 }
 606
 607 void dispc_wb_go(void)
 608 {
 609         enum omap_plane plane = OMAP_DSS_WB;
 610         bool enable, go;
 611
 612         enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
 613
 614         if (!enable)
 615                 return;
 616
 617         go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 618         if (go) {
 619                 DSSERR("GO bit not down for WB\n");
 620                 return;
 621         }
 622
 623         REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
 624 }
 625
 626 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 627 {
 628         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 629 }
 630
 631 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 632 {
 633         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 634 }
 635
 636 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 637 {
 638         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 639 }
 640
 641 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 642 {
 643         BUG_ON(plane == OMAP_DSS_GFX);
 644
 645         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 646 }
 647
 648 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 649                 u32 value)
 650 {
 651         BUG_ON(plane == OMAP_DSS_GFX);
 652
 653         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 654 }
 655
 656 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 657 {
 658         BUG_ON(plane == OMAP_DSS_GFX);
 659
 660         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 661 }
 662
 663 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
 664                                 int fir_vinc, int five_taps,
 665                                 enum omap_color_component color_comp)
 666 {
 667         const struct dispc_coef *h_coef, *v_coef;
 668         int i;
 669
 670         h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
 671         v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
 672
 673         for (i = 0; i < 8; i++) {
 674                 u32 h, hv;
 675
 676                 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
 677                         | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
 678                         | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
 679                         | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
 680                 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
 681                         | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
 682                         | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
 683                         | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
 684
 685                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 686                         dispc_ovl_write_firh_reg(plane, i, h);
 687                         dispc_ovl_write_firhv_reg(plane, i, hv);
 688                 } else {
 689                         dispc_ovl_write_firh2_reg(plane, i, h);
 690                         dispc_ovl_write_firhv2_reg(plane, i, hv);
 691                 }
 692
 693         }
 694
 695         if (five_taps) {
 696                 for (i = 0; i < 8; i++) {
 697                         u32 v;
 698                         v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
 699                                 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
 700                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 701                                 dispc_ovl_write_firv_reg(plane, i, v);
 702                         else
 703                                 dispc_ovl_write_firv2_reg(plane, i, v);
 704                 }
 705         }
 706 }
 707
 708
 709 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
 710                 const struct color_conv_coef *ct)
 711 {
 712 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 713
 714         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
 715         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy,  ct->rcb));
 716         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
 717         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
 718         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
 719
 720         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
 721
 722 #undef CVAL
 723 }
 724
 725 static void dispc_setup_color_conv_coef(void)
 726 {
 727         int i;
 728         int num_ovl = dss_feat_get_num_ovls();
 729         const struct color_conv_coef ctbl_bt601_5_ovl = {
 730                 /* YUV -> RGB */
 731                 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
 732         };
 733         const struct color_conv_coef ctbl_bt601_5_wb = {
 734                 /* RGB -> YUV */
 735                 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
 736         };
 737
 738         for (i = 1; i < num_ovl; i++)
 739                 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
 740
 741         if (dispc.feat->has_writeback)
 742                 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
 743 }
 744
 745 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
 746 {
 747         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 748 }
 749
 750 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
 751 {
 752         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 753 }
 754
 755 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
 756 {
 757         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 758 }
 759
 760 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
 761 {
 762         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 763 }
 764
 765 static void dispc_ovl_set_pos(enum omap_plane plane,
 766                 enum omap_overlay_caps caps, int x, int y)
 767 {
 768         u32 val;
 769
 770         if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
 771                 return;
 772
 773         val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 774
 775         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 776 }
 777
 778 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
 779                 int height)
 780 {
 781         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 782
 783         if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
 784                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 785         else
 786                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 787 }
 788
 789 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
 790                 int height)
 791 {
 792         u32 val;
 793
 794         BUG_ON(plane == OMAP_DSS_GFX);
 795
 796         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 797
 798         if (plane == OMAP_DSS_WB)
 799                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 800         else
 801                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 802 }
 803
 804 static void dispc_ovl_set_zorder(enum omap_plane plane,
 805                 enum omap_overlay_caps caps, u8 zorder)
 806 {
 807         if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
 808                 return;
 809
 810         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
 811 }
 812
 813 static void dispc_ovl_enable_zorder_planes(void)
 814 {
 815         int i;
 816
 817         if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 818                 return;
 819
 820         for (i = 0; i < dss_feat_get_num_ovls(); i++)
 821                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
 822 }
 823
 824 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
 825                 enum omap_overlay_caps caps, bool enable)
 826 {
 827         if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 828                 return;
 829
 830         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 831 }
 832
 833 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
 834                 enum omap_overlay_caps caps, u8 global_alpha)
 835 {
 836         static const unsigned shifts[] = { 0, 8, 16, 24, };
 837         int shift;
 838
 839         if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 840                 return;
 841
 842         shift = shifts[plane];
 843         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 844 }
 845
 846 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
 847 {
 848         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 849 }
 850
 851 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
 852 {
 853         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 854 }
 855
 856 static void dispc_ovl_set_color_mode(enum omap_plane plane,
 857                 enum omap_color_mode color_mode)
 858 {
 859         u32 m = 0;
 860         if (plane != OMAP_DSS_GFX) {
 861                 switch (color_mode) {
 862                 case OMAP_DSS_COLOR_NV12:
 863                         m = 0x0; break;
 864                 case OMAP_DSS_COLOR_RGBX16:
 865                         m = 0x1; break;
 866                 case OMAP_DSS_COLOR_RGBA16:
 867                         m = 0x2; break;
 868                 case OMAP_DSS_COLOR_RGB12U:
 869                         m = 0x4; break;
 870                 case OMAP_DSS_COLOR_ARGB16:
 871                         m = 0x5; break;
 872                 case OMAP_DSS_COLOR_RGB16:
 873                         m = 0x6; break;
 874                 case OMAP_DSS_COLOR_ARGB16_1555:
 875                         m = 0x7; break;
 876                 case OMAP_DSS_COLOR_RGB24U:
 877                         m = 0x8; break;
 878                 case OMAP_DSS_COLOR_RGB24P:
 879                         m = 0x9; break;
 880                 case OMAP_DSS_COLOR_YUV2:
 881                         m = 0xa; break;
 882                 case OMAP_DSS_COLOR_UYVY:
 883                         m = 0xb; break;
 884                 case OMAP_DSS_COLOR_ARGB32:
 885                         m = 0xc; break;
 886                 case OMAP_DSS_COLOR_RGBA32:
 887                         m = 0xd; break;
 888                 case OMAP_DSS_COLOR_RGBX32:
 889                         m = 0xe; break;
 890                 case OMAP_DSS_COLOR_XRGB16_1555:
 891                         m = 0xf; break;
 892                 default:
 893                         BUG(); return;
 894                 }
 895         } else {
 896                 switch (color_mode) {
 897                 case OMAP_DSS_COLOR_CLUT1:
 898                         m = 0x0; break;
 899                 case OMAP_DSS_COLOR_CLUT2:
 900                         m = 0x1; break;
 901                 case OMAP_DSS_COLOR_CLUT4:
 902                         m = 0x2; break;
 903                 case OMAP_DSS_COLOR_CLUT8:
 904                         m = 0x3; break;
 905                 case OMAP_DSS_COLOR_RGB12U:
 906                         m = 0x4; break;
 907                 case OMAP_DSS_COLOR_ARGB16:
 908                         m = 0x5; break;
 909                 case OMAP_DSS_COLOR_RGB16:
 910                         m = 0x6; break;
 911                 case OMAP_DSS_COLOR_ARGB16_1555:
 912                         m = 0x7; break;
 913                 case OMAP_DSS_COLOR_RGB24U:
 914                         m = 0x8; break;
 915                 case OMAP_DSS_COLOR_RGB24P:
 916                         m = 0x9; break;
 917                 case OMAP_DSS_COLOR_RGBX16:
 918                         m = 0xa; break;
 919                 case OMAP_DSS_COLOR_RGBA16:
 920                         m = 0xb; break;
 921                 case OMAP_DSS_COLOR_ARGB32:
 922                         m = 0xc; break;
 923                 case OMAP_DSS_COLOR_RGBA32:
 924                         m = 0xd; break;
 925                 case OMAP_DSS_COLOR_RGBX32:
 926                         m = 0xe; break;
 927                 case OMAP_DSS_COLOR_XRGB16_1555:
 928                         m = 0xf; break;
 929                 default:
 930                         BUG(); return;
 931                 }
 932         }
 933
 934         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 935 }
 936
 937 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
 938                 enum omap_dss_rotation_type rotation_type)
 939 {
 940         if (dss_has_feature(FEAT_BURST_2D) == 0)
 941                 return;
 942
 943         if (rotation_type == OMAP_DSS_ROT_TILER)
 944                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
 945         else
 946                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
 947 }
 948
 949 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
 950 {
 951         int shift;
 952         u32 val;
 953         int chan = 0, chan2 = 0;
 954
 955         switch (plane) {
 956         case OMAP_DSS_GFX:
 957                 shift = 8;
 958                 break;
 959         case OMAP_DSS_VIDEO1:
 960         case OMAP_DSS_VIDEO2:
 961         case OMAP_DSS_VIDEO3:
 962                 shift = 16;
 963                 break;
 964         default:
 965                 BUG();
 966                 return;
 967         }
 968
 969         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 970         if (dss_has_feature(FEAT_MGR_LCD2)) {
 971                 switch (channel) {
 972                 case OMAP_DSS_CHANNEL_LCD:
 973                         chan = 0;
 974                         chan2 = 0;
 975                         break;
 976                 case OMAP_DSS_CHANNEL_DIGIT:
 977                         chan = 1;
 978                         chan2 = 0;
 979                         break;
 980                 case OMAP_DSS_CHANNEL_LCD2:
 981                         chan = 0;
 982                         chan2 = 1;
 983                         break;
 984                 case OMAP_DSS_CHANNEL_LCD3:
 985                         if (dss_has_feature(FEAT_MGR_LCD3)) {
 986                                 chan = 0;
 987                                 chan2 = 2;
 988                         } else {
 989                                 BUG();
 990                                 return;
 991                         }
 992                         break;
 993                 case OMAP_DSS_CHANNEL_WB:
 994                         chan = 0;
 995                         chan2 = 3;
 996                         break;
 997                 default:
 998                         BUG();
 999                         return;
1000                 }
1001
1002                 val = FLD_MOD(val, chan, shift, shift);
1003                 val = FLD_MOD(val, chan2, 31, 30);
1004         } else {
1005                 val = FLD_MOD(val, channel, shift, shift);
1006         }
1007         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1008 }
1009 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
1010
1011 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
1012 {
1013         int shift;
1014         u32 val;
1015
1016         switch (plane) {
1017         case OMAP_DSS_GFX:
1018                 shift = 8;
1019                 break;
1020         case OMAP_DSS_VIDEO1:
1021         case OMAP_DSS_VIDEO2:
1022         case OMAP_DSS_VIDEO3:
1023                 shift = 16;
1024                 break;
1025         default:
1026                 BUG();
1027                 return 0;
1028         }
1029
1030         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1031
1032         if (FLD_GET(val, shift, shift) == 1)
1033                 return OMAP_DSS_CHANNEL_DIGIT;
1034
1035         if (!dss_has_feature(FEAT_MGR_LCD2))
1036                 return OMAP_DSS_CHANNEL_LCD;
1037
1038         switch (FLD_GET(val, 31, 30)) {
1039         case 0:
1040         default:
1041                 return OMAP_DSS_CHANNEL_LCD;
1042         case 1:
1043                 return OMAP_DSS_CHANNEL_LCD2;
1044         case 2:
1045                 return OMAP_DSS_CHANNEL_LCD3;
1046         case 3:
1047                 return OMAP_DSS_CHANNEL_WB;
1048         }
1049 }
1050
1051 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1052 {
1053         enum omap_plane plane = OMAP_DSS_WB;
1054
1055         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1056 }
1057
1058 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1059                 enum omap_burst_size burst_size)
1060 {
1061         static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1062         int shift;
1063
1064         shift = shifts[plane];
1065         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1066 }
1067
1068 static void dispc_configure_burst_sizes(void)
1069 {
1070         int i;
1071         const int burst_size = BURST_SIZE_X8;
1072
1073         /* Configure burst size always to maximum size */
1074         for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1075                 dispc_ovl_set_burst_size(i, burst_size);
1076         if (dispc.feat->has_writeback)
1077                 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
1078 }
1079
1080 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1081 {
1082         unsigned unit = dss_feat_get_burst_size_unit();
1083         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1084         return unit * 8;
1085 }
1086
1087 void dispc_enable_gamma_table(bool enable)
1088 {
1089         /*
1090          * This is partially implemented to support only disabling of
1091          * the gamma table.
1092          */
1093         if (enable) {
1094                 DSSWARN("Gamma table enabling for TV not yet supported");
1095                 return;
1096         }
1097
1098         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1099 }
1100
1101 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1102 {
1103         if (channel == OMAP_DSS_CHANNEL_DIGIT)
1104                 return;
1105
1106         mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1107 }
1108
1109 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1110                 const struct omap_dss_cpr_coefs *coefs)
1111 {
1112         u32 coef_r, coef_g, coef_b;
1113
1114         if (!dss_mgr_is_lcd(channel))
1115                 return;
1116
1117         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1118                 FLD_VAL(coefs->rb, 9, 0);
1119         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1120                 FLD_VAL(coefs->gb, 9, 0);
1121         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1122                 FLD_VAL(coefs->bb, 9, 0);
1123
1124         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1125         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1126         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1127 }
1128
1129 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1130 {
1131         u32 val;
1132
1133         BUG_ON(plane == OMAP_DSS_GFX);
1134
1135         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1136         val = FLD_MOD(val, enable, 9, 9);
1137         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1138 }
1139
1140 static void dispc_ovl_enable_replication(enum omap_plane plane,
1141                 enum omap_overlay_caps caps, bool enable)
1142 {
1143         static const unsigned shifts[] = { 5, 10, 10, 10 };
1144         int shift;
1145
1146         if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1147                 return;
1148
1149         shift = shifts[plane];
1150         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1151 }
1152
1153 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1154                 u16 height)
1155 {
1156         u32 val;
1157
1158         val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1159                 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1160
1161         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1162 }
1163
1164 static void dispc_init_fifos(void)
1165 {
1166         u32 size;
1167         int fifo;
1168         u8 start, end;
1169         u32 unit;
1170         int i;
1171
1172         unit = dss_feat_get_buffer_size_unit();
1173
1174         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1175
1176         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1177                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1178                 size *= unit;
1179                 dispc.fifo_size[fifo] = size;
1180
1181                 /*
1182                  * By default fifos are mapped directly to overlays, fifo 0 to
1183                  * ovl 0, fifo 1 to ovl 1, etc.
1184                  */
1185                 dispc.fifo_assignment[fifo] = fifo;
1186         }
1187
1188         /*
1189          * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1190          * causes problems with certain use cases, like using the tiler in 2D
1191          * mode. The below hack swaps the fifos of GFX and WB planes, thus
1192          * giving GFX plane a larger fifo. WB but should work fine with a
1193          * smaller fifo.
1194          */
1195         if (dispc.feat->gfx_fifo_workaround) {
1196                 u32 v;
1197
1198                 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1199
1200                 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1201                 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1202                 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1203                 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1204
1205                 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1206
1207                 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1208                 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1209         }
1210
1211         /*
1212          * Setup default fifo thresholds.
1213          */
1214         for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1215                 u32 low, high;
1216                 const bool use_fifomerge = false;
1217                 const bool manual_update = false;
1218
1219                 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1220                         use_fifomerge, manual_update);
1221
1222                 dispc_ovl_set_fifo_threshold(i, low, high);
1223         }
1224
1225         if (dispc.feat->has_writeback) {
1226                 u32 low, high;
1227                 const bool use_fifomerge = false;
1228                 const bool manual_update = false;
1229
1230                 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1231                         use_fifomerge, manual_update);
1232
1233                 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1234         }
1235 }
1236
1237 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1238 {
1239         int fifo;
1240         u32 size = 0;
1241
1242         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1243                 if (dispc.fifo_assignment[fifo] == plane)
1244                         size += dispc.fifo_size[fifo];
1245         }
1246
1247         return size;
1248 }
1249
1250 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1251 {
1252         u8 hi_start, hi_end, lo_start, lo_end;
1253         u32 unit;
1254
1255         unit = dss_feat_get_buffer_size_unit();
1256
1257         WARN_ON(low % unit != 0);
1258         WARN_ON(high % unit != 0);
1259
1260         low /= unit;
1261         high /= unit;
1262
1263         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1264         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1265
1266         DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1267                         plane,
1268                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1269                                 lo_start, lo_end) * unit,
1270                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1271                                 hi_start, hi_end) * unit,
1272                         low * unit, high * unit);
1273
1274         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1275                         FLD_VAL(high, hi_start, hi_end) |
1276                         FLD_VAL(low, lo_start, lo_end));
1277
1278         /*
1279          * configure the preload to the pipeline's high threhold, if HT it's too
1280          * large for the preload field, set the threshold to the maximum value
1281          * that can be held by the preload register
1282          */
1283         if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1284                         plane != OMAP_DSS_WB)
1285                 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1286 }
1287
1288 void dispc_enable_fifomerge(bool enable)
1289 {
1290         if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1291                 WARN_ON(enable);
1292                 return;
1293         }
1294
1295         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1296         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1297 }
1298
1299 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1300                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1301                 bool manual_update)
1302 {
1303         /*
1304          * All sizes are in bytes. Both the buffer and burst are made of
1305          * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1306          */
1307
1308         unsigned buf_unit = dss_feat_get_buffer_size_unit();
1309         unsigned ovl_fifo_size, total_fifo_size, burst_size;
1310         int i;
1311
1312         burst_size = dispc_ovl_get_burst_size(plane);
1313         ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1314
1315         if (use_fifomerge) {
1316                 total_fifo_size = 0;
1317                 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1318                         total_fifo_size += dispc_ovl_get_fifo_size(i);
1319         } else {
1320                 total_fifo_size = ovl_fifo_size;
1321         }
1322
1323         /*
1324          * We use the same low threshold for both fifomerge and non-fifomerge
1325          * cases, but for fifomerge we calculate the high threshold using the
1326          * combined fifo size
1327          */
1328
1329         if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1330                 *fifo_low = ovl_fifo_size - burst_size * 2;
1331                 *fifo_high = total_fifo_size - burst_size;
1332         } else if (plane == OMAP_DSS_WB) {
1333                 /*
1334                  * Most optimal configuration for writeback is to push out data
1335                  * to the interconnect the moment writeback pushes enough pixels
1336                  * in the FIFO to form a burst
1337                  */
1338                 *fifo_low = 0;
1339                 *fifo_high = burst_size;
1340         } else {
1341                 *fifo_low = ovl_fifo_size - burst_size;
1342                 *fifo_high = total_fifo_size - buf_unit;
1343         }
1344 }
1345
1346 static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1347 {
1348         int bit;
1349
1350         if (plane == OMAP_DSS_GFX)
1351                 bit = 14;
1352         else
1353                 bit = 23;
1354
1355         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1356 }
1357
1358 static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1359         int low, int high)
1360 {
1361         dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1362                 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1363 }
1364
1365 static void dispc_init_mflag(void)
1366 {
1367         int i;
1368
1369         /*
1370          * HACK: NV12 color format and MFLAG seem to have problems working
1371          * together: using two displays, and having an NV12 overlay on one of
1372          * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1373          * Changing MFLAG thresholds and PRELOAD to certain values seem to
1374          * remove the errors, but there doesn't seem to be a clear logic on
1375          * which values work and which not.
1376          *
1377          * As a work-around, set force MFLAG to always on.
1378          */
1379         dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1380                 (1 << 0) |      /* MFLAG_CTRL = force always on */
1381                 (0 << 2));      /* MFLAG_START = disable */
1382
1383         for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1384                 u32 size = dispc_ovl_get_fifo_size(i);
1385                 u32 unit = dss_feat_get_buffer_size_unit();
1386                 u32 low, high;
1387
1388                 dispc_ovl_set_mflag(i, true);
1389
1390                 /*
1391                  * Simulation team suggests below thesholds:
1392                  * HT = fifosize * 5 / 8;
1393                  * LT = fifosize * 4 / 8;
1394                  */
1395
1396                 low = size * 4 / 8 / unit;
1397                 high = size * 5 / 8 / unit;
1398
1399                 dispc_ovl_set_mflag_threshold(i, low, high);
1400         }
1401
1402         if (dispc.feat->has_writeback) {
1403                 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1404                 u32 unit = dss_feat_get_buffer_size_unit();
1405                 u32 low, high;
1406
1407                 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1408
1409                 /*
1410                  * Simulation team suggests below thesholds:
1411                  * HT = fifosize * 5 / 8;
1412                  * LT = fifosize * 4 / 8;
1413                  */
1414
1415                 low = size * 4 / 8 / unit;
1416                 high = size * 5 / 8 / unit;
1417
1418                 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1419         }
1420 }
1421
1422 static void dispc_ovl_set_fir(enum omap_plane plane,
1423                                 int hinc, int vinc,
1424                                 enum omap_color_component color_comp)
1425 {
1426         u32 val;
1427
1428         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1429                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1430
1431                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1432                                         &hinc_start, &hinc_end);
1433                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1434                                         &vinc_start, &vinc_end);
1435                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1436                                 FLD_VAL(hinc, hinc_start, hinc_end);
1437
1438                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1439         } else {
1440                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1441                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1442         }
1443 }
1444
1445 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1446 {
1447         u32 val;
1448         u8 hor_start, hor_end, vert_start, vert_end;
1449
1450         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1451         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1452
1453         val = FLD_VAL(vaccu, vert_start, vert_end) |
1454                         FLD_VAL(haccu, hor_start, hor_end);
1455
1456         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1457 }
1458
1459 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1460 {
1461         u32 val;
1462         u8 hor_start, hor_end, vert_start, vert_end;
1463
1464         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1465         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1466
1467         val = FLD_VAL(vaccu, vert_start, vert_end) |
1468                         FLD_VAL(haccu, hor_start, hor_end);
1469
1470         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1471 }
1472
1473 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1474                 int vaccu)
1475 {
1476         u32 val;
1477
1478         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1479         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1480 }
1481
1482 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1483                 int vaccu)
1484 {
1485         u32 val;
1486
1487         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1488         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1489 }
1490
1491 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1492                 u16 orig_width, u16 orig_height,
1493                 u16 out_width, u16 out_height,
1494                 bool five_taps, u8 rotation,
1495                 enum omap_color_component color_comp)
1496 {
1497         int fir_hinc, fir_vinc;
1498
1499         fir_hinc = 1024 * orig_width / out_width;
1500         fir_vinc = 1024 * orig_height / out_height;
1501
1502         dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1503                                 color_comp);
1504         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1505 }
1506
1507 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1508                 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1509                 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1510 {
1511         int h_accu2_0, h_accu2_1;
1512         int v_accu2_0, v_accu2_1;
1513         int chroma_hinc, chroma_vinc;
1514         int idx;
1515
1516         struct accu {
1517                 s8 h0_m, h0_n;
1518                 s8 h1_m, h1_n;
1519                 s8 v0_m, v0_n;
1520                 s8 v1_m, v1_n;
1521         };
1522
1523         const struct accu *accu_table;
1524         const struct accu *accu_val;
1525
1526         static const struct accu accu_nv12[4] = {
1527                 {  0, 1,  0, 1 , -1, 2, 0, 1 },
1528                 {  1, 2, -3, 4 ,  0, 1, 0, 1 },
1529                 { -1, 1,  0, 1 , -1, 2, 0, 1 },
1530                 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1531         };
1532
1533         static const struct accu accu_nv12_ilace[4] = {
1534                 {  0, 1,  0, 1 , -3, 4, -1, 4 },
1535                 { -1, 4, -3, 4 ,  0, 1,  0, 1 },
1536                 { -1, 1,  0, 1 , -1, 4, -3, 4 },
1537                 { -3, 4, -3, 4 , -1, 1,  0, 1 },
1538         };
1539
1540         static const struct accu accu_yuv[4] = {
1541                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1542                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1543                 { -1, 1, 0, 1,  0, 1, 0, 1 },
1544                 {  0, 1, 0, 1, -1, 1, 0, 1 },
1545         };
1546
1547         switch (rotation) {
1548         case OMAP_DSS_ROT_0:
1549                 idx = 0;
1550                 break;
1551         case OMAP_DSS_ROT_90:
1552                 idx = 1;
1553                 break;
1554         case OMAP_DSS_ROT_180:
1555                 idx = 2;
1556                 break;
1557         case OMAP_DSS_ROT_270:
1558                 idx = 3;
1559                 break;
1560         default:
1561                 BUG();
1562                 return;
1563         }
1564
1565         switch (color_mode) {
1566         case OMAP_DSS_COLOR_NV12:
1567                 if (ilace)
1568                         accu_table = accu_nv12_ilace;
1569                 else
1570                         accu_table = accu_nv12;
1571                 break;
1572         case OMAP_DSS_COLOR_YUV2:
1573         case OMAP_DSS_COLOR_UYVY:
1574                 accu_table = accu_yuv;
1575                 break;
1576         default:
1577                 BUG();
1578                 return;
1579         }
1580
1581         accu_val = &accu_table[idx];
1582
1583         chroma_hinc = 1024 * orig_width / out_width;
1584         chroma_vinc = 1024 * orig_height / out_height;
1585
1586         h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1587         h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1588         v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1589         v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1590
1591         dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1592         dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1593 }
1594
1595 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1596                 u16 orig_width, u16 orig_height,
1597                 u16 out_width, u16 out_height,
1598                 bool ilace, bool five_taps,
1599                 bool fieldmode, enum omap_color_mode color_mode,
1600                 u8 rotation)
1601 {
1602         int accu0 = 0;
1603         int accu1 = 0;
1604         u32 l;
1605
1606         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1607                                 out_width, out_height, five_taps,
1608                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1609         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1610
1611         /* RESIZEENABLE and VERTICALTAPS */
1612         l &= ~((0x3 << 5) | (0x1 << 21));
1613         l |= (orig_width != out_width) ? (1 << 5) : 0;
1614         l |= (orig_height != out_height) ? (1 << 6) : 0;
1615         l |= five_taps ? (1 << 21) : 0;
1616
1617         /* VRESIZECONF and HRESIZECONF */
1618         if (dss_has_feature(FEAT_RESIZECONF)) {
1619                 l &= ~(0x3 << 7);
1620                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1621                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1622         }
1623
1624         /* LINEBUFFERSPLIT */
1625         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1626                 l &= ~(0x1 << 22);
1627                 l |= five_taps ? (1 << 22) : 0;
1628         }
1629
1630         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1631
1632         /*
1633          * field 0 = even field = bottom field
1634          * field 1 = odd field = top field
1635          */
1636         if (ilace && !fieldmode) {
1637                 accu1 = 0;
1638                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1639                 if (accu0 >= 1024/2) {
1640                         accu1 = 1024/2;
1641                         accu0 -= accu1;
1642                 }
1643         }
1644
1645         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1646         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1647 }
1648
1649 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1650                 u16 orig_width, u16 orig_height,
1651                 u16 out_width, u16 out_height,
1652                 bool ilace, bool five_taps,
1653                 bool fieldmode, enum omap_color_mode color_mode,
1654                 u8 rotation)
1655 {
1656         int scale_x = out_width != orig_width;
1657         int scale_y = out_height != orig_height;
1658         bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1659
1660         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1661                 return;
1662         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1663                         color_mode != OMAP_DSS_COLOR_UYVY &&
1664                         color_mode != OMAP_DSS_COLOR_NV12)) {
1665                 /* reset chroma resampling for RGB formats  */
1666                 if (plane != OMAP_DSS_WB)
1667                         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1668                 return;
1669         }
1670
1671         dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1672                         out_height, ilace, color_mode, rotation);
1673
1674         switch (color_mode) {
1675         case OMAP_DSS_COLOR_NV12:
1676                 if (chroma_upscale) {
1677                         /* UV is subsampled by 2 horizontally and vertically */
1678                         orig_height >>= 1;
1679                         orig_width >>= 1;
1680                 } else {
1681                         /* UV is downsampled by 2 horizontally and vertically */
1682                         orig_height <<= 1;
1683                         orig_width <<= 1;
1684                 }
1685
1686                 break;
1687         case OMAP_DSS_COLOR_YUV2:
1688         case OMAP_DSS_COLOR_UYVY:
1689                 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1690                 if (rotation == OMAP_DSS_ROT_0 ||
1691                                 rotation == OMAP_DSS_ROT_180) {
1692                         if (chroma_upscale)
1693                                 /* UV is subsampled by 2 horizontally */
1694                                 orig_width >>= 1;
1695                         else
1696                                 /* UV is downsampled by 2 horizontally */
1697                                 orig_width <<= 1;
1698                 }
1699
1700                 /* must use FIR for YUV422 if rotated */
1701                 if (rotation != OMAP_DSS_ROT_0)
1702                         scale_x = scale_y = true;
1703
1704                 break;
1705         default:
1706                 BUG();
1707                 return;
1708         }
1709
1710         if (out_width != orig_width)
1711                 scale_x = true;
1712         if (out_height != orig_height)
1713                 scale_y = true;
1714
1715         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1716                         out_width, out_height, five_taps,
1717                                 rotation, DISPC_COLOR_COMPONENT_UV);
1718
1719         if (plane != OMAP_DSS_WB)
1720                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1721                         (scale_x || scale_y) ? 1 : 0, 8, 8);
1722
1723         /* set H scaling */
1724         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1725         /* set V scaling */
1726         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1727 }
1728
1729 static void dispc_ovl_set_scaling(enum omap_plane plane,
1730                 u16 orig_width, u16 orig_height,
1731                 u16 out_width, u16 out_height,
1732                 bool ilace, bool five_taps,
1733                 bool fieldmode, enum omap_color_mode color_mode,
1734                 u8 rotation)
1735 {
1736         BUG_ON(plane == OMAP_DSS_GFX);
1737
1738         dispc_ovl_set_scaling_common(plane,
1739                         orig_width, orig_height,
1740                         out_width, out_height,
1741                         ilace, five_taps,
1742                         fieldmode, color_mode,
1743                         rotation);
1744
1745         dispc_ovl_set_scaling_uv(plane,
1746                 orig_width, orig_height,
1747                 out_width, out_height,
1748                 ilace, five_taps,
1749                 fieldmode, color_mode,
1750                 rotation);
1751 }
1752
1753 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1754                 enum omap_dss_rotation_type rotation_type,
1755                 bool mirroring, enum omap_color_mode color_mode)
1756 {
1757         bool row_repeat = false;
1758         int vidrot = 0;
1759
1760         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1761                         color_mode == OMAP_DSS_COLOR_UYVY) {
1762
1763                 if (mirroring) {
1764                         switch (rotation) {
1765                         case OMAP_DSS_ROT_0:
1766                                 vidrot = 2;
1767                                 break;
1768                         case OMAP_DSS_ROT_90:
1769                                 vidrot = 1;
1770                                 break;
1771                         case OMAP_DSS_ROT_180:
1772                                 vidrot = 0;
1773                                 break;
1774                         case OMAP_DSS_ROT_270:
1775                                 vidrot = 3;
1776                                 break;
1777                         }
1778                 } else {
1779                         switch (rotation) {
1780                         case OMAP_DSS_ROT_0:
1781                                 vidrot = 0;
1782                                 break;
1783                         case OMAP_DSS_ROT_90:
1784                                 vidrot = 1;
1785                                 break;
1786                         case OMAP_DSS_ROT_180:
1787                                 vidrot = 2;
1788                                 break;
1789                         case OMAP_DSS_ROT_270:
1790                                 vidrot = 3;
1791                                 break;
1792                         }
1793                 }
1794
1795                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1796                         row_repeat = true;
1797                 else
1798                         row_repeat = false;
1799         }
1800
1801         /*
1802          * OMAP4/5 Errata i631:
1803          * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1804          * rows beyond the framebuffer, which may cause OCP error.
1805          */
1806         if (color_mode == OMAP_DSS_COLOR_NV12 &&
1807                         rotation_type != OMAP_DSS_ROT_TILER)
1808                 vidrot = 1;
1809
1810         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1811         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1812                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1813                         row_repeat ? 1 : 0, 18, 18);
1814
1815         if (color_mode == OMAP_DSS_COLOR_NV12) {
1816                 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1817                                         (rotation == OMAP_DSS_ROT_0 ||
1818                                         rotation == OMAP_DSS_ROT_180);
1819                 /* DOUBLESTRIDE */
1820                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1821         }
1822
1823 }
1824
1825 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1826 {
1827         switch (color_mode) {
1828         case OMAP_DSS_COLOR_CLUT1:
1829                 return 1;
1830         case OMAP_DSS_COLOR_CLUT2:
1831                 return 2;
1832         case OMAP_DSS_COLOR_CLUT4:
1833                 return 4;
1834         case OMAP_DSS_COLOR_CLUT8:
1835         case OMAP_DSS_COLOR_NV12:
1836                 return 8;
1837         case OMAP_DSS_COLOR_RGB12U:
1838         case OMAP_DSS_COLOR_RGB16:
1839         case OMAP_DSS_COLOR_ARGB16:
1840         case OMAP_DSS_COLOR_YUV2:
1841         case OMAP_DSS_COLOR_UYVY:
1842         case OMAP_DSS_COLOR_RGBA16:
1843         case OMAP_DSS_COLOR_RGBX16:
1844         case OMAP_DSS_COLOR_ARGB16_1555:
1845         case OMAP_DSS_COLOR_XRGB16_1555:
1846                 return 16;
1847         case OMAP_DSS_COLOR_RGB24P:
1848                 return 24;
1849         case OMAP_DSS_COLOR_RGB24U:
1850         case OMAP_DSS_COLOR_ARGB32:
1851         case OMAP_DSS_COLOR_RGBA32:
1852         case OMAP_DSS_COLOR_RGBX32:
1853                 return 32;
1854         default:
1855                 BUG();
1856                 return 0;
1857         }
1858 }
1859
1860 static s32 pixinc(int pixels, u8 ps)
1861 {
1862         if (pixels == 1)
1863                 return 1;
1864         else if (pixels > 1)
1865                 return 1 + (pixels - 1) * ps;
1866         else if (pixels < 0)
1867                 return 1 - (-pixels + 1) * ps;
1868         else
1869                 BUG();
1870                 return 0;
1871 }
1872
1873 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1874                 u16 screen_width,
1875                 u16 width, u16 height,
1876                 enum omap_color_mode color_mode, bool fieldmode,
1877                 unsigned int field_offset,
1878                 unsigned *offset0, unsigned *offset1,
1879                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1880 {
1881         u8 ps;
1882
1883         /* FIXME CLUT formats */
1884         switch (color_mode) {
1885         case OMAP_DSS_COLOR_CLUT1:
1886         case OMAP_DSS_COLOR_CLUT2:
1887         case OMAP_DSS_COLOR_CLUT4:
1888         case OMAP_DSS_COLOR_CLUT8:
1889                 BUG();
1890                 return;
1891         case OMAP_DSS_COLOR_YUV2:
1892         case OMAP_DSS_COLOR_UYVY:
1893                 ps = 4;
1894                 break;
1895         default:
1896                 ps = color_mode_to_bpp(color_mode) / 8;
1897                 break;
1898         }
1899
1900         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1901                         width, height);
1902
1903         /*
1904          * field 0 = even field = bottom field
1905          * field 1 = odd field = top field
1906          */
1907         switch (rotation + mirror * 4) {
1908         case OMAP_DSS_ROT_0:
1909         case OMAP_DSS_ROT_180:
1910                 /*
1911                  * If the pixel format is YUV or UYVY divide the width
1912                  * of the image by 2 for 0 and 180 degree rotation.
1913                  */
1914                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1915                         color_mode == OMAP_DSS_COLOR_UYVY)
1916                         width = width >> 1;
1917         case OMAP_DSS_ROT_90:
1918         case OMAP_DSS_ROT_270:
1919                 *offset1 = 0;
1920                 if (field_offset)
1921                         *offset0 = field_offset * screen_width * ps;
1922                 else
1923                         *offset0 = 0;
1924
1925                 *row_inc = pixinc(1 +
1926                         (y_predecim * screen_width - x_predecim * width) +
1927                         (fieldmode ? screen_width : 0), ps);
1928                 *pix_inc = pixinc(x_predecim, ps);
1929                 break;
1930
1931         case OMAP_DSS_ROT_0 + 4:
1932         case OMAP_DSS_ROT_180 + 4:
1933                 /* If the pixel format is YUV or UYVY divide the width
1934                  * of the image by 2  for 0 degree and 180 degree
1935                  */
1936                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1937                         color_mode == OMAP_DSS_COLOR_UYVY)
1938                         width = width >> 1;
1939         case OMAP_DSS_ROT_90 + 4:
1940         case OMAP_DSS_ROT_270 + 4:
1941                 *offset1 = 0;
1942                 if (field_offset)
1943                         *offset0 = field_offset * screen_width * ps;
1944                 else
1945                         *offset0 = 0;
1946                 *row_inc = pixinc(1 -
1947                         (y_predecim * screen_width + x_predecim * width) -
1948                         (fieldmode ? screen_width : 0), ps);
1949                 *pix_inc = pixinc(x_predecim, ps);
1950                 break;
1951
1952         default:
1953                 BUG();
1954                 return;
1955         }
1956 }
1957
1958 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1959                 u16 screen_width,
1960                 u16 width, u16 height,
1961                 enum omap_color_mode color_mode, bool fieldmode,
1962                 unsigned int field_offset,
1963                 unsigned *offset0, unsigned *offset1,
1964                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1965 {
1966         u8 ps;
1967         u16 fbw, fbh;
1968
1969         /* FIXME CLUT formats */
1970         switch (color_mode) {
1971         case OMAP_DSS_COLOR_CLUT1:
1972         case OMAP_DSS_COLOR_CLUT2:
1973         case OMAP_DSS_COLOR_CLUT4:
1974         case OMAP_DSS_COLOR_CLUT8:
1975                 BUG();
1976                 return;
1977         default:
1978                 ps = color_mode_to_bpp(color_mode) / 8;
1979                 break;
1980         }
1981
1982         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1983                         width, height);
1984
1985         /* width & height are overlay sizes, convert to fb sizes */
1986
1987         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1988                 fbw = width;
1989                 fbh = height;
1990         } else {
1991                 fbw = height;
1992                 fbh = width;
1993         }
1994
1995         /*
1996          * field 0 = even field = bottom field
1997          * field 1 = odd field = top field
1998          */
1999         switch (rotation + mirror * 4) {
2000         case OMAP_DSS_ROT_0:
2001                 *offset1 = 0;
2002                 if (field_offset)
2003                         *offset0 = *offset1 + field_offset * screen_width * ps;
2004                 else
2005                         *offset0 = *offset1;
2006                 *row_inc = pixinc(1 +
2007                         (y_predecim * screen_width - fbw * x_predecim) +
2008                         (fieldmode ? screen_width : 0), ps);
2009                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2010                         color_mode == OMAP_DSS_COLOR_UYVY)
2011                         *pix_inc = pixinc(x_predecim, 2 * ps);
2012                 else
2013                         *pix_inc = pixinc(x_predecim, ps);
2014                 break;
2015         case OMAP_DSS_ROT_90:
2016                 *offset1 = screen_width * (fbh - 1) * ps;
2017                 if (field_offset)
2018                         *offset0 = *offset1 + field_offset * ps;
2019                 else
2020                         *offset0 = *offset1;
2021                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
2022                                 y_predecim + (fieldmode ? 1 : 0), ps);
2023                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2024                 break;
2025         case OMAP_DSS_ROT_180:
2026                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2027                 if (field_offset)
2028                         *offset0 = *offset1 - field_offset * screen_width * ps;
2029                 else
2030                         *offset0 = *offset1;
2031                 *row_inc = pixinc(-1 -
2032                         (y_predecim * screen_width - fbw * x_predecim) -
2033                         (fieldmode ? screen_width : 0), ps);
2034                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2035                         color_mode == OMAP_DSS_COLOR_UYVY)
2036                         *pix_inc = pixinc(-x_predecim, 2 * ps);
2037                 else
2038                         *pix_inc = pixinc(-x_predecim, ps);
2039                 break;
2040         case OMAP_DSS_ROT_270:
2041                 *offset1 = (fbw - 1) * ps;
2042                 if (field_offset)
2043                         *offset0 = *offset1 - field_offset * ps;
2044                 else
2045                         *offset0 = *offset1;
2046                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
2047                                 y_predecim - (fieldmode ? 1 : 0), ps);
2048                 *pix_inc = pixinc(x_predecim * screen_width, ps);
2049                 break;
2050
2051         /* mirroring */
2052         case OMAP_DSS_ROT_0 + 4:
2053                 *offset1 = (fbw - 1) * ps;
2054                 if (field_offset)
2055                         *offset0 = *offset1 + field_offset * screen_width * ps;
2056                 else
2057                         *offset0 = *offset1;
2058                 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
2059                                 (fieldmode ? screen_width : 0),
2060                                 ps);
2061                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2062                         color_mode == OMAP_DSS_COLOR_UYVY)
2063                         *pix_inc = pixinc(-x_predecim, 2 * ps);
2064                 else
2065                         *pix_inc = pixinc(-x_predecim, ps);
2066                 break;
2067
2068         case OMAP_DSS_ROT_90 + 4:
2069                 *offset1 = 0;
2070                 if (field_offset)
2071                         *offset0 = *offset1 + field_offset * ps;
2072                 else
2073                         *offset0 = *offset1;
2074                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2075                                 y_predecim + (fieldmode ? 1 : 0),
2076                                 ps);
2077                 *pix_inc = pixinc(x_predecim * screen_width, ps);
2078                 break;
2079
2080         case OMAP_DSS_ROT_180 + 4:
2081                 *offset1 = screen_width * (fbh - 1) * ps;
2082                 if (field_offset)
2083                         *offset0 = *offset1 - field_offset * screen_width * ps;
2084                 else
2085                         *offset0 = *offset1;
2086                 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
2087                                 (fieldmode ? screen_width : 0),
2088                                 ps);
2089                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2090                         color_mode == OMAP_DSS_COLOR_UYVY)
2091                         *pix_inc = pixinc(x_predecim, 2 * ps);
2092                 else
2093                         *pix_inc = pixinc(x_predecim, ps);
2094                 break;
2095
2096         case OMAP_DSS_ROT_270 + 4:
2097                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2098                 if (field_offset)
2099                         *offset0 = *offset1 - field_offset * ps;
2100                 else
2101                         *offset0 = *offset1;
2102                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2103                                 y_predecim - (fieldmode ? 1 : 0),
2104                                 ps);
2105                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2106                 break;
2107
2108         default:
2109                 BUG();
2110                 return;
2111         }
2112 }
2113
2114 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2115                 enum omap_color_mode color_mode, bool fieldmode,
2116                 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2117                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2118 {
2119         u8 ps;
2120
2121         switch (color_mode) {
2122         case OMAP_DSS_COLOR_CLUT1:
2123         case OMAP_DSS_COLOR_CLUT2:
2124         case OMAP_DSS_COLOR_CLUT4:
2125         case OMAP_DSS_COLOR_CLUT8:
2126                 BUG();
2127                 return;
2128         default:
2129                 ps = color_mode_to_bpp(color_mode) / 8;
2130                 break;
2131         }
2132
2133         DSSDBG("scrw %d, width %d\n", screen_width, width);
2134
2135         /*
2136          * field 0 = even field = bottom field
2137          * field 1 = odd field = top field
2138          */
2139         *offset1 = 0;
2140         if (field_offset)
2141                 *offset0 = *offset1 + field_offset * screen_width * ps;
2142         else
2143                 *offset0 = *offset1;
2144         *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2145                         (fieldmode ? screen_width : 0), ps);
2146         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2147                 color_mode == OMAP_DSS_COLOR_UYVY)
2148                 *pix_inc = pixinc(x_predecim, 2 * ps);
2149         else
2150                 *pix_inc = pixinc(x_predecim, ps);
2151 }
2152
2153 /*
2154  * This function is used to avoid synclosts in OMAP3, because of some
2155  * undocumented horizontal position and timing related limitations.
2156  */
2157 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2158                 const struct omap_video_timings *t, u16 pos_x,
2159                 u16 width, u16 height, u16 out_width, u16 out_height,
2160                 bool five_taps)
2161 {
2162         const int ds = DIV_ROUND_UP(height, out_height);
2163         unsigned long nonactive;
2164         static const u8 limits[3] = { 8, 10, 20 };
2165         u64 val, blank;
2166         int i;
2167
2168         nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2169
2170         i = 0;
2171         if (out_height < height)
2172                 i++;
2173         if (out_width < width)
2174                 i++;
2175         blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2176         DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2177         if (blank <= limits[i])
2178                 return -EINVAL;
2179
2180         /* FIXME add checks for 3-tap filter once the limitations are known */
2181         if (!five_taps)
2182                 return 0;
2183
2184         /*
2185          * Pixel data should be prepared before visible display point starts.
2186          * So, atleast DS-2 lines must have already been fetched by DISPC
2187          * during nonactive - pos_x period.
2188          */
2189         val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2190         DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2191                 val, max(0, ds - 2) * width);
2192         if (val < max(0, ds - 2) * width)
2193                 return -EINVAL;
2194
2195         /*
2196          * All lines need to be refilled during the nonactive period of which
2197          * only one line can be loaded during the active period. So, atleast
2198          * DS - 1 lines should be loaded during nonactive period.
2199          */
2200         val =  div_u64((u64)nonactive * lclk, pclk);
2201         DSSDBG("nonactive * pcd  = %llu, max(0, DS - 1) * width = %d\n",
2202                 val, max(0, ds - 1) * width);
2203         if (val < max(0, ds - 1) * width)
2204                 return -EINVAL;
2205
2206         return 0;
2207 }
2208
2209 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2210                 const struct omap_video_timings *mgr_timings, u16 width,
2211                 u16 height, u16 out_width, u16 out_height,
2212                 enum omap_color_mode color_mode)
2213 {
2214         u32 core_clk = 0;
2215         u64 tmp;
2216
2217         if (height <= out_height && width <= out_width)
2218                 return (unsigned long) pclk;
2219
2220         if (height > out_height) {
2221                 unsigned int ppl = mgr_timings->x_res;
2222
2223                 tmp = (u64)pclk * height * out_width;
2224                 do_div(tmp, 2 * out_height * ppl);
2225                 core_clk = tmp;
2226
2227                 if (height > 2 * out_height) {
2228                         if (ppl == out_width)
2229                                 return 0;
2230
2231                         tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2232                         do_div(tmp, 2 * out_height * (ppl - out_width));
2233                         core_clk = max_t(u32, core_clk, tmp);
2234                 }
2235         }
2236
2237         if (width > out_width) {
2238                 tmp = (u64)pclk * width;
2239                 do_div(tmp, out_width);
2240                 core_clk = max_t(u32, core_clk, tmp);
2241
2242                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2243                         core_clk <<= 1;
2244         }
2245
2246         return core_clk;
2247 }
2248
2249 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2250                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2251 {
2252         if (height > out_height && width > out_width)
2253                 return pclk * 4;
2254         else
2255                 return pclk * 2;
2256 }
2257
2258 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2259                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2260 {
2261         unsigned int hf, vf;
2262
2263         /*
2264          * FIXME how to determine the 'A' factor
2265          * for the no downscaling case ?
2266          */
2267
2268         if (width > 3 * out_width)
2269                 hf = 4;
2270         else if (width > 2 * out_width)
2271                 hf = 3;
2272         else if (width > out_width)
2273                 hf = 2;
2274         else
2275                 hf = 1;
2276         if (height > out_height)
2277                 vf = 2;
2278         else
2279                 vf = 1;
2280
2281         return pclk * vf * hf;
2282 }
2283
2284 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2285                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2286 {
2287         /*
2288          * If the overlay/writeback is in mem to mem mode, there are no
2289          * downscaling limitations with respect to pixel clock, return 1 as
2290          * required core clock to represent that we have sufficient enough
2291          * core clock to do maximum downscaling
2292          */
2293         if (mem_to_mem)
2294                 return 1;
2295
2296         if (width > out_width)
2297                 return DIV_ROUND_UP(pclk, out_width) * width;
2298         else
2299                 return pclk;
2300 }
2301
2302 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2303                 const struct omap_video_timings *mgr_timings,
2304                 u16 width, u16 height, u16 out_width, u16 out_height,
2305                 enum omap_color_mode color_mode, bool *five_taps,
2306                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2307                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2308 {
2309         int error;
2310         u16 in_width, in_height;
2311         int min_factor = min(*decim_x, *decim_y);
2312         const int maxsinglelinewidth =
2313                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2314
2315         *five_taps = false;
2316
2317         do {
2318                 in_height = height / *decim_y;
2319                 in_width = width / *decim_x;
2320                 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2321                                 in_height, out_width, out_height, mem_to_mem);
2322                 error = (in_width > maxsinglelinewidth || !*core_clk ||
2323                         *core_clk > dispc_core_clk_rate());
2324                 if (error) {
2325                         if (*decim_x == *decim_y) {
2326                                 *decim_x = min_factor;
2327                                 ++*decim_y;
2328                         } else {
2329                                 swap(*decim_x, *decim_y);
2330                                 if (*decim_x < *decim_y)
2331                                         ++*decim_x;
2332                         }
2333                 }
2334         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2335
2336         if (error) {
2337                 DSSERR("failed to find scaling settings\n");
2338                 return -EINVAL;
2339         }
2340
2341         if (in_width > maxsinglelinewidth) {
2342                 DSSERR("Cannot scale max input width exceeded");
2343                 return -EINVAL;
2344         }
2345         return 0;
2346 }
2347
2348 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2349                 const struct omap_video_timings *mgr_timings,
2350                 u16 width, u16 height, u16 out_width, u16 out_height,
2351                 enum omap_color_mode color_mode, bool *five_taps,
2352                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2353                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2354 {
2355         int error;
2356         u16 in_width, in_height;
2357         const int maxsinglelinewidth =
2358                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2359
2360         do {
2361                 in_height = height / *decim_y;
2362                 in_width = width / *decim_x;
2363                 *five_taps = in_height > out_height;
2364
2365                 if (in_width > maxsinglelinewidth)
2366                         if (in_height > out_height &&
2367                                                 in_height < out_height * 2)
2368                                 *five_taps = false;
2369 again:
2370                 if (*five_taps)
2371                         *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2372                                                 in_width, in_height, out_width,
2373                                                 out_height, color_mode);
2374                 else
2375                         *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2376                                         in_height, out_width, out_height,
2377                                         mem_to_mem);
2378
2379                 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2380                                 pos_x, in_width, in_height, out_width,
2381                                 out_height, *five_taps);
2382                 if (error && *five_taps) {
2383                         *five_taps = false;
2384                         goto again;
2385                 }
2386
2387                 error = (error || in_width > maxsinglelinewidth * 2 ||
2388                         (in_width > maxsinglelinewidth && *five_taps) ||
2389                         !*core_clk || *core_clk > dispc_core_clk_rate());
2390
2391                 if (!error) {
2392                         /* verify that we're inside the limits of scaler */
2393                         if (in_width / 4 > out_width)
2394                                         error = 1;
2395
2396                         if (*five_taps) {
2397                                 if (in_height / 4 > out_height)
2398                                         error = 1;
2399                         } else {
2400                                 if (in_height / 2 > out_height)
2401                                         error = 1;
2402                         }
2403                 }
2404
2405                 if (error)
2406                         ++*decim_y;
2407         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2408
2409         if (error) {
2410                 DSSERR("failed to find scaling settings\n");
2411                 return -EINVAL;
2412         }
2413
2414         if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2415                                 in_height, out_width, out_height, *five_taps)) {
2416                         DSSERR("horizontal timing too tight\n");
2417                         return -EINVAL;
2418         }
2419
2420         if (in_width > (maxsinglelinewidth * 2)) {
2421                 DSSERR("Cannot setup scaling");
2422                 DSSERR("width exceeds maximum width possible");
2423                 return -EINVAL;
2424         }
2425
2426         if (in_width > maxsinglelinewidth && *five_taps) {
2427                 DSSERR("cannot setup scaling with five taps");
2428                 return -EINVAL;
2429         }
2430         return 0;
2431 }
2432
2433 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2434                 const struct omap_video_timings *mgr_timings,
2435                 u16 width, u16 height, u16 out_width, u16 out_height,
2436                 enum omap_color_mode color_mode, bool *five_taps,
2437                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2438                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2439 {
2440         u16 in_width, in_width_max;
2441         int decim_x_min = *decim_x;
2442         u16 in_height = height / *decim_y;
2443         const int maxsinglelinewidth =
2444                                 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2445         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2446
2447         if (mem_to_mem) {
2448                 in_width_max = out_width * maxdownscale;
2449         } else {
2450                 in_width_max = dispc_core_clk_rate() /
2451                                         DIV_ROUND_UP(pclk, out_width);
2452         }
2453
2454         *decim_x = DIV_ROUND_UP(width, in_width_max);
2455
2456         *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2457         if (*decim_x > *x_predecim)
2458                 return -EINVAL;
2459
2460         do {
2461                 in_width = width / *decim_x;
2462         } while (*decim_x <= *x_predecim &&
2463                         in_width > maxsinglelinewidth && ++*decim_x);
2464
2465         if (in_width > maxsinglelinewidth) {
2466                 DSSERR("Cannot scale width exceeds max line width");
2467                 return -EINVAL;
2468         }
2469
2470         *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2471                                 out_width, out_height, mem_to_mem);
2472         return 0;
2473 }
2474
2475 #define DIV_FRAC(dividend, divisor) \
2476         ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2477
2478 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2479                 enum omap_overlay_caps caps,
2480                 const struct omap_video_timings *mgr_timings,
2481                 u16 width, u16 height, u16 out_width, u16 out_height,
2482                 enum omap_color_mode color_mode, bool *five_taps,
2483                 int *x_predecim, int *y_predecim, u16 pos_x,
2484                 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2485 {
2486         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2487         const int max_decim_limit = 16;
2488         unsigned long core_clk = 0;
2489         int decim_x, decim_y, ret;
2490
2491         if (width == out_width && height == out_height)
2492                 return 0;
2493
2494         if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) {
2495                 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2496                 return -EINVAL;
2497         }
2498
2499         if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2500                 return -EINVAL;
2501
2502         if (mem_to_mem) {
2503                 *x_predecim = *y_predecim = 1;
2504         } else {
2505                 *x_predecim = max_decim_limit;
2506                 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2507                                 dss_has_feature(FEAT_BURST_2D)) ?
2508                                 2 : max_decim_limit;
2509         }
2510
2511         if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2512             color_mode == OMAP_DSS_COLOR_CLUT2 ||
2513             color_mode == OMAP_DSS_COLOR_CLUT4 ||
2514             color_mode == OMAP_DSS_COLOR_CLUT8) {
2515                 *x_predecim = 1;
2516                 *y_predecim = 1;
2517                 *five_taps = false;
2518                 return 0;
2519         }
2520
2521         decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2522         decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2523
2524         if (decim_x > *x_predecim || out_width > width * 8)
2525                 return -EINVAL;
2526
2527         if (decim_y > *y_predecim || out_height > height * 8)
2528                 return -EINVAL;
2529
2530         ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2531                 out_width, out_height, color_mode, five_taps,
2532                 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2533                 mem_to_mem);
2534         if (ret)
2535                 return ret;
2536
2537         DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2538                 width, height,
2539                 out_width, out_height,
2540                 out_width / width, DIV_FRAC(out_width, width),
2541                 out_height / height, DIV_FRAC(out_height, height),
2542
2543                 decim_x, decim_y,
2544                 width / decim_x, height / decim_y,
2545                 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2546                 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2547
2548                 *five_taps ? 5 : 3,
2549                 core_clk, dispc_core_clk_rate());
2550
2551         if (!core_clk || core_clk > dispc_core_clk_rate()) {
2552                 DSSERR("failed to set up scaling, "
2553                         "required core clk rate = %lu Hz, "
2554                         "current core clk rate = %lu Hz\n",
2555                         core_clk, dispc_core_clk_rate());
2556                 return -EINVAL;
2557         }
2558
2559         *x_predecim = decim_x;
2560         *y_predecim = decim_y;
2561         return 0;
2562 }
2563
2564 static int dispc_ovl_setup_common(enum omap_plane plane,
2565                 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2566                 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2567                 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2568                 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2569                 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2570                 bool replication, const struct omap_video_timings *mgr_timings,
2571                 bool mem_to_mem)
2572 {
2573         bool five_taps = true;
2574         bool fieldmode = false;
2575         int r, cconv = 0;
2576         unsigned offset0, offset1;
2577         s32 row_inc;
2578         s32 pix_inc;
2579         u16 frame_width, frame_height;
2580         unsigned int field_offset = 0;
2581         u16 in_height = height;
2582         u16 in_width = width;
2583         int x_predecim = 1, y_predecim = 1;
2584         bool ilace = mgr_timings->interlace;
2585         unsigned long pclk = dispc_plane_pclk_rate(plane);
2586         unsigned long lclk = dispc_plane_lclk_rate(plane);
2587
2588         if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2589                 return -EINVAL;
2590
2591         switch (color_mode) {
2592         case OMAP_DSS_COLOR_YUV2:
2593         case OMAP_DSS_COLOR_UYVY:
2594         case OMAP_DSS_COLOR_NV12:
2595                 if (in_width & 1) {
2596                         DSSERR("input width %d is not even for YUV format\n",
2597                                 in_width);
2598                         return -EINVAL;
2599                 }
2600                 break;
2601
2602         default:
2603                 break;
2604         }
2605
2606         out_width = out_width == 0 ? width : out_width;
2607         out_height = out_height == 0 ? height : out_height;
2608
2609         if (ilace && height == out_height)
2610                 fieldmode = true;
2611
2612         if (ilace) {
2613                 if (fieldmode)
2614                         in_height /= 2;
2615                 pos_y /= 2;
2616                 out_height /= 2;
2617
2618                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2619                         "out_height %d\n", in_height, pos_y,
2620                         out_height);
2621         }
2622
2623         if (!dss_feat_color_mode_supported(plane, color_mode))
2624                 return -EINVAL;
2625
2626         r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2627                         in_height, out_width, out_height, color_mode,
2628                         &five_taps, &x_predecim, &y_predecim, pos_x,
2629                         rotation_type, mem_to_mem);
2630         if (r)
2631                 return r;
2632
2633         in_width = in_width / x_predecim;
2634         in_height = in_height / y_predecim;
2635
2636         if (x_predecim > 1 || y_predecim > 1)
2637                 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2638                         x_predecim, y_predecim, in_width, in_height);
2639
2640         switch (color_mode) {
2641         case OMAP_DSS_COLOR_YUV2:
2642         case OMAP_DSS_COLOR_UYVY:
2643         case OMAP_DSS_COLOR_NV12:
2644                 if (in_width & 1) {
2645                         DSSDBG("predecimated input width is not even for YUV format\n");
2646                         DSSDBG("adjusting input width %d -> %d\n",
2647                                 in_width, in_width & ~1);
2648
2649                         in_width &= ~1;
2650                 }
2651                 break;
2652
2653         default:
2654                 break;
2655         }
2656
2657         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2658                         color_mode == OMAP_DSS_COLOR_UYVY ||
2659                         color_mode == OMAP_DSS_COLOR_NV12)
2660                 cconv = 1;
2661
2662         if (ilace && !fieldmode) {
2663                 /*
2664                  * when downscaling the bottom field may have to start several
2665                  * source lines below the top field. Unfortunately ACCUI
2666                  * registers will only hold the fractional part of the offset
2667                  * so the integer part must be added to the base address of the
2668                  * bottom field.
2669                  */
2670                 if (!in_height || in_height == out_height)
2671                         field_offset = 0;
2672                 else
2673                         field_offset = in_height / out_height / 2;
2674         }
2675
2676         /* Fields are independent but interleaved in memory. */
2677         if (fieldmode)
2678                 field_offset = 1;
2679
2680         offset0 = 0;
2681         offset1 = 0;
2682         row_inc = 0;
2683         pix_inc = 0;
2684
2685         if (plane == OMAP_DSS_WB) {
2686                 frame_width = out_width;
2687                 frame_height = out_height;
2688         } else {
2689                 frame_width = in_width;
2690                 frame_height = height;
2691         }
2692
2693         if (rotation_type == OMAP_DSS_ROT_TILER)
2694                 calc_tiler_rotation_offset(screen_width, frame_width,
2695                                 color_mode, fieldmode, field_offset,
2696                                 &offset0, &offset1, &row_inc, &pix_inc,
2697                                 x_predecim, y_predecim);
2698         else if (rotation_type == OMAP_DSS_ROT_DMA)
2699                 calc_dma_rotation_offset(rotation, mirror, screen_width,
2700                                 frame_width, frame_height,
2701                                 color_mode, fieldmode, field_offset,
2702                                 &offset0, &offset1, &row_inc, &pix_inc,
2703                                 x_predecim, y_predecim);
2704         else
2705                 calc_vrfb_rotation_offset(rotation, mirror,
2706                                 screen_width, frame_width, frame_height,
2707                                 color_mode, fieldmode, field_offset,
2708                                 &offset0, &offset1, &row_inc, &pix_inc,
2709                                 x_predecim, y_predecim);
2710
2711         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2712                         offset0, offset1, row_inc, pix_inc);
2713
2714         dispc_ovl_set_color_mode(plane, color_mode);
2715
2716         dispc_ovl_configure_burst_type(plane, rotation_type);
2717
2718         if (dispc.feat->reverse_ilace_field_order)
2719                 swap(offset0, offset1);
2720
2721         dispc_ovl_set_ba0(plane, paddr + offset0);
2722         dispc_ovl_set_ba1(plane, paddr + offset1);
2723
2724         if (OMAP_DSS_COLOR_NV12 == color_mode) {
2725                 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2726                 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2727         }
2728
2729         if (dispc.feat->last_pixel_inc_missing)
2730                 row_inc += pix_inc - 1;
2731
2732         dispc_ovl_set_row_inc(plane, row_inc);
2733         dispc_ovl_set_pix_inc(plane, pix_inc);
2734
2735         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2736                         in_height, out_width, out_height);
2737
2738         dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2739
2740         dispc_ovl_set_input_size(plane, in_width, in_height);
2741
2742         if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2743                 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2744                                    out_height, ilace, five_taps, fieldmode,
2745                                    color_mode, rotation);
2746                 dispc_ovl_set_output_size(plane, out_width, out_height);
2747                 dispc_ovl_set_vid_color_conv(plane, cconv);
2748         }
2749
2750         dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2751                         color_mode);
2752
2753         dispc_ovl_set_zorder(plane, caps, zorder);
2754         dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2755         dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2756
2757         dispc_ovl_enable_replication(plane, caps, replication);
2758
2759         return 0;
2760 }
2761
2762 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2763                 bool replication, const struct omap_video_timings *mgr_timings,
2764                 bool mem_to_mem)
2765 {
2766         int r;
2767         enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2768         enum omap_channel channel;
2769
2770         channel = dispc_ovl_get_channel_out(plane);
2771
2772         DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2773                 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2774                 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2775                 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2776                 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2777
2778         r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2779                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2780                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2781                 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2782                 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2783
2784         return r;
2785 }
2786 EXPORT_SYMBOL(dispc_ovl_setup);
2787
2788 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2789                 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2790 {
2791         int r;
2792         u32 l;
2793         enum omap_plane plane = OMAP_DSS_WB;
2794         const int pos_x = 0, pos_y = 0;
2795         const u8 zorder = 0, global_alpha = 0;
2796         const bool replication = false;
2797         bool truncation;
2798         int in_width = mgr_timings->x_res;
2799         int in_height = mgr_timings->y_res;
2800         enum omap_overlay_caps caps =
2801                 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2802
2803         DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2804                 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2805                 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2806                 wi->mirror);
2807
2808         r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2809                 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2810                 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2811                 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2812                 replication, mgr_timings, mem_to_mem);
2813
2814         switch (wi->color_mode) {
2815         case OMAP_DSS_COLOR_RGB16:
2816         case OMAP_DSS_COLOR_RGB24P:
2817         case OMAP_DSS_COLOR_ARGB16:
2818         case OMAP_DSS_COLOR_RGBA16:
2819         case OMAP_DSS_COLOR_RGB12U:
2820         case OMAP_DSS_COLOR_ARGB16_1555:
2821         case OMAP_DSS_COLOR_XRGB16_1555:
2822         case OMAP_DSS_COLOR_RGBX16:
2823                 truncation = true;
2824                 break;
2825         default:
2826                 truncation = false;
2827                 break;
2828         }
2829
2830         /* setup extra DISPC_WB_ATTRIBUTES */
2831         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2832         l = FLD_MOD(l, truncation, 10, 10);     /* TRUNCATIONENABLE */
2833         l = FLD_MOD(l, mem_to_mem, 19, 19);     /* WRITEBACKMODE */
2834         if (mem_to_mem)
2835                 l = FLD_MOD(l, 1, 26, 24);      /* CAPTUREMODE */
2836         else
2837                 l = FLD_MOD(l, 0, 26, 24);      /* CAPTUREMODE */
2838         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2839
2840         if (mem_to_mem) {
2841                 /* WBDELAYCOUNT */
2842                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2843         } else {
2844                 int wbdelay;
2845
2846                 wbdelay = min(mgr_timings->vfp + mgr_timings->vsw +
2847                         mgr_timings->vbp, 255);
2848
2849                 /* WBDELAYCOUNT */
2850                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2851         }
2852
2853         return r;
2854 }
2855
2856 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2857 {
2858         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2859
2860         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2861
2862         return 0;
2863 }
2864 EXPORT_SYMBOL(dispc_ovl_enable);
2865
2866 bool dispc_ovl_enabled(enum omap_plane plane)
2867 {
2868         return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2869 }
2870 EXPORT_SYMBOL(dispc_ovl_enabled);
2871
2872 enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel)
2873 {
2874         return dss_feat_get_supported_outputs(channel);
2875 }
2876 EXPORT_SYMBOL(dispc_mgr_get_supported_outputs);
2877
2878 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2879 {
2880         mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2881         /* flush posted write */
2882         mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2883 }
2884 EXPORT_SYMBOL(dispc_mgr_enable);
2885
2886 bool dispc_mgr_is_enabled(enum omap_channel channel)
2887 {
2888         return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2889 }
2890 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2891
2892 void dispc_wb_enable(bool enable)
2893 {
2894         dispc_ovl_enable(OMAP_DSS_WB, enable);
2895 }
2896
2897 bool dispc_wb_is_enabled(void)
2898 {
2899         return dispc_ovl_enabled(OMAP_DSS_WB);
2900 }
2901
2902 static void dispc_lcd_enable_signal_polarity(bool act_high)
2903 {
2904         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2905                 return;
2906
2907         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2908 }
2909
2910 void dispc_lcd_enable_signal(bool enable)
2911 {
2912         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2913                 return;
2914
2915         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2916 }
2917
2918 void dispc_pck_free_enable(bool enable)
2919 {
2920         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2921                 return;
2922
2923         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2924 }
2925
2926 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2927 {
2928         mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2929 }
2930
2931
2932 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2933 {
2934         mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2935 }
2936
2937 static void dispc_set_loadmode(enum omap_dss_load_mode mode)
2938 {
2939         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2940 }
2941
2942
2943 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2944 {
2945         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2946 }
2947
2948 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2949                 enum omap_dss_trans_key_type type,
2950                 u32 trans_key)
2951 {
2952         mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2953
2954         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2955 }
2956
2957 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2958 {
2959         mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2960 }
2961
2962 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2963                 bool enable)
2964 {
2965         if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2966                 return;
2967
2968         if (ch == OMAP_DSS_CHANNEL_LCD)
2969                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2970         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2971                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2972 }
2973
2974 void dispc_mgr_setup(enum omap_channel channel,
2975                 const struct omap_overlay_manager_info *info)
2976 {
2977         dispc_mgr_set_default_color(channel, info->default_color);
2978         dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2979         dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2980         dispc_mgr_enable_alpha_fixed_zorder(channel,
2981                         info->partial_alpha_enabled);
2982         if (dss_has_feature(FEAT_CPR)) {
2983                 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2984                 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2985         }
2986 }
2987 EXPORT_SYMBOL(dispc_mgr_setup);
2988
2989 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2990 {
2991         int code;
2992
2993         switch (data_lines) {
2994         case 12:
2995                 code = 0;
2996                 break;
2997         case 16:
2998                 code = 1;
2999                 break;
3000         case 18:
3001                 code = 2;
3002                 break;
3003         case 24:
3004                 code = 3;
3005                 break;
3006         default:
3007                 BUG();
3008                 return;
3009         }
3010
3011         mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
3012 }
3013
3014 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
3015 {
3016         u32 l;
3017         int gpout0, gpout1;
3018
3019         switch (mode) {
3020         case DSS_IO_PAD_MODE_RESET:
3021                 gpout0 = 0;
3022                 gpout1 = 0;
3023                 break;
3024         case DSS_IO_PAD_MODE_RFBI:
3025                 gpout0 = 1;
3026                 gpout1 = 0;
3027                 break;
3028         case DSS_IO_PAD_MODE_BYPASS:
3029                 gpout0 = 1;
3030                 gpout1 = 1;
3031                 break;
3032         default:
3033                 BUG();
3034                 return;
3035         }
3036
3037         l = dispc_read_reg(DISPC_CONTROL);
3038         l = FLD_MOD(l, gpout0, 15, 15);
3039         l = FLD_MOD(l, gpout1, 16, 16);
3040         dispc_write_reg(DISPC_CONTROL, l);
3041 }
3042
3043 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
3044 {
3045         mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
3046 }
3047
3048 void dispc_mgr_set_lcd_config(enum omap_channel channel,
3049                 const struct dss_lcd_mgr_config *config)
3050 {
3051         dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3052
3053         dispc_mgr_enable_stallmode(channel, config->stallmode);
3054         dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3055
3056         dispc_mgr_set_clock_div(channel, &config->clock_info);
3057
3058         dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3059
3060         dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3061
3062         dispc_mgr_set_lcd_type_tft(channel);
3063 }
3064 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
3065
3066 static bool _dispc_mgr_size_ok(u16 width, u16 height)
3067 {
3068         return width <= dispc.feat->mgr_width_max &&
3069                 height <= dispc.feat->mgr_height_max;
3070 }
3071
3072 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
3073                 int vsw, int vfp, int vbp)
3074 {
3075         if (hsw < 1 || hsw > dispc.feat->sw_max ||
3076                         hfp < 1 || hfp > dispc.feat->hp_max ||
3077                         hbp < 1 || hbp > dispc.feat->hp_max ||
3078                         vsw < 1 || vsw > dispc.feat->sw_max ||
3079                         vfp < 0 || vfp > dispc.feat->vp_max ||
3080                         vbp < 0 || vbp > dispc.feat->vp_max)
3081                 return false;
3082         return true;
3083 }
3084
3085 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3086                 unsigned long pclk)
3087 {
3088         if (dss_mgr_is_lcd(channel))
3089                 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
3090         else
3091                 return pclk <= dispc.feat->max_tv_pclk ? true : false;
3092 }
3093
3094 bool dispc_mgr_timings_ok(enum omap_channel channel,
3095                 const struct omap_video_timings *timings)
3096 {
3097         if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3098                 return false;
3099
3100         if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3101                 return false;
3102
3103         if (dss_mgr_is_lcd(channel)) {
3104                 /* TODO: OMAP4+ supports interlace for LCD outputs */
3105                 if (timings->interlace)
3106                         return false;
3107
3108                 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
3109                                 timings->hbp, timings->vsw, timings->vfp,
3110                                 timings->vbp))
3111                         return false;
3112         }
3113
3114         return true;
3115 }
3116
3117 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
3118                 int hfp, int hbp, int vsw, int vfp, int vbp,
3119                 enum omap_dss_signal_level vsync_level,
3120                 enum omap_dss_signal_level hsync_level,
3121                 enum omap_dss_signal_edge data_pclk_edge,
3122                 enum omap_dss_signal_level de_level,
3123                 enum omap_dss_signal_edge sync_pclk_edge)
3124
3125 {
3126         u32 timing_h, timing_v, l;
3127         bool onoff, rf, ipc, vs, hs, de;
3128
3129         timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3130                         FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3131                         FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3132         timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3133                         FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3134                         FLD_VAL(vbp, dispc.feat->bp_start, 20);
3135
3136         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3137         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3138
3139         switch (vsync_level) {
3140         case OMAPDSS_SIG_ACTIVE_LOW:
3141                 vs = true;
3142                 break;
3143         case OMAPDSS_SIG_ACTIVE_HIGH:
3144                 vs = false;
3145                 break;
3146         default:
3147                 BUG();
3148         }
3149
3150         switch (hsync_level) {
3151         case OMAPDSS_SIG_ACTIVE_LOW:
3152                 hs = true;
3153                 break;
3154         case OMAPDSS_SIG_ACTIVE_HIGH:
3155                 hs = false;
3156                 break;
3157         default:
3158                 BUG();
3159         }
3160
3161         switch (de_level) {
3162         case OMAPDSS_SIG_ACTIVE_LOW:
3163                 de = true;
3164                 break;
3165         case OMAPDSS_SIG_ACTIVE_HIGH:
3166                 de = false;
3167                 break;
3168         default:
3169                 BUG();
3170         }
3171
3172         switch (data_pclk_edge) {
3173         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3174                 ipc = false;
3175                 break;
3176         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3177                 ipc = true;
3178                 break;
3179         default:
3180                 BUG();
3181         }
3182
3183         /* always use the 'rf' setting */
3184         onoff = true;
3185
3186         switch (sync_pclk_edge) {
3187         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3188                 rf = false;
3189                 break;
3190         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3191                 rf = true;
3192                 break;
3193         default:
3194                 BUG();
3195         }
3196
3197         l = FLD_VAL(onoff, 17, 17) |
3198                 FLD_VAL(rf, 16, 16) |
3199                 FLD_VAL(de, 15, 15) |
3200                 FLD_VAL(ipc, 14, 14) |
3201                 FLD_VAL(hs, 13, 13) |
3202                 FLD_VAL(vs, 12, 12);
3203
3204         /* always set ALIGN bit when available */
3205         if (dispc.feat->supports_sync_align)
3206                 l |= (1 << 18);
3207
3208         dispc_write_reg(DISPC_POL_FREQ(channel), l);
3209
3210         if (dispc.syscon_pol) {
3211                 const int shifts[] = {
3212                         [OMAP_DSS_CHANNEL_LCD] = 0,
3213                         [OMAP_DSS_CHANNEL_LCD2] = 1,
3214                         [OMAP_DSS_CHANNEL_LCD3] = 2,
3215                 };
3216
3217                 u32 mask, val;
3218
3219                 mask = (1 << 0) | (1 << 3) | (1 << 6);
3220                 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3221
3222                 mask <<= 16 + shifts[channel];
3223                 val <<= 16 + shifts[channel];
3224
3225                 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3226                         mask, val);
3227         }
3228 }
3229
3230 /* change name to mode? */
3231 void dispc_mgr_set_timings(enum omap_channel channel,
3232                 const struct omap_video_timings *timings)
3233 {
3234         unsigned xtot, ytot;
3235         unsigned long ht, vt;
3236         struct omap_video_timings t = *timings;
3237
3238         DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
3239
3240         if (!dispc_mgr_timings_ok(channel, &t)) {
3241                 BUG();
3242                 return;
3243         }
3244
3245         if (dss_mgr_is_lcd(channel)) {
3246                 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3247                                 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3248                                 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3249
3250                 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3251                 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3252
3253                 ht = timings->pixelclock / xtot;
3254                 vt = timings->pixelclock / xtot / ytot;
3255
3256                 DSSDBG("pck %u\n", timings->pixelclock);
3257                 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3258                         t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3259                 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3260                         t.vsync_level, t.hsync_level, t.data_pclk_edge,
3261                         t.de_level, t.sync_pclk_edge);
3262
3263                 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3264         } else {
3265                 if (t.interlace)
3266                         t.y_res /= 2;
3267
3268                 if (dispc.feat->supports_double_pixel)
3269                         REG_FLD_MOD(DISPC_CONTROL, t.double_pixel ? 1 : 0,
3270                                 19, 17);
3271         }
3272
3273         dispc_mgr_set_size(channel, t.x_res, t.y_res);
3274 }
3275 EXPORT_SYMBOL(dispc_mgr_set_timings);
3276
3277 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3278                 u16 pck_div)
3279 {
3280         BUG_ON(lck_div < 1);
3281         BUG_ON(pck_div < 1);
3282
3283         dispc_write_reg(DISPC_DIVISORo(channel),
3284                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3285
3286         if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
3287                         channel == OMAP_DSS_CHANNEL_LCD)
3288                 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3289 }
3290
3291 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3292                 int *pck_div)
3293 {
3294         u32 l;
3295         l = dispc_read_reg(DISPC_DIVISORo(channel));
3296         *lck_div = FLD_GET(l, 23, 16);
3297         *pck_div = FLD_GET(l, 7, 0);
3298 }
3299
3300 static unsigned long dispc_fclk_rate(void)
3301 {
3302         struct dss_pll *pll;
3303         unsigned long r = 0;
3304
3305         switch (dss_get_dispc_clk_source()) {
3306         case OMAP_DSS_CLK_SRC_FCK:
3307                 r = dss_get_dispc_clk_rate();
3308                 break;
3309         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3310                 pll = dss_pll_find("dsi0");
3311                 if (!pll)
3312                         pll = dss_pll_find("video0");
3313
3314                 r = pll->cinfo.clkout[0];
3315                 break;
3316         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3317                 pll = dss_pll_find("dsi1");
3318                 if (!pll)
3319                         pll = dss_pll_find("video1");
3320
3321                 r = pll->cinfo.clkout[0];
3322                 break;
3323         default:
3324                 BUG();
3325                 return 0;
3326         }
3327
3328         return r;
3329 }
3330
3331 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3332 {
3333         struct dss_pll *pll;
3334         int lcd;
3335         unsigned long r;
3336         u32 l;
3337
3338         if (dss_mgr_is_lcd(channel)) {
3339                 l = dispc_read_reg(DISPC_DIVISORo(channel));
3340
3341                 lcd = FLD_GET(l, 23, 16);
3342
3343                 switch (dss_get_lcd_clk_source(channel)) {
3344                 case OMAP_DSS_CLK_SRC_FCK:
3345                         r = dss_get_dispc_clk_rate();
3346                         break;
3347                 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3348                         pll = dss_pll_find("dsi0");
3349                         if (!pll)
3350                                 pll = dss_pll_find("video0");
3351
3352                         r = pll->cinfo.clkout[0];
3353                         break;
3354                 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3355                         pll = dss_pll_find("dsi1");
3356                         if (!pll)
3357                                 pll = dss_pll_find("video1");
3358
3359                         r = pll->cinfo.clkout[0];
3360                         break;
3361                 default:
3362                         BUG();
3363                         return 0;
3364                 }
3365
3366                 return r / lcd;
3367         } else {
3368                 return dispc_fclk_rate();
3369         }
3370 }
3371
3372 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3373 {
3374         unsigned long r;
3375
3376         if (dss_mgr_is_lcd(channel)) {
3377                 int pcd;
3378                 u32 l;
3379
3380                 l = dispc_read_reg(DISPC_DIVISORo(channel));
3381
3382                 pcd = FLD_GET(l, 7, 0);
3383
3384                 r = dispc_mgr_lclk_rate(channel);
3385
3386                 return r / pcd;
3387         } else {
3388                 return dispc.tv_pclk_rate;
3389         }
3390 }
3391
3392 void dispc_set_tv_pclk(unsigned long pclk)
3393 {
3394         dispc.tv_pclk_rate = pclk;
3395 }
3396
3397 static unsigned long dispc_core_clk_rate(void)
3398 {
3399         return dispc.core_clk_rate;
3400 }
3401
3402 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3403 {
3404         enum omap_channel channel;
3405
3406         if (plane == OMAP_DSS_WB)
3407                 return 0;
3408
3409         channel = dispc_ovl_get_channel_out(plane);
3410
3411         return dispc_mgr_pclk_rate(channel);
3412 }
3413
3414 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3415 {
3416         enum omap_channel channel;
3417
3418         if (plane == OMAP_DSS_WB)
3419                 return 0;
3420
3421         channel = dispc_ovl_get_channel_out(plane);
3422
3423         return dispc_mgr_lclk_rate(channel);
3424 }
3425
3426 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3427 {
3428         int lcd, pcd;
3429         enum omap_dss_clk_source lcd_clk_src;
3430
3431         seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3432
3433         lcd_clk_src = dss_get_lcd_clk_source(channel);
3434
3435         seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3436                 dss_get_generic_clk_source_name(lcd_clk_src),
3437                 dss_feat_get_clk_source_name(lcd_clk_src));
3438
3439         dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3440
3441         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3442                 dispc_mgr_lclk_rate(channel), lcd);
3443         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3444                 dispc_mgr_pclk_rate(channel), pcd);
3445 }
3446
3447 void dispc_dump_clocks(struct seq_file *s)
3448 {
3449         int lcd;
3450         u32 l;
3451         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3452
3453         if (dispc_runtime_get())
3454                 return;
3455
3456         seq_printf(s, "- DISPC -\n");
3457
3458         seq_printf(s, "dispc fclk source = %s (%s)\n",
3459                         dss_get_generic_clk_source_name(dispc_clk_src),
3460                         dss_feat_get_clk_source_name(dispc_clk_src));
3461
3462         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3463
3464         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3465                 seq_printf(s, "- DISPC-CORE-CLK -\n");
3466                 l = dispc_read_reg(DISPC_DIVISOR);
3467                 lcd = FLD_GET(l, 23, 16);
3468
3469                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3470                                 (dispc_fclk_rate()/lcd), lcd);
3471         }
3472
3473         dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3474
3475         if (dss_has_feature(FEAT_MGR_LCD2))
3476                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3477         if (dss_has_feature(FEAT_MGR_LCD3))
3478                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3479
3480         dispc_runtime_put();
3481 }
3482
3483 static void dispc_dump_regs(struct seq_file *s)
3484 {
3485         int i, j;
3486         const char *mgr_names[] = {
3487                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
3488                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
3489                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
3490                 [OMAP_DSS_CHANNEL_LCD3]         = "LCD3",
3491         };
3492         const char *ovl_names[] = {
3493                 [OMAP_DSS_GFX]          = "GFX",
3494                 [OMAP_DSS_VIDEO1]       = "VID1",
3495                 [OMAP_DSS_VIDEO2]       = "VID2",
3496                 [OMAP_DSS_VIDEO3]       = "VID3",
3497                 [OMAP_DSS_WB]           = "WB",
3498         };
3499         const char **p_names;
3500
3501 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3502
3503         if (dispc_runtime_get())
3504                 return;
3505
3506         /* DISPC common registers */
3507         DUMPREG(DISPC_REVISION);
3508         DUMPREG(DISPC_SYSCONFIG);
3509         DUMPREG(DISPC_SYSSTATUS);
3510         DUMPREG(DISPC_IRQSTATUS);
3511         DUMPREG(DISPC_IRQENABLE);
3512         DUMPREG(DISPC_CONTROL);
3513         DUMPREG(DISPC_CONFIG);
3514         DUMPREG(DISPC_CAPABLE);
3515         DUMPREG(DISPC_LINE_STATUS);
3516         DUMPREG(DISPC_LINE_NUMBER);
3517         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3518                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3519                 DUMPREG(DISPC_GLOBAL_ALPHA);
3520         if (dss_has_feature(FEAT_MGR_LCD2)) {
3521                 DUMPREG(DISPC_CONTROL2);
3522                 DUMPREG(DISPC_CONFIG2);
3523         }
3524         if (dss_has_feature(FEAT_MGR_LCD3)) {
3525                 DUMPREG(DISPC_CONTROL3);
3526                 DUMPREG(DISPC_CONFIG3);
3527         }
3528         if (dss_has_feature(FEAT_MFLAG))
3529                 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3530
3531 #undef DUMPREG
3532
3533 #define DISPC_REG(i, name) name(i)
3534 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3535         (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3536         dispc_read_reg(DISPC_REG(i, r)))
3537
3538         p_names = mgr_names;
3539
3540         /* DISPC channel specific registers */
3541         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3542                 DUMPREG(i, DISPC_DEFAULT_COLOR);
3543                 DUMPREG(i, DISPC_TRANS_COLOR);
3544                 DUMPREG(i, DISPC_SIZE_MGR);
3545
3546                 if (i == OMAP_DSS_CHANNEL_DIGIT)
3547                         continue;
3548
3549                 DUMPREG(i, DISPC_TIMING_H);
3550                 DUMPREG(i, DISPC_TIMING_V);
3551                 DUMPREG(i, DISPC_POL_FREQ);
3552                 DUMPREG(i, DISPC_DIVISORo);
3553
3554                 DUMPREG(i, DISPC_DATA_CYCLE1);
3555                 DUMPREG(i, DISPC_DATA_CYCLE2);
3556                 DUMPREG(i, DISPC_DATA_CYCLE3);
3557
3558                 if (dss_has_feature(FEAT_CPR)) {
3559                         DUMPREG(i, DISPC_CPR_COEF_R);
3560                         DUMPREG(i, DISPC_CPR_COEF_G);
3561                         DUMPREG(i, DISPC_CPR_COEF_B);
3562                 }
3563         }
3564
3565         p_names = ovl_names;
3566
3567         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3568                 DUMPREG(i, DISPC_OVL_BA0);
3569                 DUMPREG(i, DISPC_OVL_BA1);
3570                 DUMPREG(i, DISPC_OVL_POSITION);
3571                 DUMPREG(i, DISPC_OVL_SIZE);
3572                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3573                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3574                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3575                 DUMPREG(i, DISPC_OVL_ROW_INC);
3576                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3577
3578                 if (dss_has_feature(FEAT_PRELOAD))
3579                         DUMPREG(i, DISPC_OVL_PRELOAD);
3580                 if (dss_has_feature(FEAT_MFLAG))
3581                         DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3582
3583                 if (i == OMAP_DSS_GFX) {
3584                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3585                         DUMPREG(i, DISPC_OVL_TABLE_BA);
3586                         continue;
3587                 }
3588
3589                 DUMPREG(i, DISPC_OVL_FIR);
3590                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3591                 DUMPREG(i, DISPC_OVL_ACCU0);
3592                 DUMPREG(i, DISPC_OVL_ACCU1);
3593                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3594                         DUMPREG(i, DISPC_OVL_BA0_UV);
3595                         DUMPREG(i, DISPC_OVL_BA1_UV);
3596                         DUMPREG(i, DISPC_OVL_FIR2);
3597                         DUMPREG(i, DISPC_OVL_ACCU2_0);
3598                         DUMPREG(i, DISPC_OVL_ACCU2_1);
3599                 }
3600                 if (dss_has_feature(FEAT_ATTR2))
3601                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3602         }
3603
3604         if (dispc.feat->has_writeback) {
3605                 i = OMAP_DSS_WB;
3606                 DUMPREG(i, DISPC_OVL_BA0);
3607                 DUMPREG(i, DISPC_OVL_BA1);
3608                 DUMPREG(i, DISPC_OVL_SIZE);
3609                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3610                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3611                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3612                 DUMPREG(i, DISPC_OVL_ROW_INC);
3613                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3614
3615                 if (dss_has_feature(FEAT_MFLAG))
3616                         DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3617
3618                 DUMPREG(i, DISPC_OVL_FIR);
3619                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3620                 DUMPREG(i, DISPC_OVL_ACCU0);
3621                 DUMPREG(i, DISPC_OVL_ACCU1);
3622                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3623                         DUMPREG(i, DISPC_OVL_BA0_UV);
3624                         DUMPREG(i, DISPC_OVL_BA1_UV);
3625                         DUMPREG(i, DISPC_OVL_FIR2);
3626                         DUMPREG(i, DISPC_OVL_ACCU2_0);
3627                         DUMPREG(i, DISPC_OVL_ACCU2_1);
3628                 }
3629                 if (dss_has_feature(FEAT_ATTR2))
3630                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3631         }
3632
3633 #undef DISPC_REG
3634 #undef DUMPREG
3635
3636 #define DISPC_REG(plane, name, i) name(plane, i)
3637 #define DUMPREG(plane, name, i) \
3638         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3639         (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3640         dispc_read_reg(DISPC_REG(plane, name, i)))
3641
3642         /* Video pipeline coefficient registers */
3643
3644         /* start from OMAP_DSS_VIDEO1 */
3645         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3646                 for (j = 0; j < 8; j++)
3647                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3648
3649                 for (j = 0; j < 8; j++)
3650                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3651
3652                 for (j = 0; j < 5; j++)
3653                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3654
3655                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3656                         for (j = 0; j < 8; j++)
3657                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3658                 }
3659
3660                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3661                         for (j = 0; j < 8; j++)
3662                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3663
3664                         for (j = 0; j < 8; j++)
3665                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3666
3667                         for (j = 0; j < 8; j++)
3668                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3669                 }
3670         }
3671
3672         dispc_runtime_put();
3673
3674 #undef DISPC_REG
3675 #undef DUMPREG
3676 }
3677
3678 /* calculate clock rates using dividers in cinfo */
3679 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3680                 struct dispc_clock_info *cinfo)
3681 {
3682         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3683                 return -EINVAL;
3684         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3685                 return -EINVAL;
3686
3687         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3688         cinfo->pck = cinfo->lck / cinfo->pck_div;
3689
3690         return 0;
3691 }
3692
3693 bool dispc_div_calc(unsigned long dispc,
3694                 unsigned long pck_min, unsigned long pck_max,
3695                 dispc_div_calc_func func, void *data)
3696 {
3697         int lckd, lckd_start, lckd_stop;
3698         int pckd, pckd_start, pckd_stop;
3699         unsigned long pck, lck;
3700         unsigned long lck_max;
3701         unsigned long pckd_hw_min, pckd_hw_max;
3702         unsigned min_fck_per_pck;
3703         unsigned long fck;
3704
3705 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3706         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3707 #else
3708         min_fck_per_pck = 0;
3709 #endif
3710
3711         pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3712         pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3713
3714         lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3715
3716         pck_min = pck_min ? pck_min : 1;
3717         pck_max = pck_max ? pck_max : ULONG_MAX;
3718
3719         lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3720         lckd_stop = min(dispc / pck_min, 255ul);
3721
3722         for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3723                 lck = dispc / lckd;
3724
3725                 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3726                 pckd_stop = min(lck / pck_min, pckd_hw_max);
3727
3728                 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3729                         pck = lck / pckd;
3730
3731                         /*
3732                          * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3733                          * clock, which means we're configuring DISPC fclk here
3734                          * also. Thus we need to use the calculated lck. For
3735                          * OMAP4+ the DISPC fclk is a separate clock.
3736                          */
3737                         if (dss_has_feature(FEAT_CORE_CLK_DIV))
3738                                 fck = dispc_core_clk_rate();
3739                         else
3740                                 fck = lck;
3741
3742                         if (fck < pck * min_fck_per_pck)
3743                                 continue;
3744
3745                         if (func(lckd, pckd, lck, pck, data))
3746                                 return true;
3747                 }
3748         }
3749
3750         return false;
3751 }
3752
3753 void dispc_mgr_set_clock_div(enum omap_channel channel,
3754                 const struct dispc_clock_info *cinfo)
3755 {
3756         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3757         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3758
3759         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3760 }
3761
3762 int dispc_mgr_get_clock_div(enum omap_channel channel,
3763                 struct dispc_clock_info *cinfo)
3764 {
3765         unsigned long fck;
3766
3767         fck = dispc_fclk_rate();
3768
3769         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3770         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3771
3772         cinfo->lck = fck / cinfo->lck_div;
3773         cinfo->pck = cinfo->lck / cinfo->pck_div;
3774
3775         return 0;
3776 }
3777
3778 u32 dispc_read_irqstatus(void)
3779 {
3780         return dispc_read_reg(DISPC_IRQSTATUS);
3781 }
3782 EXPORT_SYMBOL(dispc_read_irqstatus);
3783
3784 void dispc_clear_irqstatus(u32 mask)
3785 {
3786         dispc_write_reg(DISPC_IRQSTATUS, mask);
3787 }
3788 EXPORT_SYMBOL(dispc_clear_irqstatus);
3789
3790 u32 dispc_read_irqenable(void)
3791 {
3792         return dispc_read_reg(DISPC_IRQENABLE);
3793 }
3794 EXPORT_SYMBOL(dispc_read_irqenable);
3795
3796 void dispc_write_irqenable(u32 mask)
3797 {
3798         u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3799
3800         /* clear the irqstatus for newly enabled irqs */
3801         dispc_clear_irqstatus((mask ^ old_mask) & mask);
3802
3803         dispc_write_reg(DISPC_IRQENABLE, mask);
3804 }
3805 EXPORT_SYMBOL(dispc_write_irqenable);
3806
3807 void dispc_enable_sidle(void)
3808 {
3809         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3810 }
3811
3812 void dispc_disable_sidle(void)
3813 {
3814         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3815 }
3816
3817 static void _omap_dispc_initial_config(void)
3818 {
3819         u32 l;
3820
3821         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3822         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3823                 l = dispc_read_reg(DISPC_DIVISOR);
3824                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3825                 l = FLD_MOD(l, 1, 0, 0);
3826                 l = FLD_MOD(l, 1, 23, 16);
3827                 dispc_write_reg(DISPC_DIVISOR, l);
3828
3829                 dispc.core_clk_rate = dispc_fclk_rate();
3830         }
3831
3832         /* FUNCGATED */
3833         if (dss_has_feature(FEAT_FUNCGATED))
3834                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3835
3836         dispc_setup_color_conv_coef();
3837
3838         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3839
3840         dispc_init_fifos();
3841
3842         dispc_configure_burst_sizes();
3843
3844         dispc_ovl_enable_zorder_planes();
3845
3846         if (dispc.feat->mstandby_workaround)
3847                 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3848
3849         if (dss_has_feature(FEAT_MFLAG))
3850                 dispc_init_mflag();
3851 }
3852
3853 static const struct dispc_features omap24xx_dispc_feats = {
3854         .sw_start               =       5,
3855         .fp_start               =       15,
3856         .bp_start               =       27,
3857         .sw_max                 =       64,
3858         .vp_max                 =       255,
3859         .hp_max                 =       256,
3860         .mgr_width_start        =       10,
3861         .mgr_height_start       =       26,
3862         .mgr_width_max          =       2048,
3863         .mgr_height_max         =       2048,
3864         .max_lcd_pclk           =       66500000,
3865         .calc_scaling           =       dispc_ovl_calc_scaling_24xx,
3866         .calc_core_clk          =       calc_core_clk_24xx,
3867         .num_fifos              =       3,
3868         .no_framedone_tv        =       true,
3869         .set_max_preload        =       false,
3870         .last_pixel_inc_missing =       true,
3871 };
3872
3873 static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
3874         .sw_start               =       5,
3875         .fp_start               =       15,
3876         .bp_start               =       27,
3877         .sw_max                 =       64,
3878         .vp_max                 =       255,
3879         .hp_max                 =       256,
3880         .mgr_width_start        =       10,
3881         .mgr_height_start       =       26,
3882         .mgr_width_max          =       2048,
3883         .mgr_height_max         =       2048,
3884         .max_lcd_pclk           =       173000000,
3885         .max_tv_pclk            =       59000000,
3886         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3887         .calc_core_clk          =       calc_core_clk_34xx,
3888         .num_fifos              =       3,
3889         .no_framedone_tv        =       true,
3890         .set_max_preload        =       false,
3891         .last_pixel_inc_missing =       true,
3892 };
3893
3894 static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
3895         .sw_start               =       7,
3896         .fp_start               =       19,
3897         .bp_start               =       31,
3898         .sw_max                 =       256,
3899         .vp_max                 =       4095,
3900         .hp_max                 =       4096,
3901         .mgr_width_start        =       10,
3902         .mgr_height_start       =       26,
3903         .mgr_width_max          =       2048,
3904         .mgr_height_max         =       2048,
3905         .max_lcd_pclk           =       173000000,
3906         .max_tv_pclk            =       59000000,
3907         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3908         .calc_core_clk          =       calc_core_clk_34xx,
3909         .num_fifos              =       3,
3910         .no_framedone_tv        =       true,
3911         .set_max_preload        =       false,
3912         .last_pixel_inc_missing =       true,
3913 };
3914
3915 static const struct dispc_features omap44xx_dispc_feats = {
3916         .sw_start               =       7,
3917         .fp_start               =       19,
3918         .bp_start               =       31,
3919         .sw_max                 =       256,
3920         .vp_max                 =       4095,
3921         .hp_max                 =       4096,
3922         .mgr_width_start        =       10,
3923         .mgr_height_start       =       26,
3924         .mgr_width_max          =       2048,
3925         .mgr_height_max         =       2048,
3926         .max_lcd_pclk           =       170000000,
3927         .max_tv_pclk            =       185625000,
3928         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3929         .calc_core_clk          =       calc_core_clk_44xx,
3930         .num_fifos              =       5,
3931         .gfx_fifo_workaround    =       true,
3932         .set_max_preload        =       true,
3933         .supports_sync_align    =       true,
3934         .has_writeback          =       true,
3935         .supports_double_pixel  =       true,
3936         .reverse_ilace_field_order =    true,
3937 };
3938
3939 static const struct dispc_features omap54xx_dispc_feats = {
3940         .sw_start               =       7,
3941         .fp_start               =       19,
3942         .bp_start               =       31,
3943         .sw_max                 =       256,
3944         .vp_max                 =       4095,
3945         .hp_max                 =       4096,
3946         .mgr_width_start        =       11,
3947         .mgr_height_start       =       27,
3948         .mgr_width_max          =       4096,
3949         .mgr_height_max         =       4096,
3950         .max_lcd_pclk           =       170000000,
3951         .max_tv_pclk            =       186000000,
3952         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3953         .calc_core_clk          =       calc_core_clk_44xx,
3954         .num_fifos              =       5,
3955         .gfx_fifo_workaround    =       true,
3956         .mstandby_workaround    =       true,
3957         .set_max_preload        =       true,
3958         .supports_sync_align    =       true,
3959         .has_writeback          =       true,
3960         .supports_double_pixel  =       true,
3961         .reverse_ilace_field_order =    true,
3962 };
3963
3964 static int dispc_init_features(struct platform_device *pdev)
3965 {
3966         const struct dispc_features *src;
3967         struct dispc_features *dst;
3968
3969         dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
3970         if (!dst) {
3971                 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
3972                 return -ENOMEM;
3973         }
3974
3975         switch (omapdss_get_version()) {
3976         case OMAPDSS_VER_OMAP24xx:
3977                 src = &omap24xx_dispc_feats;
3978                 break;
3979
3980         case OMAPDSS_VER_OMAP34xx_ES1:
3981                 src = &omap34xx_rev1_0_dispc_feats;
3982                 break;
3983
3984         case OMAPDSS_VER_OMAP34xx_ES3:
3985         case OMAPDSS_VER_OMAP3630:
3986         case OMAPDSS_VER_AM35xx:
3987         case OMAPDSS_VER_AM43xx:
3988                 src = &omap34xx_rev3_0_dispc_feats;
3989                 break;
3990
3991         case OMAPDSS_VER_OMAP4430_ES1:
3992         case OMAPDSS_VER_OMAP4430_ES2:
3993         case OMAPDSS_VER_OMAP4:
3994                 src = &omap44xx_dispc_feats;
3995                 break;
3996
3997         case OMAPDSS_VER_OMAP5:
3998         case OMAPDSS_VER_DRA7xx:
3999                 src = &omap54xx_dispc_feats;
4000                 break;
4001
4002         default:
4003                 return -ENODEV;
4004         }
4005
4006         memcpy(dst, src, sizeof(*dst));
4007         dispc.feat = dst;
4008
4009         return 0;
4010 }
4011
4012 static irqreturn_t dispc_irq_handler(int irq, void *arg)
4013 {
4014         if (!dispc.is_enabled)
4015                 return IRQ_NONE;
4016
4017         return dispc.user_handler(irq, dispc.user_data);
4018 }
4019
4020 int dispc_request_irq(irq_handler_t handler, void *dev_id)
4021 {
4022         int r;
4023
4024         if (dispc.user_handler != NULL)
4025                 return -EBUSY;
4026
4027         dispc.user_handler = handler;
4028         dispc.user_data = dev_id;
4029
4030         /* ensure the dispc_irq_handler sees the values above */
4031         smp_wmb();
4032
4033         r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
4034                              IRQF_SHARED, "OMAP DISPC", &dispc);
4035         if (r) {
4036                 dispc.user_handler = NULL;
4037                 dispc.user_data = NULL;
4038         }
4039
4040         return r;
4041 }
4042 EXPORT_SYMBOL(dispc_request_irq);
4043
4044 void dispc_free_irq(void *dev_id)
4045 {
4046         devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
4047
4048         dispc.user_handler = NULL;
4049         dispc.user_data = NULL;
4050 }
4051 EXPORT_SYMBOL(dispc_free_irq);
4052
4053 /* DISPC HW IP initialisation */
4054 static int dispc_bind(struct device *dev, struct device *master, void *data)
4055 {
4056         struct platform_device *pdev = to_platform_device(dev);
4057         u32 rev;
4058         int r = 0;
4059         struct resource *dispc_mem;
4060         struct device_node *np = pdev->dev.of_node;
4061
4062         dispc.pdev = pdev;
4063
4064         spin_lock_init(&dispc.control_lock);
4065
4066         r = dispc_init_features(dispc.pdev);
4067         if (r)
4068                 return r;
4069
4070         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4071         if (!dispc_mem) {
4072                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
4073                 return -EINVAL;
4074         }
4075
4076         dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4077                                   resource_size(dispc_mem));
4078         if (!dispc.base) {
4079                 DSSERR("can't ioremap DISPC\n");
4080                 return -ENOMEM;
4081         }
4082
4083         dispc.irq = platform_get_irq(dispc.pdev, 0);
4084         if (dispc.irq < 0) {
4085                 DSSERR("platform_get_irq failed\n");
4086                 return -ENODEV;
4087         }
4088
4089         if (np && of_property_read_bool(np, "syscon-pol")) {
4090                 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4091                 if (IS_ERR(dispc.syscon_pol)) {
4092                         dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4093                         return PTR_ERR(dispc.syscon_pol);
4094                 }
4095
4096                 if (of_property_read_u32_index(np, "syscon-pol", 1,
4097                                 &dispc.syscon_pol_offset)) {
4098                         dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4099                         return -EINVAL;
4100                 }
4101         }
4102
4103         pm_runtime_enable(&pdev->dev);
4104
4105         r = dispc_runtime_get();
4106         if (r)
4107                 goto err_runtime_get;
4108
4109         _omap_dispc_initial_config();
4110
4111         rev = dispc_read_reg(DISPC_REVISION);
4112         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4113                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4114
4115         dispc_runtime_put();
4116
4117         dss_debugfs_create_file("dispc", dispc_dump_regs);
4118
4119         return 0;
4120
4121 err_runtime_get:
4122         pm_runtime_disable(&pdev->dev);
4123         return r;
4124 }
4125
4126 static void dispc_unbind(struct device *dev, struct device *master,
4127                                void *data)
4128 {
4129         pm_runtime_disable(dev);
4130 }
4131
4132 static const struct component_ops dispc_component_ops = {
4133         .bind   = dispc_bind,
4134         .unbind = dispc_unbind,
4135 };
4136
4137 static int dispc_probe(struct platform_device *pdev)
4138 {
4139         return component_add(&pdev->dev, &dispc_component_ops);
4140 }
4141
4142 static int dispc_remove(struct platform_device *pdev)
4143 {
4144         component_del(&pdev->dev, &dispc_component_ops);
4145         return 0;
4146 }
4147
4148 static int dispc_runtime_suspend(struct device *dev)
4149 {
4150         dispc.is_enabled = false;
4151         /* ensure the dispc_irq_handler sees the is_enabled value */
4152         smp_wmb();
4153         /* wait for current handler to finish before turning the DISPC off */
4154         synchronize_irq(dispc.irq);
4155
4156         dispc_save_context();
4157
4158         return 0;
4159 }
4160
4161 static int dispc_runtime_resume(struct device *dev)
4162 {
4163         /*
4164          * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4165          * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4166          * _omap_dispc_initial_config(). We can thus use it to detect if
4167          * we have lost register context.
4168          */
4169         if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4170                 _omap_dispc_initial_config();
4171
4172                 dispc_restore_context();
4173         }
4174
4175         dispc.is_enabled = true;
4176         /* ensure the dispc_irq_handler sees the is_enabled value */
4177         smp_wmb();
4178
4179         return 0;
4180 }
4181
4182 static const struct dev_pm_ops dispc_pm_ops = {
4183         .runtime_suspend = dispc_runtime_suspend,
4184         .runtime_resume = dispc_runtime_resume,
4185 };
4186
4187 static const struct of_device_id dispc_of_match[] = {
4188         { .compatible = "ti,omap2-dispc", },
4189         { .compatible = "ti,omap3-dispc", },
4190         { .compatible = "ti,omap4-dispc", },
4191         { .compatible = "ti,omap5-dispc", },
4192         { .compatible = "ti,dra7-dispc", },
4193         {},
4194 };
4195
4196 static struct platform_driver omap_dispchw_driver = {
4197         .probe          = dispc_probe,
4198         .remove         = dispc_remove,
4199         .driver         = {
4200                 .name   = "omapdss_dispc",
4201                 .pm     = &dispc_pm_ops,
4202                 .of_match_table = dispc_of_match,
4203                 .suppress_bind_attrs = true,
4204         },
4205 };
4206
4207 int __init dispc_init_platform_driver(void)
4208 {
4209         return platform_driver_register(&omap_dispchw_driver);
4210 }
4211
4212 void dispc_uninit_platform_driver(void)
4213 {
4214         platform_driver_unregister(&omap_dispchw_driver);
4215 }