drivers/gpu/drm/omapdrm/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/export.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/jiffies.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/delay.h>
  34 #include <linux/workqueue.h>
  35 #include <linux/hardirq.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/pm_runtime.h>
  38 #include <linux/sizes.h>
  39 #include <linux/mfd/syscon.h>
  40 #include <linux/regmap.h>
  41 #include <linux/of.h>
  42 #include <linux/component.h>
  43
  44 #include "omapdss.h"
  45 #include "dss.h"
  46 #include "dss_features.h"
  47 #include "dispc.h"
  48
  49 /* DISPC */
  50 #define DISPC_SZ_REGS                   SZ_4K
  51
  52 enum omap_burst_size {
  53         BURST_SIZE_X2 = 0,
  54         BURST_SIZE_X4 = 1,
  55         BURST_SIZE_X8 = 2,
  56 };
  57
  58 #define REG_GET(idx, start, end) \
  59         FLD_GET(dispc_read_reg(idx), start, end)
  60
  61 #define REG_FLD_MOD(idx, val, start, end)                               \
  62         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  63
  64 struct dispc_features {
  65         u8 sw_start;
  66         u8 fp_start;
  67         u8 bp_start;
  68         u16 sw_max;
  69         u16 vp_max;
  70         u16 hp_max;
  71         u8 mgr_width_start;
  72         u8 mgr_height_start;
  73         u16 mgr_width_max;
  74         u16 mgr_height_max;
  75         unsigned long max_lcd_pclk;
  76         unsigned long max_tv_pclk;
  77         int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
  78                 const struct omap_video_timings *mgr_timings,
  79                 u16 width, u16 height, u16 out_width, u16 out_height,
  80                 enum omap_color_mode color_mode, bool *five_taps,
  81                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
  82                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
  83         unsigned long (*calc_core_clk) (unsigned long pclk,
  84                 u16 width, u16 height, u16 out_width, u16 out_height,
  85                 bool mem_to_mem);
  86         u8 num_fifos;
  87
  88         /* swap GFX & WB fifos */
  89         bool gfx_fifo_workaround:1;
  90
  91         /* no DISPC_IRQ_FRAMEDONETV on this SoC */
  92         bool no_framedone_tv:1;
  93
  94         /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
  95         bool mstandby_workaround:1;
  96
  97         bool set_max_preload:1;
  98
  99         /* PIXEL_INC is not added to the last pixel of a line */
 100         bool last_pixel_inc_missing:1;
 101
 102         /* POL_FREQ has ALIGN bit */
 103         bool supports_sync_align:1;
 104
 105         bool has_writeback:1;
 106
 107         bool supports_double_pixel:1;
 108
 109         /*
 110          * Field order for VENC is different than HDMI. We should handle this in
 111          * some intelligent manner, but as the SoCs have either HDMI or VENC,
 112          * never both, we can just use this flag for now.
 113          */
 114         bool reverse_ilace_field_order:1;
 115
 116         bool has_gamma_table:1;
 117 };
 118
 119 #define DISPC_MAX_NR_FIFOS 5
 120 #define DISPC_MAX_CHANNEL_GAMMA 4
 121
 122 static struct {
 123         struct platform_device *pdev;
 124         void __iomem    *base;
 125
 126         int irq;
 127         irq_handler_t user_handler;
 128         void *user_data;
 129
 130         unsigned long core_clk_rate;
 131         unsigned long tv_pclk_rate;
 132
 133         u32 fifo_size[DISPC_MAX_NR_FIFOS];
 134         /* maps which plane is using a fifo. fifo-id -> plane-id */
 135         int fifo_assignment[DISPC_MAX_NR_FIFOS];
 136
 137         bool            ctx_valid;
 138         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 139
 140         u32 *gamma_table[DISPC_MAX_CHANNEL_GAMMA];
 141
 142         const struct dispc_features *feat;
 143
 144         bool is_enabled;
 145
 146         struct regmap *syscon_pol;
 147         u32 syscon_pol_offset;
 148
 149         /* DISPC_CONTROL & DISPC_CONFIG lock*/
 150         spinlock_t control_lock;
 151 } dispc;
 152
 153 enum omap_color_component {
 154         /* used for all color formats for OMAP3 and earlier
 155          * and for RGB and Y color component on OMAP4
 156          */
 157         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 158         /* used for UV component for
 159          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 160          * color formats on OMAP4
 161          */
 162         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 163 };
 164
 165 enum mgr_reg_fields {
 166         DISPC_MGR_FLD_ENABLE,
 167         DISPC_MGR_FLD_STNTFT,
 168         DISPC_MGR_FLD_GO,
 169         DISPC_MGR_FLD_TFTDATALINES,
 170         DISPC_MGR_FLD_STALLMODE,
 171         DISPC_MGR_FLD_TCKENABLE,
 172         DISPC_MGR_FLD_TCKSELECTION,
 173         DISPC_MGR_FLD_CPR,
 174         DISPC_MGR_FLD_FIFOHANDCHECK,
 175         /* used to maintain a count of the above fields */
 176         DISPC_MGR_FLD_NUM,
 177 };
 178
 179 struct dispc_reg_field {
 180         u16 reg;
 181         u8 high;
 182         u8 low;
 183 };
 184
 185 struct dispc_gamma_desc {
 186         u32 len;
 187         u32 bits;
 188         u16 reg;
 189         bool has_index;
 190 };
 191
 192 static const struct {
 193         const char *name;
 194         u32 vsync_irq;
 195         u32 framedone_irq;
 196         u32 sync_lost_irq;
 197         struct dispc_gamma_desc gamma;
 198         struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
 199 } mgr_desc[] = {
 200         [OMAP_DSS_CHANNEL_LCD] = {
 201                 .name           = "LCD",
 202                 .vsync_irq      = DISPC_IRQ_VSYNC,
 203                 .framedone_irq  = DISPC_IRQ_FRAMEDONE,
 204                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST,
 205                 .gamma          = {
 206                         .len    = 256,
 207                         .bits   = 8,
 208                         .reg    = DISPC_GAMMA_TABLE0,
 209                         .has_index = true,
 210                 },
 211                 .reg_desc       = {
 212                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  0,  0 },
 213                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL,  3,  3 },
 214                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  5,  5 },
 215                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL,  9,  8 },
 216                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL, 11, 11 },
 217                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  10, 10 },
 218                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  11, 11 },
 219                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG,  15, 15 },
 220                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 221                 },
 222         },
 223         [OMAP_DSS_CHANNEL_DIGIT] = {
 224                 .name           = "DIGIT",
 225                 .vsync_irq      = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
 226                 .framedone_irq  = DISPC_IRQ_FRAMEDONETV,
 227                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST_DIGIT,
 228                 .gamma          = {
 229                         .len    = 1024,
 230                         .bits   = 10,
 231                         .reg    = DISPC_GAMMA_TABLE2,
 232                         .has_index = false,
 233                 },
 234                 .reg_desc       = {
 235                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  1,  1 },
 236                         [DISPC_MGR_FLD_STNTFT]          = { },
 237                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  6,  6 },
 238                         [DISPC_MGR_FLD_TFTDATALINES]    = { },
 239                         [DISPC_MGR_FLD_STALLMODE]       = { },
 240                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  12, 12 },
 241                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  13, 13 },
 242                         [DISPC_MGR_FLD_CPR]             = { },
 243                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 244                 },
 245         },
 246         [OMAP_DSS_CHANNEL_LCD2] = {
 247                 .name           = "LCD2",
 248                 .vsync_irq      = DISPC_IRQ_VSYNC2,
 249                 .framedone_irq  = DISPC_IRQ_FRAMEDONE2,
 250                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST2,
 251                 .gamma          = {
 252                         .len    = 256,
 253                         .bits   = 8,
 254                         .reg    = DISPC_GAMMA_TABLE1,
 255                         .has_index = true,
 256                 },
 257                 .reg_desc       = {
 258                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL2,  0,  0 },
 259                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL2,  3,  3 },
 260                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL2,  5,  5 },
 261                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL2,  9,  8 },
 262                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL2, 11, 11 },
 263                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG2,  10, 10 },
 264                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG2,  11, 11 },
 265                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG2,  15, 15 },
 266                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG2,  16, 16 },
 267                 },
 268         },
 269         [OMAP_DSS_CHANNEL_LCD3] = {
 270                 .name           = "LCD3",
 271                 .vsync_irq      = DISPC_IRQ_VSYNC3,
 272                 .framedone_irq  = DISPC_IRQ_FRAMEDONE3,
 273                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST3,
 274                 .gamma          = {
 275                         .len    = 256,
 276                         .bits   = 8,
 277                         .reg    = DISPC_GAMMA_TABLE3,
 278                         .has_index = true,
 279                 },
 280                 .reg_desc       = {
 281                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL3,  0,  0 },
 282                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL3,  3,  3 },
 283                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL3,  5,  5 },
 284                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL3,  9,  8 },
 285                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL3, 11, 11 },
 286                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG3,  10, 10 },
 287                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG3,  11, 11 },
 288                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG3,  15, 15 },
 289                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG3,  16, 16 },
 290                 },
 291         },
 292 };
 293
 294 struct color_conv_coef {
 295         int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
 296         int full_range;
 297 };
 298
 299 static unsigned long dispc_fclk_rate(void);
 300 static unsigned long dispc_core_clk_rate(void);
 301 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
 302 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
 303
 304 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
 305 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
 306
 307 static inline void dispc_write_reg(const u16 idx, u32 val)
 308 {
 309         __raw_writel(val, dispc.base + idx);
 310 }
 311
 312 static inline u32 dispc_read_reg(const u16 idx)
 313 {
 314         return __raw_readl(dispc.base + idx);
 315 }
 316
 317 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
 318 {
 319         const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 320         return REG_GET(rfld.reg, rfld.high, rfld.low);
 321 }
 322
 323 static void mgr_fld_write(enum omap_channel channel,
 324                                         enum mgr_reg_fields regfld, int val) {
 325         const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 326         const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
 327         unsigned long flags;
 328
 329         if (need_lock)
 330                 spin_lock_irqsave(&dispc.control_lock, flags);
 331
 332         REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
 333
 334         if (need_lock)
 335                 spin_unlock_irqrestore(&dispc.control_lock, flags);
 336 }
 337
 338 #define SR(reg) \
 339         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 340 #define RR(reg) \
 341         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 342
 343 static void dispc_save_context(void)
 344 {
 345         int i, j;
 346
 347         DSSDBG("dispc_save_context\n");
 348
 349         SR(IRQENABLE);
 350         SR(CONTROL);
 351         SR(CONFIG);
 352         SR(LINE_NUMBER);
 353         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 354                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 355                 SR(GLOBAL_ALPHA);
 356         if (dss_has_feature(FEAT_MGR_LCD2)) {
 357                 SR(CONTROL2);
 358                 SR(CONFIG2);
 359         }
 360         if (dss_has_feature(FEAT_MGR_LCD3)) {
 361                 SR(CONTROL3);
 362                 SR(CONFIG3);
 363         }
 364
 365         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 366                 SR(DEFAULT_COLOR(i));
 367                 SR(TRANS_COLOR(i));
 368                 SR(SIZE_MGR(i));
 369                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 370                         continue;
 371                 SR(TIMING_H(i));
 372                 SR(TIMING_V(i));
 373                 SR(POL_FREQ(i));
 374                 SR(DIVISORo(i));
 375
 376                 SR(DATA_CYCLE1(i));
 377                 SR(DATA_CYCLE2(i));
 378                 SR(DATA_CYCLE3(i));
 379
 380                 if (dss_has_feature(FEAT_CPR)) {
 381                         SR(CPR_COEF_R(i));
 382                         SR(CPR_COEF_G(i));
 383                         SR(CPR_COEF_B(i));
 384                 }
 385         }
 386
 387         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 388                 SR(OVL_BA0(i));
 389                 SR(OVL_BA1(i));
 390                 SR(OVL_POSITION(i));
 391                 SR(OVL_SIZE(i));
 392                 SR(OVL_ATTRIBUTES(i));
 393                 SR(OVL_FIFO_THRESHOLD(i));
 394                 SR(OVL_ROW_INC(i));
 395                 SR(OVL_PIXEL_INC(i));
 396                 if (dss_has_feature(FEAT_PRELOAD))
 397                         SR(OVL_PRELOAD(i));
 398                 if (i == OMAP_DSS_GFX) {
 399                         SR(OVL_WINDOW_SKIP(i));
 400                         SR(OVL_TABLE_BA(i));
 401                         continue;
 402                 }
 403                 SR(OVL_FIR(i));
 404                 SR(OVL_PICTURE_SIZE(i));
 405                 SR(OVL_ACCU0(i));
 406                 SR(OVL_ACCU1(i));
 407
 408                 for (j = 0; j < 8; j++)
 409                         SR(OVL_FIR_COEF_H(i, j));
 410
 411                 for (j = 0; j < 8; j++)
 412                         SR(OVL_FIR_COEF_HV(i, j));
 413
 414                 for (j = 0; j < 5; j++)
 415                         SR(OVL_CONV_COEF(i, j));
 416
 417                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 418                         for (j = 0; j < 8; j++)
 419                                 SR(OVL_FIR_COEF_V(i, j));
 420                 }
 421
 422                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 423                         SR(OVL_BA0_UV(i));
 424                         SR(OVL_BA1_UV(i));
 425                         SR(OVL_FIR2(i));
 426                         SR(OVL_ACCU2_0(i));
 427                         SR(OVL_ACCU2_1(i));
 428
 429                         for (j = 0; j < 8; j++)
 430                                 SR(OVL_FIR_COEF_H2(i, j));
 431
 432                         for (j = 0; j < 8; j++)
 433                                 SR(OVL_FIR_COEF_HV2(i, j));
 434
 435                         for (j = 0; j < 8; j++)
 436                                 SR(OVL_FIR_COEF_V2(i, j));
 437                 }
 438                 if (dss_has_feature(FEAT_ATTR2))
 439                         SR(OVL_ATTRIBUTES2(i));
 440         }
 441
 442         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 443                 SR(DIVISOR);
 444
 445         dispc.ctx_valid = true;
 446
 447         DSSDBG("context saved\n");
 448 }
 449
 450 static void dispc_restore_context(void)
 451 {
 452         int i, j;
 453
 454         DSSDBG("dispc_restore_context\n");
 455
 456         if (!dispc.ctx_valid)
 457                 return;
 458
 459         /*RR(IRQENABLE);*/
 460         /*RR(CONTROL);*/
 461         RR(CONFIG);
 462         RR(LINE_NUMBER);
 463         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 464                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 465                 RR(GLOBAL_ALPHA);
 466         if (dss_has_feature(FEAT_MGR_LCD2))
 467                 RR(CONFIG2);
 468         if (dss_has_feature(FEAT_MGR_LCD3))
 469                 RR(CONFIG3);
 470
 471         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 472                 RR(DEFAULT_COLOR(i));
 473                 RR(TRANS_COLOR(i));
 474                 RR(SIZE_MGR(i));
 475                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 476                         continue;
 477                 RR(TIMING_H(i));
 478                 RR(TIMING_V(i));
 479                 RR(POL_FREQ(i));
 480                 RR(DIVISORo(i));
 481
 482                 RR(DATA_CYCLE1(i));
 483                 RR(DATA_CYCLE2(i));
 484                 RR(DATA_CYCLE3(i));
 485
 486                 if (dss_has_feature(FEAT_CPR)) {
 487                         RR(CPR_COEF_R(i));
 488                         RR(CPR_COEF_G(i));
 489                         RR(CPR_COEF_B(i));
 490                 }
 491         }
 492
 493         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 494                 RR(OVL_BA0(i));
 495                 RR(OVL_BA1(i));
 496                 RR(OVL_POSITION(i));
 497                 RR(OVL_SIZE(i));
 498                 RR(OVL_ATTRIBUTES(i));
 499                 RR(OVL_FIFO_THRESHOLD(i));
 500                 RR(OVL_ROW_INC(i));
 501                 RR(OVL_PIXEL_INC(i));
 502                 if (dss_has_feature(FEAT_PRELOAD))
 503                         RR(OVL_PRELOAD(i));
 504                 if (i == OMAP_DSS_GFX) {
 505                         RR(OVL_WINDOW_SKIP(i));
 506                         RR(OVL_TABLE_BA(i));
 507                         continue;
 508                 }
 509                 RR(OVL_FIR(i));
 510                 RR(OVL_PICTURE_SIZE(i));
 511                 RR(OVL_ACCU0(i));
 512                 RR(OVL_ACCU1(i));
 513
 514                 for (j = 0; j < 8; j++)
 515                         RR(OVL_FIR_COEF_H(i, j));
 516
 517                 for (j = 0; j < 8; j++)
 518                         RR(OVL_FIR_COEF_HV(i, j));
 519
 520                 for (j = 0; j < 5; j++)
 521                         RR(OVL_CONV_COEF(i, j));
 522
 523                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 524                         for (j = 0; j < 8; j++)
 525                                 RR(OVL_FIR_COEF_V(i, j));
 526                 }
 527
 528                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 529                         RR(OVL_BA0_UV(i));
 530                         RR(OVL_BA1_UV(i));
 531                         RR(OVL_FIR2(i));
 532                         RR(OVL_ACCU2_0(i));
 533                         RR(OVL_ACCU2_1(i));
 534
 535                         for (j = 0; j < 8; j++)
 536                                 RR(OVL_FIR_COEF_H2(i, j));
 537
 538                         for (j = 0; j < 8; j++)
 539                                 RR(OVL_FIR_COEF_HV2(i, j));
 540
 541                         for (j = 0; j < 8; j++)
 542                                 RR(OVL_FIR_COEF_V2(i, j));
 543                 }
 544                 if (dss_has_feature(FEAT_ATTR2))
 545                         RR(OVL_ATTRIBUTES2(i));
 546         }
 547
 548         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 549                 RR(DIVISOR);
 550
 551         /* enable last, because LCD & DIGIT enable are here */
 552         RR(CONTROL);
 553         if (dss_has_feature(FEAT_MGR_LCD2))
 554                 RR(CONTROL2);
 555         if (dss_has_feature(FEAT_MGR_LCD3))
 556                 RR(CONTROL3);
 557         /* clear spurious SYNC_LOST_DIGIT interrupts */
 558         dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
 559
 560         /*
 561          * enable last so IRQs won't trigger before
 562          * the context is fully restored
 563          */
 564         RR(IRQENABLE);
 565
 566         DSSDBG("context restored\n");
 567 }
 568
 569 #undef SR
 570 #undef RR
 571
 572 int dispc_runtime_get(void)
 573 {
 574         int r;
 575
 576         DSSDBG("dispc_runtime_get\n");
 577
 578         r = pm_runtime_get_sync(&dispc.pdev->dev);
 579         WARN_ON(r < 0);
 580         return r < 0 ? r : 0;
 581 }
 582 EXPORT_SYMBOL(dispc_runtime_get);
 583
 584 void dispc_runtime_put(void)
 585 {
 586         int r;
 587
 588         DSSDBG("dispc_runtime_put\n");
 589
 590         r = pm_runtime_put_sync(&dispc.pdev->dev);
 591         WARN_ON(r < 0 && r != -ENOSYS);
 592 }
 593 EXPORT_SYMBOL(dispc_runtime_put);
 594
 595 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
 596 {
 597         return mgr_desc[channel].vsync_irq;
 598 }
 599 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
 600
 601 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
 602 {
 603         if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
 604                 return 0;
 605
 606         return mgr_desc[channel].framedone_irq;
 607 }
 608 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
 609
 610 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
 611 {
 612         return mgr_desc[channel].sync_lost_irq;
 613 }
 614 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
 615
 616 u32 dispc_wb_get_framedone_irq(void)
 617 {
 618         return DISPC_IRQ_FRAMEDONEWB;
 619 }
 620
 621 bool dispc_mgr_go_busy(enum omap_channel channel)
 622 {
 623         return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
 624 }
 625 EXPORT_SYMBOL(dispc_mgr_go_busy);
 626
 627 void dispc_mgr_go(enum omap_channel channel)
 628 {
 629         WARN_ON(!dispc_mgr_is_enabled(channel));
 630         WARN_ON(dispc_mgr_go_busy(channel));
 631
 632         DSSDBG("GO %s\n", mgr_desc[channel].name);
 633
 634         mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
 635 }
 636 EXPORT_SYMBOL(dispc_mgr_go);
 637
 638 bool dispc_wb_go_busy(void)
 639 {
 640         return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 641 }
 642
 643 void dispc_wb_go(void)
 644 {
 645         enum omap_plane plane = OMAP_DSS_WB;
 646         bool enable, go;
 647
 648         enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
 649
 650         if (!enable)
 651                 return;
 652
 653         go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 654         if (go) {
 655                 DSSERR("GO bit not down for WB\n");
 656                 return;
 657         }
 658
 659         REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
 660 }
 661
 662 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 663 {
 664         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 665 }
 666
 667 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 668 {
 669         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 670 }
 671
 672 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 673 {
 674         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 675 }
 676
 677 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 678 {
 679         BUG_ON(plane == OMAP_DSS_GFX);
 680
 681         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 682 }
 683
 684 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 685                 u32 value)
 686 {
 687         BUG_ON(plane == OMAP_DSS_GFX);
 688
 689         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 690 }
 691
 692 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 693 {
 694         BUG_ON(plane == OMAP_DSS_GFX);
 695
 696         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 697 }
 698
 699 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
 700                                 int fir_vinc, int five_taps,
 701                                 enum omap_color_component color_comp)
 702 {
 703         const struct dispc_coef *h_coef, *v_coef;
 704         int i;
 705
 706         h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
 707         v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
 708
 709         for (i = 0; i < 8; i++) {
 710                 u32 h, hv;
 711
 712                 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
 713                         | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
 714                         | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
 715                         | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
 716                 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
 717                         | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
 718                         | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
 719                         | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
 720
 721                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 722                         dispc_ovl_write_firh_reg(plane, i, h);
 723                         dispc_ovl_write_firhv_reg(plane, i, hv);
 724                 } else {
 725                         dispc_ovl_write_firh2_reg(plane, i, h);
 726                         dispc_ovl_write_firhv2_reg(plane, i, hv);
 727                 }
 728
 729         }
 730
 731         if (five_taps) {
 732                 for (i = 0; i < 8; i++) {
 733                         u32 v;
 734                         v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
 735                                 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
 736                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 737                                 dispc_ovl_write_firv_reg(plane, i, v);
 738                         else
 739                                 dispc_ovl_write_firv2_reg(plane, i, v);
 740                 }
 741         }
 742 }
 743
 744
 745 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
 746                 const struct color_conv_coef *ct)
 747 {
 748 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 749
 750         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
 751         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy,  ct->rcb));
 752         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
 753         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
 754         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
 755
 756         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
 757
 758 #undef CVAL
 759 }
 760
 761 static void dispc_setup_color_conv_coef(void)
 762 {
 763         int i;
 764         int num_ovl = dss_feat_get_num_ovls();
 765         const struct color_conv_coef ctbl_bt601_5_ovl = {
 766                 /* YUV -> RGB */
 767                 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
 768         };
 769         const struct color_conv_coef ctbl_bt601_5_wb = {
 770                 /* RGB -> YUV */
 771                 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
 772         };
 773
 774         for (i = 1; i < num_ovl; i++)
 775                 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
 776
 777         if (dispc.feat->has_writeback)
 778                 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
 779 }
 780
 781 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
 782 {
 783         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 784 }
 785
 786 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
 787 {
 788         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 789 }
 790
 791 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
 792 {
 793         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 794 }
 795
 796 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
 797 {
 798         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 799 }
 800
 801 static void dispc_ovl_set_pos(enum omap_plane plane,
 802                 enum omap_overlay_caps caps, int x, int y)
 803 {
 804         u32 val;
 805
 806         if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
 807                 return;
 808
 809         val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 810
 811         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 812 }
 813
 814 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
 815                 int height)
 816 {
 817         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 818
 819         if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
 820                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 821         else
 822                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 823 }
 824
 825 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
 826                 int height)
 827 {
 828         u32 val;
 829
 830         BUG_ON(plane == OMAP_DSS_GFX);
 831
 832         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 833
 834         if (plane == OMAP_DSS_WB)
 835                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 836         else
 837                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 838 }
 839
 840 static void dispc_ovl_set_zorder(enum omap_plane plane,
 841                 enum omap_overlay_caps caps, u8 zorder)
 842 {
 843         if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
 844                 return;
 845
 846         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
 847 }
 848
 849 static void dispc_ovl_enable_zorder_planes(void)
 850 {
 851         int i;
 852
 853         if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 854                 return;
 855
 856         for (i = 0; i < dss_feat_get_num_ovls(); i++)
 857                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
 858 }
 859
 860 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
 861                 enum omap_overlay_caps caps, bool enable)
 862 {
 863         if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 864                 return;
 865
 866         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 867 }
 868
 869 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
 870                 enum omap_overlay_caps caps, u8 global_alpha)
 871 {
 872         static const unsigned shifts[] = { 0, 8, 16, 24, };
 873         int shift;
 874
 875         if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 876                 return;
 877
 878         shift = shifts[plane];
 879         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 880 }
 881
 882 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
 883 {
 884         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 885 }
 886
 887 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
 888 {
 889         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 890 }
 891
 892 static void dispc_ovl_set_color_mode(enum omap_plane plane,
 893                 enum omap_color_mode color_mode)
 894 {
 895         u32 m = 0;
 896         if (plane != OMAP_DSS_GFX) {
 897                 switch (color_mode) {
 898                 case OMAP_DSS_COLOR_NV12:
 899                         m = 0x0; break;
 900                 case OMAP_DSS_COLOR_RGBX16:
 901                         m = 0x1; break;
 902                 case OMAP_DSS_COLOR_RGBA16:
 903                         m = 0x2; break;
 904                 case OMAP_DSS_COLOR_RGB12U:
 905                         m = 0x4; break;
 906                 case OMAP_DSS_COLOR_ARGB16:
 907                         m = 0x5; break;
 908                 case OMAP_DSS_COLOR_RGB16:
 909                         m = 0x6; break;
 910                 case OMAP_DSS_COLOR_ARGB16_1555:
 911                         m = 0x7; break;
 912                 case OMAP_DSS_COLOR_RGB24U:
 913                         m = 0x8; break;
 914                 case OMAP_DSS_COLOR_RGB24P:
 915                         m = 0x9; break;
 916                 case OMAP_DSS_COLOR_YUV2:
 917                         m = 0xa; break;
 918                 case OMAP_DSS_COLOR_UYVY:
 919                         m = 0xb; break;
 920                 case OMAP_DSS_COLOR_ARGB32:
 921                         m = 0xc; break;
 922                 case OMAP_DSS_COLOR_RGBA32:
 923                         m = 0xd; break;
 924                 case OMAP_DSS_COLOR_RGBX32:
 925                         m = 0xe; break;
 926                 case OMAP_DSS_COLOR_XRGB16_1555:
 927                         m = 0xf; break;
 928                 default:
 929                         BUG(); return;
 930                 }
 931         } else {
 932                 switch (color_mode) {
 933                 case OMAP_DSS_COLOR_CLUT1:
 934                         m = 0x0; break;
 935                 case OMAP_DSS_COLOR_CLUT2:
 936                         m = 0x1; break;
 937                 case OMAP_DSS_COLOR_CLUT4:
 938                         m = 0x2; break;
 939                 case OMAP_DSS_COLOR_CLUT8:
 940                         m = 0x3; break;
 941                 case OMAP_DSS_COLOR_RGB12U:
 942                         m = 0x4; break;
 943                 case OMAP_DSS_COLOR_ARGB16:
 944                         m = 0x5; break;
 945                 case OMAP_DSS_COLOR_RGB16:
 946                         m = 0x6; break;
 947                 case OMAP_DSS_COLOR_ARGB16_1555:
 948                         m = 0x7; break;
 949                 case OMAP_DSS_COLOR_RGB24U:
 950                         m = 0x8; break;
 951                 case OMAP_DSS_COLOR_RGB24P:
 952                         m = 0x9; break;
 953                 case OMAP_DSS_COLOR_RGBX16:
 954                         m = 0xa; break;
 955                 case OMAP_DSS_COLOR_RGBA16:
 956                         m = 0xb; break;
 957                 case OMAP_DSS_COLOR_ARGB32:
 958                         m = 0xc; break;
 959                 case OMAP_DSS_COLOR_RGBA32:
 960                         m = 0xd; break;
 961                 case OMAP_DSS_COLOR_RGBX32:
 962                         m = 0xe; break;
 963                 case OMAP_DSS_COLOR_XRGB16_1555:
 964                         m = 0xf; break;
 965                 default:
 966                         BUG(); return;
 967                 }
 968         }
 969
 970         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 971 }
 972
 973 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
 974                 enum omap_dss_rotation_type rotation_type)
 975 {
 976         if (dss_has_feature(FEAT_BURST_2D) == 0)
 977                 return;
 978
 979         if (rotation_type == OMAP_DSS_ROT_TILER)
 980                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
 981         else
 982                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
 983 }
 984
 985 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
 986 {
 987         int shift;
 988         u32 val;
 989         int chan = 0, chan2 = 0;
 990
 991         switch (plane) {
 992         case OMAP_DSS_GFX:
 993                 shift = 8;
 994                 break;
 995         case OMAP_DSS_VIDEO1:
 996         case OMAP_DSS_VIDEO2:
 997         case OMAP_DSS_VIDEO3:
 998                 shift = 16;
 999                 break;
1000         default:
1001                 BUG();
1002                 return;
1003         }
1004
1005         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1006         if (dss_has_feature(FEAT_MGR_LCD2)) {
1007                 switch (channel) {
1008                 case OMAP_DSS_CHANNEL_LCD:
1009                         chan = 0;
1010                         chan2 = 0;
1011                         break;
1012                 case OMAP_DSS_CHANNEL_DIGIT:
1013                         chan = 1;
1014                         chan2 = 0;
1015                         break;
1016                 case OMAP_DSS_CHANNEL_LCD2:
1017                         chan = 0;
1018                         chan2 = 1;
1019                         break;
1020                 case OMAP_DSS_CHANNEL_LCD3:
1021                         if (dss_has_feature(FEAT_MGR_LCD3)) {
1022                                 chan = 0;
1023                                 chan2 = 2;
1024                         } else {
1025                                 BUG();
1026                                 return;
1027                         }
1028                         break;
1029                 case OMAP_DSS_CHANNEL_WB:
1030                         chan = 0;
1031                         chan2 = 3;
1032                         break;
1033                 default:
1034                         BUG();
1035                         return;
1036                 }
1037
1038                 val = FLD_MOD(val, chan, shift, shift);
1039                 val = FLD_MOD(val, chan2, 31, 30);
1040         } else {
1041                 val = FLD_MOD(val, channel, shift, shift);
1042         }
1043         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1044 }
1045 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
1046
1047 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
1048 {
1049         int shift;
1050         u32 val;
1051
1052         switch (plane) {
1053         case OMAP_DSS_GFX:
1054                 shift = 8;
1055                 break;
1056         case OMAP_DSS_VIDEO1:
1057         case OMAP_DSS_VIDEO2:
1058         case OMAP_DSS_VIDEO3:
1059                 shift = 16;
1060                 break;
1061         default:
1062                 BUG();
1063                 return 0;
1064         }
1065
1066         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1067
1068         if (FLD_GET(val, shift, shift) == 1)
1069                 return OMAP_DSS_CHANNEL_DIGIT;
1070
1071         if (!dss_has_feature(FEAT_MGR_LCD2))
1072                 return OMAP_DSS_CHANNEL_LCD;
1073
1074         switch (FLD_GET(val, 31, 30)) {
1075         case 0:
1076         default:
1077                 return OMAP_DSS_CHANNEL_LCD;
1078         case 1:
1079                 return OMAP_DSS_CHANNEL_LCD2;
1080         case 2:
1081                 return OMAP_DSS_CHANNEL_LCD3;
1082         case 3:
1083                 return OMAP_DSS_CHANNEL_WB;
1084         }
1085 }
1086
1087 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1088 {
1089         enum omap_plane plane = OMAP_DSS_WB;
1090
1091         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1092 }
1093
1094 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1095                 enum omap_burst_size burst_size)
1096 {
1097         static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1098         int shift;
1099
1100         shift = shifts[plane];
1101         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1102 }
1103
1104 static void dispc_configure_burst_sizes(void)
1105 {
1106         int i;
1107         const int burst_size = BURST_SIZE_X8;
1108
1109         /* Configure burst size always to maximum size */
1110         for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1111                 dispc_ovl_set_burst_size(i, burst_size);
1112         if (dispc.feat->has_writeback)
1113                 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
1114 }
1115
1116 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1117 {
1118         unsigned unit = dss_feat_get_burst_size_unit();
1119         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1120         return unit * 8;
1121 }
1122
1123 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1124 {
1125         if (channel == OMAP_DSS_CHANNEL_DIGIT)
1126                 return;
1127
1128         mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1129 }
1130
1131 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1132                 const struct omap_dss_cpr_coefs *coefs)
1133 {
1134         u32 coef_r, coef_g, coef_b;
1135
1136         if (!dss_mgr_is_lcd(channel))
1137                 return;
1138
1139         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1140                 FLD_VAL(coefs->rb, 9, 0);
1141         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1142                 FLD_VAL(coefs->gb, 9, 0);
1143         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1144                 FLD_VAL(coefs->bb, 9, 0);
1145
1146         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1147         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1148         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1149 }
1150
1151 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1152 {
1153         u32 val;
1154
1155         BUG_ON(plane == OMAP_DSS_GFX);
1156
1157         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1158         val = FLD_MOD(val, enable, 9, 9);
1159         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1160 }
1161
1162 static void dispc_ovl_enable_replication(enum omap_plane plane,
1163                 enum omap_overlay_caps caps, bool enable)
1164 {
1165         static const unsigned shifts[] = { 5, 10, 10, 10 };
1166         int shift;
1167
1168         if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1169                 return;
1170
1171         shift = shifts[plane];
1172         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1173 }
1174
1175 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1176                 u16 height)
1177 {
1178         u32 val;
1179
1180         val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1181                 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1182
1183         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1184 }
1185
1186 static void dispc_init_fifos(void)
1187 {
1188         u32 size;
1189         int fifo;
1190         u8 start, end;
1191         u32 unit;
1192         int i;
1193
1194         unit = dss_feat_get_buffer_size_unit();
1195
1196         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1197
1198         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1199                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1200                 size *= unit;
1201                 dispc.fifo_size[fifo] = size;
1202
1203                 /*
1204                  * By default fifos are mapped directly to overlays, fifo 0 to
1205                  * ovl 0, fifo 1 to ovl 1, etc.
1206                  */
1207                 dispc.fifo_assignment[fifo] = fifo;
1208         }
1209
1210         /*
1211          * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1212          * causes problems with certain use cases, like using the tiler in 2D
1213          * mode. The below hack swaps the fifos of GFX and WB planes, thus
1214          * giving GFX plane a larger fifo. WB but should work fine with a
1215          * smaller fifo.
1216          */
1217         if (dispc.feat->gfx_fifo_workaround) {
1218                 u32 v;
1219
1220                 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1221
1222                 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1223                 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1224                 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1225                 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1226
1227                 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1228
1229                 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1230                 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1231         }
1232
1233         /*
1234          * Setup default fifo thresholds.
1235          */
1236         for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1237                 u32 low, high;
1238                 const bool use_fifomerge = false;
1239                 const bool manual_update = false;
1240
1241                 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1242                         use_fifomerge, manual_update);
1243
1244                 dispc_ovl_set_fifo_threshold(i, low, high);
1245         }
1246
1247         if (dispc.feat->has_writeback) {
1248                 u32 low, high;
1249                 const bool use_fifomerge = false;
1250                 const bool manual_update = false;
1251
1252                 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1253                         use_fifomerge, manual_update);
1254
1255                 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1256         }
1257 }
1258
1259 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1260 {
1261         int fifo;
1262         u32 size = 0;
1263
1264         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1265                 if (dispc.fifo_assignment[fifo] == plane)
1266                         size += dispc.fifo_size[fifo];
1267         }
1268
1269         return size;
1270 }
1271
1272 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1273 {
1274         u8 hi_start, hi_end, lo_start, lo_end;
1275         u32 unit;
1276
1277         unit = dss_feat_get_buffer_size_unit();
1278
1279         WARN_ON(low % unit != 0);
1280         WARN_ON(high % unit != 0);
1281
1282         low /= unit;
1283         high /= unit;
1284
1285         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1286         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1287
1288         DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1289                         plane,
1290                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1291                                 lo_start, lo_end) * unit,
1292                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1293                                 hi_start, hi_end) * unit,
1294                         low * unit, high * unit);
1295
1296         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1297                         FLD_VAL(high, hi_start, hi_end) |
1298                         FLD_VAL(low, lo_start, lo_end));
1299
1300         /*
1301          * configure the preload to the pipeline's high threhold, if HT it's too
1302          * large for the preload field, set the threshold to the maximum value
1303          * that can be held by the preload register
1304          */
1305         if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1306                         plane != OMAP_DSS_WB)
1307                 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1308 }
1309
1310 void dispc_enable_fifomerge(bool enable)
1311 {
1312         if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1313                 WARN_ON(enable);
1314                 return;
1315         }
1316
1317         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1318         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1319 }
1320
1321 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1322                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1323                 bool manual_update)
1324 {
1325         /*
1326          * All sizes are in bytes. Both the buffer and burst are made of
1327          * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1328          */
1329
1330         unsigned buf_unit = dss_feat_get_buffer_size_unit();
1331         unsigned ovl_fifo_size, total_fifo_size, burst_size;
1332         int i;
1333
1334         burst_size = dispc_ovl_get_burst_size(plane);
1335         ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1336
1337         if (use_fifomerge) {
1338                 total_fifo_size = 0;
1339                 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1340                         total_fifo_size += dispc_ovl_get_fifo_size(i);
1341         } else {
1342                 total_fifo_size = ovl_fifo_size;
1343         }
1344
1345         /*
1346          * We use the same low threshold for both fifomerge and non-fifomerge
1347          * cases, but for fifomerge we calculate the high threshold using the
1348          * combined fifo size
1349          */
1350
1351         if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1352                 *fifo_low = ovl_fifo_size - burst_size * 2;
1353                 *fifo_high = total_fifo_size - burst_size;
1354         } else if (plane == OMAP_DSS_WB) {
1355                 /*
1356                  * Most optimal configuration for writeback is to push out data
1357                  * to the interconnect the moment writeback pushes enough pixels
1358                  * in the FIFO to form a burst
1359                  */
1360                 *fifo_low = 0;
1361                 *fifo_high = burst_size;
1362         } else {
1363                 *fifo_low = ovl_fifo_size - burst_size;
1364                 *fifo_high = total_fifo_size - buf_unit;
1365         }
1366 }
1367
1368 static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1369 {
1370         int bit;
1371
1372         if (plane == OMAP_DSS_GFX)
1373                 bit = 14;
1374         else
1375                 bit = 23;
1376
1377         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1378 }
1379
1380 static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1381         int low, int high)
1382 {
1383         dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1384                 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1385 }
1386
1387 static void dispc_init_mflag(void)
1388 {
1389         int i;
1390
1391         /*
1392          * HACK: NV12 color format and MFLAG seem to have problems working
1393          * together: using two displays, and having an NV12 overlay on one of
1394          * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1395          * Changing MFLAG thresholds and PRELOAD to certain values seem to
1396          * remove the errors, but there doesn't seem to be a clear logic on
1397          * which values work and which not.
1398          *
1399          * As a work-around, set force MFLAG to always on.
1400          */
1401         dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1402                 (1 << 0) |      /* MFLAG_CTRL = force always on */
1403                 (0 << 2));      /* MFLAG_START = disable */
1404
1405         for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1406                 u32 size = dispc_ovl_get_fifo_size(i);
1407                 u32 unit = dss_feat_get_buffer_size_unit();
1408                 u32 low, high;
1409
1410                 dispc_ovl_set_mflag(i, true);
1411
1412                 /*
1413                  * Simulation team suggests below thesholds:
1414                  * HT = fifosize * 5 / 8;
1415                  * LT = fifosize * 4 / 8;
1416                  */
1417
1418                 low = size * 4 / 8 / unit;
1419                 high = size * 5 / 8 / unit;
1420
1421                 dispc_ovl_set_mflag_threshold(i, low, high);
1422         }
1423
1424         if (dispc.feat->has_writeback) {
1425                 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1426                 u32 unit = dss_feat_get_buffer_size_unit();
1427                 u32 low, high;
1428
1429                 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1430
1431                 /*
1432                  * Simulation team suggests below thesholds:
1433                  * HT = fifosize * 5 / 8;
1434                  * LT = fifosize * 4 / 8;
1435                  */
1436
1437                 low = size * 4 / 8 / unit;
1438                 high = size * 5 / 8 / unit;
1439
1440                 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1441         }
1442 }
1443
1444 static void dispc_ovl_set_fir(enum omap_plane plane,
1445                                 int hinc, int vinc,
1446                                 enum omap_color_component color_comp)
1447 {
1448         u32 val;
1449
1450         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1451                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1452
1453                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1454                                         &hinc_start, &hinc_end);
1455                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1456                                         &vinc_start, &vinc_end);
1457                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1458                                 FLD_VAL(hinc, hinc_start, hinc_end);
1459
1460                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1461         } else {
1462                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1463                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1464         }
1465 }
1466
1467 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1468 {
1469         u32 val;
1470         u8 hor_start, hor_end, vert_start, vert_end;
1471
1472         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1473         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1474
1475         val = FLD_VAL(vaccu, vert_start, vert_end) |
1476                         FLD_VAL(haccu, hor_start, hor_end);
1477
1478         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1479 }
1480
1481 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1482 {
1483         u32 val;
1484         u8 hor_start, hor_end, vert_start, vert_end;
1485
1486         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1487         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1488
1489         val = FLD_VAL(vaccu, vert_start, vert_end) |
1490                         FLD_VAL(haccu, hor_start, hor_end);
1491
1492         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1493 }
1494
1495 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1496                 int vaccu)
1497 {
1498         u32 val;
1499
1500         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1501         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1502 }
1503
1504 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1505                 int vaccu)
1506 {
1507         u32 val;
1508
1509         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1510         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1511 }
1512
1513 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1514                 u16 orig_width, u16 orig_height,
1515                 u16 out_width, u16 out_height,
1516                 bool five_taps, u8 rotation,
1517                 enum omap_color_component color_comp)
1518 {
1519         int fir_hinc, fir_vinc;
1520
1521         fir_hinc = 1024 * orig_width / out_width;
1522         fir_vinc = 1024 * orig_height / out_height;
1523
1524         dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1525                                 color_comp);
1526         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1527 }
1528
1529 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1530                 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1531                 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1532 {
1533         int h_accu2_0, h_accu2_1;
1534         int v_accu2_0, v_accu2_1;
1535         int chroma_hinc, chroma_vinc;
1536         int idx;
1537
1538         struct accu {
1539                 s8 h0_m, h0_n;
1540                 s8 h1_m, h1_n;
1541                 s8 v0_m, v0_n;
1542                 s8 v1_m, v1_n;
1543         };
1544
1545         const struct accu *accu_table;
1546         const struct accu *accu_val;
1547
1548         static const struct accu accu_nv12[4] = {
1549                 {  0, 1,  0, 1 , -1, 2, 0, 1 },
1550                 {  1, 2, -3, 4 ,  0, 1, 0, 1 },
1551                 { -1, 1,  0, 1 , -1, 2, 0, 1 },
1552                 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1553         };
1554
1555         static const struct accu accu_nv12_ilace[4] = {
1556                 {  0, 1,  0, 1 , -3, 4, -1, 4 },
1557                 { -1, 4, -3, 4 ,  0, 1,  0, 1 },
1558                 { -1, 1,  0, 1 , -1, 4, -3, 4 },
1559                 { -3, 4, -3, 4 , -1, 1,  0, 1 },
1560         };
1561
1562         static const struct accu accu_yuv[4] = {
1563                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1564                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1565                 { -1, 1, 0, 1,  0, 1, 0, 1 },
1566                 {  0, 1, 0, 1, -1, 1, 0, 1 },
1567         };
1568
1569         switch (rotation) {
1570         case OMAP_DSS_ROT_0:
1571                 idx = 0;
1572                 break;
1573         case OMAP_DSS_ROT_90:
1574                 idx = 1;
1575                 break;
1576         case OMAP_DSS_ROT_180:
1577                 idx = 2;
1578                 break;
1579         case OMAP_DSS_ROT_270:
1580                 idx = 3;
1581                 break;
1582         default:
1583                 BUG();
1584                 return;
1585         }
1586
1587         switch (color_mode) {
1588         case OMAP_DSS_COLOR_NV12:
1589                 if (ilace)
1590                         accu_table = accu_nv12_ilace;
1591                 else
1592                         accu_table = accu_nv12;
1593                 break;
1594         case OMAP_DSS_COLOR_YUV2:
1595         case OMAP_DSS_COLOR_UYVY:
1596                 accu_table = accu_yuv;
1597                 break;
1598         default:
1599                 BUG();
1600                 return;
1601         }
1602
1603         accu_val = &accu_table[idx];
1604
1605         chroma_hinc = 1024 * orig_width / out_width;
1606         chroma_vinc = 1024 * orig_height / out_height;
1607
1608         h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1609         h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1610         v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1611         v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1612
1613         dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1614         dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1615 }
1616
1617 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1618                 u16 orig_width, u16 orig_height,
1619                 u16 out_width, u16 out_height,
1620                 bool ilace, bool five_taps,
1621                 bool fieldmode, enum omap_color_mode color_mode,
1622                 u8 rotation)
1623 {
1624         int accu0 = 0;
1625         int accu1 = 0;
1626         u32 l;
1627
1628         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1629                                 out_width, out_height, five_taps,
1630                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1631         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1632
1633         /* RESIZEENABLE and VERTICALTAPS */
1634         l &= ~((0x3 << 5) | (0x1 << 21));
1635         l |= (orig_width != out_width) ? (1 << 5) : 0;
1636         l |= (orig_height != out_height) ? (1 << 6) : 0;
1637         l |= five_taps ? (1 << 21) : 0;
1638
1639         /* VRESIZECONF and HRESIZECONF */
1640         if (dss_has_feature(FEAT_RESIZECONF)) {
1641                 l &= ~(0x3 << 7);
1642                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1643                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1644         }
1645
1646         /* LINEBUFFERSPLIT */
1647         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1648                 l &= ~(0x1 << 22);
1649                 l |= five_taps ? (1 << 22) : 0;
1650         }
1651
1652         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1653
1654         /*
1655          * field 0 = even field = bottom field
1656          * field 1 = odd field = top field
1657          */
1658         if (ilace && !fieldmode) {
1659                 accu1 = 0;
1660                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1661                 if (accu0 >= 1024/2) {
1662                         accu1 = 1024/2;
1663                         accu0 -= accu1;
1664                 }
1665         }
1666
1667         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1668         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1669 }
1670
1671 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1672                 u16 orig_width, u16 orig_height,
1673                 u16 out_width, u16 out_height,
1674                 bool ilace, bool five_taps,
1675                 bool fieldmode, enum omap_color_mode color_mode,
1676                 u8 rotation)
1677 {
1678         int scale_x = out_width != orig_width;
1679         int scale_y = out_height != orig_height;
1680         bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1681
1682         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1683                 return;
1684         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1685                         color_mode != OMAP_DSS_COLOR_UYVY &&
1686                         color_mode != OMAP_DSS_COLOR_NV12)) {
1687                 /* reset chroma resampling for RGB formats  */
1688                 if (plane != OMAP_DSS_WB)
1689                         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1690                 return;
1691         }
1692
1693         dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1694                         out_height, ilace, color_mode, rotation);
1695
1696         switch (color_mode) {
1697         case OMAP_DSS_COLOR_NV12:
1698                 if (chroma_upscale) {
1699                         /* UV is subsampled by 2 horizontally and vertically */
1700                         orig_height >>= 1;
1701                         orig_width >>= 1;
1702                 } else {
1703                         /* UV is downsampled by 2 horizontally and vertically */
1704                         orig_height <<= 1;
1705                         orig_width <<= 1;
1706                 }
1707
1708                 break;
1709         case OMAP_DSS_COLOR_YUV2:
1710         case OMAP_DSS_COLOR_UYVY:
1711                 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1712                 if (rotation == OMAP_DSS_ROT_0 ||
1713                                 rotation == OMAP_DSS_ROT_180) {
1714                         if (chroma_upscale)
1715                                 /* UV is subsampled by 2 horizontally */
1716                                 orig_width >>= 1;
1717                         else
1718                                 /* UV is downsampled by 2 horizontally */
1719                                 orig_width <<= 1;
1720                 }
1721
1722                 /* must use FIR for YUV422 if rotated */
1723                 if (rotation != OMAP_DSS_ROT_0)
1724                         scale_x = scale_y = true;
1725
1726                 break;
1727         default:
1728                 BUG();
1729                 return;
1730         }
1731
1732         if (out_width != orig_width)
1733                 scale_x = true;
1734         if (out_height != orig_height)
1735                 scale_y = true;
1736
1737         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1738                         out_width, out_height, five_taps,
1739                                 rotation, DISPC_COLOR_COMPONENT_UV);
1740
1741         if (plane != OMAP_DSS_WB)
1742                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1743                         (scale_x || scale_y) ? 1 : 0, 8, 8);
1744
1745         /* set H scaling */
1746         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1747         /* set V scaling */
1748         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1749 }
1750
1751 static void dispc_ovl_set_scaling(enum omap_plane plane,
1752                 u16 orig_width, u16 orig_height,
1753                 u16 out_width, u16 out_height,
1754                 bool ilace, bool five_taps,
1755                 bool fieldmode, enum omap_color_mode color_mode,
1756                 u8 rotation)
1757 {
1758         BUG_ON(plane == OMAP_DSS_GFX);
1759
1760         dispc_ovl_set_scaling_common(plane,
1761                         orig_width, orig_height,
1762                         out_width, out_height,
1763                         ilace, five_taps,
1764                         fieldmode, color_mode,
1765                         rotation);
1766
1767         dispc_ovl_set_scaling_uv(plane,
1768                 orig_width, orig_height,
1769                 out_width, out_height,
1770                 ilace, five_taps,
1771                 fieldmode, color_mode,
1772                 rotation);
1773 }
1774
1775 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1776                 enum omap_dss_rotation_type rotation_type,
1777                 bool mirroring, enum omap_color_mode color_mode)
1778 {
1779         bool row_repeat = false;
1780         int vidrot = 0;
1781
1782         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1783                         color_mode == OMAP_DSS_COLOR_UYVY) {
1784
1785                 if (mirroring) {
1786                         switch (rotation) {
1787                         case OMAP_DSS_ROT_0:
1788                                 vidrot = 2;
1789                                 break;
1790                         case OMAP_DSS_ROT_90:
1791                                 vidrot = 1;
1792                                 break;
1793                         case OMAP_DSS_ROT_180:
1794                                 vidrot = 0;
1795                                 break;
1796                         case OMAP_DSS_ROT_270:
1797                                 vidrot = 3;
1798                                 break;
1799                         }
1800                 } else {
1801                         switch (rotation) {
1802                         case OMAP_DSS_ROT_0:
1803                                 vidrot = 0;
1804                                 break;
1805                         case OMAP_DSS_ROT_90:
1806                                 vidrot = 1;
1807                                 break;
1808                         case OMAP_DSS_ROT_180:
1809                                 vidrot = 2;
1810                                 break;
1811                         case OMAP_DSS_ROT_270:
1812                                 vidrot = 3;
1813                                 break;
1814                         }
1815                 }
1816
1817                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1818                         row_repeat = true;
1819                 else
1820                         row_repeat = false;
1821         }
1822
1823         /*
1824          * OMAP4/5 Errata i631:
1825          * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1826          * rows beyond the framebuffer, which may cause OCP error.
1827          */
1828         if (color_mode == OMAP_DSS_COLOR_NV12 &&
1829                         rotation_type != OMAP_DSS_ROT_TILER)
1830                 vidrot = 1;
1831
1832         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1833         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1834                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1835                         row_repeat ? 1 : 0, 18, 18);
1836
1837         if (color_mode == OMAP_DSS_COLOR_NV12) {
1838                 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1839                                         (rotation == OMAP_DSS_ROT_0 ||
1840                                         rotation == OMAP_DSS_ROT_180);
1841                 /* DOUBLESTRIDE */
1842                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1843         }
1844
1845 }
1846
1847 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1848 {
1849         switch (color_mode) {
1850         case OMAP_DSS_COLOR_CLUT1:
1851                 return 1;
1852         case OMAP_DSS_COLOR_CLUT2:
1853                 return 2;
1854         case OMAP_DSS_COLOR_CLUT4:
1855                 return 4;
1856         case OMAP_DSS_COLOR_CLUT8:
1857         case OMAP_DSS_COLOR_NV12:
1858                 return 8;
1859         case OMAP_DSS_COLOR_RGB12U:
1860         case OMAP_DSS_COLOR_RGB16:
1861         case OMAP_DSS_COLOR_ARGB16:
1862         case OMAP_DSS_COLOR_YUV2:
1863         case OMAP_DSS_COLOR_UYVY:
1864         case OMAP_DSS_COLOR_RGBA16:
1865         case OMAP_DSS_COLOR_RGBX16:
1866         case OMAP_DSS_COLOR_ARGB16_1555:
1867         case OMAP_DSS_COLOR_XRGB16_1555:
1868                 return 16;
1869         case OMAP_DSS_COLOR_RGB24P:
1870                 return 24;
1871         case OMAP_DSS_COLOR_RGB24U:
1872         case OMAP_DSS_COLOR_ARGB32:
1873         case OMAP_DSS_COLOR_RGBA32:
1874         case OMAP_DSS_COLOR_RGBX32:
1875                 return 32;
1876         default:
1877                 BUG();
1878                 return 0;
1879         }
1880 }
1881
1882 static s32 pixinc(int pixels, u8 ps)
1883 {
1884         if (pixels == 1)
1885                 return 1;
1886         else if (pixels > 1)
1887                 return 1 + (pixels - 1) * ps;
1888         else if (pixels < 0)
1889                 return 1 - (-pixels + 1) * ps;
1890         else
1891                 BUG();
1892                 return 0;
1893 }
1894
1895 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1896                 u16 screen_width,
1897                 u16 width, u16 height,
1898                 enum omap_color_mode color_mode, bool fieldmode,
1899                 unsigned int field_offset,
1900                 unsigned *offset0, unsigned *offset1,
1901                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1902 {
1903         u8 ps;
1904
1905         /* FIXME CLUT formats */
1906         switch (color_mode) {
1907         case OMAP_DSS_COLOR_CLUT1:
1908         case OMAP_DSS_COLOR_CLUT2:
1909         case OMAP_DSS_COLOR_CLUT4:
1910         case OMAP_DSS_COLOR_CLUT8:
1911                 BUG();
1912                 return;
1913         case OMAP_DSS_COLOR_YUV2:
1914         case OMAP_DSS_COLOR_UYVY:
1915                 ps = 4;
1916                 break;
1917         default:
1918                 ps = color_mode_to_bpp(color_mode) / 8;
1919                 break;
1920         }
1921
1922         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1923                         width, height);
1924
1925         /*
1926          * field 0 = even field = bottom field
1927          * field 1 = odd field = top field
1928          */
1929         switch (rotation + mirror * 4) {
1930         case OMAP_DSS_ROT_0:
1931         case OMAP_DSS_ROT_180:
1932                 /*
1933                  * If the pixel format is YUV or UYVY divide the width
1934                  * of the image by 2 for 0 and 180 degree rotation.
1935                  */
1936                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1937                         color_mode == OMAP_DSS_COLOR_UYVY)
1938                         width = width >> 1;
1939         case OMAP_DSS_ROT_90:
1940         case OMAP_DSS_ROT_270:
1941                 *offset1 = 0;
1942                 if (field_offset)
1943                         *offset0 = field_offset * screen_width * ps;
1944                 else
1945                         *offset0 = 0;
1946
1947                 *row_inc = pixinc(1 +
1948                         (y_predecim * screen_width - x_predecim * width) +
1949                         (fieldmode ? screen_width : 0), ps);
1950                 *pix_inc = pixinc(x_predecim, ps);
1951                 break;
1952
1953         case OMAP_DSS_ROT_0 + 4:
1954         case OMAP_DSS_ROT_180 + 4:
1955                 /* If the pixel format is YUV or UYVY divide the width
1956                  * of the image by 2  for 0 degree and 180 degree
1957                  */
1958                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1959                         color_mode == OMAP_DSS_COLOR_UYVY)
1960                         width = width >> 1;
1961         case OMAP_DSS_ROT_90 + 4:
1962         case OMAP_DSS_ROT_270 + 4:
1963                 *offset1 = 0;
1964                 if (field_offset)
1965                         *offset0 = field_offset * screen_width * ps;
1966                 else
1967                         *offset0 = 0;
1968                 *row_inc = pixinc(1 -
1969                         (y_predecim * screen_width + x_predecim * width) -
1970                         (fieldmode ? screen_width : 0), ps);
1971                 *pix_inc = pixinc(x_predecim, ps);
1972                 break;
1973
1974         default:
1975                 BUG();
1976                 return;
1977         }
1978 }
1979
1980 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1981                 u16 screen_width,
1982                 u16 width, u16 height,
1983                 enum omap_color_mode color_mode, bool fieldmode,
1984                 unsigned int field_offset,
1985                 unsigned *offset0, unsigned *offset1,
1986                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1987 {
1988         u8 ps;
1989         u16 fbw, fbh;
1990
1991         /* FIXME CLUT formats */
1992         switch (color_mode) {
1993         case OMAP_DSS_COLOR_CLUT1:
1994         case OMAP_DSS_COLOR_CLUT2:
1995         case OMAP_DSS_COLOR_CLUT4:
1996         case OMAP_DSS_COLOR_CLUT8:
1997                 BUG();
1998                 return;
1999         default:
2000                 ps = color_mode_to_bpp(color_mode) / 8;
2001                 break;
2002         }
2003
2004         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
2005                         width, height);
2006
2007         /* width & height are overlay sizes, convert to fb sizes */
2008
2009         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
2010                 fbw = width;
2011                 fbh = height;
2012         } else {
2013                 fbw = height;
2014                 fbh = width;
2015         }
2016
2017         /*
2018          * field 0 = even field = bottom field
2019          * field 1 = odd field = top field
2020          */
2021         switch (rotation + mirror * 4) {
2022         case OMAP_DSS_ROT_0:
2023                 *offset1 = 0;
2024                 if (field_offset)
2025                         *offset0 = *offset1 + field_offset * screen_width * ps;
2026                 else
2027                         *offset0 = *offset1;
2028                 *row_inc = pixinc(1 +
2029                         (y_predecim * screen_width - fbw * x_predecim) +
2030                         (fieldmode ? screen_width : 0), ps);
2031                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2032                         color_mode == OMAP_DSS_COLOR_UYVY)
2033                         *pix_inc = pixinc(x_predecim, 2 * ps);
2034                 else
2035                         *pix_inc = pixinc(x_predecim, ps);
2036                 break;
2037         case OMAP_DSS_ROT_90:
2038                 *offset1 = screen_width * (fbh - 1) * ps;
2039                 if (field_offset)
2040                         *offset0 = *offset1 + field_offset * ps;
2041                 else
2042                         *offset0 = *offset1;
2043                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
2044                                 y_predecim + (fieldmode ? 1 : 0), ps);
2045                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2046                 break;
2047         case OMAP_DSS_ROT_180:
2048                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2049                 if (field_offset)
2050                         *offset0 = *offset1 - field_offset * screen_width * ps;
2051                 else
2052                         *offset0 = *offset1;
2053                 *row_inc = pixinc(-1 -
2054                         (y_predecim * screen_width - fbw * x_predecim) -
2055                         (fieldmode ? screen_width : 0), ps);
2056                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2057                         color_mode == OMAP_DSS_COLOR_UYVY)
2058                         *pix_inc = pixinc(-x_predecim, 2 * ps);
2059                 else
2060                         *pix_inc = pixinc(-x_predecim, ps);
2061                 break;
2062         case OMAP_DSS_ROT_270:
2063                 *offset1 = (fbw - 1) * ps;
2064                 if (field_offset)
2065                         *offset0 = *offset1 - field_offset * ps;
2066                 else
2067                         *offset0 = *offset1;
2068                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
2069                                 y_predecim - (fieldmode ? 1 : 0), ps);
2070                 *pix_inc = pixinc(x_predecim * screen_width, ps);
2071                 break;
2072
2073         /* mirroring */
2074         case OMAP_DSS_ROT_0 + 4:
2075                 *offset1 = (fbw - 1) * ps;
2076                 if (field_offset)
2077                         *offset0 = *offset1 + field_offset * screen_width * ps;
2078                 else
2079                         *offset0 = *offset1;
2080                 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
2081                                 (fieldmode ? screen_width : 0),
2082                                 ps);
2083                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2084                         color_mode == OMAP_DSS_COLOR_UYVY)
2085                         *pix_inc = pixinc(-x_predecim, 2 * ps);
2086                 else
2087                         *pix_inc = pixinc(-x_predecim, ps);
2088                 break;
2089
2090         case OMAP_DSS_ROT_90 + 4:
2091                 *offset1 = 0;
2092                 if (field_offset)
2093                         *offset0 = *offset1 + field_offset * ps;
2094                 else
2095                         *offset0 = *offset1;
2096                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2097                                 y_predecim + (fieldmode ? 1 : 0),
2098                                 ps);
2099                 *pix_inc = pixinc(x_predecim * screen_width, ps);
2100                 break;
2101
2102         case OMAP_DSS_ROT_180 + 4:
2103                 *offset1 = screen_width * (fbh - 1) * ps;
2104                 if (field_offset)
2105                         *offset0 = *offset1 - field_offset * screen_width * ps;
2106                 else
2107                         *offset0 = *offset1;
2108                 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
2109                                 (fieldmode ? screen_width : 0),
2110                                 ps);
2111                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2112                         color_mode == OMAP_DSS_COLOR_UYVY)
2113                         *pix_inc = pixinc(x_predecim, 2 * ps);
2114                 else
2115                         *pix_inc = pixinc(x_predecim, ps);
2116                 break;
2117
2118         case OMAP_DSS_ROT_270 + 4:
2119                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2120                 if (field_offset)
2121                         *offset0 = *offset1 - field_offset * ps;
2122                 else
2123                         *offset0 = *offset1;
2124                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2125                                 y_predecim - (fieldmode ? 1 : 0),
2126                                 ps);
2127                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2128                 break;
2129
2130         default:
2131                 BUG();
2132                 return;
2133         }
2134 }
2135
2136 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2137                 enum omap_color_mode color_mode, bool fieldmode,
2138                 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2139                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2140 {
2141         u8 ps;
2142
2143         switch (color_mode) {
2144         case OMAP_DSS_COLOR_CLUT1:
2145         case OMAP_DSS_COLOR_CLUT2:
2146         case OMAP_DSS_COLOR_CLUT4:
2147         case OMAP_DSS_COLOR_CLUT8:
2148                 BUG();
2149                 return;
2150         default:
2151                 ps = color_mode_to_bpp(color_mode) / 8;
2152                 break;
2153         }
2154
2155         DSSDBG("scrw %d, width %d\n", screen_width, width);
2156
2157         /*
2158          * field 0 = even field = bottom field
2159          * field 1 = odd field = top field
2160          */
2161         *offset1 = 0;
2162         if (field_offset)
2163                 *offset0 = *offset1 + field_offset * screen_width * ps;
2164         else
2165                 *offset0 = *offset1;
2166         *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2167                         (fieldmode ? screen_width : 0), ps);
2168         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2169                 color_mode == OMAP_DSS_COLOR_UYVY)
2170                 *pix_inc = pixinc(x_predecim, 2 * ps);
2171         else
2172                 *pix_inc = pixinc(x_predecim, ps);
2173 }
2174
2175 /*
2176  * This function is used to avoid synclosts in OMAP3, because of some
2177  * undocumented horizontal position and timing related limitations.
2178  */
2179 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2180                 const struct omap_video_timings *t, u16 pos_x,
2181                 u16 width, u16 height, u16 out_width, u16 out_height,
2182                 bool five_taps)
2183 {
2184         const int ds = DIV_ROUND_UP(height, out_height);
2185         unsigned long nonactive;
2186         static const u8 limits[3] = { 8, 10, 20 };
2187         u64 val, blank;
2188         int i;
2189
2190         nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2191
2192         i = 0;
2193         if (out_height < height)
2194                 i++;
2195         if (out_width < width)
2196                 i++;
2197         blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2198         DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2199         if (blank <= limits[i])
2200                 return -EINVAL;
2201
2202         /* FIXME add checks for 3-tap filter once the limitations are known */
2203         if (!five_taps)
2204                 return 0;
2205
2206         /*
2207          * Pixel data should be prepared before visible display point starts.
2208          * So, atleast DS-2 lines must have already been fetched by DISPC
2209          * during nonactive - pos_x period.
2210          */
2211         val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2212         DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2213                 val, max(0, ds - 2) * width);
2214         if (val < max(0, ds - 2) * width)
2215                 return -EINVAL;
2216
2217         /*
2218          * All lines need to be refilled during the nonactive period of which
2219          * only one line can be loaded during the active period. So, atleast
2220          * DS - 1 lines should be loaded during nonactive period.
2221          */
2222         val =  div_u64((u64)nonactive * lclk, pclk);
2223         DSSDBG("nonactive * pcd  = %llu, max(0, DS - 1) * width = %d\n",
2224                 val, max(0, ds - 1) * width);
2225         if (val < max(0, ds - 1) * width)
2226                 return -EINVAL;
2227
2228         return 0;
2229 }
2230
2231 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2232                 const struct omap_video_timings *mgr_timings, u16 width,
2233                 u16 height, u16 out_width, u16 out_height,
2234                 enum omap_color_mode color_mode)
2235 {
2236         u32 core_clk = 0;
2237         u64 tmp;
2238
2239         if (height <= out_height && width <= out_width)
2240                 return (unsigned long) pclk;
2241
2242         if (height > out_height) {
2243                 unsigned int ppl = mgr_timings->x_res;
2244
2245                 tmp = (u64)pclk * height * out_width;
2246                 do_div(tmp, 2 * out_height * ppl);
2247                 core_clk = tmp;
2248
2249                 if (height > 2 * out_height) {
2250                         if (ppl == out_width)
2251                                 return 0;
2252
2253                         tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2254                         do_div(tmp, 2 * out_height * (ppl - out_width));
2255                         core_clk = max_t(u32, core_clk, tmp);
2256                 }
2257         }
2258
2259         if (width > out_width) {
2260                 tmp = (u64)pclk * width;
2261                 do_div(tmp, out_width);
2262                 core_clk = max_t(u32, core_clk, tmp);
2263
2264                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2265                         core_clk <<= 1;
2266         }
2267
2268         return core_clk;
2269 }
2270
2271 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2272                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2273 {
2274         if (height > out_height && width > out_width)
2275                 return pclk * 4;
2276         else
2277                 return pclk * 2;
2278 }
2279
2280 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2281                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2282 {
2283         unsigned int hf, vf;
2284
2285         /*
2286          * FIXME how to determine the 'A' factor
2287          * for the no downscaling case ?
2288          */
2289
2290         if (width > 3 * out_width)
2291                 hf = 4;
2292         else if (width > 2 * out_width)
2293                 hf = 3;
2294         else if (width > out_width)
2295                 hf = 2;
2296         else
2297                 hf = 1;
2298         if (height > out_height)
2299                 vf = 2;
2300         else
2301                 vf = 1;
2302
2303         return pclk * vf * hf;
2304 }
2305
2306 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2307                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2308 {
2309         /*
2310          * If the overlay/writeback is in mem to mem mode, there are no
2311          * downscaling limitations with respect to pixel clock, return 1 as
2312          * required core clock to represent that we have sufficient enough
2313          * core clock to do maximum downscaling
2314          */
2315         if (mem_to_mem)
2316                 return 1;
2317
2318         if (width > out_width)
2319                 return DIV_ROUND_UP(pclk, out_width) * width;
2320         else
2321                 return pclk;
2322 }
2323
2324 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2325                 const struct omap_video_timings *mgr_timings,
2326                 u16 width, u16 height, u16 out_width, u16 out_height,
2327                 enum omap_color_mode color_mode, bool *five_taps,
2328                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2329                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2330 {
2331         int error;
2332         u16 in_width, in_height;
2333         int min_factor = min(*decim_x, *decim_y);
2334         const int maxsinglelinewidth =
2335                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2336
2337         *five_taps = false;
2338
2339         do {
2340                 in_height = height / *decim_y;
2341                 in_width = width / *decim_x;
2342                 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2343                                 in_height, out_width, out_height, mem_to_mem);
2344                 error = (in_width > maxsinglelinewidth || !*core_clk ||
2345                         *core_clk > dispc_core_clk_rate());
2346                 if (error) {
2347                         if (*decim_x == *decim_y) {
2348                                 *decim_x = min_factor;
2349                                 ++*decim_y;
2350                         } else {
2351                                 swap(*decim_x, *decim_y);
2352                                 if (*decim_x < *decim_y)
2353                                         ++*decim_x;
2354                         }
2355                 }
2356         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2357
2358         if (error) {
2359                 DSSERR("failed to find scaling settings\n");
2360                 return -EINVAL;
2361         }
2362
2363         if (in_width > maxsinglelinewidth) {
2364                 DSSERR("Cannot scale max input width exceeded");
2365                 return -EINVAL;
2366         }
2367         return 0;
2368 }
2369
2370 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2371                 const struct omap_video_timings *mgr_timings,
2372                 u16 width, u16 height, u16 out_width, u16 out_height,
2373                 enum omap_color_mode color_mode, bool *five_taps,
2374                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2375                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2376 {
2377         int error;
2378         u16 in_width, in_height;
2379         const int maxsinglelinewidth =
2380                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2381
2382         do {
2383                 in_height = height / *decim_y;
2384                 in_width = width / *decim_x;
2385                 *five_taps = in_height > out_height;
2386
2387                 if (in_width > maxsinglelinewidth)
2388                         if (in_height > out_height &&
2389                                                 in_height < out_height * 2)
2390                                 *five_taps = false;
2391 again:
2392                 if (*five_taps)
2393                         *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2394                                                 in_width, in_height, out_width,
2395                                                 out_height, color_mode);
2396                 else
2397                         *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2398                                         in_height, out_width, out_height,
2399                                         mem_to_mem);
2400
2401                 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2402                                 pos_x, in_width, in_height, out_width,
2403                                 out_height, *five_taps);
2404                 if (error && *five_taps) {
2405                         *five_taps = false;
2406                         goto again;
2407                 }
2408
2409                 error = (error || in_width > maxsinglelinewidth * 2 ||
2410                         (in_width > maxsinglelinewidth && *five_taps) ||
2411                         !*core_clk || *core_clk > dispc_core_clk_rate());
2412
2413                 if (!error) {
2414                         /* verify that we're inside the limits of scaler */
2415                         if (in_width / 4 > out_width)
2416                                         error = 1;
2417
2418                         if (*five_taps) {
2419                                 if (in_height / 4 > out_height)
2420                                         error = 1;
2421                         } else {
2422                                 if (in_height / 2 > out_height)
2423                                         error = 1;
2424                         }
2425                 }
2426
2427                 if (error)
2428                         ++*decim_y;
2429         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2430
2431         if (error) {
2432                 DSSERR("failed to find scaling settings\n");
2433                 return -EINVAL;
2434         }
2435
2436         if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2437                                 in_height, out_width, out_height, *five_taps)) {
2438                         DSSERR("horizontal timing too tight\n");
2439                         return -EINVAL;
2440         }
2441
2442         if (in_width > (maxsinglelinewidth * 2)) {
2443                 DSSERR("Cannot setup scaling");
2444                 DSSERR("width exceeds maximum width possible");
2445                 return -EINVAL;
2446         }
2447
2448         if (in_width > maxsinglelinewidth && *five_taps) {
2449                 DSSERR("cannot setup scaling with five taps");
2450                 return -EINVAL;
2451         }
2452         return 0;
2453 }
2454
2455 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2456                 const struct omap_video_timings *mgr_timings,
2457                 u16 width, u16 height, u16 out_width, u16 out_height,
2458                 enum omap_color_mode color_mode, bool *five_taps,
2459                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2460                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2461 {
2462         u16 in_width, in_width_max;
2463         int decim_x_min = *decim_x;
2464         u16 in_height = height / *decim_y;
2465         const int maxsinglelinewidth =
2466                                 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2467         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2468
2469         if (mem_to_mem) {
2470                 in_width_max = out_width * maxdownscale;
2471         } else {
2472                 in_width_max = dispc_core_clk_rate() /
2473                                         DIV_ROUND_UP(pclk, out_width);
2474         }
2475
2476         *decim_x = DIV_ROUND_UP(width, in_width_max);
2477
2478         *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2479         if (*decim_x > *x_predecim)
2480                 return -EINVAL;
2481
2482         do {
2483                 in_width = width / *decim_x;
2484         } while (*decim_x <= *x_predecim &&
2485                         in_width > maxsinglelinewidth && ++*decim_x);
2486
2487         if (in_width > maxsinglelinewidth) {
2488                 DSSERR("Cannot scale width exceeds max line width");
2489                 return -EINVAL;
2490         }
2491
2492         *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2493                                 out_width, out_height, mem_to_mem);
2494         return 0;
2495 }
2496
2497 #define DIV_FRAC(dividend, divisor) \
2498         ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2499
2500 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2501                 enum omap_overlay_caps caps,
2502                 const struct omap_video_timings *mgr_timings,
2503                 u16 width, u16 height, u16 out_width, u16 out_height,
2504                 enum omap_color_mode color_mode, bool *five_taps,
2505                 int *x_predecim, int *y_predecim, u16 pos_x,
2506                 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2507 {
2508         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2509         const int max_decim_limit = 16;
2510         unsigned long core_clk = 0;
2511         int decim_x, decim_y, ret;
2512
2513         if (width == out_width && height == out_height)
2514                 return 0;
2515
2516         if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) {
2517                 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2518                 return -EINVAL;
2519         }
2520
2521         if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2522                 return -EINVAL;
2523
2524         if (mem_to_mem) {
2525                 *x_predecim = *y_predecim = 1;
2526         } else {
2527                 *x_predecim = max_decim_limit;
2528                 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2529                                 dss_has_feature(FEAT_BURST_2D)) ?
2530                                 2 : max_decim_limit;
2531         }
2532
2533         if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2534             color_mode == OMAP_DSS_COLOR_CLUT2 ||
2535             color_mode == OMAP_DSS_COLOR_CLUT4 ||
2536             color_mode == OMAP_DSS_COLOR_CLUT8) {
2537                 *x_predecim = 1;
2538                 *y_predecim = 1;
2539                 *five_taps = false;
2540                 return 0;
2541         }
2542
2543         decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2544         decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2545
2546         if (decim_x > *x_predecim || out_width > width * 8)
2547                 return -EINVAL;
2548
2549         if (decim_y > *y_predecim || out_height > height * 8)
2550                 return -EINVAL;
2551
2552         ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2553                 out_width, out_height, color_mode, five_taps,
2554                 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2555                 mem_to_mem);
2556         if (ret)
2557                 return ret;
2558
2559         DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2560                 width, height,
2561                 out_width, out_height,
2562                 out_width / width, DIV_FRAC(out_width, width),
2563                 out_height / height, DIV_FRAC(out_height, height),
2564
2565                 decim_x, decim_y,
2566                 width / decim_x, height / decim_y,
2567                 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2568                 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2569
2570                 *five_taps ? 5 : 3,
2571                 core_clk, dispc_core_clk_rate());
2572
2573         if (!core_clk || core_clk > dispc_core_clk_rate()) {
2574                 DSSERR("failed to set up scaling, "
2575                         "required core clk rate = %lu Hz, "
2576                         "current core clk rate = %lu Hz\n",
2577                         core_clk, dispc_core_clk_rate());
2578                 return -EINVAL;
2579         }
2580
2581         *x_predecim = decim_x;
2582         *y_predecim = decim_y;
2583         return 0;
2584 }
2585
2586 static int dispc_ovl_setup_common(enum omap_plane plane,
2587                 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2588                 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2589                 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2590                 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2591                 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2592                 bool replication, const struct omap_video_timings *mgr_timings,
2593                 bool mem_to_mem)
2594 {
2595         bool five_taps = true;
2596         bool fieldmode = false;
2597         int r, cconv = 0;
2598         unsigned offset0, offset1;
2599         s32 row_inc;
2600         s32 pix_inc;
2601         u16 frame_width, frame_height;
2602         unsigned int field_offset = 0;
2603         u16 in_height = height;
2604         u16 in_width = width;
2605         int x_predecim = 1, y_predecim = 1;
2606         bool ilace = mgr_timings->interlace;
2607         unsigned long pclk = dispc_plane_pclk_rate(plane);
2608         unsigned long lclk = dispc_plane_lclk_rate(plane);
2609
2610         if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2611                 return -EINVAL;
2612
2613         switch (color_mode) {
2614         case OMAP_DSS_COLOR_YUV2:
2615         case OMAP_DSS_COLOR_UYVY:
2616         case OMAP_DSS_COLOR_NV12:
2617                 if (in_width & 1) {
2618                         DSSERR("input width %d is not even for YUV format\n",
2619                                 in_width);
2620                         return -EINVAL;
2621                 }
2622                 break;
2623
2624         default:
2625                 break;
2626         }
2627
2628         out_width = out_width == 0 ? width : out_width;
2629         out_height = out_height == 0 ? height : out_height;
2630
2631         if (ilace && height == out_height)
2632                 fieldmode = true;
2633
2634         if (ilace) {
2635                 if (fieldmode)
2636                         in_height /= 2;
2637                 pos_y /= 2;
2638                 out_height /= 2;
2639
2640                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2641                         "out_height %d\n", in_height, pos_y,
2642                         out_height);
2643         }
2644
2645         if (!dss_feat_color_mode_supported(plane, color_mode))
2646                 return -EINVAL;
2647
2648         r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2649                         in_height, out_width, out_height, color_mode,
2650                         &five_taps, &x_predecim, &y_predecim, pos_x,
2651                         rotation_type, mem_to_mem);
2652         if (r)
2653                 return r;
2654
2655         in_width = in_width / x_predecim;
2656         in_height = in_height / y_predecim;
2657
2658         if (x_predecim > 1 || y_predecim > 1)
2659                 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2660                         x_predecim, y_predecim, in_width, in_height);
2661
2662         switch (color_mode) {
2663         case OMAP_DSS_COLOR_YUV2:
2664         case OMAP_DSS_COLOR_UYVY:
2665         case OMAP_DSS_COLOR_NV12:
2666                 if (in_width & 1) {
2667                         DSSDBG("predecimated input width is not even for YUV format\n");
2668                         DSSDBG("adjusting input width %d -> %d\n",
2669                                 in_width, in_width & ~1);
2670
2671                         in_width &= ~1;
2672                 }
2673                 break;
2674
2675         default:
2676                 break;
2677         }
2678
2679         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2680                         color_mode == OMAP_DSS_COLOR_UYVY ||
2681                         color_mode == OMAP_DSS_COLOR_NV12)
2682                 cconv = 1;
2683
2684         if (ilace && !fieldmode) {
2685                 /*
2686                  * when downscaling the bottom field may have to start several
2687                  * source lines below the top field. Unfortunately ACCUI
2688                  * registers will only hold the fractional part of the offset
2689                  * so the integer part must be added to the base address of the
2690                  * bottom field.
2691                  */
2692                 if (!in_height || in_height == out_height)
2693                         field_offset = 0;
2694                 else
2695                         field_offset = in_height / out_height / 2;
2696         }
2697
2698         /* Fields are independent but interleaved in memory. */
2699         if (fieldmode)
2700                 field_offset = 1;
2701
2702         offset0 = 0;
2703         offset1 = 0;
2704         row_inc = 0;
2705         pix_inc = 0;
2706
2707         if (plane == OMAP_DSS_WB) {
2708                 frame_width = out_width;
2709                 frame_height = out_height;
2710         } else {
2711                 frame_width = in_width;
2712                 frame_height = height;
2713         }
2714
2715         if (rotation_type == OMAP_DSS_ROT_TILER)
2716                 calc_tiler_rotation_offset(screen_width, frame_width,
2717                                 color_mode, fieldmode, field_offset,
2718                                 &offset0, &offset1, &row_inc, &pix_inc,
2719                                 x_predecim, y_predecim);
2720         else if (rotation_type == OMAP_DSS_ROT_DMA)
2721                 calc_dma_rotation_offset(rotation, mirror, screen_width,
2722                                 frame_width, frame_height,
2723                                 color_mode, fieldmode, field_offset,
2724                                 &offset0, &offset1, &row_inc, &pix_inc,
2725                                 x_predecim, y_predecim);
2726         else
2727                 calc_vrfb_rotation_offset(rotation, mirror,
2728                                 screen_width, frame_width, frame_height,
2729                                 color_mode, fieldmode, field_offset,
2730                                 &offset0, &offset1, &row_inc, &pix_inc,
2731                                 x_predecim, y_predecim);
2732
2733         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2734                         offset0, offset1, row_inc, pix_inc);
2735
2736         dispc_ovl_set_color_mode(plane, color_mode);
2737
2738         dispc_ovl_configure_burst_type(plane, rotation_type);
2739
2740         if (dispc.feat->reverse_ilace_field_order)
2741                 swap(offset0, offset1);
2742
2743         dispc_ovl_set_ba0(plane, paddr + offset0);
2744         dispc_ovl_set_ba1(plane, paddr + offset1);
2745
2746         if (OMAP_DSS_COLOR_NV12 == color_mode) {
2747                 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2748                 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2749         }
2750
2751         if (dispc.feat->last_pixel_inc_missing)
2752                 row_inc += pix_inc - 1;
2753
2754         dispc_ovl_set_row_inc(plane, row_inc);
2755         dispc_ovl_set_pix_inc(plane, pix_inc);
2756
2757         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2758                         in_height, out_width, out_height);
2759
2760         dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2761
2762         dispc_ovl_set_input_size(plane, in_width, in_height);
2763
2764         if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2765                 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2766                                    out_height, ilace, five_taps, fieldmode,
2767                                    color_mode, rotation);
2768                 dispc_ovl_set_output_size(plane, out_width, out_height);
2769                 dispc_ovl_set_vid_color_conv(plane, cconv);
2770         }
2771
2772         dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2773                         color_mode);
2774
2775         dispc_ovl_set_zorder(plane, caps, zorder);
2776         dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2777         dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2778
2779         dispc_ovl_enable_replication(plane, caps, replication);
2780
2781         return 0;
2782 }
2783
2784 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2785                 bool replication, const struct omap_video_timings *mgr_timings,
2786                 bool mem_to_mem)
2787 {
2788         int r;
2789         enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2790         enum omap_channel channel;
2791
2792         channel = dispc_ovl_get_channel_out(plane);
2793
2794         DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2795                 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2796                 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2797                 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2798                 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2799
2800         r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2801                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2802                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2803                 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2804                 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2805
2806         return r;
2807 }
2808 EXPORT_SYMBOL(dispc_ovl_setup);
2809
2810 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2811                 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2812 {
2813         int r;
2814         u32 l;
2815         enum omap_plane plane = OMAP_DSS_WB;
2816         const int pos_x = 0, pos_y = 0;
2817         const u8 zorder = 0, global_alpha = 0;
2818         const bool replication = false;
2819         bool truncation;
2820         int in_width = mgr_timings->x_res;
2821         int in_height = mgr_timings->y_res;
2822         enum omap_overlay_caps caps =
2823                 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2824
2825         DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2826                 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2827                 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2828                 wi->mirror);
2829
2830         r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2831                 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2832                 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2833                 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2834                 replication, mgr_timings, mem_to_mem);
2835
2836         switch (wi->color_mode) {
2837         case OMAP_DSS_COLOR_RGB16:
2838         case OMAP_DSS_COLOR_RGB24P:
2839         case OMAP_DSS_COLOR_ARGB16:
2840         case OMAP_DSS_COLOR_RGBA16:
2841         case OMAP_DSS_COLOR_RGB12U:
2842         case OMAP_DSS_COLOR_ARGB16_1555:
2843         case OMAP_DSS_COLOR_XRGB16_1555:
2844         case OMAP_DSS_COLOR_RGBX16:
2845                 truncation = true;
2846                 break;
2847         default:
2848                 truncation = false;
2849                 break;
2850         }
2851
2852         /* setup extra DISPC_WB_ATTRIBUTES */
2853         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2854         l = FLD_MOD(l, truncation, 10, 10);     /* TRUNCATIONENABLE */
2855         l = FLD_MOD(l, mem_to_mem, 19, 19);     /* WRITEBACKMODE */
2856         if (mem_to_mem)
2857                 l = FLD_MOD(l, 1, 26, 24);      /* CAPTUREMODE */
2858         else
2859                 l = FLD_MOD(l, 0, 26, 24);      /* CAPTUREMODE */
2860         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2861
2862         if (mem_to_mem) {
2863                 /* WBDELAYCOUNT */
2864                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2865         } else {
2866                 int wbdelay;
2867
2868                 wbdelay = min(mgr_timings->vfp + mgr_timings->vsw +
2869                         mgr_timings->vbp, 255);
2870
2871                 /* WBDELAYCOUNT */
2872                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2873         }
2874
2875         return r;
2876 }
2877
2878 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2879 {
2880         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2881
2882         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2883
2884         return 0;
2885 }
2886 EXPORT_SYMBOL(dispc_ovl_enable);
2887
2888 bool dispc_ovl_enabled(enum omap_plane plane)
2889 {
2890         return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2891 }
2892 EXPORT_SYMBOL(dispc_ovl_enabled);
2893
2894 enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel)
2895 {
2896         return dss_feat_get_supported_outputs(channel);
2897 }
2898 EXPORT_SYMBOL(dispc_mgr_get_supported_outputs);
2899
2900 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2901 {
2902         mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2903         /* flush posted write */
2904         mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2905 }
2906 EXPORT_SYMBOL(dispc_mgr_enable);
2907
2908 bool dispc_mgr_is_enabled(enum omap_channel channel)
2909 {
2910         return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2911 }
2912 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2913
2914 void dispc_wb_enable(bool enable)
2915 {
2916         dispc_ovl_enable(OMAP_DSS_WB, enable);
2917 }
2918
2919 bool dispc_wb_is_enabled(void)
2920 {
2921         return dispc_ovl_enabled(OMAP_DSS_WB);
2922 }
2923
2924 static void dispc_lcd_enable_signal_polarity(bool act_high)
2925 {
2926         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2927                 return;
2928
2929         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2930 }
2931
2932 void dispc_lcd_enable_signal(bool enable)
2933 {
2934         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2935                 return;
2936
2937         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2938 }
2939
2940 void dispc_pck_free_enable(bool enable)
2941 {
2942         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2943                 return;
2944
2945         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2946 }
2947
2948 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2949 {
2950         mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2951 }
2952
2953
2954 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2955 {
2956         mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2957 }
2958
2959 static void dispc_set_loadmode(enum omap_dss_load_mode mode)
2960 {
2961         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2962 }
2963
2964
2965 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2966 {
2967         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2968 }
2969
2970 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2971                 enum omap_dss_trans_key_type type,
2972                 u32 trans_key)
2973 {
2974         mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2975
2976         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2977 }
2978
2979 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2980 {
2981         mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2982 }
2983
2984 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2985                 bool enable)
2986 {
2987         if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2988                 return;
2989
2990         if (ch == OMAP_DSS_CHANNEL_LCD)
2991                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2992         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2993                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2994 }
2995
2996 void dispc_mgr_setup(enum omap_channel channel,
2997                 const struct omap_overlay_manager_info *info)
2998 {
2999         dispc_mgr_set_default_color(channel, info->default_color);
3000         dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
3001         dispc_mgr_enable_trans_key(channel, info->trans_enabled);
3002         dispc_mgr_enable_alpha_fixed_zorder(channel,
3003                         info->partial_alpha_enabled);
3004         if (dss_has_feature(FEAT_CPR)) {
3005                 dispc_mgr_enable_cpr(channel, info->cpr_enable);
3006                 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
3007         }
3008 }
3009 EXPORT_SYMBOL(dispc_mgr_setup);
3010
3011 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
3012 {
3013         int code;
3014
3015         switch (data_lines) {
3016         case 12:
3017                 code = 0;
3018                 break;
3019         case 16:
3020                 code = 1;
3021                 break;
3022         case 18:
3023                 code = 2;
3024                 break;
3025         case 24:
3026                 code = 3;
3027                 break;
3028         default:
3029                 BUG();
3030                 return;
3031         }
3032
3033         mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
3034 }
3035
3036 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
3037 {
3038         u32 l;
3039         int gpout0, gpout1;
3040
3041         switch (mode) {
3042         case DSS_IO_PAD_MODE_RESET:
3043                 gpout0 = 0;
3044                 gpout1 = 0;
3045                 break;
3046         case DSS_IO_PAD_MODE_RFBI:
3047                 gpout0 = 1;
3048                 gpout1 = 0;
3049                 break;
3050         case DSS_IO_PAD_MODE_BYPASS:
3051                 gpout0 = 1;
3052                 gpout1 = 1;
3053                 break;
3054         default:
3055                 BUG();
3056                 return;
3057         }
3058
3059         l = dispc_read_reg(DISPC_CONTROL);
3060         l = FLD_MOD(l, gpout0, 15, 15);
3061         l = FLD_MOD(l, gpout1, 16, 16);
3062         dispc_write_reg(DISPC_CONTROL, l);
3063 }
3064
3065 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
3066 {
3067         mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
3068 }
3069
3070 void dispc_mgr_set_lcd_config(enum omap_channel channel,
3071                 const struct dss_lcd_mgr_config *config)
3072 {
3073         dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3074
3075         dispc_mgr_enable_stallmode(channel, config->stallmode);
3076         dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3077
3078         dispc_mgr_set_clock_div(channel, &config->clock_info);
3079
3080         dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3081
3082         dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3083
3084         dispc_mgr_set_lcd_type_tft(channel);
3085 }
3086 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
3087
3088 static bool _dispc_mgr_size_ok(u16 width, u16 height)
3089 {
3090         return width <= dispc.feat->mgr_width_max &&
3091                 height <= dispc.feat->mgr_height_max;
3092 }
3093
3094 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
3095                 int vsw, int vfp, int vbp)
3096 {
3097         if (hsw < 1 || hsw > dispc.feat->sw_max ||
3098                         hfp < 1 || hfp > dispc.feat->hp_max ||
3099                         hbp < 1 || hbp > dispc.feat->hp_max ||
3100                         vsw < 1 || vsw > dispc.feat->sw_max ||
3101                         vfp < 0 || vfp > dispc.feat->vp_max ||
3102                         vbp < 0 || vbp > dispc.feat->vp_max)
3103                 return false;
3104         return true;
3105 }
3106
3107 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3108                 unsigned long pclk)
3109 {
3110         if (dss_mgr_is_lcd(channel))
3111                 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
3112         else
3113                 return pclk <= dispc.feat->max_tv_pclk ? true : false;
3114 }
3115
3116 bool dispc_mgr_timings_ok(enum omap_channel channel,
3117                 const struct omap_video_timings *timings)
3118 {
3119         if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3120                 return false;
3121
3122         if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3123                 return false;
3124
3125         if (dss_mgr_is_lcd(channel)) {
3126                 /* TODO: OMAP4+ supports interlace for LCD outputs */
3127                 if (timings->interlace)
3128                         return false;
3129
3130                 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
3131                                 timings->hbp, timings->vsw, timings->vfp,
3132                                 timings->vbp))
3133                         return false;
3134         }
3135
3136         return true;
3137 }
3138
3139 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
3140                 int hfp, int hbp, int vsw, int vfp, int vbp,
3141                 enum omap_dss_signal_level vsync_level,
3142                 enum omap_dss_signal_level hsync_level,
3143                 enum omap_dss_signal_edge data_pclk_edge,
3144                 enum omap_dss_signal_level de_level,
3145                 enum omap_dss_signal_edge sync_pclk_edge)
3146
3147 {
3148         u32 timing_h, timing_v, l;
3149         bool onoff, rf, ipc, vs, hs, de;
3150
3151         timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3152                         FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3153                         FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3154         timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3155                         FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3156                         FLD_VAL(vbp, dispc.feat->bp_start, 20);
3157
3158         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3159         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3160
3161         switch (vsync_level) {
3162         case OMAPDSS_SIG_ACTIVE_LOW:
3163                 vs = true;
3164                 break;
3165         case OMAPDSS_SIG_ACTIVE_HIGH:
3166                 vs = false;
3167                 break;
3168         default:
3169                 BUG();
3170         }
3171
3172         switch (hsync_level) {
3173         case OMAPDSS_SIG_ACTIVE_LOW:
3174                 hs = true;
3175                 break;
3176         case OMAPDSS_SIG_ACTIVE_HIGH:
3177                 hs = false;
3178                 break;
3179         default:
3180                 BUG();
3181         }
3182
3183         switch (de_level) {
3184         case OMAPDSS_SIG_ACTIVE_LOW:
3185                 de = true;
3186                 break;
3187         case OMAPDSS_SIG_ACTIVE_HIGH:
3188                 de = false;
3189                 break;
3190         default:
3191                 BUG();
3192         }
3193
3194         switch (data_pclk_edge) {
3195         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3196                 ipc = false;
3197                 break;
3198         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3199                 ipc = true;
3200                 break;
3201         default:
3202                 BUG();
3203         }
3204
3205         /* always use the 'rf' setting */
3206         onoff = true;
3207
3208         switch (sync_pclk_edge) {
3209         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3210                 rf = false;
3211                 break;
3212         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3213                 rf = true;
3214                 break;
3215         default:
3216                 BUG();
3217         }
3218
3219         l = FLD_VAL(onoff, 17, 17) |
3220                 FLD_VAL(rf, 16, 16) |
3221                 FLD_VAL(de, 15, 15) |
3222                 FLD_VAL(ipc, 14, 14) |
3223                 FLD_VAL(hs, 13, 13) |
3224                 FLD_VAL(vs, 12, 12);
3225
3226         /* always set ALIGN bit when available */
3227         if (dispc.feat->supports_sync_align)
3228                 l |= (1 << 18);
3229
3230         dispc_write_reg(DISPC_POL_FREQ(channel), l);
3231
3232         if (dispc.syscon_pol) {
3233                 const int shifts[] = {
3234                         [OMAP_DSS_CHANNEL_LCD] = 0,
3235                         [OMAP_DSS_CHANNEL_LCD2] = 1,
3236                         [OMAP_DSS_CHANNEL_LCD3] = 2,
3237                 };
3238
3239                 u32 mask, val;
3240
3241                 mask = (1 << 0) | (1 << 3) | (1 << 6);
3242                 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3243
3244                 mask <<= 16 + shifts[channel];
3245                 val <<= 16 + shifts[channel];
3246
3247                 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3248                         mask, val);
3249         }
3250 }
3251
3252 /* change name to mode? */
3253 void dispc_mgr_set_timings(enum omap_channel channel,
3254                 const struct omap_video_timings *timings)
3255 {
3256         unsigned xtot, ytot;
3257         unsigned long ht, vt;
3258         struct omap_video_timings t = *timings;
3259
3260         DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
3261
3262         if (!dispc_mgr_timings_ok(channel, &t)) {
3263                 BUG();
3264                 return;
3265         }
3266
3267         if (dss_mgr_is_lcd(channel)) {
3268                 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3269                                 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3270                                 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3271
3272                 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3273                 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3274
3275                 ht = timings->pixelclock / xtot;
3276                 vt = timings->pixelclock / xtot / ytot;
3277
3278                 DSSDBG("pck %u\n", timings->pixelclock);
3279                 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3280                         t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3281                 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3282                         t.vsync_level, t.hsync_level, t.data_pclk_edge,
3283                         t.de_level, t.sync_pclk_edge);
3284
3285                 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3286         } else {
3287                 if (t.interlace)
3288                         t.y_res /= 2;
3289
3290                 if (dispc.feat->supports_double_pixel)
3291                         REG_FLD_MOD(DISPC_CONTROL, t.double_pixel ? 1 : 0,
3292                                 19, 17);
3293         }
3294
3295         dispc_mgr_set_size(channel, t.x_res, t.y_res);
3296 }
3297 EXPORT_SYMBOL(dispc_mgr_set_timings);
3298
3299 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3300                 u16 pck_div)
3301 {
3302         BUG_ON(lck_div < 1);
3303         BUG_ON(pck_div < 1);
3304
3305         dispc_write_reg(DISPC_DIVISORo(channel),
3306                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3307
3308         if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
3309                         channel == OMAP_DSS_CHANNEL_LCD)
3310                 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3311 }
3312
3313 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3314                 int *pck_div)
3315 {
3316         u32 l;
3317         l = dispc_read_reg(DISPC_DIVISORo(channel));
3318         *lck_div = FLD_GET(l, 23, 16);
3319         *pck_div = FLD_GET(l, 7, 0);
3320 }
3321
3322 static unsigned long dispc_fclk_rate(void)
3323 {
3324         unsigned long r;
3325         enum dss_clk_source src;
3326
3327         src = dss_get_dispc_clk_source();
3328
3329         if (src == DSS_CLK_SRC_FCK) {
3330                 r = dss_get_dispc_clk_rate();
3331         } else {
3332                 struct dss_pll *pll;
3333                 unsigned clkout_idx;
3334
3335                 pll = dss_pll_find_by_src(src);
3336                 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
3337
3338                 r = pll->cinfo.clkout[clkout_idx];
3339         }
3340
3341         return r;
3342 }
3343
3344 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3345 {
3346         int lcd;
3347         unsigned long r;
3348         enum dss_clk_source src;
3349
3350         /* for TV, LCLK rate is the FCLK rate */
3351         if (!dss_mgr_is_lcd(channel))
3352                 return dispc_fclk_rate();
3353
3354         src = dss_get_lcd_clk_source(channel);
3355
3356         if (src == DSS_CLK_SRC_FCK) {
3357                 r = dss_get_dispc_clk_rate();
3358         } else {
3359                 struct dss_pll *pll;
3360                 unsigned clkout_idx;
3361
3362                 pll = dss_pll_find_by_src(src);
3363                 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
3364
3365                 r = pll->cinfo.clkout[clkout_idx];
3366         }
3367
3368         lcd = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3369
3370         return r / lcd;
3371 }
3372
3373 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3374 {
3375         unsigned long r;
3376
3377         if (dss_mgr_is_lcd(channel)) {
3378                 int pcd;
3379                 u32 l;
3380
3381                 l = dispc_read_reg(DISPC_DIVISORo(channel));
3382
3383                 pcd = FLD_GET(l, 7, 0);
3384
3385                 r = dispc_mgr_lclk_rate(channel);
3386
3387                 return r / pcd;
3388         } else {
3389                 return dispc.tv_pclk_rate;
3390         }
3391 }
3392
3393 void dispc_set_tv_pclk(unsigned long pclk)
3394 {
3395         dispc.tv_pclk_rate = pclk;
3396 }
3397
3398 static unsigned long dispc_core_clk_rate(void)
3399 {
3400         return dispc.core_clk_rate;
3401 }
3402
3403 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3404 {
3405         enum omap_channel channel;
3406
3407         if (plane == OMAP_DSS_WB)
3408                 return 0;
3409
3410         channel = dispc_ovl_get_channel_out(plane);
3411
3412         return dispc_mgr_pclk_rate(channel);
3413 }
3414
3415 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3416 {
3417         enum omap_channel channel;
3418
3419         if (plane == OMAP_DSS_WB)
3420                 return 0;
3421
3422         channel = dispc_ovl_get_channel_out(plane);
3423
3424         return dispc_mgr_lclk_rate(channel);
3425 }
3426
3427 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3428 {
3429         int lcd, pcd;
3430         enum dss_clk_source lcd_clk_src;
3431
3432         seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3433
3434         lcd_clk_src = dss_get_lcd_clk_source(channel);
3435
3436         seq_printf(s, "%s clk source = %s\n", mgr_desc[channel].name,
3437                 dss_get_clk_source_name(lcd_clk_src));
3438
3439         dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3440
3441         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3442                 dispc_mgr_lclk_rate(channel), lcd);
3443         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3444                 dispc_mgr_pclk_rate(channel), pcd);
3445 }
3446
3447 void dispc_dump_clocks(struct seq_file *s)
3448 {
3449         int lcd;
3450         u32 l;
3451         enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3452
3453         if (dispc_runtime_get())
3454                 return;
3455
3456         seq_printf(s, "- DISPC -\n");
3457
3458         seq_printf(s, "dispc fclk source = %s\n",
3459                         dss_get_clk_source_name(dispc_clk_src));
3460
3461         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3462
3463         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3464                 seq_printf(s, "- DISPC-CORE-CLK -\n");
3465                 l = dispc_read_reg(DISPC_DIVISOR);
3466                 lcd = FLD_GET(l, 23, 16);
3467
3468                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3469                                 (dispc_fclk_rate()/lcd), lcd);
3470         }
3471
3472         dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3473
3474         if (dss_has_feature(FEAT_MGR_LCD2))
3475                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3476         if (dss_has_feature(FEAT_MGR_LCD3))
3477                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3478
3479         dispc_runtime_put();
3480 }
3481
3482 static void dispc_dump_regs(struct seq_file *s)
3483 {
3484         int i, j;
3485         const char *mgr_names[] = {
3486                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
3487                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
3488                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
3489                 [OMAP_DSS_CHANNEL_LCD3]         = "LCD3",
3490         };
3491         const char *ovl_names[] = {
3492                 [OMAP_DSS_GFX]          = "GFX",
3493                 [OMAP_DSS_VIDEO1]       = "VID1",
3494                 [OMAP_DSS_VIDEO2]       = "VID2",
3495                 [OMAP_DSS_VIDEO3]       = "VID3",
3496                 [OMAP_DSS_WB]           = "WB",
3497         };
3498         const char **p_names;
3499
3500 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3501
3502         if (dispc_runtime_get())
3503                 return;
3504
3505         /* DISPC common registers */
3506         DUMPREG(DISPC_REVISION);
3507         DUMPREG(DISPC_SYSCONFIG);
3508         DUMPREG(DISPC_SYSSTATUS);
3509         DUMPREG(DISPC_IRQSTATUS);
3510         DUMPREG(DISPC_IRQENABLE);
3511         DUMPREG(DISPC_CONTROL);
3512         DUMPREG(DISPC_CONFIG);
3513         DUMPREG(DISPC_CAPABLE);
3514         DUMPREG(DISPC_LINE_STATUS);
3515         DUMPREG(DISPC_LINE_NUMBER);
3516         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3517                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3518                 DUMPREG(DISPC_GLOBAL_ALPHA);
3519         if (dss_has_feature(FEAT_MGR_LCD2)) {
3520                 DUMPREG(DISPC_CONTROL2);
3521                 DUMPREG(DISPC_CONFIG2);
3522         }
3523         if (dss_has_feature(FEAT_MGR_LCD3)) {
3524                 DUMPREG(DISPC_CONTROL3);
3525                 DUMPREG(DISPC_CONFIG3);
3526         }
3527         if (dss_has_feature(FEAT_MFLAG))
3528                 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3529
3530 #undef DUMPREG
3531
3532 #define DISPC_REG(i, name) name(i)
3533 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3534         (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3535         dispc_read_reg(DISPC_REG(i, r)))
3536
3537         p_names = mgr_names;
3538
3539         /* DISPC channel specific registers */
3540         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3541                 DUMPREG(i, DISPC_DEFAULT_COLOR);
3542                 DUMPREG(i, DISPC_TRANS_COLOR);
3543                 DUMPREG(i, DISPC_SIZE_MGR);
3544
3545                 if (i == OMAP_DSS_CHANNEL_DIGIT)
3546                         continue;
3547
3548                 DUMPREG(i, DISPC_TIMING_H);
3549                 DUMPREG(i, DISPC_TIMING_V);
3550                 DUMPREG(i, DISPC_POL_FREQ);
3551                 DUMPREG(i, DISPC_DIVISORo);
3552
3553                 DUMPREG(i, DISPC_DATA_CYCLE1);
3554                 DUMPREG(i, DISPC_DATA_CYCLE2);
3555                 DUMPREG(i, DISPC_DATA_CYCLE3);
3556
3557                 if (dss_has_feature(FEAT_CPR)) {
3558                         DUMPREG(i, DISPC_CPR_COEF_R);
3559                         DUMPREG(i, DISPC_CPR_COEF_G);
3560                         DUMPREG(i, DISPC_CPR_COEF_B);
3561                 }
3562         }
3563
3564         p_names = ovl_names;
3565
3566         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3567                 DUMPREG(i, DISPC_OVL_BA0);
3568                 DUMPREG(i, DISPC_OVL_BA1);
3569                 DUMPREG(i, DISPC_OVL_POSITION);
3570                 DUMPREG(i, DISPC_OVL_SIZE);
3571                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3572                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3573                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3574                 DUMPREG(i, DISPC_OVL_ROW_INC);
3575                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3576
3577                 if (dss_has_feature(FEAT_PRELOAD))
3578                         DUMPREG(i, DISPC_OVL_PRELOAD);
3579                 if (dss_has_feature(FEAT_MFLAG))
3580                         DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3581
3582                 if (i == OMAP_DSS_GFX) {
3583                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3584                         DUMPREG(i, DISPC_OVL_TABLE_BA);
3585                         continue;
3586                 }
3587
3588                 DUMPREG(i, DISPC_OVL_FIR);
3589                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3590                 DUMPREG(i, DISPC_OVL_ACCU0);
3591                 DUMPREG(i, DISPC_OVL_ACCU1);
3592                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3593                         DUMPREG(i, DISPC_OVL_BA0_UV);
3594                         DUMPREG(i, DISPC_OVL_BA1_UV);
3595                         DUMPREG(i, DISPC_OVL_FIR2);
3596                         DUMPREG(i, DISPC_OVL_ACCU2_0);
3597                         DUMPREG(i, DISPC_OVL_ACCU2_1);
3598                 }
3599                 if (dss_has_feature(FEAT_ATTR2))
3600                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3601         }
3602
3603         if (dispc.feat->has_writeback) {
3604                 i = OMAP_DSS_WB;
3605                 DUMPREG(i, DISPC_OVL_BA0);
3606                 DUMPREG(i, DISPC_OVL_BA1);
3607                 DUMPREG(i, DISPC_OVL_SIZE);
3608                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3609                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3610                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3611                 DUMPREG(i, DISPC_OVL_ROW_INC);
3612                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3613
3614                 if (dss_has_feature(FEAT_MFLAG))
3615                         DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3616
3617                 DUMPREG(i, DISPC_OVL_FIR);
3618                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3619                 DUMPREG(i, DISPC_OVL_ACCU0);
3620                 DUMPREG(i, DISPC_OVL_ACCU1);
3621                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3622                         DUMPREG(i, DISPC_OVL_BA0_UV);
3623                         DUMPREG(i, DISPC_OVL_BA1_UV);
3624                         DUMPREG(i, DISPC_OVL_FIR2);
3625                         DUMPREG(i, DISPC_OVL_ACCU2_0);
3626                         DUMPREG(i, DISPC_OVL_ACCU2_1);
3627                 }
3628                 if (dss_has_feature(FEAT_ATTR2))
3629                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3630         }
3631
3632 #undef DISPC_REG
3633 #undef DUMPREG
3634
3635 #define DISPC_REG(plane, name, i) name(plane, i)
3636 #define DUMPREG(plane, name, i) \
3637         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3638         (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3639         dispc_read_reg(DISPC_REG(plane, name, i)))
3640
3641         /* Video pipeline coefficient registers */
3642
3643         /* start from OMAP_DSS_VIDEO1 */
3644         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3645                 for (j = 0; j < 8; j++)
3646                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3647
3648                 for (j = 0; j < 8; j++)
3649                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3650
3651                 for (j = 0; j < 5; j++)
3652                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3653
3654                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3655                         for (j = 0; j < 8; j++)
3656                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3657                 }
3658
3659                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3660                         for (j = 0; j < 8; j++)
3661                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3662
3663                         for (j = 0; j < 8; j++)
3664                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3665
3666                         for (j = 0; j < 8; j++)
3667                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3668                 }
3669         }
3670
3671         dispc_runtime_put();
3672
3673 #undef DISPC_REG
3674 #undef DUMPREG
3675 }
3676
3677 /* calculate clock rates using dividers in cinfo */
3678 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3679                 struct dispc_clock_info *cinfo)
3680 {
3681         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3682                 return -EINVAL;
3683         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3684                 return -EINVAL;
3685
3686         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3687         cinfo->pck = cinfo->lck / cinfo->pck_div;
3688
3689         return 0;
3690 }
3691
3692 bool dispc_div_calc(unsigned long dispc,
3693                 unsigned long pck_min, unsigned long pck_max,
3694                 dispc_div_calc_func func, void *data)
3695 {
3696         int lckd, lckd_start, lckd_stop;
3697         int pckd, pckd_start, pckd_stop;
3698         unsigned long pck, lck;
3699         unsigned long lck_max;
3700         unsigned long pckd_hw_min, pckd_hw_max;
3701         unsigned min_fck_per_pck;
3702         unsigned long fck;
3703
3704 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3705         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3706 #else
3707         min_fck_per_pck = 0;
3708 #endif
3709
3710         pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3711         pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3712
3713         lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3714
3715         pck_min = pck_min ? pck_min : 1;
3716         pck_max = pck_max ? pck_max : ULONG_MAX;
3717
3718         lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3719         lckd_stop = min(dispc / pck_min, 255ul);
3720
3721         for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3722                 lck = dispc / lckd;
3723
3724                 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3725                 pckd_stop = min(lck / pck_min, pckd_hw_max);
3726
3727                 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3728                         pck = lck / pckd;
3729
3730                         /*
3731                          * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3732                          * clock, which means we're configuring DISPC fclk here
3733                          * also. Thus we need to use the calculated lck. For
3734                          * OMAP4+ the DISPC fclk is a separate clock.
3735                          */
3736                         if (dss_has_feature(FEAT_CORE_CLK_DIV))
3737                                 fck = dispc_core_clk_rate();
3738                         else
3739                                 fck = lck;
3740
3741                         if (fck < pck * min_fck_per_pck)
3742                                 continue;
3743
3744                         if (func(lckd, pckd, lck, pck, data))
3745                                 return true;
3746                 }
3747         }
3748
3749         return false;
3750 }
3751
3752 void dispc_mgr_set_clock_div(enum omap_channel channel,
3753                 const struct dispc_clock_info *cinfo)
3754 {
3755         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3756         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3757
3758         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3759 }
3760
3761 int dispc_mgr_get_clock_div(enum omap_channel channel,
3762                 struct dispc_clock_info *cinfo)
3763 {
3764         unsigned long fck;
3765
3766         fck = dispc_fclk_rate();
3767
3768         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3769         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3770
3771         cinfo->lck = fck / cinfo->lck_div;
3772         cinfo->pck = cinfo->lck / cinfo->pck_div;
3773
3774         return 0;
3775 }
3776
3777 u32 dispc_read_irqstatus(void)
3778 {
3779         return dispc_read_reg(DISPC_IRQSTATUS);
3780 }
3781 EXPORT_SYMBOL(dispc_read_irqstatus);
3782
3783 void dispc_clear_irqstatus(u32 mask)
3784 {
3785         dispc_write_reg(DISPC_IRQSTATUS, mask);
3786 }
3787 EXPORT_SYMBOL(dispc_clear_irqstatus);
3788
3789 u32 dispc_read_irqenable(void)
3790 {
3791         return dispc_read_reg(DISPC_IRQENABLE);
3792 }
3793 EXPORT_SYMBOL(dispc_read_irqenable);
3794
3795 void dispc_write_irqenable(u32 mask)
3796 {
3797         u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3798
3799         /* clear the irqstatus for newly enabled irqs */
3800         dispc_clear_irqstatus((mask ^ old_mask) & mask);
3801
3802         dispc_write_reg(DISPC_IRQENABLE, mask);
3803 }
3804 EXPORT_SYMBOL(dispc_write_irqenable);
3805
3806 void dispc_enable_sidle(void)
3807 {
3808         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3809 }
3810
3811 void dispc_disable_sidle(void)
3812 {
3813         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3814 }
3815
3816 u32 dispc_mgr_gamma_size(enum omap_channel channel)
3817 {
3818         const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3819
3820         if (!dispc.feat->has_gamma_table)
3821                 return 0;
3822
3823         return gdesc->len;
3824 }
3825 EXPORT_SYMBOL(dispc_mgr_gamma_size);
3826
3827 static void dispc_mgr_write_gamma_table(enum omap_channel channel)
3828 {
3829         const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3830         u32 *table = dispc.gamma_table[channel];
3831         unsigned int i;
3832
3833         DSSDBG("%s: channel %d\n", __func__, channel);
3834
3835         for (i = 0; i < gdesc->len; ++i) {
3836                 u32 v = table[i];
3837
3838                 if (gdesc->has_index)
3839                         v |= i << 24;
3840                 else if (i == 0)
3841                         v |= 1 << 31;
3842
3843                 dispc_write_reg(gdesc->reg, v);
3844         }
3845 }
3846
3847 static void dispc_restore_gamma_tables(void)
3848 {
3849         DSSDBG("%s()\n", __func__);
3850
3851         if (!dispc.feat->has_gamma_table)
3852                 return;
3853
3854         dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD);
3855
3856         dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_DIGIT);
3857
3858         if (dss_has_feature(FEAT_MGR_LCD2))
3859                 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD2);
3860
3861         if (dss_has_feature(FEAT_MGR_LCD3))
3862                 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD3);
3863 }
3864
3865 static const struct drm_color_lut dispc_mgr_gamma_default_lut[] = {
3866         { .red = 0, .green = 0, .blue = 0, },
3867         { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, },
3868 };
3869
3870 void dispc_mgr_set_gamma(enum omap_channel channel,
3871                          const struct drm_color_lut *lut,
3872                          unsigned int length)
3873 {
3874         const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3875         u32 *table = dispc.gamma_table[channel];
3876         uint i;
3877
3878         DSSDBG("%s: channel %d, lut len %u, hw len %u\n", __func__,
3879                channel, length, gdesc->len);
3880
3881         if (!dispc.feat->has_gamma_table)
3882                 return;
3883
3884         if (lut == NULL || length < 2) {
3885                 lut = dispc_mgr_gamma_default_lut;
3886                 length = ARRAY_SIZE(dispc_mgr_gamma_default_lut);
3887         }
3888
3889         for (i = 0; i < length - 1; ++i) {
3890                 uint first = i * (gdesc->len - 1) / (length - 1);
3891                 uint last = (i + 1) * (gdesc->len - 1) / (length - 1);
3892                 uint w = last - first;
3893                 u16 r, g, b;
3894                 uint j;
3895
3896                 if (w == 0)
3897                         continue;
3898
3899                 for (j = 0; j <= w; j++) {
3900                         r = (lut[i].red * (w - j) + lut[i+1].red * j) / w;
3901                         g = (lut[i].green * (w - j) + lut[i+1].green * j) / w;
3902                         b = (lut[i].blue * (w - j) + lut[i+1].blue * j) / w;
3903
3904                         r >>= 16 - gdesc->bits;
3905                         g >>= 16 - gdesc->bits;
3906                         b >>= 16 - gdesc->bits;
3907
3908                         table[first + j] = (r << (gdesc->bits * 2)) |
3909                                 (g << gdesc->bits) | b;
3910                 }
3911         }
3912
3913         if (dispc.is_enabled)
3914                 dispc_mgr_write_gamma_table(channel);
3915 }
3916 EXPORT_SYMBOL(dispc_mgr_set_gamma);
3917
3918 static int dispc_init_gamma_tables(void)
3919 {
3920         int channel;
3921
3922         if (!dispc.feat->has_gamma_table)
3923                 return 0;
3924
3925         for (channel = 0; channel < ARRAY_SIZE(dispc.gamma_table); channel++) {
3926                 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3927                 u32 *gt;
3928
3929                 if (channel == OMAP_DSS_CHANNEL_LCD2 &&
3930                     !dss_has_feature(FEAT_MGR_LCD2))
3931                         continue;
3932
3933                 if (channel == OMAP_DSS_CHANNEL_LCD3 &&
3934                     !dss_has_feature(FEAT_MGR_LCD3))
3935                         continue;
3936
3937                 gt = devm_kmalloc_array(&dispc.pdev->dev, gdesc->len,
3938                                            sizeof(u32), GFP_KERNEL);
3939                 if (!gt)
3940                         return -ENOMEM;
3941
3942                 dispc.gamma_table[channel] = gt;
3943
3944                 dispc_mgr_set_gamma(channel, NULL, 0);
3945         }
3946         return 0;
3947 }
3948
3949 static void _omap_dispc_initial_config(void)
3950 {
3951         u32 l;
3952
3953         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3954         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3955                 l = dispc_read_reg(DISPC_DIVISOR);
3956                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3957                 l = FLD_MOD(l, 1, 0, 0);
3958                 l = FLD_MOD(l, 1, 23, 16);
3959                 dispc_write_reg(DISPC_DIVISOR, l);
3960
3961                 dispc.core_clk_rate = dispc_fclk_rate();
3962         }
3963
3964         /* Use gamma table mode, instead of palette mode */
3965         if (dispc.feat->has_gamma_table)
3966                 REG_FLD_MOD(DISPC_CONFIG, 1, 3, 3);
3967
3968         /* For older DSS versions (FEAT_FUNCGATED) this enables
3969          * func-clock auto-gating. For newer versions
3970          * (dispc.feat->has_gamma_table) this enables tv-out gamma tables.
3971          */
3972         if (dss_has_feature(FEAT_FUNCGATED) || dispc.feat->has_gamma_table)
3973                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3974
3975         dispc_setup_color_conv_coef();
3976
3977         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3978
3979         dispc_init_fifos();
3980
3981         dispc_configure_burst_sizes();
3982
3983         dispc_ovl_enable_zorder_planes();
3984
3985         if (dispc.feat->mstandby_workaround)
3986                 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3987
3988         if (dss_has_feature(FEAT_MFLAG))
3989                 dispc_init_mflag();
3990 }
3991
3992 static const struct dispc_features omap24xx_dispc_feats = {
3993         .sw_start               =       5,
3994         .fp_start               =       15,
3995         .bp_start               =       27,
3996         .sw_max                 =       64,
3997         .vp_max                 =       255,
3998         .hp_max                 =       256,
3999         .mgr_width_start        =       10,
4000         .mgr_height_start       =       26,
4001         .mgr_width_max          =       2048,
4002         .mgr_height_max         =       2048,
4003         .max_lcd_pclk           =       66500000,
4004         .calc_scaling           =       dispc_ovl_calc_scaling_24xx,
4005         .calc_core_clk          =       calc_core_clk_24xx,
4006         .num_fifos              =       3,
4007         .no_framedone_tv        =       true,
4008         .set_max_preload        =       false,
4009         .last_pixel_inc_missing =       true,
4010 };
4011
4012 static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
4013         .sw_start               =       5,
4014         .fp_start               =       15,
4015         .bp_start               =       27,
4016         .sw_max                 =       64,
4017         .vp_max                 =       255,
4018         .hp_max                 =       256,
4019         .mgr_width_start        =       10,
4020         .mgr_height_start       =       26,
4021         .mgr_width_max          =       2048,
4022         .mgr_height_max         =       2048,
4023         .max_lcd_pclk           =       173000000,
4024         .max_tv_pclk            =       59000000,
4025         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
4026         .calc_core_clk          =       calc_core_clk_34xx,
4027         .num_fifos              =       3,
4028         .no_framedone_tv        =       true,
4029         .set_max_preload        =       false,
4030         .last_pixel_inc_missing =       true,
4031 };
4032
4033 static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
4034         .sw_start               =       7,
4035         .fp_start               =       19,
4036         .bp_start               =       31,
4037         .sw_max                 =       256,
4038         .vp_max                 =       4095,
4039         .hp_max                 =       4096,
4040         .mgr_width_start        =       10,
4041         .mgr_height_start       =       26,
4042         .mgr_width_max          =       2048,
4043         .mgr_height_max         =       2048,
4044         .max_lcd_pclk           =       173000000,
4045         .max_tv_pclk            =       59000000,
4046         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
4047         .calc_core_clk          =       calc_core_clk_34xx,
4048         .num_fifos              =       3,
4049         .no_framedone_tv        =       true,
4050         .set_max_preload        =       false,
4051         .last_pixel_inc_missing =       true,
4052 };
4053
4054 static const struct dispc_features omap44xx_dispc_feats = {
4055         .sw_start               =       7,
4056         .fp_start               =       19,
4057         .bp_start               =       31,
4058         .sw_max                 =       256,
4059         .vp_max                 =       4095,
4060         .hp_max                 =       4096,
4061         .mgr_width_start        =       10,
4062         .mgr_height_start       =       26,
4063         .mgr_width_max          =       2048,
4064         .mgr_height_max         =       2048,
4065         .max_lcd_pclk           =       170000000,
4066         .max_tv_pclk            =       185625000,
4067         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
4068         .calc_core_clk          =       calc_core_clk_44xx,
4069         .num_fifos              =       5,
4070         .gfx_fifo_workaround    =       true,
4071         .set_max_preload        =       true,
4072         .supports_sync_align    =       true,
4073         .has_writeback          =       true,
4074         .supports_double_pixel  =       true,
4075         .reverse_ilace_field_order =    true,
4076         .has_gamma_table        =       true,
4077 };
4078
4079 static const struct dispc_features omap54xx_dispc_feats = {
4080         .sw_start               =       7,
4081         .fp_start               =       19,
4082         .bp_start               =       31,
4083         .sw_max                 =       256,
4084         .vp_max                 =       4095,
4085         .hp_max                 =       4096,
4086         .mgr_width_start        =       11,
4087         .mgr_height_start       =       27,
4088         .mgr_width_max          =       4096,
4089         .mgr_height_max         =       4096,
4090         .max_lcd_pclk           =       170000000,
4091         .max_tv_pclk            =       186000000,
4092         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
4093         .calc_core_clk          =       calc_core_clk_44xx,
4094         .num_fifos              =       5,
4095         .gfx_fifo_workaround    =       true,
4096         .mstandby_workaround    =       true,
4097         .set_max_preload        =       true,
4098         .supports_sync_align    =       true,
4099         .has_writeback          =       true,
4100         .supports_double_pixel  =       true,
4101         .reverse_ilace_field_order =    true,
4102         .has_gamma_table        =       true,
4103 };
4104
4105 static int dispc_init_features(struct platform_device *pdev)
4106 {
4107         const struct dispc_features *src;
4108         struct dispc_features *dst;
4109
4110         dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
4111         if (!dst) {
4112                 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
4113                 return -ENOMEM;
4114         }
4115
4116         switch (omapdss_get_version()) {
4117         case OMAPDSS_VER_OMAP24xx:
4118                 src = &omap24xx_dispc_feats;
4119                 break;
4120
4121         case OMAPDSS_VER_OMAP34xx_ES1:
4122                 src = &omap34xx_rev1_0_dispc_feats;
4123                 break;
4124
4125         case OMAPDSS_VER_OMAP34xx_ES3:
4126         case OMAPDSS_VER_OMAP3630:
4127         case OMAPDSS_VER_AM35xx:
4128         case OMAPDSS_VER_AM43xx:
4129                 src = &omap34xx_rev3_0_dispc_feats;
4130                 break;
4131
4132         case OMAPDSS_VER_OMAP4430_ES1:
4133         case OMAPDSS_VER_OMAP4430_ES2:
4134         case OMAPDSS_VER_OMAP4:
4135                 src = &omap44xx_dispc_feats;
4136                 break;
4137
4138         case OMAPDSS_VER_OMAP5:
4139         case OMAPDSS_VER_DRA7xx:
4140                 src = &omap54xx_dispc_feats;
4141                 break;
4142
4143         default:
4144                 return -ENODEV;
4145         }
4146
4147         memcpy(dst, src, sizeof(*dst));
4148         dispc.feat = dst;
4149
4150         return 0;
4151 }
4152
4153 static irqreturn_t dispc_irq_handler(int irq, void *arg)
4154 {
4155         if (!dispc.is_enabled)
4156                 return IRQ_NONE;
4157
4158         return dispc.user_handler(irq, dispc.user_data);
4159 }
4160
4161 int dispc_request_irq(irq_handler_t handler, void *dev_id)
4162 {
4163         int r;
4164
4165         if (dispc.user_handler != NULL)
4166                 return -EBUSY;
4167
4168         dispc.user_handler = handler;
4169         dispc.user_data = dev_id;
4170
4171         /* ensure the dispc_irq_handler sees the values above */
4172         smp_wmb();
4173
4174         r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
4175                              IRQF_SHARED, "OMAP DISPC", &dispc);
4176         if (r) {
4177                 dispc.user_handler = NULL;
4178                 dispc.user_data = NULL;
4179         }
4180
4181         return r;
4182 }
4183 EXPORT_SYMBOL(dispc_request_irq);
4184
4185 void dispc_free_irq(void *dev_id)
4186 {
4187         devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
4188
4189         dispc.user_handler = NULL;
4190         dispc.user_data = NULL;
4191 }
4192 EXPORT_SYMBOL(dispc_free_irq);
4193
4194 /* DISPC HW IP initialisation */
4195 static int dispc_bind(struct device *dev, struct device *master, void *data)
4196 {
4197         struct platform_device *pdev = to_platform_device(dev);
4198         u32 rev;
4199         int r = 0;
4200         struct resource *dispc_mem;
4201         struct device_node *np = pdev->dev.of_node;
4202
4203         dispc.pdev = pdev;
4204
4205         spin_lock_init(&dispc.control_lock);
4206
4207         r = dispc_init_features(dispc.pdev);
4208         if (r)
4209                 return r;
4210
4211         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4212         if (!dispc_mem) {
4213                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
4214                 return -EINVAL;
4215         }
4216
4217         dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4218                                   resource_size(dispc_mem));
4219         if (!dispc.base) {
4220                 DSSERR("can't ioremap DISPC\n");
4221                 return -ENOMEM;
4222         }
4223
4224         dispc.irq = platform_get_irq(dispc.pdev, 0);
4225         if (dispc.irq < 0) {
4226                 DSSERR("platform_get_irq failed\n");
4227                 return -ENODEV;
4228         }
4229
4230         if (np && of_property_read_bool(np, "syscon-pol")) {
4231                 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4232                 if (IS_ERR(dispc.syscon_pol)) {
4233                         dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4234                         return PTR_ERR(dispc.syscon_pol);
4235                 }
4236
4237                 if (of_property_read_u32_index(np, "syscon-pol", 1,
4238                                 &dispc.syscon_pol_offset)) {
4239                         dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4240                         return -EINVAL;
4241                 }
4242         }
4243
4244         r = dispc_init_gamma_tables();
4245         if (r)
4246                 return r;
4247
4248         pm_runtime_enable(&pdev->dev);
4249
4250         r = dispc_runtime_get();
4251         if (r)
4252                 goto err_runtime_get;
4253
4254         _omap_dispc_initial_config();
4255
4256         rev = dispc_read_reg(DISPC_REVISION);
4257         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4258                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4259
4260         dispc_runtime_put();
4261
4262         dss_debugfs_create_file("dispc", dispc_dump_regs);
4263
4264         return 0;
4265
4266 err_runtime_get:
4267         pm_runtime_disable(&pdev->dev);
4268         return r;
4269 }
4270
4271 static void dispc_unbind(struct device *dev, struct device *master,
4272                                void *data)
4273 {
4274         pm_runtime_disable(dev);
4275 }
4276
4277 static const struct component_ops dispc_component_ops = {
4278         .bind   = dispc_bind,
4279         .unbind = dispc_unbind,
4280 };
4281
4282 static int dispc_probe(struct platform_device *pdev)
4283 {
4284         return component_add(&pdev->dev, &dispc_component_ops);
4285 }
4286
4287 static int dispc_remove(struct platform_device *pdev)
4288 {
4289         component_del(&pdev->dev, &dispc_component_ops);
4290         return 0;
4291 }
4292
4293 static int dispc_runtime_suspend(struct device *dev)
4294 {
4295         dispc.is_enabled = false;
4296         /* ensure the dispc_irq_handler sees the is_enabled value */
4297         smp_wmb();
4298         /* wait for current handler to finish before turning the DISPC off */
4299         synchronize_irq(dispc.irq);
4300
4301         dispc_save_context();
4302
4303         return 0;
4304 }
4305
4306 static int dispc_runtime_resume(struct device *dev)
4307 {
4308         /*
4309          * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4310          * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4311          * _omap_dispc_initial_config(). We can thus use it to detect if
4312          * we have lost register context.
4313          */
4314         if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4315                 _omap_dispc_initial_config();
4316
4317                 dispc_restore_context();
4318
4319                 dispc_restore_gamma_tables();
4320         }
4321
4322         dispc.is_enabled = true;
4323         /* ensure the dispc_irq_handler sees the is_enabled value */
4324         smp_wmb();
4325
4326         return 0;
4327 }
4328
4329 static const struct dev_pm_ops dispc_pm_ops = {
4330         .runtime_suspend = dispc_runtime_suspend,
4331         .runtime_resume = dispc_runtime_resume,
4332 };
4333
4334 static const struct of_device_id dispc_of_match[] = {
4335         { .compatible = "ti,omap2-dispc", },
4336         { .compatible = "ti,omap3-dispc", },
4337         { .compatible = "ti,omap4-dispc", },
4338         { .compatible = "ti,omap5-dispc", },
4339         { .compatible = "ti,dra7-dispc", },
4340         {},
4341 };
4342
4343 static struct platform_driver omap_dispchw_driver = {
4344         .probe          = dispc_probe,
4345         .remove         = dispc_remove,
4346         .driver         = {
4347                 .name   = "omapdss_dispc",
4348                 .pm     = &dispc_pm_ops,
4349                 .of_match_table = dispc_of_match,
4350                 .suppress_bind_attrs = true,
4351         },
4352 };
4353
4354 int __init dispc_init_platform_driver(void)
4355 {
4356         return platform_driver_register(&omap_dispchw_driver);
4357 }
4358
4359 void dispc_uninit_platform_driver(void)
4360 {
4361         platform_driver_unregister(&omap_dispchw_driver);
4362 }