2 * Copyright 2012 Red Hat Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <engine/gr/nv40.h>
29 /******************************************************************************
30 * instmem subdev implementation
31 *****************************************************************************/
34 nv40_instmem_rd32(struct nouveau_object *object, u64 addr)
36 struct nv04_instmem_priv *priv = (void *)object;
37 return ioread32_native(priv->iomem + addr);
41 nv40_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data)
43 struct nv04_instmem_priv *priv = (void *)object;
44 iowrite32_native(data, priv->iomem + addr);
48 nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
49 struct nouveau_oclass *oclass, void *data, u32 size,
50 struct nouveau_object **pobject)
52 struct nouveau_device *device = nv_device(parent);
53 struct nv04_instmem_priv *priv;
56 ret = nouveau_instmem_create(parent, engine, oclass, &priv);
57 *pobject = nv_object(priv);
62 if (nv_device_resource_len(device, 2))
67 priv->iomem = ioremap(nv_device_resource_start(device, bar),
68 nv_device_resource_len(device, bar));
70 nv_error(priv, "unable to map PRAMIN BAR\n");
74 /* PRAMIN aperture maps over the end of vram, reserve enough space
75 * to fit graphics contexts for every channel, the magics come
76 * from engine/gr/nv40.c
78 vs = hweight8((nv_rd32(priv, 0x001540) & 0x0000ff00) >> 8);
79 if (device->chipset == 0x40) priv->base.reserved = 0x6aa0 * vs;
80 else if (device->chipset < 0x43) priv->base.reserved = 0x4f00 * vs;
81 else if (nv44_gr_class(priv)) priv->base.reserved = 0x4980 * vs;
82 else priv->base.reserved = 0x4a40 * vs;
83 priv->base.reserved += 16 * 1024;
84 priv->base.reserved *= 32; /* per-channel */
85 priv->base.reserved += 512 * 1024; /* pci(e)gart table */
86 priv->base.reserved += 512 * 1024; /* object storage */
88 priv->base.reserved = round_up(priv->base.reserved, 4096);
90 ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1);
94 /* 0x00000-0x10000: reserve for probable vbios image */
95 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0,
100 /* 0x10000-0x18000: reserve for RAMHT */
101 ret = nouveau_ramht_new(nv_object(priv), NULL, 0x08000, 0,
106 /* 0x18000-0x18200: reserve for RAMRO
107 * 0x18200-0x20000: padding
109 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x08000, 0, 0,
114 /* 0x20000-0x21000: reserve for RAMFC
115 * 0x21000-0x40000: padding and some unknown crap
117 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x20000, 0,
118 NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc);
125 struct nouveau_oclass *
126 nv40_instmem_oclass = &(struct nouveau_instmem_impl) {
127 .base.handle = NV_SUBDEV(INSTMEM, 0x40),
128 .base.ofuncs = &(struct nouveau_ofuncs) {
129 .ctor = nv40_instmem_ctor,
130 .dtor = nv04_instmem_dtor,
131 .init = _nouveau_instmem_init,
132 .fini = _nouveau_instmem_fini,
133 .rd32 = nv40_instmem_rd32,
134 .wr32 = nv40_instmem_wr32,
136 .instobj = &nv04_instobj_oclass.base,