2 * Copyright 2014 Roy Spliet
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Roy Spliet <rspliet@eclipso.eu>
33 ramxlat(const struct ramxlat *xlat, int id)
35 while (xlat->id >= 0) {
43 static const struct ramxlat
45 { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 },
46 /* The following are available in some, but not all DDR2 docs */
51 static const struct ramxlat
53 { 2, 1 }, { 3, 2 }, { 4, 3 }, { 5, 4 }, { 6, 5 },
54 /* The following are available in some, but not all DDR2 docs */
60 nvkm_sddr2_calc(struct nvkm_ram *ram)
62 int CL, WR, DLL = 0, ODT = 0;
64 switch (ram->next->bios.timing_ver) {
66 CL = ram->next->bios.timing_10_CL;
67 WR = ram->next->bios.timing_10_WR;
68 DLL = !ram->next->bios.ramcfg_DLLoff;
69 ODT = ram->next->bios.timing_10_ODT & 3;
72 CL = (ram->next->bios.timing[1] & 0x0000001f);
73 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
79 CL = ramxlat(ramddr2_cl, CL);
80 WR = ramxlat(ramddr2_wr, WR);
85 ram->mr[0] |= (WR & 0x07) << 9;
86 ram->mr[0] |= (CL & 0x07) << 4;
89 ram->mr[1] |= (ODT & 0x1) << 2;
90 ram->mr[1] |= (ODT & 0x2) << 5;