2 * Copyright 2013 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #define gk104_ram(p) container_of((p), struct gk104_ram, base)
28 #include <core/option.h>
29 #include <subdev/bios.h>
30 #include <subdev/bios/init.h>
31 #include <subdev/bios/M0205.h>
32 #include <subdev/bios/M0209.h>
33 #include <subdev/bios/pll.h>
34 #include <subdev/bios/rammap.h>
35 #include <subdev/bios/timing.h>
36 #include <subdev/clk.h>
37 #include <subdev/clk/pll.h>
38 #include <subdev/gpio.h>
43 struct nvbios_pll refpll;
44 struct nvbios_pll mempll;
46 struct ramfuc_reg r_gpioMV;
48 struct ramfuc_reg r_gpio2E;
50 struct ramfuc_reg r_gpiotrig;
52 struct ramfuc_reg r_0x132020;
53 struct ramfuc_reg r_0x132028;
54 struct ramfuc_reg r_0x132024;
55 struct ramfuc_reg r_0x132030;
56 struct ramfuc_reg r_0x132034;
57 struct ramfuc_reg r_0x132000;
58 struct ramfuc_reg r_0x132004;
59 struct ramfuc_reg r_0x132040;
61 struct ramfuc_reg r_0x10f248;
62 struct ramfuc_reg r_0x10f290;
63 struct ramfuc_reg r_0x10f294;
64 struct ramfuc_reg r_0x10f298;
65 struct ramfuc_reg r_0x10f29c;
66 struct ramfuc_reg r_0x10f2a0;
67 struct ramfuc_reg r_0x10f2a4;
68 struct ramfuc_reg r_0x10f2a8;
69 struct ramfuc_reg r_0x10f2ac;
70 struct ramfuc_reg r_0x10f2cc;
71 struct ramfuc_reg r_0x10f2e8;
72 struct ramfuc_reg r_0x10f250;
73 struct ramfuc_reg r_0x10f24c;
74 struct ramfuc_reg r_0x10fec4;
75 struct ramfuc_reg r_0x10fec8;
76 struct ramfuc_reg r_0x10f604;
77 struct ramfuc_reg r_0x10f614;
78 struct ramfuc_reg r_0x10f610;
79 struct ramfuc_reg r_0x100770;
80 struct ramfuc_reg r_0x100778;
81 struct ramfuc_reg r_0x10f224;
83 struct ramfuc_reg r_0x10f870;
84 struct ramfuc_reg r_0x10f698;
85 struct ramfuc_reg r_0x10f694;
86 struct ramfuc_reg r_0x10f6b8;
87 struct ramfuc_reg r_0x10f808;
88 struct ramfuc_reg r_0x10f670;
89 struct ramfuc_reg r_0x10f60c;
90 struct ramfuc_reg r_0x10f830;
91 struct ramfuc_reg r_0x1373ec;
92 struct ramfuc_reg r_0x10f800;
93 struct ramfuc_reg r_0x10f82c;
95 struct ramfuc_reg r_0x10f978;
96 struct ramfuc_reg r_0x10f910;
97 struct ramfuc_reg r_0x10f914;
99 struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */
101 struct ramfuc_reg r_0x62c000;
103 struct ramfuc_reg r_0x10f200;
105 struct ramfuc_reg r_0x10f210;
106 struct ramfuc_reg r_0x10f310;
107 struct ramfuc_reg r_0x10f314;
108 struct ramfuc_reg r_0x10f318;
109 struct ramfuc_reg r_0x10f090;
110 struct ramfuc_reg r_0x10f69c;
111 struct ramfuc_reg r_0x10f824;
112 struct ramfuc_reg r_0x1373f0;
113 struct ramfuc_reg r_0x1373f4;
114 struct ramfuc_reg r_0x137320;
115 struct ramfuc_reg r_0x10f65c;
116 struct ramfuc_reg r_0x10f6bc;
117 struct ramfuc_reg r_0x100710;
118 struct ramfuc_reg r_0x100750;
122 struct nvkm_ram base;
123 struct gk104_ramfuc fuc;
125 struct list_head cfg;
130 struct nvbios_ramcfg diff;
137 /*******************************************************************************
139 ******************************************************************************/
141 gk104_ram_train(struct gk104_ramfuc *fuc, u32 mask, u32 data)
143 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
144 u32 addr = 0x110974, i;
146 ram_mask(fuc, 0x10f910, mask, data);
147 ram_mask(fuc, 0x10f914, mask, data);
149 for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) {
150 if (ram->pmask & (1 << i))
152 ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
157 r1373f4_init(struct gk104_ramfuc *fuc)
159 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
160 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2);
161 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
162 const u32 runk0 = ram->fN1 << 16;
163 const u32 runk1 = ram->fN1;
165 if (ram->from == 2) {
166 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
167 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
169 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
172 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
173 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
175 /* (re)program refpll, if required */
176 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
177 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
178 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
179 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
180 ram_wr32(fuc, 0x137320, 0x00000000);
181 ram_mask(fuc, 0x132030, 0xffff0000, runk0);
182 ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
183 ram_wr32(fuc, 0x132024, rcoef);
184 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
185 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
186 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
187 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
190 /* (re)program mempll, if required */
191 if (ram->mode == 2) {
192 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
193 ram_mask(fuc, 0x132000, 0x80000000, 0x80000000);
194 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
195 ram_mask(fuc, 0x132004, 0x103fffff, mcoef);
196 ram_mask(fuc, 0x132000, 0x00000001, 0x00000001);
197 ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
198 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
200 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010100);
203 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
207 r1373f4_fini(struct gk104_ramfuc *fuc)
209 struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
210 struct nvkm_ram_data *next = ram->base.next;
211 u8 v0 = next->bios.ramcfg_11_03_c0;
212 u8 v1 = next->bios.ramcfg_11_03_30;
215 tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
216 ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16));
217 ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000);
218 if (ram->mode == 2) {
219 ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000002);
220 ram_mask(fuc, 0x1373f4, 0x00001100, 0x000000000);
222 ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000001);
223 ram_mask(fuc, 0x1373f4, 0x00010000, 0x000000000);
225 ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4);
229 gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg,
230 u32 _mask, u32 _data, u32 _copy)
232 struct nvkm_fb *fb = ram->base.fb;
233 struct ramfuc *fuc = &ram->fuc.base;
234 struct nvkm_device *device = fb->subdev.device;
235 u32 addr = 0x110000 + (reg->addr & 0xfff);
236 u32 mask = _mask | _copy;
237 u32 data = (_data & _mask) | (reg->data & _copy);
240 for (i = 0; i < 16; i++, addr += 0x1000) {
241 if (ram->pnuts & (1 << i)) {
242 u32 prev = nvkm_rd32(device, addr);
243 u32 next = (prev & ~mask) | data;
244 nvkm_memx_wr32(fuc->memx, addr, next);
248 #define ram_nuts(s,r,m,d,c) \
249 gk104_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c))
252 gk104_ram_calc_gddr5(struct gk104_ram *ram, u32 freq)
254 struct gk104_ramfuc *fuc = &ram->fuc;
255 struct nvkm_ram_data *next = ram->base.next;
256 int vc = !next->bios.ramcfg_11_02_08;
257 int mv = !next->bios.ramcfg_11_02_04;
260 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
262 ram_wr32(fuc, 0x62c000, 0x0f0f0000);
264 /* MR1: turn termination on early, for some reason.. */
265 if ((ram->base.mr[1] & 0x03c) != 0x030) {
266 ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c);
267 ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000);
270 if (vc == 1 && ram_have(fuc, gpio2E)) {
271 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
272 if (temp != ram_rd32(fuc, gpio2E)) {
273 ram_wr32(fuc, gpiotrig, 1);
274 ram_nsec(fuc, 20000);
278 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
280 gk104_ram_train(fuc, 0x01020000, 0x000c0000);
282 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
284 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
287 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
288 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
289 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
290 ram_wr32(fuc, 0x10f090, 0x00000061);
291 ram_wr32(fuc, 0x10f090, 0xc000007f);
294 ram_wr32(fuc, 0x10f698, 0x00000000);
295 ram_wr32(fuc, 0x10f69c, 0x00000000);
297 /*XXX: there does appear to be some kind of condition here, simply
298 * modifying these bits in the vbios from the default pl0
299 * entries shows no change. however, the data does appear to
300 * be correct and may be required for the transition back
304 if (ram_rd32(fuc, 0x10f978) & 0x00800000)
309 switch (next->bios.ramcfg_11_03_c0) {
310 case 3: data &= ~0x00000040; break;
311 case 2: data &= ~0x00000100; break;
312 case 1: data &= ~0x80000000; break;
313 case 0: data &= ~0x00000400; break;
316 switch (next->bios.ramcfg_11_03_30) {
317 case 3: data &= ~0x00000020; break;
318 case 2: data &= ~0x00000080; break;
319 case 1: data &= ~0x00080000; break;
320 case 0: data &= ~0x00000200; break;
324 if (next->bios.ramcfg_11_02_80)
326 if (next->bios.ramcfg_11_02_40)
328 if (next->bios.ramcfg_11_07_10)
330 if (next->bios.ramcfg_11_07_08)
334 if (ram_rd32(fuc, 0x10f978) & 0x00800000)
337 ram_mask(fuc, 0x10f824, mask, data);
339 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
341 if (ram->from == 2 && ram->mode != 2) {
342 ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
343 ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000);
344 ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004);
345 ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010);
346 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
348 ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001);
350 ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001);
352 if (ram->from != 2 && ram->mode != 2) {
357 if (ram_have(fuc, gpioMV)) {
358 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
359 if (temp != ram_rd32(fuc, gpioMV)) {
360 ram_wr32(fuc, gpiotrig, 1);
361 ram_nsec(fuc, 64000);
365 if (next->bios.ramcfg_11_02_40 ||
366 next->bios.ramcfg_11_07_10) {
367 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
368 ram_nsec(fuc, 20000);
371 if (ram->from != 2 && ram->mode == 2) {
372 if (0 /*XXX: Titan */)
373 ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000);
374 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
375 ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002);
376 ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010);
379 ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000);
380 ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000);
382 if (ram->from == 2 && ram->mode == 2) {
383 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
388 if (ram->mode != 2) /*XXX*/ {
389 if (next->bios.ramcfg_11_07_40)
390 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
393 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
394 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
395 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
397 if (!next->bios.ramcfg_11_07_08 && !next->bios.ramcfg_11_07_04) {
398 ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04);
399 ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04);
401 if (!next->bios.ramcfg_11_07_08) {
402 ram_wr32(fuc, 0x10f698, 0x00000000);
403 ram_wr32(fuc, 0x10f69c, 0x00000000);
406 if (ram->mode != 2) {
407 u32 data = 0x01000100 * next->bios.ramcfg_11_04;
408 ram_nuke(fuc, 0x10f694);
409 ram_mask(fuc, 0x10f694, 0xff00ff00, data);
412 if (ram->mode == 2 && next->bios.ramcfg_11_08_10)
416 ram_mask(fuc, 0x10f60c, 0x00000080, data);
420 if (!next->bios.ramcfg_11_02_80)
422 if (!next->bios.ramcfg_11_02_40)
424 if (!next->bios.ramcfg_11_07_10)
426 if (!next->bios.ramcfg_11_07_08)
430 ram_mask(fuc, 0x10f824, mask, data);
432 if (next->bios.ramcfg_11_01_08)
436 ram_mask(fuc, 0x10f200, 0x00001000, data);
438 if (ram_rd32(fuc, 0x10f670) & 0x80000000) {
439 ram_nsec(fuc, 10000);
440 ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000);
443 if (next->bios.ramcfg_11_08_01)
447 ram_mask(fuc, 0x10f82c, 0x00100000, data);
450 if (next->bios.ramcfg_11_08_08)
452 if (next->bios.ramcfg_11_08_04)
454 if (next->bios.ramcfg_11_08_02)
456 ram_mask(fuc, 0x10f830, 0x00007000, data);
459 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
460 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
461 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
462 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
463 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
464 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
465 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
466 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
467 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
468 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
469 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
471 data = mask = 0x00000000;
472 if (ram->diff.ramcfg_11_08_20) {
473 if (next->bios.ramcfg_11_08_20)
477 ram_mask(fuc, 0x10f200, mask, data);
479 data = mask = 0x00000000;
480 if (ram->diff.ramcfg_11_02_03) {
481 data |= next->bios.ramcfg_11_02_03 << 8;
484 if (ram->diff.ramcfg_11_01_10) {
485 if (next->bios.ramcfg_11_01_10)
489 ram_mask(fuc, 0x10f604, mask, data);
491 data = mask = 0x00000000;
492 if (ram->diff.timing_20_30_07) {
493 data |= next->bios.timing_20_30_07 << 28;
496 if (ram->diff.ramcfg_11_01_01) {
497 if (next->bios.ramcfg_11_01_01)
501 ram_mask(fuc, 0x10f614, mask, data);
503 data = mask = 0x00000000;
504 if (ram->diff.timing_20_30_07) {
505 data |= next->bios.timing_20_30_07 << 28;
508 if (ram->diff.ramcfg_11_01_02) {
509 if (next->bios.ramcfg_11_01_02)
513 ram_mask(fuc, 0x10f610, mask, data);
517 if (!next->bios.ramcfg_11_01_04)
519 if (!next->bios.ramcfg_11_07_80)
521 /*XXX: see note above about there probably being some condition
522 * for the 10f824 stuff that uses ramcfg 3...
524 if (next->bios.ramcfg_11_03_f0) {
525 if (next->bios.rammap_11_08_0c) {
526 if (!next->bios.ramcfg_11_07_80)
537 ram_mask(fuc, 0x10f808, mask, data);
539 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
541 data = mask = 0x00000000;
542 if (ram->diff.ramcfg_11_02_03) {
543 data |= next->bios.ramcfg_11_02_03;
546 if (ram->diff.ramcfg_11_01_10) {
547 if (next->bios.ramcfg_11_01_10)
552 if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) {
553 ram_mask(fuc, 0x100750, 0x00000008, 0x00000008);
554 ram_wr32(fuc, 0x100710, 0x00000000);
555 ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000);
558 data = next->bios.timing_20_30_07 << 8;
559 if (next->bios.ramcfg_11_01_01)
561 ram_mask(fuc, 0x100778, 0x00000700, data);
563 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
564 data = (next->bios.timing[10] & 0x7f000000) >> 24;
565 if (data < next->bios.timing_20_2c_1fc0)
566 data = next->bios.timing_20_2c_1fc0;
567 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
568 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
570 ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 |
571 next->bios.timing_20_31_0780 << 17 |
572 next->bios.timing_20_31_0078 << 8 |
573 next->bios.timing_20_31_0007);
574 ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 |
575 next->bios.timing_20_31_7000);
577 ram_wr32(fuc, 0x10f090, 0x4000007e);
579 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
580 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
581 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
583 if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) {
584 u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000);
585 gk104_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/
587 ram_wr32(fuc, 0x10f294, temp);
590 ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]);
591 ram_wr32(fuc, mr[0], ram->base.mr[0]);
592 ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]);
594 ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]);
595 ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */
596 ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]);
597 ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]);
599 if (vc == 0 && ram_have(fuc, gpio2E)) {
600 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
601 if (temp != ram_rd32(fuc, gpio2E)) {
602 ram_wr32(fuc, gpiotrig, 1);
603 ram_nsec(fuc, 20000);
607 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
608 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
609 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
611 ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800);
613 data = ram_rd32(fuc, 0x10f978);
616 if (!next->bios.ramcfg_11_07_08) {
617 if (!next->bios.ramcfg_11_07_04)
624 ram_wr32(fuc, 0x10f978, data);
626 if (ram->mode == 1) {
627 data = ram_rd32(fuc, 0x10f830) | 0x00000001;
628 ram_wr32(fuc, 0x10f830, data);
631 if (!next->bios.ramcfg_11_07_08) {
633 if ( next->bios.ramcfg_11_07_04)
635 if (!next->bios.rammap_11_08_10)
640 gk104_ram_train(fuc, 0xbc0f0000, data);
641 if (1) /* XXX: not always? */
644 if (ram->mode == 2) { /*XXX*/
645 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004);
649 if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5])
652 if (ram->mode != 2) {
653 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
654 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
657 if (next->bios.ramcfg_11_07_02)
658 gk104_ram_train(fuc, 0x80020000, 0x01000000);
661 ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
663 if (next->bios.rammap_11_08_01)
667 ram_mask(fuc, 0x10f200, 0x00000800, data);
668 ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800);
672 /*******************************************************************************
674 ******************************************************************************/
677 gk104_ram_calc_sddr3(struct gk104_ram *ram, u32 freq)
679 struct gk104_ramfuc *fuc = &ram->fuc;
680 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
681 const u32 runk0 = ram->fN1 << 16;
682 const u32 runk1 = ram->fN1;
683 struct nvkm_ram_data *next = ram->base.next;
684 int vc = !next->bios.ramcfg_11_02_08;
685 int mv = !next->bios.ramcfg_11_02_04;
688 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
690 ram_wr32(fuc, 0x62c000, 0x0f0f0000);
692 if (vc == 1 && ram_have(fuc, gpio2E)) {
693 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
694 if (temp != ram_rd32(fuc, gpio2E)) {
695 ram_wr32(fuc, gpiotrig, 1);
696 ram_nsec(fuc, 20000);
700 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
701 if (next->bios.ramcfg_11_03_f0)
702 ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000);
704 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
705 ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
706 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
707 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
708 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
709 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
712 ram_wr32(fuc, 0x10f090, 0x00000060);
713 ram_wr32(fuc, 0x10f090, 0xc000007e);
715 /*XXX: there does appear to be some kind of condition here, simply
716 * modifying these bits in the vbios from the default pl0
717 * entries shows no change. however, the data does appear to
718 * be correct and may be required for the transition back
726 switch (next->bios.ramcfg_11_03_c0) {
727 case 3: data &= ~0x00000040; break;
728 case 2: data &= ~0x00000100; break;
729 case 1: data &= ~0x80000000; break;
730 case 0: data &= ~0x00000400; break;
733 switch (next->bios.ramcfg_11_03_30) {
734 case 3: data &= ~0x00000020; break;
735 case 2: data &= ~0x00000080; break;
736 case 1: data &= ~0x00080000; break;
737 case 0: data &= ~0x00000200; break;
741 if (next->bios.ramcfg_11_02_80)
743 if (next->bios.ramcfg_11_02_40)
745 if (next->bios.ramcfg_11_07_10)
747 if (next->bios.ramcfg_11_07_08)
751 ram_mask(fuc, 0x10f824, mask, data);
753 ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);
755 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
756 data = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
757 data |= next->bios.ramcfg_11_03_30 << 16;
758 ram_wr32(fuc, 0x1373ec, data);
759 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
760 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);
762 /* (re)program refpll, if required */
763 if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
764 (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
765 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
766 ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
767 ram_wr32(fuc, 0x137320, 0x00000000);
768 ram_mask(fuc, 0x132030, 0xffff0000, runk0);
769 ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
770 ram_wr32(fuc, 0x132024, rcoef);
771 ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
772 ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
773 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
774 ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
777 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000010);
778 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001);
779 ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
781 if (ram_have(fuc, gpioMV)) {
782 u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
783 if (temp != ram_rd32(fuc, gpioMV)) {
784 ram_wr32(fuc, gpiotrig, 1);
785 ram_nsec(fuc, 64000);
789 if (next->bios.ramcfg_11_02_40 ||
790 next->bios.ramcfg_11_07_10) {
791 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
792 ram_nsec(fuc, 20000);
795 if (ram->mode != 2) /*XXX*/ {
796 if (next->bios.ramcfg_11_07_40)
797 ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
800 ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
801 ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
802 ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
806 if (!next->bios.ramcfg_11_02_80)
808 if (!next->bios.ramcfg_11_02_40)
810 if (!next->bios.ramcfg_11_07_10)
812 if (!next->bios.ramcfg_11_07_08)
816 ram_mask(fuc, 0x10f824, mask, data);
819 if (next->bios.ramcfg_11_08_01)
823 ram_mask(fuc, 0x10f82c, 0x00100000, data);
826 ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
827 ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
828 ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
829 ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
830 ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
831 ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
832 ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
833 ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
834 ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
835 ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
836 ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
840 if (!next->bios.ramcfg_11_01_04)
842 if (!next->bios.ramcfg_11_07_80)
844 /*XXX: see note above about there probably being some condition
845 * for the 10f824 stuff that uses ramcfg 3...
847 if (next->bios.ramcfg_11_03_f0) {
848 if (next->bios.rammap_11_08_0c) {
849 if (!next->bios.ramcfg_11_07_80)
861 ram_mask(fuc, 0x10f808, mask, data);
863 ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
865 ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
867 data = (next->bios.timing[10] & 0x7f000000) >> 24;
868 if (data < next->bios.timing_20_2c_1fc0)
869 data = next->bios.timing_20_2c_1fc0;
870 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
872 ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
874 ram_wr32(fuc, 0x10f090, 0x4000007f);
877 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
878 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
879 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
882 ram_nuke(fuc, mr[0]);
883 ram_mask(fuc, mr[0], 0x100, 0x100);
884 ram_mask(fuc, mr[0], 0x100, 0x000);
886 ram_mask(fuc, mr[2], 0xfff, ram->base.mr[2]);
887 ram_wr32(fuc, mr[0], ram->base.mr[0]);
890 ram_nuke(fuc, mr[0]);
891 ram_mask(fuc, mr[0], 0x100, 0x100);
892 ram_mask(fuc, mr[0], 0x100, 0x000);
894 if (vc == 0 && ram_have(fuc, gpio2E)) {
895 u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
896 if (temp != ram_rd32(fuc, gpio2E)) {
897 ram_wr32(fuc, gpiotrig, 1);
898 ram_nsec(fuc, 20000);
902 if (ram->mode != 2) {
903 ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
904 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
907 ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
908 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
909 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
913 ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
915 if (next->bios.rammap_11_08_01)
919 ram_mask(fuc, 0x10f200, 0x00000800, data);
923 /*******************************************************************************
925 ******************************************************************************/
928 gk104_ram_calc_data(struct gk104_ram *ram, u32 khz, struct nvkm_ram_data *data)
930 struct nvkm_subdev *subdev = &ram->base.fb->subdev;
931 struct nvkm_ram_data *cfg;
932 u32 mhz = khz / 1000;
934 list_for_each_entry(cfg, &ram->cfg, head) {
935 if (mhz >= cfg->bios.rammap_min &&
936 mhz <= cfg->bios.rammap_max) {
943 nvkm_error(subdev, "ramcfg data for %dMHz not found\n", mhz);
948 gk104_ram_calc_xits(struct gk104_ram *ram, struct nvkm_ram_data *next)
950 struct gk104_ramfuc *fuc = &ram->fuc;
951 struct nvkm_subdev *subdev = &ram->base.fb->subdev;
955 ret = ram_init(fuc, ram->base.fb);
959 ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1;
960 ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f;
962 /* XXX: this is *not* what nvidia do. on fermi nvidia generally
963 * select, based on some unknown condition, one of the two possible
964 * reference frequencies listed in the vbios table for mempll and
965 * program refpll to that frequency.
967 * so far, i've seen very weird values being chosen by nvidia on
968 * kepler boards, no idea how/why they're chosen.
972 refclk = fuc->mempll.refclk;
974 /* calculate refpll coefficients */
975 ret = gt215_pll_calc(subdev, &fuc->refpll, refclk, &ram->N1,
976 &ram->fN1, &ram->M1, &ram->P1);
977 fuc->mempll.refclk = ret;
979 nvkm_error(subdev, "unable to calc refpll\n");
983 /* calculate mempll coefficients, if we're using it */
984 if (ram->mode == 2) {
985 /* post-divider doesn't work... the reg takes the values but
986 * appears to completely ignore it. there *is* a bit at
987 * bit 28 that appears to divide the clock by 2 if set.
989 fuc->mempll.min_p = 1;
990 fuc->mempll.max_p = 2;
992 ret = gt215_pll_calc(subdev, &fuc->mempll, next->freq,
993 &ram->N2, NULL, &ram->M2, &ram->P2);
995 nvkm_error(subdev, "unable to calc mempll\n");
1000 for (i = 0; i < ARRAY_SIZE(fuc->r_mr); i++) {
1001 if (ram_have(fuc, mr[i]))
1002 ram->base.mr[i] = ram_rd32(fuc, mr[i]);
1004 ram->base.freq = next->freq;
1006 switch (ram->base.type) {
1007 case NVKM_RAM_TYPE_DDR3:
1008 ret = nvkm_sddr3_calc(&ram->base);
1010 ret = gk104_ram_calc_sddr3(ram, next->freq);
1012 case NVKM_RAM_TYPE_GDDR5:
1013 ret = nvkm_gddr5_calc(&ram->base, ram->pnuts != 0);
1015 ret = gk104_ram_calc_gddr5(ram, next->freq);
1026 gk104_ram_calc(struct nvkm_ram *base, u32 freq)
1028 struct gk104_ram *ram = gk104_ram(base);
1029 struct nvkm_clk *clk = ram->base.fb->subdev.device->clk;
1030 struct nvkm_ram_data *xits = &ram->base.xition;
1031 struct nvkm_ram_data *copy;
1034 if (ram->base.next == NULL) {
1035 ret = gk104_ram_calc_data(ram,
1036 nvkm_clk_read(clk, nv_clk_src_mem),
1041 ret = gk104_ram_calc_data(ram, freq, &ram->base.target);
1045 if (ram->base.target.freq < ram->base.former.freq) {
1046 *xits = ram->base.target;
1047 copy = &ram->base.former;
1049 *xits = ram->base.former;
1050 copy = &ram->base.target;
1053 xits->bios.ramcfg_11_02_04 = copy->bios.ramcfg_11_02_04;
1054 xits->bios.ramcfg_11_02_03 = copy->bios.ramcfg_11_02_03;
1055 xits->bios.timing_20_30_07 = copy->bios.timing_20_30_07;
1057 ram->base.next = &ram->base.target;
1058 if (memcmp(xits, &ram->base.former, sizeof(xits->bios)))
1059 ram->base.next = &ram->base.xition;
1061 BUG_ON(ram->base.next != &ram->base.xition);
1062 ram->base.next = &ram->base.target;
1065 return gk104_ram_calc_xits(ram, ram->base.next);
1069 gk104_ram_prog_0(struct gk104_ram *ram, u32 freq)
1071 struct nvkm_device *device = ram->base.fb->subdev.device;
1072 struct nvkm_ram_data *cfg;
1073 u32 mhz = freq / 1000;
1076 list_for_each_entry(cfg, &ram->cfg, head) {
1077 if (mhz >= cfg->bios.rammap_min &&
1078 mhz <= cfg->bios.rammap_max)
1082 if (&cfg->head == &ram->cfg)
1085 if (mask = 0, data = 0, ram->diff.rammap_11_0a_03fe) {
1086 data |= cfg->bios.rammap_11_0a_03fe << 12;
1089 if (ram->diff.rammap_11_09_01ff) {
1090 data |= cfg->bios.rammap_11_09_01ff;
1093 nvkm_mask(device, 0x10f468, mask, data);
1095 if (mask = 0, data = 0, ram->diff.rammap_11_0a_0400) {
1096 data |= cfg->bios.rammap_11_0a_0400;
1099 nvkm_mask(device, 0x10f420, mask, data);
1101 if (mask = 0, data = 0, ram->diff.rammap_11_0a_0800) {
1102 data |= cfg->bios.rammap_11_0a_0800;
1105 nvkm_mask(device, 0x10f430, mask, data);
1107 if (mask = 0, data = 0, ram->diff.rammap_11_0b_01f0) {
1108 data |= cfg->bios.rammap_11_0b_01f0;
1111 nvkm_mask(device, 0x10f400, mask, data);
1113 if (mask = 0, data = 0, ram->diff.rammap_11_0b_0200) {
1114 data |= cfg->bios.rammap_11_0b_0200 << 9;
1117 nvkm_mask(device, 0x10f410, mask, data);
1119 if (mask = 0, data = 0, ram->diff.rammap_11_0d) {
1120 data |= cfg->bios.rammap_11_0d << 16;
1123 if (ram->diff.rammap_11_0f) {
1124 data |= cfg->bios.rammap_11_0f << 8;
1127 nvkm_mask(device, 0x10f440, mask, data);
1129 if (mask = 0, data = 0, ram->diff.rammap_11_0e) {
1130 data |= cfg->bios.rammap_11_0e << 8;
1133 if (ram->diff.rammap_11_0b_0800) {
1134 data |= cfg->bios.rammap_11_0b_0800 << 7;
1137 if (ram->diff.rammap_11_0b_0400) {
1138 data |= cfg->bios.rammap_11_0b_0400 << 5;
1141 nvkm_mask(device, 0x10f444, mask, data);
1145 gk104_ram_prog(struct nvkm_ram *base)
1147 struct gk104_ram *ram = gk104_ram(base);
1148 struct gk104_ramfuc *fuc = &ram->fuc;
1149 struct nvkm_device *device = ram->base.fb->subdev.device;
1150 struct nvkm_ram_data *next = ram->base.next;
1152 if (!nvkm_boolopt(device->cfgopt, "NvMemExec", true)) {
1153 ram_exec(fuc, false);
1154 return (ram->base.next == &ram->base.xition);
1157 gk104_ram_prog_0(ram, 1000);
1158 ram_exec(fuc, true);
1159 gk104_ram_prog_0(ram, next->freq);
1161 return (ram->base.next == &ram->base.xition);
1165 gk104_ram_tidy(struct nvkm_ram *base)
1167 struct gk104_ram *ram = gk104_ram(base);
1168 ram->base.next = NULL;
1169 ram_exec(&ram->fuc, false);
1172 struct gk104_ram_train {
1174 struct nvbios_M0209S remap;
1175 struct nvbios_M0209S type00;
1176 struct nvbios_M0209S type01;
1177 struct nvbios_M0209S type04;
1178 struct nvbios_M0209S type06;
1179 struct nvbios_M0209S type07;
1180 struct nvbios_M0209S type08;
1181 struct nvbios_M0209S type09;
1185 gk104_ram_train_type(struct nvkm_ram *ram, int i, u8 ramcfg,
1186 struct gk104_ram_train *train)
1188 struct nvkm_bios *bios = ram->fb->subdev.device->bios;
1189 struct nvbios_M0205E M0205E;
1190 struct nvbios_M0205S M0205S;
1191 struct nvbios_M0209E M0209E;
1192 struct nvbios_M0209S *remap = &train->remap;
1193 struct nvbios_M0209S *value;
1194 u8 ver, hdr, cnt, len;
1197 /* determine type of data for this index */
1198 if (!(data = nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E)))
1201 switch (M0205E.type) {
1202 case 0x00: value = &train->type00; break;
1203 case 0x01: value = &train->type01; break;
1204 case 0x04: value = &train->type04; break;
1205 case 0x06: value = &train->type06; break;
1206 case 0x07: value = &train->type07; break;
1207 case 0x08: value = &train->type08; break;
1208 case 0x09: value = &train->type09; break;
1213 /* training data index determined by ramcfg strap */
1214 if (!(data = nvbios_M0205Sp(bios, i, ramcfg, &ver, &hdr, &M0205S)))
1218 /* training data format information */
1219 if (!(data = nvbios_M0209Ep(bios, i, &ver, &hdr, &cnt, &len, &M0209E)))
1222 /* ... and the raw data */
1223 if (!(data = nvbios_M0209Sp(bios, i, 0, &ver, &hdr, value)))
1226 if (M0209E.v02_07 == 2) {
1227 /* of course! why wouldn't we have a pointer to another entry
1228 * in the same table, and use the first one as an array of
1231 if (!(data = nvbios_M0209Sp(bios, M0209E.v03, 0, &ver, &hdr,
1235 for (i = 0; i < ARRAY_SIZE(value->data); i++)
1236 value->data[i] = remap->data[value->data[i]];
1238 if (M0209E.v02_07 != 1)
1241 train->mask |= 1 << M0205E.type;
1246 gk104_ram_train_init_0(struct nvkm_ram *ram, struct gk104_ram_train *train)
1248 struct nvkm_subdev *subdev = &ram->fb->subdev;
1249 struct nvkm_device *device = subdev->device;
1252 if ((train->mask & 0x03d3) != 0x03d3) {
1253 nvkm_warn(subdev, "missing link training data\n");
1257 for (i = 0; i < 0x30; i++) {
1258 for (j = 0; j < 8; j += 4) {
1259 nvkm_wr32(device, 0x10f968 + j, 0x00000000 | (i << 8));
1260 nvkm_wr32(device, 0x10f920 + j, 0x00000000 |
1261 train->type08.data[i] << 4 |
1262 train->type06.data[i]);
1263 nvkm_wr32(device, 0x10f918 + j, train->type00.data[i]);
1264 nvkm_wr32(device, 0x10f920 + j, 0x00000100 |
1265 train->type09.data[i] << 4 |
1266 train->type07.data[i]);
1267 nvkm_wr32(device, 0x10f918 + j, train->type01.data[i]);
1271 for (j = 0; j < 8; j += 4) {
1272 for (i = 0; i < 0x100; i++) {
1273 nvkm_wr32(device, 0x10f968 + j, i);
1274 nvkm_wr32(device, 0x10f900 + j, train->type04.data[i]);
1282 gk104_ram_train_init(struct nvkm_ram *ram)
1284 u8 ramcfg = nvbios_ramcfg_index(&ram->fb->subdev);
1285 struct gk104_ram_train *train;
1288 if (!(train = kzalloc(sizeof(*train), GFP_KERNEL)))
1291 for (i = 0; i < 0x100; i++) {
1292 ret = gk104_ram_train_type(ram, i, ramcfg, train);
1293 if (ret && ret != -ENOENT)
1297 switch (ram->type) {
1298 case NVKM_RAM_TYPE_GDDR5:
1299 ret = gk104_ram_train_init_0(ram, train);
1311 gk104_ram_init(struct nvkm_ram *ram)
1313 struct nvkm_subdev *subdev = &ram->fb->subdev;
1314 struct nvkm_device *device = subdev->device;
1315 struct nvkm_bios *bios = device->bios;
1316 u8 ver, hdr, cnt, len, snr, ssz;
1320 /* run a bunch of tables from rammap table. there's actually
1321 * individual pointers for each rammap entry too, but, nvidia
1322 * seem to just run the last two entries' scripts early on in
1323 * their init, and never again.. we'll just run 'em all once
1326 * i strongly suspect that each script is for a separate mode
1327 * (likely selected by 0x10f65c's lower bits?), and the
1328 * binary driver skips the one that's already been setup by
1331 data = nvbios_rammapTe(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
1332 if (!data || hdr < 0x15)
1335 cnt = nvbios_rd08(bios, data + 0x14); /* guess at count */
1336 data = nvbios_rd32(bios, data + 0x10); /* guess u32... */
1337 save = nvkm_rd32(device, 0x10f65c) & 0x000000f0;
1338 for (i = 0; i < cnt; i++, data += 4) {
1339 if (i != save >> 4) {
1340 nvkm_mask(device, 0x10f65c, 0x000000f0, i << 4);
1341 nvbios_exec(&(struct nvbios_init) {
1344 .offset = nvbios_rd32(bios, data),
1349 nvkm_mask(device, 0x10f65c, 0x000000f0, save);
1350 nvkm_mask(device, 0x10f584, 0x11000000, 0x00000000);
1351 nvkm_wr32(device, 0x10ecc0, 0xffffffff);
1352 nvkm_mask(device, 0x10f160, 0x00000010, 0x00000010);
1354 return gk104_ram_train_init(ram);
1358 gk104_ram_ctor_data(struct gk104_ram *ram, u8 ramcfg, int i)
1360 struct nvkm_bios *bios = ram->base.fb->subdev.device->bios;
1361 struct nvkm_ram_data *cfg;
1362 struct nvbios_ramcfg *d = &ram->diff;
1363 struct nvbios_ramcfg *p, *n;
1364 u8 ver, hdr, cnt, len;
1368 if (!(cfg = kmalloc(sizeof(*cfg), GFP_KERNEL)))
1370 p = &list_last_entry(&ram->cfg, typeof(*cfg), head)->bios;
1373 /* memory config data for a range of target frequencies */
1374 data = nvbios_rammapEp(bios, i, &ver, &hdr, &cnt, &len, &cfg->bios);
1375 if (ret = -ENOENT, !data)
1377 if (ret = -ENOSYS, ver != 0x11 || hdr < 0x12)
1380 /* ... and a portion specific to the attached memory */
1381 data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, ramcfg,
1382 &ver, &hdr, &cfg->bios);
1383 if (ret = -EINVAL, !data)
1385 if (ret = -ENOSYS, ver != 0x11 || hdr < 0x0a)
1388 /* lookup memory timings, if bios says they're present */
1389 if (cfg->bios.ramcfg_timing != 0xff) {
1390 data = nvbios_timingEp(bios, cfg->bios.ramcfg_timing,
1391 &ver, &hdr, &cnt, &len,
1393 if (ret = -EINVAL, !data)
1395 if (ret = -ENOSYS, ver != 0x20 || hdr < 0x33)
1399 list_add_tail(&cfg->head, &ram->cfg);
1400 if (ret = 0, i == 0)
1403 d->rammap_11_0a_03fe |= p->rammap_11_0a_03fe != n->rammap_11_0a_03fe;
1404 d->rammap_11_09_01ff |= p->rammap_11_09_01ff != n->rammap_11_09_01ff;
1405 d->rammap_11_0a_0400 |= p->rammap_11_0a_0400 != n->rammap_11_0a_0400;
1406 d->rammap_11_0a_0800 |= p->rammap_11_0a_0800 != n->rammap_11_0a_0800;
1407 d->rammap_11_0b_01f0 |= p->rammap_11_0b_01f0 != n->rammap_11_0b_01f0;
1408 d->rammap_11_0b_0200 |= p->rammap_11_0b_0200 != n->rammap_11_0b_0200;
1409 d->rammap_11_0d |= p->rammap_11_0d != n->rammap_11_0d;
1410 d->rammap_11_0f |= p->rammap_11_0f != n->rammap_11_0f;
1411 d->rammap_11_0e |= p->rammap_11_0e != n->rammap_11_0e;
1412 d->rammap_11_0b_0800 |= p->rammap_11_0b_0800 != n->rammap_11_0b_0800;
1413 d->rammap_11_0b_0400 |= p->rammap_11_0b_0400 != n->rammap_11_0b_0400;
1414 d->ramcfg_11_01_01 |= p->ramcfg_11_01_01 != n->ramcfg_11_01_01;
1415 d->ramcfg_11_01_02 |= p->ramcfg_11_01_02 != n->ramcfg_11_01_02;
1416 d->ramcfg_11_01_10 |= p->ramcfg_11_01_10 != n->ramcfg_11_01_10;
1417 d->ramcfg_11_02_03 |= p->ramcfg_11_02_03 != n->ramcfg_11_02_03;
1418 d->ramcfg_11_08_20 |= p->ramcfg_11_08_20 != n->ramcfg_11_08_20;
1419 d->timing_20_30_07 |= p->timing_20_30_07 != n->timing_20_30_07;
1427 gk104_ram_dtor(struct nvkm_ram *base)
1429 struct gk104_ram *ram = gk104_ram(base);
1430 struct nvkm_ram_data *cfg, *tmp;
1432 list_for_each_entry_safe(cfg, tmp, &ram->cfg, head) {
1439 static const struct nvkm_ram_func
1441 .dtor = gk104_ram_dtor,
1442 .init = gk104_ram_init,
1443 .get = gf100_ram_get,
1444 .put = gf100_ram_put,
1445 .calc = gk104_ram_calc,
1446 .prog = gk104_ram_prog,
1447 .tidy = gk104_ram_tidy,
1451 gk104_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)
1453 struct nvkm_subdev *subdev = &fb->subdev;
1454 struct nvkm_device *device = subdev->device;
1455 struct nvkm_bios *bios = device->bios;
1456 struct nvkm_gpio *gpio = device->gpio;
1457 struct dcb_gpio_func func;
1458 struct gk104_ram *ram;
1460 u8 ramcfg = nvbios_ramcfg_index(subdev);
1463 if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL)))
1467 ret = gf100_ram_ctor(&gk104_ram_func, fb, 0x022554, &ram->base);
1471 INIT_LIST_HEAD(&ram->cfg);
1473 /* calculate a mask of differently configured memory partitions,
1474 * because, of course reclocking wasn't complicated enough
1475 * already without having to treat some of them differently to
1478 ram->parts = nvkm_rd32(device, 0x022438);
1479 ram->pmask = nvkm_rd32(device, 0x022554);
1481 for (i = 0, tmp = 0; i < ram->parts; i++) {
1482 if (!(ram->pmask & (1 << i))) {
1483 u32 cfg1 = nvkm_rd32(device, 0x110204 + (i * 0x1000));
1484 if (tmp && tmp != cfg1) {
1485 ram->pnuts |= (1 << i);
1492 /* parse bios data for all rammap table entries up-front, and
1493 * build information on whether certain fields differ between
1494 * any of the entries.
1496 * the binary driver appears to completely ignore some fields
1497 * when all entries contain the same value. at first, it was
1498 * hoped that these were mere optimisations and the bios init
1499 * tables had configured as per the values here, but there is
1500 * evidence now to suggest that this isn't the case and we do
1501 * need to treat this condition as a "don't touch" indicator.
1503 for (i = 0; !ret; i++) {
1504 ret = gk104_ram_ctor_data(ram, ramcfg, i);
1505 if (ret && ret != -ENOENT) {
1506 nvkm_error(subdev, "failed to parse ramcfg data\n");
1511 /* parse bios data for both pll's */
1512 ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll);
1514 nvkm_error(subdev, "mclk refpll data not found\n");
1518 ret = nvbios_pll_parse(bios, 0x04, &ram->fuc.mempll);
1520 nvkm_error(subdev, "mclk pll data not found\n");
1524 /* lookup memory voltage gpios */
1525 ret = nvkm_gpio_find(gpio, 0, 0x18, DCB_GPIO_UNUSED, &func);
1527 ram->fuc.r_gpioMV = ramfuc_reg(0x00d610 + (func.line * 0x04));
1528 ram->fuc.r_funcMV[0] = (func.log[0] ^ 2) << 12;
1529 ram->fuc.r_funcMV[1] = (func.log[1] ^ 2) << 12;
1532 ret = nvkm_gpio_find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func);
1534 ram->fuc.r_gpio2E = ramfuc_reg(0x00d610 + (func.line * 0x04));
1535 ram->fuc.r_func2E[0] = (func.log[0] ^ 2) << 12;
1536 ram->fuc.r_func2E[1] = (func.log[1] ^ 2) << 12;
1539 ram->fuc.r_gpiotrig = ramfuc_reg(0x00d604);
1541 ram->fuc.r_0x132020 = ramfuc_reg(0x132020);
1542 ram->fuc.r_0x132028 = ramfuc_reg(0x132028);
1543 ram->fuc.r_0x132024 = ramfuc_reg(0x132024);
1544 ram->fuc.r_0x132030 = ramfuc_reg(0x132030);
1545 ram->fuc.r_0x132034 = ramfuc_reg(0x132034);
1546 ram->fuc.r_0x132000 = ramfuc_reg(0x132000);
1547 ram->fuc.r_0x132004 = ramfuc_reg(0x132004);
1548 ram->fuc.r_0x132040 = ramfuc_reg(0x132040);
1550 ram->fuc.r_0x10f248 = ramfuc_reg(0x10f248);
1551 ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290);
1552 ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294);
1553 ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298);
1554 ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c);
1555 ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0);
1556 ram->fuc.r_0x10f2a4 = ramfuc_reg(0x10f2a4);
1557 ram->fuc.r_0x10f2a8 = ramfuc_reg(0x10f2a8);
1558 ram->fuc.r_0x10f2ac = ramfuc_reg(0x10f2ac);
1559 ram->fuc.r_0x10f2cc = ramfuc_reg(0x10f2cc);
1560 ram->fuc.r_0x10f2e8 = ramfuc_reg(0x10f2e8);
1561 ram->fuc.r_0x10f250 = ramfuc_reg(0x10f250);
1562 ram->fuc.r_0x10f24c = ramfuc_reg(0x10f24c);
1563 ram->fuc.r_0x10fec4 = ramfuc_reg(0x10fec4);
1564 ram->fuc.r_0x10fec8 = ramfuc_reg(0x10fec8);
1565 ram->fuc.r_0x10f604 = ramfuc_reg(0x10f604);
1566 ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614);
1567 ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610);
1568 ram->fuc.r_0x100770 = ramfuc_reg(0x100770);
1569 ram->fuc.r_0x100778 = ramfuc_reg(0x100778);
1570 ram->fuc.r_0x10f224 = ramfuc_reg(0x10f224);
1572 ram->fuc.r_0x10f870 = ramfuc_reg(0x10f870);
1573 ram->fuc.r_0x10f698 = ramfuc_reg(0x10f698);
1574 ram->fuc.r_0x10f694 = ramfuc_reg(0x10f694);
1575 ram->fuc.r_0x10f6b8 = ramfuc_reg(0x10f6b8);
1576 ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808);
1577 ram->fuc.r_0x10f670 = ramfuc_reg(0x10f670);
1578 ram->fuc.r_0x10f60c = ramfuc_reg(0x10f60c);
1579 ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830);
1580 ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec);
1581 ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800);
1582 ram->fuc.r_0x10f82c = ramfuc_reg(0x10f82c);
1584 ram->fuc.r_0x10f978 = ramfuc_reg(0x10f978);
1585 ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910);
1586 ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914);
1588 switch (ram->base.type) {
1589 case NVKM_RAM_TYPE_GDDR5:
1590 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
1591 ram->fuc.r_mr[1] = ramfuc_reg(0x10f330);
1592 ram->fuc.r_mr[2] = ramfuc_reg(0x10f334);
1593 ram->fuc.r_mr[3] = ramfuc_reg(0x10f338);
1594 ram->fuc.r_mr[4] = ramfuc_reg(0x10f33c);
1595 ram->fuc.r_mr[5] = ramfuc_reg(0x10f340);
1596 ram->fuc.r_mr[6] = ramfuc_reg(0x10f344);
1597 ram->fuc.r_mr[7] = ramfuc_reg(0x10f348);
1598 ram->fuc.r_mr[8] = ramfuc_reg(0x10f354);
1599 ram->fuc.r_mr[15] = ramfuc_reg(0x10f34c);
1601 case NVKM_RAM_TYPE_DDR3:
1602 ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
1603 ram->fuc.r_mr[2] = ramfuc_reg(0x10f320);
1609 ram->fuc.r_0x62c000 = ramfuc_reg(0x62c000);
1610 ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200);
1611 ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210);
1612 ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310);
1613 ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314);
1614 ram->fuc.r_0x10f318 = ramfuc_reg(0x10f318);
1615 ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090);
1616 ram->fuc.r_0x10f69c = ramfuc_reg(0x10f69c);
1617 ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824);
1618 ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0);
1619 ram->fuc.r_0x1373f4 = ramfuc_reg(0x1373f4);
1620 ram->fuc.r_0x137320 = ramfuc_reg(0x137320);
1621 ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c);
1622 ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc);
1623 ram->fuc.r_0x100710 = ramfuc_reg(0x100710);
1624 ram->fuc.r_0x100750 = ramfuc_reg(0x100750);