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25 #include <subdev/fb.h>
26 #include <subdev/gsp.h>
27 #include <subdev/instmem.h>
28 #include <subdev/mmu/vmm.h>
30 #include <nvrm/nvtypes.h>
31 #include <nvrm/535.113.01/nvidia/generated/g_rpc-structures.h>
32 #include <nvrm/535.113.01/nvidia/kernel/inc/vgpu/rpc_global_enums.h>
33 #include <nvrm/535.113.01/nvidia/kernel/inc/vgpu/rpc_headers.h>
36 r535_bar_flush(struct nvkm_bar *bar)
38 ioread32_native(bar->flushBAR2);
42 r535_bar_bar2_wait(struct nvkm_bar *base)
47 r535_bar_bar2_update_pde(struct nvkm_gsp *gsp, u64 addr)
49 rpc_update_bar_pde_v15_00 *rpc;
51 rpc = nvkm_gsp_rpc_get(gsp, NV_VGPU_MSG_FUNCTION_UPDATE_BAR_PDE, sizeof(*rpc));
52 if (WARN_ON(IS_ERR_OR_NULL(rpc)))
55 rpc->info.barType = NV_RPC_UPDATE_PDE_BAR_2;
56 rpc->info.entryValue = addr ? ((addr >> 4) | 2) : 0; /* PD3 entry format! */
57 rpc->info.entryLevelShift = 47; //XXX: probably fetch this from mmu!
59 return nvkm_gsp_rpc_wr(gsp, rpc, true);
63 r535_bar_bar2_fini(struct nvkm_bar *bar)
65 struct nvkm_gsp *gsp = bar->subdev.device->gsp;
67 bar->flushBAR2 = bar->flushBAR2PhysMode;
68 nvkm_done(bar->flushFBZero);
70 WARN_ON(r535_bar_bar2_update_pde(gsp, 0));
74 r535_bar_bar2_init(struct nvkm_bar *bar)
76 struct nvkm_device *device = bar->subdev.device;
77 struct nvkm_vmm *vmm = gf100_bar(bar)->bar[0].vmm;
78 struct nvkm_gsp *gsp = device->gsp;
80 WARN_ON(r535_bar_bar2_update_pde(gsp, vmm->pd->pde[0]->pt[0]->addr));
81 vmm->rm.bar2_pdb = gsp->bar.rm_bar2_pdb;
83 if (!bar->flushFBZero) {
84 struct nvkm_memory *fbZero;
87 ret = nvkm_ram_wrap(device, 0, 0x1000, &fbZero);
89 ret = nvkm_memory_kmap(fbZero, &bar->flushFBZero);
90 nvkm_memory_unref(&fbZero);
96 bar->flushBAR2 = nvkm_kmap(bar->flushFBZero);
97 WARN_ON(!bar->flushBAR2);
101 r535_bar_bar1_wait(struct nvkm_bar *base)
106 r535_bar_bar1_fini(struct nvkm_bar *base)
111 r535_bar_bar1_init(struct nvkm_bar *bar)
113 struct nvkm_device *device = bar->subdev.device;
114 struct nvkm_gsp *gsp = device->gsp;
115 struct nvkm_vmm *vmm = gf100_bar(bar)->bar[1].vmm;
116 struct nvkm_memory *pd3;
119 ret = nvkm_ram_wrap(device, gsp->bar.rm_bar1_pdb, 0x1000, &pd3);
123 nvkm_memory_unref(&vmm->pd->pt[0]->memory);
125 ret = nvkm_memory_kmap(pd3, &vmm->pd->pt[0]->memory);
126 nvkm_memory_unref(&pd3);
130 vmm->pd->pt[0]->addr = nvkm_memory_addr(vmm->pd->pt[0]->memory);
134 r535_bar_dtor(struct nvkm_bar *bar)
136 void *data = gf100_bar_dtor(bar);
138 nvkm_memory_unref(&bar->flushFBZero);
140 if (bar->flushBAR2PhysMode)
141 iounmap(bar->flushBAR2PhysMode);
148 r535_bar_new_(const struct nvkm_bar_func *hw, struct nvkm_device *device,
149 enum nvkm_subdev_type type, int inst, struct nvkm_bar **pbar)
151 struct nvkm_bar_func *rm;
152 struct nvkm_bar *bar;
155 if (!(rm = kzalloc(sizeof(*rm), GFP_KERNEL)))
158 rm->dtor = r535_bar_dtor;
159 rm->oneinit = hw->oneinit;
160 rm->bar1.init = r535_bar_bar1_init;
161 rm->bar1.fini = r535_bar_bar1_fini;
162 rm->bar1.wait = r535_bar_bar1_wait;
163 rm->bar1.vmm = hw->bar1.vmm;
164 rm->bar2.init = r535_bar_bar2_init;
165 rm->bar2.fini = r535_bar_bar2_fini;
166 rm->bar2.wait = r535_bar_bar2_wait;
167 rm->bar2.vmm = hw->bar2.vmm;
168 rm->flush = r535_bar_flush;
170 ret = gf100_bar_new_(rm, device, type, inst, &bar);
177 bar->flushBAR2PhysMode = ioremap(device->func->resource_addr(device, 3), PAGE_SIZE);
178 if (!bar->flushBAR2PhysMode)
181 bar->flushBAR2 = bar->flushBAR2PhysMode;
183 gf100_bar(*pbar)->bar2_halve = true;