drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c

   1 /*
   2  * Copyright 2019 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "gf100.h"
  23 #include "ctxgf100.h"
  24
  25 #include <nvif/class.h>
  26
  27 void
  28 tu102_gr_init_fecs_exceptions(struct gf100_gr *gr)
  29 {
  30         nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x006e0003);
  31 }
  32
  33 void
  34 tu102_gr_init_fs(struct gf100_gr *gr)
  35 {
  36         struct nvkm_device *device = gr->base.engine.subdev.device;
  37         int sm;
  38
  39         gp100_grctx_generate_smid_config(gr);
  40         gk104_grctx_generate_gpc_tpc_nr(gr);
  41
  42         for (sm = 0; sm < gr->sm_nr; sm++) {
  43                 int tpc = gv100_gr_nonpes_aware_tpc(gr, gr->sm[sm].gpc, gr->sm[sm].tpc);
  44
  45                 nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + tpc * 4), sm);
  46         }
  47
  48         gm200_grctx_generate_dist_skip_table(gr);
  49         gf100_gr_init_num_tpc_per_gpc(gr, true, true);
  50 }
  51
  52 void
  53 tu102_gr_init_zcull(struct gf100_gr *gr)
  54 {
  55         struct nvkm_device *device = gr->base.engine.subdev.device;
  56         const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
  57         const u8 tile_nr = gr->func->gpc_nr * gr->func->tpc_nr;
  58         u8 bank[GPC_MAX] = {}, gpc, i, j;
  59         u32 data;
  60
  61         for (i = 0; i < tile_nr; i += 8) {
  62                 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {
  63                         data |= bank[gr->tile[i + j]] << (j * 4);
  64                         bank[gr->tile[i + j]]++;
  65                 }
  66                 nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);
  67         }
  68
  69         for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
  70                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
  71                           gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
  72                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
  73                                                          gr->tpc_total);
  74                 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
  75         }
  76
  77         nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
  78 }
  79
  80 static void
  81 tu102_gr_init_gpc_mmu(struct gf100_gr *gr)
  82 {
  83         struct nvkm_device *device = gr->base.engine.subdev.device;
  84
  85         nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf8001fff);
  86         nvkm_wr32(device, 0x418890, 0x00000000);
  87         nvkm_wr32(device, 0x418894, 0x00000000);
  88
  89         nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));
  90         nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));
  91         nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
  92 }
  93
  94 static const struct gf100_gr_func
  95 tu102_gr = {
  96         .oneinit_tiles = gm200_gr_oneinit_tiles,
  97         .oneinit_sm_id = gv100_gr_oneinit_sm_id,
  98         .init = gf100_gr_init,
  99         .init_419bd8 = gv100_gr_init_419bd8,
 100         .init_gpc_mmu = tu102_gr_init_gpc_mmu,
 101         .init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
 102         .init_zcull = tu102_gr_init_zcull,
 103         .init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
 104         .init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
 105         .init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
 106         .init_fs = tu102_gr_init_fs,
 107         .init_fecs_exceptions = tu102_gr_init_fecs_exceptions,
 108         .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
 109         .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
 110         .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
 111         .init_504430 = gv100_gr_init_504430,
 112         .init_shader_exceptions = gv100_gr_init_shader_exceptions,
 113         .init_rop_exceptions = gf100_gr_init_rop_exceptions,
 114         .init_exception2 = gf100_gr_init_exception2,
 115         .init_4188a4 = gv100_gr_init_4188a4,
 116         .trap_mp = gv100_gr_trap_mp,
 117         .fecs.reset = gf100_gr_fecs_reset,
 118         .rops = gm200_gr_rops,
 119         .gpc_nr = 6,
 120         .tpc_nr = 6,
 121         .ppc_nr = 3,
 122         .grctx = &tu102_grctx,
 123         .zbc = &gp102_gr_zbc,
 124         .sclass = {
 125                 { -1, -1, FERMI_TWOD_A },
 126                 { -1, -1, KEPLER_INLINE_TO_MEMORY_B },
 127                 { -1, -1, TURING_A, &gf100_fermi },
 128                 { -1, -1, TURING_COMPUTE_A },
 129                 {}
 130         }
 131 };
 132
 133 MODULE_FIRMWARE("nvidia/tu102/gr/fecs_bl.bin");
 134 MODULE_FIRMWARE("nvidia/tu102/gr/fecs_inst.bin");
 135 MODULE_FIRMWARE("nvidia/tu102/gr/fecs_data.bin");
 136 MODULE_FIRMWARE("nvidia/tu102/gr/fecs_sig.bin");
 137 MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_bl.bin");
 138 MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_inst.bin");
 139 MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_data.bin");
 140 MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_sig.bin");
 141 MODULE_FIRMWARE("nvidia/tu102/gr/sw_ctx.bin");
 142 MODULE_FIRMWARE("nvidia/tu102/gr/sw_nonctx.bin");
 143 MODULE_FIRMWARE("nvidia/tu102/gr/sw_bundle_init.bin");
 144 MODULE_FIRMWARE("nvidia/tu102/gr/sw_method_init.bin");
 145 MODULE_FIRMWARE("nvidia/tu102/gr/sw_veid_bundle_init.bin");
 146
 147 MODULE_FIRMWARE("nvidia/tu104/gr/fecs_bl.bin");
 148 MODULE_FIRMWARE("nvidia/tu104/gr/fecs_inst.bin");
 149 MODULE_FIRMWARE("nvidia/tu104/gr/fecs_data.bin");
 150 MODULE_FIRMWARE("nvidia/tu104/gr/fecs_sig.bin");
 151 MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_bl.bin");
 152 MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_inst.bin");
 153 MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_data.bin");
 154 MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_sig.bin");
 155 MODULE_FIRMWARE("nvidia/tu104/gr/sw_ctx.bin");
 156 MODULE_FIRMWARE("nvidia/tu104/gr/sw_nonctx.bin");
 157 MODULE_FIRMWARE("nvidia/tu104/gr/sw_bundle_init.bin");
 158 MODULE_FIRMWARE("nvidia/tu104/gr/sw_method_init.bin");
 159 MODULE_FIRMWARE("nvidia/tu104/gr/sw_veid_bundle_init.bin");
 160
 161 MODULE_FIRMWARE("nvidia/tu106/gr/fecs_bl.bin");
 162 MODULE_FIRMWARE("nvidia/tu106/gr/fecs_inst.bin");
 163 MODULE_FIRMWARE("nvidia/tu106/gr/fecs_data.bin");
 164 MODULE_FIRMWARE("nvidia/tu106/gr/fecs_sig.bin");
 165 MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_bl.bin");
 166 MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_inst.bin");
 167 MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_data.bin");
 168 MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_sig.bin");
 169 MODULE_FIRMWARE("nvidia/tu106/gr/sw_ctx.bin");
 170 MODULE_FIRMWARE("nvidia/tu106/gr/sw_nonctx.bin");
 171 MODULE_FIRMWARE("nvidia/tu106/gr/sw_bundle_init.bin");
 172 MODULE_FIRMWARE("nvidia/tu106/gr/sw_method_init.bin");
 173 MODULE_FIRMWARE("nvidia/tu106/gr/sw_veid_bundle_init.bin");
 174
 175 MODULE_FIRMWARE("nvidia/tu117/gr/fecs_bl.bin");
 176 MODULE_FIRMWARE("nvidia/tu117/gr/fecs_inst.bin");
 177 MODULE_FIRMWARE("nvidia/tu117/gr/fecs_data.bin");
 178 MODULE_FIRMWARE("nvidia/tu117/gr/fecs_sig.bin");
 179 MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_bl.bin");
 180 MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_inst.bin");
 181 MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_data.bin");
 182 MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_sig.bin");
 183 MODULE_FIRMWARE("nvidia/tu117/gr/sw_ctx.bin");
 184 MODULE_FIRMWARE("nvidia/tu117/gr/sw_nonctx.bin");
 185 MODULE_FIRMWARE("nvidia/tu117/gr/sw_bundle_init.bin");
 186 MODULE_FIRMWARE("nvidia/tu117/gr/sw_method_init.bin");
 187 MODULE_FIRMWARE("nvidia/tu117/gr/sw_veid_bundle_init.bin");
 188
 189 MODULE_FIRMWARE("nvidia/tu116/gr/fecs_bl.bin");
 190 MODULE_FIRMWARE("nvidia/tu116/gr/fecs_inst.bin");
 191 MODULE_FIRMWARE("nvidia/tu116/gr/fecs_data.bin");
 192 MODULE_FIRMWARE("nvidia/tu116/gr/fecs_sig.bin");
 193 MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_bl.bin");
 194 MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_inst.bin");
 195 MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_data.bin");
 196 MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_sig.bin");
 197 MODULE_FIRMWARE("nvidia/tu116/gr/sw_ctx.bin");
 198 MODULE_FIRMWARE("nvidia/tu116/gr/sw_nonctx.bin");
 199 MODULE_FIRMWARE("nvidia/tu116/gr/sw_bundle_init.bin");
 200 MODULE_FIRMWARE("nvidia/tu116/gr/sw_method_init.bin");
 201 MODULE_FIRMWARE("nvidia/tu116/gr/sw_veid_bundle_init.bin");
 202
 203 int
 204 tu102_gr_av_to_init_veid(struct nvkm_blob *blob, struct gf100_gr_pack **ppack)
 205 {
 206         return gk20a_gr_av_to_init_(blob, 64, 0x00100000, ppack);
 207 }
 208
 209 int
 210 tu102_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
 211 {
 212         int ret;
 213
 214         ret = gm200_gr_load(gr, ver, fwif);
 215         if (ret)
 216                 return ret;
 217
 218         return gk20a_gr_load_net(gr, "gr/", "sw_veid_bundle_init", ver, tu102_gr_av_to_init_veid,
 219                                  &gr->bundle_veid);
 220 }
 221
 222 static const struct gf100_gr_fwif
 223 tu102_gr_fwif[] = {
 224         {  0, gm200_gr_load, &tu102_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr },
 225         { -1, gm200_gr_nofw },
 226         {}
 227 };
 228
 229 int
 230 tu102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
 231 {
 232         return gf100_gr_new_(tu102_gr_fwif, device, type, inst, pgr);
 233 }