drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c

   1 /*
   2  * Copyright 2016 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "priv.h"
  25 #include "chan.h"
  26 #include "gk104.h"
  27 #include "changk104.h"
  28
  29 #include <core/gpuobj.h>
  30 #include <subdev/fault.h>
  31
  32 #include <nvif/class.h>
  33
  34 const struct nvkm_chan_func
  35 gm107_chan = {
  36 };
  37
  38 static void
  39 gm107_fifo_runlist_chan(struct gk104_fifo_chan *chan,
  40                         struct nvkm_memory *memory, u32 offset)
  41 {
  42         nvkm_wo32(memory, offset + 0, chan->base.chid);
  43         nvkm_wo32(memory, offset + 4, chan->base.inst->addr >> 12);
  44 }
  45
  46 const struct gk104_fifo_runlist_func
  47 gm107_fifo_runlist = {
  48         .size = 8,
  49         .cgrp = gk110_fifo_runlist_cgrp,
  50         .chan = gm107_fifo_runlist_chan,
  51         .commit = gk104_fifo_runlist_commit,
  52 };
  53
  54 const struct nvkm_enum
  55 gm107_fifo_fault_engine[] = {
  56         { 0x01, "DISPLAY" },
  57         { 0x02, "CAPTURE" },
  58         { 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
  59         { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
  60         { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
  61         { 0x06, "SCHED" },
  62         { 0x07, "HOST0", NULL, NVKM_ENGINE_FIFO },
  63         { 0x08, "HOST1", NULL, NVKM_ENGINE_FIFO },
  64         { 0x09, "HOST2", NULL, NVKM_ENGINE_FIFO },
  65         { 0x0a, "HOST3", NULL, NVKM_ENGINE_FIFO },
  66         { 0x0b, "HOST4", NULL, NVKM_ENGINE_FIFO },
  67         { 0x0c, "HOST5", NULL, NVKM_ENGINE_FIFO },
  68         { 0x0d, "HOST6", NULL, NVKM_ENGINE_FIFO },
  69         { 0x0e, "HOST7", NULL, NVKM_ENGINE_FIFO },
  70         { 0x0f, "HOSTSR" },
  71         { 0x13, "PERF" },
  72         { 0x17, "PMU" },
  73         { 0x18, "PTP" },
  74         {}
  75 };
  76
  77 const struct nvkm_fifo_func_mmu_fault
  78 gm107_fifo_mmu_fault = {
  79         .recover = gk104_fifo_fault,
  80 };
  81
  82 void
  83 gm107_fifo_intr_mmu_fault_unit(struct nvkm_fifo *fifo, int unit)
  84 {
  85         struct nvkm_device *device = fifo->engine.subdev.device;
  86         u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
  87         u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
  88         u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
  89         u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10));
  90         struct nvkm_fault_data info;
  91
  92         info.inst   =  (u64)inst << 12;
  93         info.addr   = ((u64)vahi << 32) | valo;
  94         info.time   = 0;
  95         info.engine = unit;
  96         info.valid  = 1;
  97         info.gpc    = (type & 0x1f000000) >> 24;
  98         info.client = (type & 0x00003f00) >> 8;
  99         info.access = (type & 0x00000080) >> 7;
 100         info.hub    = (type & 0x00000040) >> 6;
 101         info.reason = (type & 0x0000000f);
 102
 103         nvkm_fifo_fault(fifo, &info);
 104 }
 105
 106 static int
 107 gm107_fifo_chid_nr(struct nvkm_fifo *fifo)
 108 {
 109         return 2048;
 110 }
 111
 112 static const struct nvkm_fifo_func
 113 gm107_fifo = {
 114         .dtor = gk104_fifo_dtor,
 115         .oneinit = gk104_fifo_oneinit,
 116         .chid_nr = gm107_fifo_chid_nr,
 117         .chid_ctor = gk110_fifo_chid_ctor,
 118         .runq_nr = gf100_fifo_runq_nr,
 119         .info = gk104_fifo_info,
 120         .init = gk104_fifo_init,
 121         .fini = gk104_fifo_fini,
 122         .intr = gk104_fifo_intr,
 123         .intr_mmu_fault_unit = gm107_fifo_intr_mmu_fault_unit,
 124         .mmu_fault = &gm107_fifo_mmu_fault,
 125         .fault.access = gk104_fifo_fault_access,
 126         .fault.engine = gm107_fifo_fault_engine,
 127         .fault.reason = gk104_fifo_fault_reason,
 128         .fault.hubclient = gk104_fifo_fault_hubclient,
 129         .fault.gpcclient = gk104_fifo_fault_gpcclient,
 130         .engine_id = gk104_fifo_engine_id,
 131         .id_engine = gk104_fifo_id_engine,
 132         .uevent_init = gk104_fifo_uevent_init,
 133         .uevent_fini = gk104_fifo_uevent_fini,
 134         .recover_chan = gk104_fifo_recover_chan,
 135         .runlist = &gm107_fifo_runlist,
 136         .pbdma = &gk208_fifo_pbdma,
 137         .runq = &gk208_runq,
 138         .cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A  }, &gk110_cgrp },
 139         .chan = {{ 0, 0, KEPLER_CHANNEL_GPFIFO_B }, &gm107_chan, .ctor = &gk104_fifo_gpfifo_new },
 140 };
 141
 142 int
 143 gm107_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
 144                struct nvkm_fifo **pfifo)
 145 {
 146         return gk104_fifo_new_(&gm107_fifo, device, type, inst, 0, pfifo);
 147 }