drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "chan.h"
  25 #include "chid.h"
  26
  27 #include "gf100.h"
  28 #include "changf100.h"
  29
  30 #include <core/client.h>
  31 #include <core/enum.h>
  32 #include <core/gpuobj.h>
  33 #include <subdev/bar.h>
  34 #include <subdev/fault.h>
  35 #include <engine/sw.h>
  36
  37 #include <nvif/class.h>
  38
  39 static void
  40 gf100_fifo_uevent_init(struct nvkm_fifo *fifo)
  41 {
  42         struct nvkm_device *device = fifo->engine.subdev.device;
  43         nvkm_mask(device, 0x002140, 0x80000000, 0x80000000);
  44 }
  45
  46 static void
  47 gf100_fifo_uevent_fini(struct nvkm_fifo *fifo)
  48 {
  49         struct nvkm_device *device = fifo->engine.subdev.device;
  50         nvkm_mask(device, 0x002140, 0x80000000, 0x00000000);
  51 }
  52
  53 static const struct nvkm_chan_func
  54 gf100_chan = {
  55 };
  56
  57 static const struct nvkm_bitfield
  58 gf100_fifo_pbdma_intr[] = {
  59 /*      { 0x00008000, "" }      seen with null ib push */
  60         { 0x00200000, "ILLEGAL_MTHD" },
  61         { 0x00800000, "EMPTY_SUBC" },
  62         {}
  63 };
  64
  65 static void
  66 gf100_fifo_intr_pbdma(struct gf100_fifo *fifo, int unit)
  67 {
  68         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
  69         struct nvkm_device *device = subdev->device;
  70         u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000));
  71         u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000));
  72         u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000));
  73         u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0x7f;
  74         u32 subc = (addr & 0x00070000) >> 16;
  75         u32 mthd = (addr & 0x00003ffc);
  76         struct nvkm_fifo_chan *chan;
  77         unsigned long flags;
  78         u32 show = stat;
  79         char msg[128];
  80
  81         if (stat & 0x00800000) {
  82                 if (device->sw) {
  83                         if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data))
  84                                 show &= ~0x00800000;
  85                 }
  86         }
  87
  88         if (show) {
  89                 nvkm_snprintbf(msg, sizeof(msg), gf100_fifo_pbdma_intr, show);
  90                 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags);
  91                 nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%010llx %s] "
  92                                    "subc %d mthd %04x data %08x\n",
  93                            unit, show, msg, chid, chan ? chan->inst->addr : 0,
  94                            chan ? chan->object.client->name : "unknown",
  95                            subc, mthd, data);
  96                 nvkm_fifo_chan_put(&fifo->base, flags, &chan);
  97         }
  98
  99         nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008);
 100         nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat);
 101 }
 102
 103 void
 104 gf100_fifo_runlist_commit(struct gf100_fifo *fifo)
 105 {
 106         struct gf100_fifo_chan *chan;
 107         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 108         struct nvkm_device *device = subdev->device;
 109         struct nvkm_memory *cur;
 110         int nr = 0;
 111         int target;
 112
 113         mutex_lock(&fifo->base.mutex);
 114         cur = fifo->runlist.mem[fifo->runlist.active];
 115         fifo->runlist.active = !fifo->runlist.active;
 116
 117         nvkm_kmap(cur);
 118         list_for_each_entry(chan, &fifo->chan, head) {
 119                 nvkm_wo32(cur, (nr * 8) + 0, chan->base.chid);
 120                 nvkm_wo32(cur, (nr * 8) + 4, 0x00000004);
 121                 nr++;
 122         }
 123         nvkm_done(cur);
 124
 125         switch (nvkm_memory_target(cur)) {
 126         case NVKM_MEM_TARGET_VRAM: target = 0; break;
 127         case NVKM_MEM_TARGET_NCOH: target = 3; break;
 128         default:
 129                 mutex_unlock(&fifo->base.mutex);
 130                 WARN_ON(1);
 131                 return;
 132         }
 133
 134         nvkm_wr32(device, 0x002270, (nvkm_memory_addr(cur) >> 12) |
 135                                     (target << 28));
 136         nvkm_wr32(device, 0x002274, 0x01f00000 | nr);
 137
 138         if (wait_event_timeout(fifo->runlist.wait,
 139                                !(nvkm_rd32(device, 0x00227c) & 0x00100000),
 140                                msecs_to_jiffies(2000)) == 0)
 141                 nvkm_error(subdev, "runlist update timeout\n");
 142         mutex_unlock(&fifo->base.mutex);
 143 }
 144
 145 void
 146 gf100_fifo_runlist_remove(struct gf100_fifo *fifo, struct gf100_fifo_chan *chan)
 147 {
 148         mutex_lock(&fifo->base.mutex);
 149         list_del_init(&chan->head);
 150         mutex_unlock(&fifo->base.mutex);
 151 }
 152
 153 void
 154 gf100_fifo_runlist_insert(struct gf100_fifo *fifo, struct gf100_fifo_chan *chan)
 155 {
 156         mutex_lock(&fifo->base.mutex);
 157         list_add_tail(&chan->head, &fifo->chan);
 158         mutex_unlock(&fifo->base.mutex);
 159 }
 160
 161 static struct nvkm_engine *
 162 gf100_fifo_id_engine(struct nvkm_fifo *fifo, int engi)
 163 {
 164         enum nvkm_subdev_type type;
 165         int inst;
 166
 167         switch (engi) {
 168         case GF100_FIFO_ENGN_GR    : type = NVKM_ENGINE_GR    ; inst = 0; break;
 169         case GF100_FIFO_ENGN_MSPDEC: type = NVKM_ENGINE_MSPDEC; inst = 0; break;
 170         case GF100_FIFO_ENGN_MSPPP : type = NVKM_ENGINE_MSPPP ; inst = 0; break;
 171         case GF100_FIFO_ENGN_MSVLD : type = NVKM_ENGINE_MSVLD ; inst = 0; break;
 172         case GF100_FIFO_ENGN_CE0   : type = NVKM_ENGINE_CE    ; inst = 0; break;
 173         case GF100_FIFO_ENGN_CE1   : type = NVKM_ENGINE_CE    ; inst = 1; break;
 174         case GF100_FIFO_ENGN_SW    : type = NVKM_ENGINE_SW    ; inst = 0; break;
 175         default:
 176                 WARN_ON(1);
 177                 return NULL;
 178         }
 179
 180         return nvkm_device_engine(fifo->engine.subdev.device, type, inst);
 181 }
 182
 183 static int
 184 gf100_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine)
 185 {
 186         switch (engine->subdev.type) {
 187         case NVKM_ENGINE_GR    : return GF100_FIFO_ENGN_GR;
 188         case NVKM_ENGINE_MSPDEC: return GF100_FIFO_ENGN_MSPDEC;
 189         case NVKM_ENGINE_MSPPP : return GF100_FIFO_ENGN_MSPPP;
 190         case NVKM_ENGINE_MSVLD : return GF100_FIFO_ENGN_MSVLD;
 191         case NVKM_ENGINE_CE    : return GF100_FIFO_ENGN_CE0 + engine->subdev.inst;
 192         case NVKM_ENGINE_SW    : return GF100_FIFO_ENGN_SW;
 193         default:
 194                 WARN_ON(1);
 195                 return -1;
 196         }
 197 }
 198
 199 static void
 200 gf100_fifo_recover_work(struct work_struct *w)
 201 {
 202         struct gf100_fifo *fifo = container_of(w, typeof(*fifo), recover.work);
 203         struct nvkm_device *device = fifo->base.engine.subdev.device;
 204         struct nvkm_engine *engine;
 205         unsigned long flags;
 206         u32 engm, engn, todo;
 207
 208         spin_lock_irqsave(&fifo->base.lock, flags);
 209         engm = fifo->recover.mask;
 210         fifo->recover.mask = 0ULL;
 211         spin_unlock_irqrestore(&fifo->base.lock, flags);
 212
 213         nvkm_mask(device, 0x002630, engm, engm);
 214
 215         for (todo = engm; engn = __ffs(todo), todo; todo &= ~BIT_ULL(engn)) {
 216                 if ((engine = gf100_fifo_id_engine(&fifo->base, engn))) {
 217                         nvkm_subdev_fini(&engine->subdev, false);
 218                         WARN_ON(nvkm_subdev_init(&engine->subdev));
 219                 }
 220         }
 221
 222         gf100_fifo_runlist_commit(fifo);
 223         nvkm_wr32(device, 0x00262c, engm);
 224         nvkm_mask(device, 0x002630, engm, 0x00000000);
 225 }
 226
 227 static void
 228 gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine,
 229                    struct gf100_fifo_chan *chan)
 230 {
 231         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 232         struct nvkm_device *device = subdev->device;
 233         u32 chid = chan->base.chid;
 234         int engi = gf100_fifo_engine_id(&fifo->base, engine);
 235
 236         nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n",
 237                    engine->subdev.name, chid);
 238         assert_spin_locked(&fifo->base.lock);
 239
 240         nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000);
 241         list_del_init(&chan->head);
 242         chan->killed = true;
 243
 244         if (engi >= 0 && engi != GF100_FIFO_ENGN_SW)
 245                 fifo->recover.mask |= BIT(engi);
 246         schedule_work(&fifo->recover.work);
 247         nvkm_fifo_kevent(&fifo->base, chid);
 248 }
 249
 250 static const struct nvkm_enum
 251 gf100_fifo_fault_engine[] = {
 252         { 0x00, "PGRAPH", NULL, NVKM_ENGINE_GR },
 253         { 0x03, "PEEPHOLE", NULL, NVKM_ENGINE_IFB },
 254         { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
 255         { 0x05, "BAR3", NULL, NVKM_SUBDEV_INSTMEM },
 256         { 0x07, "PFIFO", NULL, NVKM_ENGINE_FIFO },
 257         { 0x10, "PMSVLD", NULL, NVKM_ENGINE_MSVLD },
 258         { 0x11, "PMSPPP", NULL, NVKM_ENGINE_MSPPP },
 259         { 0x13, "PCOUNTER" },
 260         { 0x14, "PMSPDEC", NULL, NVKM_ENGINE_MSPDEC },
 261         { 0x15, "PCE0", NULL, NVKM_ENGINE_CE, 0 },
 262         { 0x16, "PCE1", NULL, NVKM_ENGINE_CE, 1 },
 263         { 0x17, "PMU" },
 264         {}
 265 };
 266
 267 static const struct nvkm_enum
 268 gf100_fifo_fault_reason[] = {
 269         { 0x00, "PT_NOT_PRESENT" },
 270         { 0x01, "PT_TOO_SHORT" },
 271         { 0x02, "PAGE_NOT_PRESENT" },
 272         { 0x03, "VM_LIMIT_EXCEEDED" },
 273         { 0x04, "NO_CHANNEL" },
 274         { 0x05, "PAGE_SYSTEM_ONLY" },
 275         { 0x06, "PAGE_READ_ONLY" },
 276         { 0x0a, "COMPRESSED_SYSRAM" },
 277         { 0x0c, "INVALID_STORAGE_TYPE" },
 278         {}
 279 };
 280
 281 static const struct nvkm_enum
 282 gf100_fifo_fault_hubclient[] = {
 283         { 0x01, "PCOPY0" },
 284         { 0x02, "PCOPY1" },
 285         { 0x04, "DISPATCH" },
 286         { 0x05, "CTXCTL" },
 287         { 0x06, "PFIFO" },
 288         { 0x07, "BAR_READ" },
 289         { 0x08, "BAR_WRITE" },
 290         { 0x0b, "PVP" },
 291         { 0x0c, "PMSPPP" },
 292         { 0x0d, "PMSVLD" },
 293         { 0x11, "PCOUNTER" },
 294         { 0x12, "PMU" },
 295         { 0x14, "CCACHE" },
 296         { 0x15, "CCACHE_POST" },
 297         {}
 298 };
 299
 300 static const struct nvkm_enum
 301 gf100_fifo_fault_gpcclient[] = {
 302         { 0x01, "TEX" },
 303         { 0x0c, "ESETUP" },
 304         { 0x0e, "CTXCTL" },
 305         { 0x0f, "PROP" },
 306         {}
 307 };
 308
 309 static void
 310 gf100_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info)
 311 {
 312         struct gf100_fifo *fifo = gf100_fifo(base);
 313         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 314         struct nvkm_device *device = subdev->device;
 315         const struct nvkm_enum *er, *eu, *ec;
 316         struct nvkm_engine *engine = NULL;
 317         struct nvkm_fifo_chan *chan;
 318         unsigned long flags;
 319         char gpcid[8] = "";
 320
 321         er = nvkm_enum_find(gf100_fifo_fault_reason, info->reason);
 322         eu = nvkm_enum_find(gf100_fifo_fault_engine, info->engine);
 323         if (info->hub) {
 324                 ec = nvkm_enum_find(gf100_fifo_fault_hubclient, info->client);
 325         } else {
 326                 ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, info->client);
 327                 snprintf(gpcid, sizeof(gpcid), "GPC%d/", info->gpc);
 328         }
 329
 330         if (eu && eu->data2) {
 331                 switch (eu->data2) {
 332                 case NVKM_SUBDEV_BAR:
 333                         nvkm_bar_bar1_reset(device);
 334                         break;
 335                 case NVKM_SUBDEV_INSTMEM:
 336                         nvkm_bar_bar2_reset(device);
 337                         break;
 338                 case NVKM_ENGINE_IFB:
 339                         nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
 340                         break;
 341                 default:
 342                         engine = nvkm_device_engine(device, eu->data2, eu->inst);
 343                         break;
 344                 }
 345         }
 346
 347         chan = nvkm_fifo_chan_inst(&fifo->base, info->inst, &flags);
 348
 349         nvkm_error(subdev,
 350                    "%s fault at %010llx engine %02x [%s] client %02x [%s%s] "
 351                    "reason %02x [%s] on channel %d [%010llx %s]\n",
 352                    info->access ? "write" : "read", info->addr,
 353                    info->engine, eu ? eu->name : "",
 354                    info->client, gpcid, ec ? ec->name : "",
 355                    info->reason, er ? er->name : "", chan ? chan->chid : -1,
 356                    info->inst, chan ? chan->object.client->name : "unknown");
 357
 358         if (engine && chan)
 359                 gf100_fifo_recover(fifo, engine, (void *)chan);
 360         nvkm_fifo_chan_put(&fifo->base, flags, &chan);
 361 }
 362
 363 static const struct nvkm_fifo_func_mmu_fault
 364 gf100_fifo_mmu_fault = {
 365         .recover = gf100_fifo_fault,
 366 };
 367
 368 static const struct nvkm_enum
 369 gf100_fifo_sched_reason[] = {
 370         { 0x0a, "CTXSW_TIMEOUT" },
 371         {}
 372 };
 373
 374 static void
 375 gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo)
 376 {
 377         struct nvkm_device *device = fifo->base.engine.subdev.device;
 378         struct nvkm_engine *engine;
 379         struct gf100_fifo_chan *chan;
 380         unsigned long flags;
 381         u32 engn;
 382
 383         spin_lock_irqsave(&fifo->base.lock, flags);
 384         for (engn = 0; engn < 6; engn++) {
 385                 u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04));
 386                 u32 busy = (stat & 0x80000000);
 387                 u32 save = (stat & 0x00100000); /* maybe? */
 388                 u32 unk0 = (stat & 0x00040000);
 389                 u32 unk1 = (stat & 0x00001000);
 390                 u32 chid = (stat & 0x0000007f);
 391                 (void)save;
 392
 393                 if (busy && unk0 && unk1) {
 394                         list_for_each_entry(chan, &fifo->chan, head) {
 395                                 if (chan->base.chid == chid) {
 396                                         engine = gf100_fifo_id_engine(&fifo->base, engn);
 397                                         if (!engine)
 398                                                 break;
 399                                         gf100_fifo_recover(fifo, engine, chan);
 400                                         break;
 401                                 }
 402                         }
 403                 }
 404         }
 405         spin_unlock_irqrestore(&fifo->base.lock, flags);
 406 }
 407
 408 static void
 409 gf100_fifo_intr_sched(struct gf100_fifo *fifo)
 410 {
 411         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 412         struct nvkm_device *device = subdev->device;
 413         u32 intr = nvkm_rd32(device, 0x00254c);
 414         u32 code = intr & 0x000000ff;
 415         const struct nvkm_enum *en;
 416
 417         en = nvkm_enum_find(gf100_fifo_sched_reason, code);
 418
 419         nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : "");
 420
 421         switch (code) {
 422         case 0x0a:
 423                 gf100_fifo_intr_sched_ctxsw(fifo);
 424                 break;
 425         default:
 426                 break;
 427         }
 428 }
 429
 430 void
 431 gf100_fifo_intr_mmu_fault_unit(struct nvkm_fifo *fifo, int unit)
 432 {
 433         struct nvkm_device *device = fifo->engine.subdev.device;
 434         u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
 435         u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
 436         u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
 437         u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10));
 438         struct nvkm_fault_data info;
 439
 440         info.inst   =  (u64)inst << 12;
 441         info.addr   = ((u64)vahi << 32) | valo;
 442         info.time   = 0;
 443         info.engine = unit;
 444         info.valid  = 1;
 445         info.gpc    = (type & 0x1f000000) >> 24;
 446         info.client = (type & 0x00001f00) >> 8;
 447         info.access = (type & 0x00000080) >> 7;
 448         info.hub    = (type & 0x00000040) >> 6;
 449         info.reason = (type & 0x0000000f);
 450
 451         nvkm_fifo_fault(fifo, &info);
 452 }
 453
 454 static void
 455 gf100_fifo_intr_runlist(struct gf100_fifo *fifo)
 456 {
 457         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 458         struct nvkm_device *device = subdev->device;
 459         u32 intr = nvkm_rd32(device, 0x002a00);
 460
 461         if (intr & 0x10000000) {
 462                 wake_up(&fifo->runlist.wait);
 463                 nvkm_wr32(device, 0x002a00, 0x10000000);
 464                 intr &= ~0x10000000;
 465         }
 466
 467         if (intr) {
 468                 nvkm_error(subdev, "RUNLIST %08x\n", intr);
 469                 nvkm_wr32(device, 0x002a00, intr);
 470         }
 471 }
 472
 473 static void
 474 gf100_fifo_intr_engine_unit(struct gf100_fifo *fifo, int engn)
 475 {
 476         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 477         struct nvkm_device *device = subdev->device;
 478         u32 intr = nvkm_rd32(device, 0x0025a8 + (engn * 0x04));
 479         u32 inte = nvkm_rd32(device, 0x002628);
 480         u32 unkn;
 481
 482         nvkm_wr32(device, 0x0025a8 + (engn * 0x04), intr);
 483
 484         for (unkn = 0; unkn < 8; unkn++) {
 485                 u32 ints = (intr >> (unkn * 0x04)) & inte;
 486                 if (ints & 0x1) {
 487                         nvkm_fifo_uevent(&fifo->base);
 488                         ints &= ~1;
 489                 }
 490                 if (ints) {
 491                         nvkm_error(subdev, "ENGINE %d %d %01x",
 492                                    engn, unkn, ints);
 493                         nvkm_mask(device, 0x002628, ints, 0);
 494                 }
 495         }
 496 }
 497
 498 void
 499 gf100_fifo_intr_engine(struct gf100_fifo *fifo)
 500 {
 501         struct nvkm_device *device = fifo->base.engine.subdev.device;
 502         u32 mask = nvkm_rd32(device, 0x0025a4);
 503         while (mask) {
 504                 u32 unit = __ffs(mask);
 505                 gf100_fifo_intr_engine_unit(fifo, unit);
 506                 mask &= ~(1 << unit);
 507         }
 508 }
 509
 510 static void
 511 gf100_fifo_intr(struct nvkm_fifo *base)
 512 {
 513         struct gf100_fifo *fifo = gf100_fifo(base);
 514         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 515         struct nvkm_device *device = subdev->device;
 516         u32 mask = nvkm_rd32(device, 0x002140);
 517         u32 stat = nvkm_rd32(device, 0x002100) & mask;
 518
 519         if (stat & 0x00000001) {
 520                 u32 intr = nvkm_rd32(device, 0x00252c);
 521                 nvkm_warn(subdev, "INTR 00000001: %08x\n", intr);
 522                 nvkm_wr32(device, 0x002100, 0x00000001);
 523                 stat &= ~0x00000001;
 524         }
 525
 526         if (stat & 0x00000100) {
 527                 gf100_fifo_intr_sched(fifo);
 528                 nvkm_wr32(device, 0x002100, 0x00000100);
 529                 stat &= ~0x00000100;
 530         }
 531
 532         if (stat & 0x00010000) {
 533                 u32 intr = nvkm_rd32(device, 0x00256c);
 534                 nvkm_warn(subdev, "INTR 00010000: %08x\n", intr);
 535                 nvkm_wr32(device, 0x002100, 0x00010000);
 536                 stat &= ~0x00010000;
 537         }
 538
 539         if (stat & 0x01000000) {
 540                 u32 intr = nvkm_rd32(device, 0x00258c);
 541                 nvkm_warn(subdev, "INTR 01000000: %08x\n", intr);
 542                 nvkm_wr32(device, 0x002100, 0x01000000);
 543                 stat &= ~0x01000000;
 544         }
 545
 546         if (stat & 0x10000000) {
 547                 u32 mask = nvkm_rd32(device, 0x00259c);
 548                 while (mask) {
 549                         u32 unit = __ffs(mask);
 550                         gf100_fifo_intr_mmu_fault_unit(&fifo->base, unit);
 551                         nvkm_wr32(device, 0x00259c, (1 << unit));
 552                         mask &= ~(1 << unit);
 553                 }
 554                 stat &= ~0x10000000;
 555         }
 556
 557         if (stat & 0x20000000) {
 558                 u32 mask = nvkm_rd32(device, 0x0025a0);
 559                 while (mask) {
 560                         u32 unit = __ffs(mask);
 561                         gf100_fifo_intr_pbdma(fifo, unit);
 562                         nvkm_wr32(device, 0x0025a0, (1 << unit));
 563                         mask &= ~(1 << unit);
 564                 }
 565                 stat &= ~0x20000000;
 566         }
 567
 568         if (stat & 0x40000000) {
 569                 gf100_fifo_intr_runlist(fifo);
 570                 stat &= ~0x40000000;
 571         }
 572
 573         if (stat & 0x80000000) {
 574                 gf100_fifo_intr_engine(fifo);
 575                 stat &= ~0x80000000;
 576         }
 577
 578         if (stat) {
 579                 nvkm_error(subdev, "INTR %08x\n", stat);
 580                 nvkm_mask(device, 0x002140, stat, 0x00000000);
 581                 nvkm_wr32(device, 0x002100, stat);
 582         }
 583 }
 584
 585 static void
 586 gf100_fifo_fini(struct nvkm_fifo *base)
 587 {
 588         struct gf100_fifo *fifo = gf100_fifo(base);
 589         flush_work(&fifo->recover.work);
 590 }
 591
 592 static void
 593 gf100_fifo_init(struct nvkm_fifo *base)
 594 {
 595         struct gf100_fifo *fifo = gf100_fifo(base);
 596         struct nvkm_device *device = fifo->base.engine.subdev.device;
 597         int i;
 598
 599         /* Enable PBDMAs. */
 600         nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1);
 601         nvkm_wr32(device, 0x002204, (1 << fifo->pbdma_nr) - 1);
 602
 603         /* Assign engines to PBDMAs. */
 604         if (fifo->pbdma_nr >= 3) {
 605                 nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */
 606                 nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */
 607                 nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */
 608                 nvkm_wr32(device, 0x002214, ~(1 << 1)); /* PMSVLD */
 609                 nvkm_wr32(device, 0x002218, ~(1 << 2)); /* PCE0 */
 610                 nvkm_wr32(device, 0x00221c, ~(1 << 1)); /* PCE1 */
 611         }
 612
 613         /* PBDMA[n] */
 614         for (i = 0; i < fifo->pbdma_nr; i++) {
 615                 nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
 616                 nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
 617                 nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
 618         }
 619
 620         nvkm_mask(device, 0x002200, 0x00000001, 0x00000001);
 621         nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar->addr >> 12);
 622
 623         nvkm_wr32(device, 0x002100, 0xffffffff);
 624         nvkm_wr32(device, 0x002140, 0x7fffffff);
 625         nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */
 626 }
 627
 628 int
 629 gf100_fifo_chid_ctor(struct nvkm_fifo *fifo, int nr)
 630 {
 631         return nvkm_chid_new(&nvkm_chan_event, &fifo->engine.subdev, nr, 0, nr, &fifo->chid);
 632 }
 633
 634 static int
 635 gf100_fifo_oneinit(struct nvkm_fifo *base)
 636 {
 637         struct gf100_fifo *fifo = gf100_fifo(base);
 638         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 639         struct nvkm_device *device = subdev->device;
 640         struct nvkm_vmm *bar = nvkm_bar_bar1_vmm(device);
 641         int ret;
 642
 643         /* Determine number of PBDMAs by checking valid enable bits. */
 644         nvkm_wr32(device, 0x002204, 0xffffffff);
 645         fifo->pbdma_nr = hweight32(nvkm_rd32(device, 0x002204));
 646         nvkm_debug(subdev, "%d PBDMA(s)\n", fifo->pbdma_nr);
 647
 648
 649         ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000,
 650                               false, &fifo->runlist.mem[0]);
 651         if (ret)
 652                 return ret;
 653
 654         ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000,
 655                               false, &fifo->runlist.mem[1]);
 656         if (ret)
 657                 return ret;
 658
 659         init_waitqueue_head(&fifo->runlist.wait);
 660
 661         ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 0x1000,
 662                               0x1000, false, &fifo->user.mem);
 663         if (ret)
 664                 return ret;
 665
 666         ret = nvkm_vmm_get(bar, 12, nvkm_memory_size(fifo->user.mem),
 667                            &fifo->user.bar);
 668         if (ret)
 669                 return ret;
 670
 671         return nvkm_memory_map(fifo->user.mem, 0, bar, fifo->user.bar, NULL, 0);
 672 }
 673
 674 static void *
 675 gf100_fifo_dtor(struct nvkm_fifo *base)
 676 {
 677         struct gf100_fifo *fifo = gf100_fifo(base);
 678         struct nvkm_device *device = fifo->base.engine.subdev.device;
 679         nvkm_vmm_put(nvkm_bar_bar1_vmm(device), &fifo->user.bar);
 680         nvkm_memory_unref(&fifo->user.mem);
 681         nvkm_memory_unref(&fifo->runlist.mem[0]);
 682         nvkm_memory_unref(&fifo->runlist.mem[1]);
 683         return fifo;
 684 }
 685
 686 static const struct nvkm_fifo_func
 687 gf100_fifo = {
 688         .dtor = gf100_fifo_dtor,
 689         .oneinit = gf100_fifo_oneinit,
 690         .chid_nr = nv50_fifo_chid_nr,
 691         .chid_ctor = gf100_fifo_chid_ctor,
 692         .init = gf100_fifo_init,
 693         .fini = gf100_fifo_fini,
 694         .intr = gf100_fifo_intr,
 695         .mmu_fault = &gf100_fifo_mmu_fault,
 696         .engine_id = gf100_fifo_engine_id,
 697         .id_engine = gf100_fifo_id_engine,
 698         .uevent_init = gf100_fifo_uevent_init,
 699         .uevent_fini = gf100_fifo_uevent_fini,
 700         .cgrp = {{                            }, &nv04_cgrp },
 701         .chan = {{ 0, 0, FERMI_CHANNEL_GPFIFO }, &gf100_chan, .oclass = &gf100_fifo_gpfifo_oclass },
 702 };
 703
 704 int
 705 gf100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
 706                struct nvkm_fifo **pfifo)
 707 {
 708         struct gf100_fifo *fifo;
 709
 710         if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
 711                 return -ENOMEM;
 712         INIT_LIST_HEAD(&fifo->chan);
 713         INIT_WORK(&fifo->recover.work, gf100_fifo_recover_work);
 714         *pfifo = &fifo->base;
 715
 716         return nvkm_fifo_ctor(&gf100_fifo, device, type, inst, &fifo->base);
 717 }