drivers/gpu/drm/nouveau/nvc0_graph.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27
  28 #include <drm/drmP.h>
  29
  30 #include "nouveau_drv.h"
  31 #include "nouveau_mm.h"
  32 #include "nouveau_fifo.h"
  33
  34 #include "nvc0_graph.h"
  35 #include "nvc0_grhub.fuc.h"
  36 #include "nvc0_grgpc.fuc.h"
  37
  38 static void
  39 nvc0_graph_ctxctl_debug_unit(struct drm_device *dev, u32 base)
  40 {
  41         NV_INFO(dev, "PGRAPH: %06x - done 0x%08x\n", base,
  42                 nv_rd32(dev, base + 0x400));
  43         NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
  44                 nv_rd32(dev, base + 0x800), nv_rd32(dev, base + 0x804),
  45                 nv_rd32(dev, base + 0x808), nv_rd32(dev, base + 0x80c));
  46         NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
  47                 nv_rd32(dev, base + 0x810), nv_rd32(dev, base + 0x814),
  48                 nv_rd32(dev, base + 0x818), nv_rd32(dev, base + 0x81c));
  49 }
  50
  51 static void
  52 nvc0_graph_ctxctl_debug(struct drm_device *dev)
  53 {
  54         u32 gpcnr = nv_rd32(dev, 0x409604) & 0xffff;
  55         u32 gpc;
  56
  57         nvc0_graph_ctxctl_debug_unit(dev, 0x409000);
  58         for (gpc = 0; gpc < gpcnr; gpc++)
  59                 nvc0_graph_ctxctl_debug_unit(dev, 0x502000 + (gpc * 0x8000));
  60 }
  61
  62 static int
  63 nvc0_graph_load_context(struct nouveau_channel *chan)
  64 {
  65         struct drm_device *dev = chan->dev;
  66
  67         nv_wr32(dev, 0x409840, 0x00000030);
  68         nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
  69         nv_wr32(dev, 0x409504, 0x00000003);
  70         if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
  71                 NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
  72
  73         return 0;
  74 }
  75
  76 static int
  77 nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan)
  78 {
  79         nv_wr32(dev, 0x409840, 0x00000003);
  80         nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12);
  81         nv_wr32(dev, 0x409504, 0x00000009);
  82         if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) {
  83                 NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n");
  84                 return -EBUSY;
  85         }
  86
  87         return 0;
  88 }
  89
  90 static int
  91 nvc0_graph_construct_context(struct nouveau_channel *chan)
  92 {
  93         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  94         struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
  95         struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
  96         struct drm_device *dev = chan->dev;
  97         int ret, i;
  98         u32 *ctx;
  99
 100         ctx = kmalloc(priv->grctx_size, GFP_KERNEL);
 101         if (!ctx)
 102                 return -ENOMEM;
 103
 104         if (!nouveau_ctxfw) {
 105                 nv_wr32(dev, 0x409840, 0x80000000);
 106                 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
 107                 nv_wr32(dev, 0x409504, 0x00000001);
 108                 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
 109                         NV_ERROR(dev, "PGRAPH: HUB_SET_CHAN timeout\n");
 110                         nvc0_graph_ctxctl_debug(dev);
 111                         ret = -EBUSY;
 112                         goto err;
 113                 }
 114         } else {
 115                 nvc0_graph_load_context(chan);
 116
 117                 nv_wo32(grch->grctx, 0x1c, 1);
 118                 nv_wo32(grch->grctx, 0x20, 0);
 119                 nv_wo32(grch->grctx, 0x28, 0);
 120                 nv_wo32(grch->grctx, 0x2c, 0);
 121                 dev_priv->engine.instmem.flush(dev);
 122         }
 123
 124         ret = nvc0_grctx_generate(chan);
 125         if (ret)
 126                 goto err;
 127
 128         if (!nouveau_ctxfw) {
 129                 nv_wr32(dev, 0x409840, 0x80000000);
 130                 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
 131                 nv_wr32(dev, 0x409504, 0x00000002);
 132                 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
 133                         NV_ERROR(dev, "PGRAPH: HUB_CTX_SAVE timeout\n");
 134                         nvc0_graph_ctxctl_debug(dev);
 135                         ret = -EBUSY;
 136                         goto err;
 137                 }
 138         } else {
 139                 ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst);
 140                 if (ret)
 141                         goto err;
 142         }
 143
 144         for (i = 0; i < priv->grctx_size; i += 4)
 145                 ctx[i / 4] = nv_ro32(grch->grctx, i);
 146
 147         priv->grctx_vals = ctx;
 148         return 0;
 149
 150 err:
 151         kfree(ctx);
 152         return ret;
 153 }
 154
 155 static int
 156 nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
 157 {
 158         struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
 159         struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
 160         struct drm_device *dev = chan->dev;
 161         struct drm_nouveau_private *dev_priv = dev->dev_private;
 162         int i = 0, gpc, tp, ret;
 163
 164         ret = nouveau_gpuobj_new(dev, chan, 0x2000, 256, NVOBJ_FLAG_VM,
 165                                  &grch->unk408004);
 166         if (ret)
 167                 return ret;
 168
 169         ret = nouveau_gpuobj_new(dev, chan, 0x8000, 256, NVOBJ_FLAG_VM,
 170                                  &grch->unk40800c);
 171         if (ret)
 172                 return ret;
 173
 174         ret = nouveau_gpuobj_new(dev, chan, 384 * 1024, 4096,
 175                                  NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER,
 176                                  &grch->unk418810);
 177         if (ret)
 178                 return ret;
 179
 180         ret = nouveau_gpuobj_new(dev, chan, 0x1000, 0, NVOBJ_FLAG_VM,
 181                                  &grch->mmio);
 182         if (ret)
 183                 return ret;
 184
 185
 186         nv_wo32(grch->mmio, i++ * 4, 0x00408004);
 187         nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8);
 188         nv_wo32(grch->mmio, i++ * 4, 0x00408008);
 189         nv_wo32(grch->mmio, i++ * 4, 0x80000018);
 190
 191         nv_wo32(grch->mmio, i++ * 4, 0x0040800c);
 192         nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8);
 193         nv_wo32(grch->mmio, i++ * 4, 0x00408010);
 194         nv_wo32(grch->mmio, i++ * 4, 0x80000000);
 195
 196         nv_wo32(grch->mmio, i++ * 4, 0x00418810);
 197         nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->linst >> 12);
 198         nv_wo32(grch->mmio, i++ * 4, 0x00419848);
 199         nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->linst >> 12);
 200
 201         nv_wo32(grch->mmio, i++ * 4, 0x00419004);
 202         nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8);
 203         nv_wo32(grch->mmio, i++ * 4, 0x00419008);
 204         nv_wo32(grch->mmio, i++ * 4, 0x00000000);
 205
 206         nv_wo32(grch->mmio, i++ * 4, 0x00418808);
 207         nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8);
 208         nv_wo32(grch->mmio, i++ * 4, 0x0041880c);
 209         nv_wo32(grch->mmio, i++ * 4, 0x80000018);
 210
 211         if (dev_priv->chipset != 0xc1) {
 212                 u32 magic = 0x02180000;
 213                 nv_wo32(grch->mmio, i++ * 4, 0x00405830);
 214                 nv_wo32(grch->mmio, i++ * 4, magic);
 215                 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 216                         for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
 217                                 u32 reg = TP_UNIT(gpc, tp, 0x520);
 218                                 nv_wo32(grch->mmio, i++ * 4, reg);
 219                                 nv_wo32(grch->mmio, i++ * 4, magic);
 220                                 magic += 0x0324;
 221                         }
 222                 }
 223         } else {
 224                 u32 magic = 0x02180000;
 225                 nv_wo32(grch->mmio, i++ * 4, 0x00405830);
 226                 nv_wo32(grch->mmio, i++ * 4, magic | 0x0000218);
 227                 nv_wo32(grch->mmio, i++ * 4, 0x004064c4);
 228                 nv_wo32(grch->mmio, i++ * 4, 0x0086ffff);
 229                 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 230                         for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
 231                                 u32 reg = TP_UNIT(gpc, tp, 0x520);
 232                                 nv_wo32(grch->mmio, i++ * 4, reg);
 233                                 nv_wo32(grch->mmio, i++ * 4, (1 << 28) | magic);
 234                                 magic += 0x0324;
 235                         }
 236                         for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
 237                                 u32 reg = TP_UNIT(gpc, tp, 0x544);
 238                                 nv_wo32(grch->mmio, i++ * 4, reg);
 239                                 nv_wo32(grch->mmio, i++ * 4, magic);
 240                                 magic += 0x0324;
 241                         }
 242                 }
 243         }
 244
 245         grch->mmio_nr = i / 2;
 246         return 0;
 247 }
 248
 249 static int
 250 nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
 251 {
 252         struct drm_device *dev = chan->dev;
 253         struct drm_nouveau_private *dev_priv = dev->dev_private;
 254         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
 255         struct nvc0_graph_priv *priv = nv_engine(dev, engine);
 256         struct nvc0_graph_chan *grch;
 257         struct nouveau_gpuobj *grctx;
 258         int ret, i;
 259
 260         grch = kzalloc(sizeof(*grch), GFP_KERNEL);
 261         if (!grch)
 262                 return -ENOMEM;
 263         chan->engctx[NVOBJ_ENGINE_GR] = grch;
 264
 265         ret = nouveau_gpuobj_new(dev, chan, priv->grctx_size, 256,
 266                                  NVOBJ_FLAG_VM | NVOBJ_FLAG_ZERO_ALLOC,
 267                                  &grch->grctx);
 268         if (ret)
 269                 goto error;
 270         grctx = grch->grctx;
 271
 272         ret = nvc0_graph_create_context_mmio_list(chan);
 273         if (ret)
 274                 goto error;
 275
 276         nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->linst) | 4);
 277         nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->linst));
 278         pinstmem->flush(dev);
 279
 280         if (!priv->grctx_vals) {
 281                 ret = nvc0_graph_construct_context(chan);
 282                 if (ret)
 283                         goto error;
 284         }
 285
 286         for (i = 0; i < priv->grctx_size; i += 4)
 287                 nv_wo32(grctx, i, priv->grctx_vals[i / 4]);
 288
 289         if (!nouveau_ctxfw) {
 290                 nv_wo32(grctx, 0x00, grch->mmio_nr);
 291                 nv_wo32(grctx, 0x04, grch->mmio->linst >> 8);
 292         } else {
 293                 nv_wo32(grctx, 0xf4, 0);
 294                 nv_wo32(grctx, 0xf8, 0);
 295                 nv_wo32(grctx, 0x10, grch->mmio_nr);
 296                 nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->linst));
 297                 nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->linst));
 298                 nv_wo32(grctx, 0x1c, 1);
 299                 nv_wo32(grctx, 0x20, 0);
 300                 nv_wo32(grctx, 0x28, 0);
 301                 nv_wo32(grctx, 0x2c, 0);
 302         }
 303         pinstmem->flush(dev);
 304         return 0;
 305
 306 error:
 307         priv->base.context_del(chan, engine);
 308         return ret;
 309 }
 310
 311 static void
 312 nvc0_graph_context_del(struct nouveau_channel *chan, int engine)
 313 {
 314         struct nvc0_graph_chan *grch = chan->engctx[engine];
 315
 316         nouveau_gpuobj_ref(NULL, &grch->mmio);
 317         nouveau_gpuobj_ref(NULL, &grch->unk418810);
 318         nouveau_gpuobj_ref(NULL, &grch->unk40800c);
 319         nouveau_gpuobj_ref(NULL, &grch->unk408004);
 320         nouveau_gpuobj_ref(NULL, &grch->grctx);
 321         chan->engctx[engine] = NULL;
 322 }
 323
 324 static int
 325 nvc0_graph_object_new(struct nouveau_channel *chan, int engine,
 326                       u32 handle, u16 class)
 327 {
 328         return 0;
 329 }
 330
 331 static int
 332 nvc0_graph_fini(struct drm_device *dev, int engine, bool suspend)
 333 {
 334         return 0;
 335 }
 336
 337 static void
 338 nvc0_graph_init_obj418880(struct drm_device *dev)
 339 {
 340         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 341         int i;
 342
 343         nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000);
 344         nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000);
 345         for (i = 0; i < 4; i++)
 346                 nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
 347         nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8);
 348         nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8);
 349 }
 350
 351 static void
 352 nvc0_graph_init_regs(struct drm_device *dev)
 353 {
 354         nv_wr32(dev, 0x400080, 0x003083c2);
 355         nv_wr32(dev, 0x400088, 0x00006fe7);
 356         nv_wr32(dev, 0x40008c, 0x00000000);
 357         nv_wr32(dev, 0x400090, 0x00000030);
 358         nv_wr32(dev, 0x40013c, 0x013901f7);
 359         nv_wr32(dev, 0x400140, 0x00000100);
 360         nv_wr32(dev, 0x400144, 0x00000000);
 361         nv_wr32(dev, 0x400148, 0x00000110);
 362         nv_wr32(dev, 0x400138, 0x00000000);
 363         nv_wr32(dev, 0x400130, 0x00000000);
 364         nv_wr32(dev, 0x400134, 0x00000000);
 365         nv_wr32(dev, 0x400124, 0x00000002);
 366 }
 367
 368 static void
 369 nvc0_graph_init_gpc_0(struct drm_device *dev)
 370 {
 371         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 372         const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tp_total);
 373         u32 data[TP_MAX / 8];
 374         u8  tpnr[GPC_MAX];
 375         int i, gpc, tpc;
 376
 377         nv_wr32(dev, TP_UNIT(0, 0, 0x5c), 1); /* affects TFB offset queries */
 378
 379         /*
 380          *      TP      ROP UNKVAL(magic_not_rop_nr)
 381          * 450: 4/0/0/0 2        3
 382          * 460: 3/4/0/0 4        1
 383          * 465: 3/4/4/0 4        7
 384          * 470: 3/3/4/4 5        5
 385          * 480: 3/4/4/4 6        6
 386          */
 387
 388         memset(data, 0x00, sizeof(data));
 389         memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr));
 390         for (i = 0, gpc = -1; i < priv->tp_total; i++) {
 391                 do {
 392                         gpc = (gpc + 1) % priv->gpc_nr;
 393                 } while (!tpnr[gpc]);
 394                 tpc = priv->tp_nr[gpc] - tpnr[gpc]--;
 395
 396                 data[i / 8] |= tpc << ((i % 8) * 4);
 397         }
 398
 399         nv_wr32(dev, GPC_BCAST(0x0980), data[0]);
 400         nv_wr32(dev, GPC_BCAST(0x0984), data[1]);
 401         nv_wr32(dev, GPC_BCAST(0x0988), data[2]);
 402         nv_wr32(dev, GPC_BCAST(0x098c), data[3]);
 403
 404         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 405                 nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
 406                                                   priv->tp_nr[gpc]);
 407                 nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tp_total);
 408                 nv_wr32(dev, GPC_UNIT(gpc, 0x0918), magicgpc918);
 409         }
 410
 411         nv_wr32(dev, GPC_BCAST(0x1bd4), magicgpc918);
 412         nv_wr32(dev, GPC_BCAST(0x08ac), nv_rd32(dev, 0x100800));
 413 }
 414
 415 static void
 416 nvc0_graph_init_units(struct drm_device *dev)
 417 {
 418         nv_wr32(dev, 0x409c24, 0x000f0000);
 419         nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */
 420         nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */
 421         nv_wr32(dev, 0x408030, 0xc0000000);
 422         nv_wr32(dev, 0x40601c, 0xc0000000);
 423         nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */
 424         nv_wr32(dev, 0x406018, 0xc0000000);
 425         nv_wr32(dev, 0x405840, 0xc0000000);
 426         nv_wr32(dev, 0x405844, 0x00ffffff);
 427         nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008);
 428         nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000);
 429 }
 430
 431 static void
 432 nvc0_graph_init_gpc_1(struct drm_device *dev)
 433 {
 434         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 435         int gpc, tp;
 436
 437         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 438                 nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000);
 439                 nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000);
 440                 nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000);
 441                 nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000);
 442                 for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
 443                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x508), 0xffffffff);
 444                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x50c), 0xffffffff);
 445                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000);
 446                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000);
 447                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000);
 448                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x644), 0x001ffffe);
 449                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x64c), 0x0000000f);
 450                 }
 451                 nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
 452                 nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
 453         }
 454 }
 455
 456 static void
 457 nvc0_graph_init_rop(struct drm_device *dev)
 458 {
 459         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 460         int rop;
 461
 462         for (rop = 0; rop < priv->rop_nr; rop++) {
 463                 nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000);
 464                 nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000);
 465                 nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff);
 466                 nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff);
 467         }
 468 }
 469
 470 static void
 471 nvc0_graph_init_fuc(struct drm_device *dev, u32 fuc_base,
 472                     struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data)
 473 {
 474         int i;
 475
 476         nv_wr32(dev, fuc_base + 0x01c0, 0x01000000);
 477         for (i = 0; i < data->size / 4; i++)
 478                 nv_wr32(dev, fuc_base + 0x01c4, data->data[i]);
 479
 480         nv_wr32(dev, fuc_base + 0x0180, 0x01000000);
 481         for (i = 0; i < code->size / 4; i++) {
 482                 if ((i & 0x3f) == 0)
 483                         nv_wr32(dev, fuc_base + 0x0188, i >> 6);
 484                 nv_wr32(dev, fuc_base + 0x0184, code->data[i]);
 485         }
 486 }
 487
 488 static int
 489 nvc0_graph_init_ctxctl(struct drm_device *dev)
 490 {
 491         struct drm_nouveau_private *dev_priv = dev->dev_private;
 492         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 493         u32 r000260;
 494         int i;
 495
 496         if (!nouveau_ctxfw) {
 497                 /* load HUB microcode */
 498                 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
 499                 nv_wr32(dev, 0x4091c0, 0x01000000);
 500                 for (i = 0; i < sizeof(nvc0_grhub_data) / 4; i++)
 501                         nv_wr32(dev, 0x4091c4, nvc0_grhub_data[i]);
 502
 503                 nv_wr32(dev, 0x409180, 0x01000000);
 504                 for (i = 0; i < sizeof(nvc0_grhub_code) / 4; i++) {
 505                         if ((i & 0x3f) == 0)
 506                                 nv_wr32(dev, 0x409188, i >> 6);
 507                         nv_wr32(dev, 0x409184, nvc0_grhub_code[i]);
 508                 }
 509
 510                 /* load GPC microcode */
 511                 nv_wr32(dev, 0x41a1c0, 0x01000000);
 512                 for (i = 0; i < sizeof(nvc0_grgpc_data) / 4; i++)
 513                         nv_wr32(dev, 0x41a1c4, nvc0_grgpc_data[i]);
 514
 515                 nv_wr32(dev, 0x41a180, 0x01000000);
 516                 for (i = 0; i < sizeof(nvc0_grgpc_code) / 4; i++) {
 517                         if ((i & 0x3f) == 0)
 518                                 nv_wr32(dev, 0x41a188, i >> 6);
 519                         nv_wr32(dev, 0x41a184, nvc0_grgpc_code[i]);
 520                 }
 521                 nv_wr32(dev, 0x000260, r000260);
 522
 523                 /* start HUB ucode running, it'll init the GPCs */
 524                 nv_wr32(dev, 0x409800, dev_priv->chipset);
 525                 nv_wr32(dev, 0x40910c, 0x00000000);
 526                 nv_wr32(dev, 0x409100, 0x00000002);
 527                 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
 528                         NV_ERROR(dev, "PGRAPH: HUB_INIT timed out\n");
 529                         nvc0_graph_ctxctl_debug(dev);
 530                         return -EBUSY;
 531                 }
 532
 533                 priv->grctx_size = nv_rd32(dev, 0x409804);
 534                 return 0;
 535         }
 536
 537         /* load fuc microcode */
 538         r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
 539         nvc0_graph_init_fuc(dev, 0x409000, &priv->fuc409c, &priv->fuc409d);
 540         nvc0_graph_init_fuc(dev, 0x41a000, &priv->fuc41ac, &priv->fuc41ad);
 541         nv_wr32(dev, 0x000260, r000260);
 542
 543         /* start both of them running */
 544         nv_wr32(dev, 0x409840, 0xffffffff);
 545         nv_wr32(dev, 0x41a10c, 0x00000000);
 546         nv_wr32(dev, 0x40910c, 0x00000000);
 547         nv_wr32(dev, 0x41a100, 0x00000002);
 548         nv_wr32(dev, 0x409100, 0x00000002);
 549         if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001))
 550                 NV_INFO(dev, "0x409800 wait failed\n");
 551
 552         nv_wr32(dev, 0x409840, 0xffffffff);
 553         nv_wr32(dev, 0x409500, 0x7fffffff);
 554         nv_wr32(dev, 0x409504, 0x00000021);
 555
 556         nv_wr32(dev, 0x409840, 0xffffffff);
 557         nv_wr32(dev, 0x409500, 0x00000000);
 558         nv_wr32(dev, 0x409504, 0x00000010);
 559         if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
 560                 NV_ERROR(dev, "fuc09 req 0x10 timeout\n");
 561                 return -EBUSY;
 562         }
 563         priv->grctx_size = nv_rd32(dev, 0x409800);
 564
 565         nv_wr32(dev, 0x409840, 0xffffffff);
 566         nv_wr32(dev, 0x409500, 0x00000000);
 567         nv_wr32(dev, 0x409504, 0x00000016);
 568         if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
 569                 NV_ERROR(dev, "fuc09 req 0x16 timeout\n");
 570                 return -EBUSY;
 571         }
 572
 573         nv_wr32(dev, 0x409840, 0xffffffff);
 574         nv_wr32(dev, 0x409500, 0x00000000);
 575         nv_wr32(dev, 0x409504, 0x00000025);
 576         if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
 577                 NV_ERROR(dev, "fuc09 req 0x25 timeout\n");
 578                 return -EBUSY;
 579         }
 580
 581         return 0;
 582 }
 583
 584 static int
 585 nvc0_graph_init(struct drm_device *dev, int engine)
 586 {
 587         int ret;
 588
 589         nv_mask(dev, 0x000200, 0x18001000, 0x00000000);
 590         nv_mask(dev, 0x000200, 0x18001000, 0x18001000);
 591
 592         nvc0_graph_init_obj418880(dev);
 593         nvc0_graph_init_regs(dev);
 594         /*nvc0_graph_init_unitplemented_magics(dev);*/
 595         nvc0_graph_init_gpc_0(dev);
 596         /*nvc0_graph_init_unitplemented_c242(dev);*/
 597
 598         nv_wr32(dev, 0x400500, 0x00010001);
 599         nv_wr32(dev, 0x400100, 0xffffffff);
 600         nv_wr32(dev, 0x40013c, 0xffffffff);
 601
 602         nvc0_graph_init_units(dev);
 603         nvc0_graph_init_gpc_1(dev);
 604         nvc0_graph_init_rop(dev);
 605
 606         nv_wr32(dev, 0x400108, 0xffffffff);
 607         nv_wr32(dev, 0x400138, 0xffffffff);
 608         nv_wr32(dev, 0x400118, 0xffffffff);
 609         nv_wr32(dev, 0x400130, 0xffffffff);
 610         nv_wr32(dev, 0x40011c, 0xffffffff);
 611         nv_wr32(dev, 0x400134, 0xffffffff);
 612         nv_wr32(dev, 0x400054, 0x34ce3464);
 613
 614         ret = nvc0_graph_init_ctxctl(dev);
 615         if (ret)
 616                 return ret;
 617
 618         return 0;
 619 }
 620
 621 int
 622 nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
 623 {
 624         struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
 625         struct drm_nouveau_private *dev_priv = dev->dev_private;
 626         struct nouveau_channel *chan;
 627         unsigned long flags;
 628         int i;
 629
 630         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 631         for (i = 0; i < pfifo->channels; i++) {
 632                 chan = dev_priv->channels.ptr[i];
 633                 if (!chan || !chan->ramin)
 634                         continue;
 635
 636                 if (inst == chan->ramin->vinst)
 637                         break;
 638         }
 639         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 640         return i;
 641 }
 642
 643 static void
 644 nvc0_graph_ctxctl_isr(struct drm_device *dev)
 645 {
 646         u32 ustat = nv_rd32(dev, 0x409c18);
 647
 648         if (ustat & 0x00000001)
 649                 NV_INFO(dev, "PGRAPH: CTXCTRL ucode error\n");
 650         if (ustat & 0x00080000)
 651                 NV_INFO(dev, "PGRAPH: CTXCTRL watchdog timeout\n");
 652         if (ustat & ~0x00080001)
 653                 NV_INFO(dev, "PGRAPH: CTXCTRL 0x%08x\n", ustat);
 654
 655         nvc0_graph_ctxctl_debug(dev);
 656         nv_wr32(dev, 0x409c20, ustat);
 657 }
 658
 659 static void
 660 nvc0_graph_isr(struct drm_device *dev)
 661 {
 662         u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
 663         u32 chid = nvc0_graph_isr_chid(dev, inst);
 664         u32 stat = nv_rd32(dev, 0x400100);
 665         u32 addr = nv_rd32(dev, 0x400704);
 666         u32 mthd = (addr & 0x00003ffc);
 667         u32 subc = (addr & 0x00070000) >> 16;
 668         u32 data = nv_rd32(dev, 0x400708);
 669         u32 code = nv_rd32(dev, 0x400110);
 670         u32 class = nv_rd32(dev, 0x404200 + (subc * 4));
 671
 672         if (stat & 0x00000010) {
 673                 if (nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data)) {
 674                         NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] "
 675                                      "subc %d class 0x%04x mthd 0x%04x "
 676                                      "data 0x%08x\n",
 677                                 chid, inst, subc, class, mthd, data);
 678                 }
 679                 nv_wr32(dev, 0x400100, 0x00000010);
 680                 stat &= ~0x00000010;
 681         }
 682
 683         if (stat & 0x00000020) {
 684                 NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d "
 685                              "class 0x%04x mthd 0x%04x data 0x%08x\n",
 686                         chid, inst, subc, class, mthd, data);
 687                 nv_wr32(dev, 0x400100, 0x00000020);
 688                 stat &= ~0x00000020;
 689         }
 690
 691         if (stat & 0x00100000) {
 692                 NV_INFO(dev, "PGRAPH: DATA_ERROR [");
 693                 nouveau_enum_print(nv50_data_error_names, code);
 694                 printk("] ch %d [0x%010llx] subc %d class 0x%04x "
 695                        "mthd 0x%04x data 0x%08x\n",
 696                        chid, inst, subc, class, mthd, data);
 697                 nv_wr32(dev, 0x400100, 0x00100000);
 698                 stat &= ~0x00100000;
 699         }
 700
 701         if (stat & 0x00200000) {
 702                 u32 trap = nv_rd32(dev, 0x400108);
 703                 NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap);
 704                 nv_wr32(dev, 0x400108, trap);
 705                 nv_wr32(dev, 0x400100, 0x00200000);
 706                 stat &= ~0x00200000;
 707         }
 708
 709         if (stat & 0x00080000) {
 710                 nvc0_graph_ctxctl_isr(dev);
 711                 nv_wr32(dev, 0x400100, 0x00080000);
 712                 stat &= ~0x00080000;
 713         }
 714
 715         if (stat) {
 716                 NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat);
 717                 nv_wr32(dev, 0x400100, stat);
 718         }
 719
 720         nv_wr32(dev, 0x400500, 0x00010001);
 721 }
 722
 723 static int
 724 nvc0_graph_create_fw(struct drm_device *dev, const char *fwname,
 725                      struct nvc0_graph_fuc *fuc)
 726 {
 727         struct drm_nouveau_private *dev_priv = dev->dev_private;
 728         const struct firmware *fw;
 729         char f[32];
 730         int ret;
 731
 732         snprintf(f, sizeof(f), "nouveau/nv%02x_%s", dev_priv->chipset, fwname);
 733         ret = request_firmware(&fw, f, &dev->pdev->dev);
 734         if (ret) {
 735                 snprintf(f, sizeof(f), "nouveau/%s", fwname);
 736                 ret = request_firmware(&fw, f, &dev->pdev->dev);
 737                 if (ret) {
 738                         NV_ERROR(dev, "failed to load %s\n", fwname);
 739                         return ret;
 740                 }
 741         }
 742
 743         fuc->size = fw->size;
 744         fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
 745         release_firmware(fw);
 746         return (fuc->data != NULL) ? 0 : -ENOMEM;
 747 }
 748
 749 static void
 750 nvc0_graph_destroy_fw(struct nvc0_graph_fuc *fuc)
 751 {
 752         if (fuc->data) {
 753                 kfree(fuc->data);
 754                 fuc->data = NULL;
 755         }
 756 }
 757
 758 static void
 759 nvc0_graph_destroy(struct drm_device *dev, int engine)
 760 {
 761         struct nvc0_graph_priv *priv = nv_engine(dev, engine);
 762
 763         if (nouveau_ctxfw) {
 764                 nvc0_graph_destroy_fw(&priv->fuc409c);
 765                 nvc0_graph_destroy_fw(&priv->fuc409d);
 766                 nvc0_graph_destroy_fw(&priv->fuc41ac);
 767                 nvc0_graph_destroy_fw(&priv->fuc41ad);
 768         }
 769
 770         nouveau_irq_unregister(dev, 12);
 771
 772         nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
 773         nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
 774
 775         if (priv->grctx_vals)
 776                 kfree(priv->grctx_vals);
 777
 778         NVOBJ_ENGINE_DEL(dev, GR);
 779         kfree(priv);
 780 }
 781
 782 int
 783 nvc0_graph_create(struct drm_device *dev)
 784 {
 785         struct drm_nouveau_private *dev_priv = dev->dev_private;
 786         struct nvc0_graph_priv *priv;
 787         int ret, gpc, i;
 788         u32 fermi;
 789
 790         fermi = nvc0_graph_class(dev);
 791         if (!fermi) {
 792                 NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
 793                 return 0;
 794         }
 795
 796         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 797         if (!priv)
 798                 return -ENOMEM;
 799
 800         priv->base.destroy = nvc0_graph_destroy;
 801         priv->base.init = nvc0_graph_init;
 802         priv->base.fini = nvc0_graph_fini;
 803         priv->base.context_new = nvc0_graph_context_new;
 804         priv->base.context_del = nvc0_graph_context_del;
 805         priv->base.object_new = nvc0_graph_object_new;
 806
 807         NVOBJ_ENGINE_ADD(dev, GR, &priv->base);
 808         nouveau_irq_register(dev, 12, nvc0_graph_isr);
 809
 810         if (nouveau_ctxfw) {
 811                 NV_INFO(dev, "PGRAPH: using external firmware\n");
 812                 if (nvc0_graph_create_fw(dev, "fuc409c", &priv->fuc409c) ||
 813                     nvc0_graph_create_fw(dev, "fuc409d", &priv->fuc409d) ||
 814                     nvc0_graph_create_fw(dev, "fuc41ac", &priv->fuc41ac) ||
 815                     nvc0_graph_create_fw(dev, "fuc41ad", &priv->fuc41ad)) {
 816                         ret = 0;
 817                         goto error;
 818                 }
 819         }
 820
 821         ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4);
 822         if (ret)
 823                 goto error;
 824
 825         ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8);
 826         if (ret)
 827                 goto error;
 828
 829         for (i = 0; i < 0x1000; i += 4) {
 830                 nv_wo32(priv->unk4188b4, i, 0x00000010);
 831                 nv_wo32(priv->unk4188b8, i, 0x00000010);
 832         }
 833
 834         priv->gpc_nr  =  nv_rd32(dev, 0x409604) & 0x0000001f;
 835         priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16;
 836         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 837                 priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608));
 838                 priv->tp_total += priv->tp_nr[gpc];
 839         }
 840
 841         /*XXX: these need figuring out... */
 842         switch (dev_priv->chipset) {
 843         case 0xc0:
 844                 if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */
 845                         priv->magic_not_rop_nr = 0x07;
 846                 } else
 847                 if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */
 848                         priv->magic_not_rop_nr = 0x05;
 849                 } else
 850                 if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */
 851                         priv->magic_not_rop_nr = 0x06;
 852                 }
 853                 break;
 854         case 0xc3: /* 450, 4/0/0/0, 2 */
 855                 priv->magic_not_rop_nr = 0x03;
 856                 break;
 857         case 0xc4: /* 460, 3/4/0/0, 4 */
 858                 priv->magic_not_rop_nr = 0x01;
 859                 break;
 860         case 0xc1: /* 2/0/0/0, 1 */
 861                 priv->magic_not_rop_nr = 0x01;
 862                 break;
 863         case 0xc8: /* 4/4/3/4, 5 */
 864                 priv->magic_not_rop_nr = 0x06;
 865                 break;
 866         case 0xce: /* 4/4/0/0, 4 */
 867                 priv->magic_not_rop_nr = 0x03;
 868                 break;
 869         case 0xcf: /* 4/0/0/0, 3 */
 870                 priv->magic_not_rop_nr = 0x03;
 871                 break;
 872         case 0xd9: /* 1/0/0/0, 1 */
 873                 priv->magic_not_rop_nr = 0x01;
 874                 break;
 875         }
 876
 877         if (!priv->magic_not_rop_nr) {
 878                 NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
 879                          priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2],
 880                          priv->tp_nr[3], priv->rop_nr);
 881                 priv->magic_not_rop_nr = 0x00;
 882         }
 883
 884         NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
 885         NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
 886         NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
 887         if (fermi >= 0x9197)
 888                 NVOBJ_CLASS(dev, 0x9197, GR); /* 3D (NVC1-) */
 889         if (fermi >= 0x9297)
 890                 NVOBJ_CLASS(dev, 0x9297, GR); /* 3D (NVC8-) */
 891         NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
 892         return 0;
 893
 894 error:
 895         nvc0_graph_destroy(dev, NVOBJ_ENGINE_GR);
 896         return ret;
 897 }