2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "nouveau_drv.h"
27 #include "nouveau_dma.h"
28 #include <engine/fifo.h>
29 #include <core/ramht.h>
30 #include "nouveau_fence.h"
32 struct nvc0_fence_priv {
33 struct nouveau_fence_priv base;
34 struct nouveau_bo *bo;
38 struct nvc0_fence_chan {
39 struct nouveau_fence_chan base;
40 struct nouveau_vma vma;
44 nvc0_fence_emit(struct nouveau_fence *fence)
46 struct nouveau_channel *chan = fence->channel;
47 struct nvc0_fence_chan *fctx = chan->fence;
48 u64 addr = fctx->vma.offset + chan->id * 16;
51 ret = RING_SPACE(chan, 5);
53 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
54 OUT_RING (chan, upper_32_bits(addr));
55 OUT_RING (chan, lower_32_bits(addr));
56 OUT_RING (chan, fence->sequence);
57 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
65 nvc0_fence_sync(struct nouveau_fence *fence,
66 struct nouveau_channel *prev, struct nouveau_channel *chan)
68 struct nvc0_fence_chan *fctx = chan->fence;
69 u64 addr = fctx->vma.offset + prev->id * 16;
72 ret = RING_SPACE(chan, 5);
74 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
75 OUT_RING (chan, upper_32_bits(addr));
76 OUT_RING (chan, lower_32_bits(addr));
77 OUT_RING (chan, fence->sequence);
78 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL |
79 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
87 nvc0_fence_read(struct nouveau_channel *chan)
89 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
90 struct nvc0_fence_priv *priv = dev_priv->fence.func;
91 return nouveau_bo_rd32(priv->bo, chan->id * 16/4);
95 nvc0_fence_context_del(struct nouveau_channel *chan)
97 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
98 struct nvc0_fence_priv *priv = dev_priv->fence.func;
99 struct nvc0_fence_chan *fctx = chan->fence;
101 nouveau_bo_vma_del(priv->bo, &fctx->vma);
102 nouveau_fence_context_del(&fctx->base);
108 nvc0_fence_context_new(struct nouveau_channel *chan)
110 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
111 struct nvc0_fence_priv *priv = dev_priv->fence.func;
112 struct nvc0_fence_chan *fctx;
115 fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
119 nouveau_fence_context_new(&fctx->base);
121 ret = nouveau_bo_vma_add(priv->bo, chan->vm, &fctx->vma);
123 nvc0_fence_context_del(chan);
125 nouveau_bo_wr32(priv->bo, chan->id * 16/4, 0x00000000);
130 nvc0_fence_suspend(struct drm_device *dev)
132 struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
133 struct drm_nouveau_private *dev_priv = dev->dev_private;
134 struct nvc0_fence_priv *priv = dev_priv->fence.func;
137 priv->suspend = vmalloc(pfifo->channels * sizeof(u32));
139 for (i = 0; i < pfifo->channels; i++)
140 priv->suspend[i] = nouveau_bo_rd32(priv->bo, i);
143 return priv->suspend != NULL;
147 nvc0_fence_resume(struct drm_device *dev)
149 struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
150 struct drm_nouveau_private *dev_priv = dev->dev_private;
151 struct nvc0_fence_priv *priv = dev_priv->fence.func;
155 for (i = 0; i < pfifo->channels; i++)
156 nouveau_bo_wr32(priv->bo, i, priv->suspend[i]);
157 vfree(priv->suspend);
158 priv->suspend = NULL;
163 nvc0_fence_destroy(struct drm_device *dev)
165 struct drm_nouveau_private *dev_priv = dev->dev_private;
166 struct nvc0_fence_priv *priv = dev_priv->fence.func;
168 nouveau_bo_unmap(priv->bo);
169 nouveau_bo_ref(NULL, &priv->bo);
170 dev_priv->fence.func = NULL;
175 nvc0_fence_create(struct drm_device *dev)
177 struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
178 struct drm_nouveau_private *dev_priv = dev->dev_private;
179 struct nvc0_fence_priv *priv;
182 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
186 priv->base.dtor = nvc0_fence_destroy;
187 priv->base.suspend = nvc0_fence_suspend;
188 priv->base.resume = nvc0_fence_resume;
189 priv->base.context_new = nvc0_fence_context_new;
190 priv->base.context_del = nvc0_fence_context_del;
191 priv->base.emit = nvc0_fence_emit;
192 priv->base.sync = nvc0_fence_sync;
193 priv->base.read = nvc0_fence_read;
194 dev_priv->fence.func = priv;
196 ret = nouveau_bo_new(dev, 16 * pfifo->channels, 0, TTM_PL_FLAG_VRAM,
197 0, 0, NULL, &priv->bo);
199 ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
201 ret = nouveau_bo_map(priv->bo);
203 nouveau_bo_ref(NULL, &priv->bo);
207 nvc0_fence_destroy(dev);