drivers/gpu/drm/nouveau/nv84_fence.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/object.h>
  26 #include <core/class.h>
  27
  28 #include <engine/fifo.h>
  29
  30 #include "nouveau_drm.h"
  31 #include "nouveau_dma.h"
  32 #include "nouveau_fence.h"
  33
  34 struct nv84_fence_chan {
  35         struct nouveau_fence_chan base;
  36 };
  37
  38 struct nv84_fence_priv {
  39         struct nouveau_fence_priv base;
  40         struct nouveau_gpuobj *mem;
  41 };
  42
  43 static int
  44 nv84_fence_emit(struct nouveau_fence *fence)
  45 {
  46         struct nouveau_channel *chan = fence->channel;
  47         struct nouveau_fifo_chan *fifo = (void *)chan->object;
  48         int ret = RING_SPACE(chan, 7);
  49         if (ret == 0) {
  50                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
  51                 OUT_RING  (chan, NvSema);
  52                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
  53                 OUT_RING  (chan, upper_32_bits(fifo->chid * 16));
  54                 OUT_RING  (chan, lower_32_bits(fifo->chid * 16));
  55                 OUT_RING  (chan, fence->sequence);
  56                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
  57                 FIRE_RING (chan);
  58         }
  59         return ret;
  60 }
  61
  62
  63 static int
  64 nv84_fence_sync(struct nouveau_fence *fence,
  65                 struct nouveau_channel *prev, struct nouveau_channel *chan)
  66 {
  67         struct nouveau_fifo_chan *fifo = (void *)prev->object;
  68         int ret = RING_SPACE(chan, 7);
  69         if (ret == 0) {
  70                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
  71                 OUT_RING  (chan, NvSema);
  72                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
  73                 OUT_RING  (chan, upper_32_bits(fifo->chid * 16));
  74                 OUT_RING  (chan, lower_32_bits(fifo->chid * 16));
  75                 OUT_RING  (chan, fence->sequence);
  76                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
  77                 FIRE_RING (chan);
  78         }
  79         return ret;
  80 }
  81
  82 static u32
  83 nv84_fence_read(struct nouveau_channel *chan)
  84 {
  85         struct nouveau_fifo_chan *fifo = (void *)chan->object;
  86         struct nv84_fence_priv *priv = chan->drm->fence;
  87         return nv_ro32(priv->mem, fifo->chid * 16);
  88 }
  89
  90 static void
  91 nv84_fence_context_del(struct nouveau_channel *chan)
  92 {
  93         struct nv84_fence_chan *fctx = chan->fence;
  94         nouveau_fence_context_del(&fctx->base);
  95         chan->fence = NULL;
  96         kfree(fctx);
  97 }
  98
  99 static int
 100 nv84_fence_context_new(struct nouveau_channel *chan)
 101 {
 102         struct nouveau_fifo_chan *fifo = (void *)chan->object;
 103         struct nv84_fence_priv *priv = chan->drm->fence;
 104         struct nv84_fence_chan *fctx;
 105         struct nouveau_object *object;
 106         int ret, i;
 107
 108         fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
 109         if (!fctx)
 110                 return -ENOMEM;
 111
 112         nouveau_fence_context_new(&fctx->base);
 113
 114         ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
 115                                  NvSema, 0x0002,
 116                                  &(struct nv_dma_class) {
 117                                         .flags = NV_DMA_TARGET_VRAM |
 118                                                  NV_DMA_ACCESS_RDWR,
 119                                         .start = priv->mem->addr,
 120                                         .limit = priv->mem->addr +
 121                                                  priv->mem->size - 1,
 122                                  }, sizeof(struct nv_dma_class),
 123                                  &object);
 124
 125         /* dma objects for display sync channel semaphore blocks */
 126         for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) {
 127                 struct nouveau_bo *bo = nv50sema(chan->drm->dev, i);
 128
 129                 ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
 130                                          NvEvoSema0 + i, 0x003d,
 131                                          &(struct nv_dma_class) {
 132                                                 .flags = NV_DMA_TARGET_VRAM |
 133                                                          NV_DMA_ACCESS_RDWR,
 134                                                 .start = bo->bo.offset,
 135                                                 .limit = bo->bo.offset + 0xfff,
 136                                          }, sizeof(struct nv_dma_class),
 137                                          &object);
 138         }
 139
 140         if (ret)
 141                 nv84_fence_context_del(chan);
 142         nv_wo32(priv->mem, fifo->chid * 16, 0x00000000);
 143         return ret;
 144 }
 145
 146 static void
 147 nv84_fence_destroy(struct nouveau_drm *drm)
 148 {
 149         struct nv84_fence_priv *priv = drm->fence;
 150         nouveau_gpuobj_ref(NULL, &priv->mem);
 151         drm->fence = NULL;
 152         kfree(priv);
 153 }
 154
 155 int
 156 nv84_fence_create(struct nouveau_drm *drm)
 157 {
 158         struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
 159         struct nv84_fence_priv *priv;
 160         u32 chan = pfifo->max + 1;
 161         int ret;
 162
 163         priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
 164         if (!priv)
 165                 return -ENOMEM;
 166
 167         priv->base.dtor = nv84_fence_destroy;
 168         priv->base.context_new = nv84_fence_context_new;
 169         priv->base.context_del = nv84_fence_context_del;
 170         priv->base.emit = nv84_fence_emit;
 171         priv->base.sync = nv84_fence_sync;
 172         priv->base.read = nv84_fence_read;
 173
 174         ret = nouveau_gpuobj_new(drm->device, NULL, chan * 16, 0x1000, 0,
 175                                 &priv->mem);
 176         if (ret)
 177                 nv84_fence_destroy(drm);
 178         return ret;
 179 }