drivers/gpu/drm/nouveau/nv84_fence.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26 #include "nouveau_drv.h"
  27 #include "nouveau_dma.h"
  28 #include <engine/fifo.h>
  29 #include <core/ramht.h>
  30 #include "nouveau_fence.h"
  31
  32 struct nv84_fence_chan {
  33         struct nouveau_fence_chan base;
  34 };
  35
  36 struct nv84_fence_priv {
  37         struct nouveau_fence_priv base;
  38         struct nouveau_gpuobj *mem;
  39 };
  40
  41 static int
  42 nv84_fence_emit(struct nouveau_fence *fence)
  43 {
  44         struct nouveau_channel *chan = fence->channel;
  45         int ret = RING_SPACE(chan, 7);
  46         if (ret == 0) {
  47                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
  48                 OUT_RING  (chan, NvSema);
  49                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
  50                 OUT_RING  (chan, upper_32_bits(chan->id * 16));
  51                 OUT_RING  (chan, lower_32_bits(chan->id * 16));
  52                 OUT_RING  (chan, fence->sequence);
  53                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
  54                 FIRE_RING (chan);
  55         }
  56         return ret;
  57 }
  58
  59
  60 static int
  61 nv84_fence_sync(struct nouveau_fence *fence,
  62                 struct nouveau_channel *prev, struct nouveau_channel *chan)
  63 {
  64         int ret = RING_SPACE(chan, 7);
  65         if (ret == 0) {
  66                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
  67                 OUT_RING  (chan, NvSema);
  68                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
  69                 OUT_RING  (chan, upper_32_bits(prev->id * 16));
  70                 OUT_RING  (chan, lower_32_bits(prev->id * 16));
  71                 OUT_RING  (chan, fence->sequence);
  72                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
  73                 FIRE_RING (chan);
  74         }
  75         return ret;
  76 }
  77
  78 static u32
  79 nv84_fence_read(struct nouveau_channel *chan)
  80 {
  81         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  82         struct nv84_fence_priv *priv = dev_priv->fence.func;
  83         return nv_ro32(priv->mem, chan->id * 16);
  84 }
  85
  86 static void
  87 nv84_fence_context_del(struct nouveau_channel *chan)
  88 {
  89         struct nv84_fence_chan *fctx = chan->fence;
  90         nouveau_fence_context_del(&fctx->base);
  91         chan->fence = NULL;
  92         kfree(fctx);
  93 }
  94
  95 static int
  96 nv84_fence_context_new(struct nouveau_channel *chan)
  97 {
  98         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  99         struct nv84_fence_priv *priv = dev_priv->fence.func;
 100         struct nv84_fence_chan *fctx;
 101         struct nouveau_gpuobj *obj;
 102         int ret;
 103
 104         fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
 105         if (!fctx)
 106                 return -ENOMEM;
 107
 108         nouveau_fence_context_new(&fctx->base);
 109
 110         ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_FROM_MEMORY,
 111                                      priv->mem->addr, priv->mem->size,
 112                                      NV_MEM_ACCESS_RW,
 113                                      NV_MEM_TARGET_VRAM, &obj);
 114         if (ret == 0) {
 115                 ret = nouveau_ramht_insert(chan, NvSema, obj);
 116                 nouveau_gpuobj_ref(NULL, &obj);
 117                 nv_wo32(priv->mem, chan->id * 16, 0x00000000);
 118         }
 119
 120         if (ret)
 121                 nv84_fence_context_del(chan);
 122         return ret;
 123 }
 124
 125 static void
 126 nv84_fence_destroy(struct drm_device *dev)
 127 {
 128         struct drm_nouveau_private *dev_priv = dev->dev_private;
 129         struct nv84_fence_priv *priv = dev_priv->fence.func;
 130
 131         nouveau_gpuobj_ref(NULL, &priv->mem);
 132         dev_priv->fence.func = NULL;
 133         kfree(priv);
 134 }
 135
 136 int
 137 nv84_fence_create(struct drm_device *dev)
 138 {
 139         struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
 140         struct drm_nouveau_private *dev_priv = dev->dev_private;
 141         struct nv84_fence_priv *priv;
 142         int ret;
 143
 144         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 145         if (!priv)
 146                 return -ENOMEM;
 147
 148         priv->base.dtor = nv84_fence_destroy;
 149         priv->base.context_new = nv84_fence_context_new;
 150         priv->base.context_del = nv84_fence_context_del;
 151         priv->base.emit = nv84_fence_emit;
 152         priv->base.sync = nv84_fence_sync;
 153         priv->base.read = nv84_fence_read;
 154         dev_priv->fence.func = priv;
 155
 156         ret = nouveau_gpuobj_new(dev, NULL, 16 * pfifo->channels,
 157                                  0x1000, 0, &priv->mem);
 158         if (ret)
 159                 goto out;
 160
 161 out:
 162         if (ret)
 163                 nv84_fence_destroy(dev);
 164         return ret;
 165 }