2 * Copyright 2010 Red Hat Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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27 #include "nouveau_drv.h"
28 #include "nouveau_vm.h"
31 nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 type, u32 pde,
32 struct nouveau_gpuobj *pgt)
34 struct drm_nouveau_private *dev_priv = pgd->dev->dev_private;
35 u32 coverage = (pgt->size >> 3) << type;
39 phys |= 0x01; /* present */
40 phys |= (type == 12) ? 0x02 : 0x00; /* 4KiB pages */
41 if (dev_priv->vram_sys_base) {
42 phys += dev_priv->vram_sys_base;
46 if (coverage <= 32 * 1024 * 1024)
48 else if (coverage <= 64 * 1024 * 1024)
50 else if (coverage < 128 * 1024 * 1024)
53 nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys));
54 nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys));
58 nv50_vm_unmap_pgt(struct nouveau_gpuobj *pgd, u32 pde)
60 nv_wo32(pgd, (pde * 8) + 0, 0x00000000);
61 nv_wo32(pgd, (pde * 8) + 4, 0xdeadcafe);
65 nv50_vm_addr(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
66 u64 phys, u32 memtype, u32 target)
68 struct drm_nouveau_private *dev_priv = pgt->dev->dev_private;
70 phys |= 1; /* present */
71 phys |= (u64)memtype << 40;
73 /* IGPs don't have real VRAM, re-target to stolen system memory */
74 if (target == 0 && dev_priv->vram_sys_base) {
75 phys += dev_priv->vram_sys_base;
81 if (vma->access & NV_MEM_ACCESS_SYS)
84 if (!(vma->access & NV_MEM_ACCESS_WO))
91 nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
92 struct nouveau_vram *mem, u32 pte, u32 cnt, u64 phys)
96 phys = nv50_vm_addr(vma, pgt, phys, mem->memtype, 0);
101 u32 offset_h = upper_32_bits(phys);
102 u32 offset_l = lower_32_bits(phys);
104 for (i = 7; i >= 0; i--) {
105 block = 1 << (i + 3);
106 if (cnt >= block && !(pte & (block - 1)))
109 offset_l |= (i << 7);
111 phys += block << (vma->node->type - 3);
115 nv_wo32(pgt, pte + 0, offset_l);
116 nv_wo32(pgt, pte + 4, offset_h);
124 nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
125 u32 pte, dma_addr_t *list, u32 cnt)
129 u64 phys = nv50_vm_addr(vma, pgt, (u64)*list++, 0, 2);
130 nv_wo32(pgt, pte + 0, lower_32_bits(phys));
131 nv_wo32(pgt, pte + 4, upper_32_bits(phys));
137 nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
141 nv_wo32(pgt, pte + 0, 0x00000000);
142 nv_wo32(pgt, pte + 4, 0x00000000);
148 nv50_vm_flush(struct nouveau_vm *vm)
150 struct drm_nouveau_private *dev_priv = vm->dev->dev_private;
151 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
153 pinstmem->flush(vm->dev);
155 nv50_vm_flush_engine(vm->dev, 6);
159 nv50_vm_flush_engine(struct drm_device *dev, int engine)
161 nv_wr32(dev, 0x100c80, (engine << 16) | 1);
162 if (!nv_wait(dev, 0x100c80, 0x00000001, 0x00000000))
163 NV_ERROR(dev, "vm flush timeout: engine %d\n", engine);