Merge commit 'v2.6.33' into tracing/core
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nv50_display.c
1 /*
2  * Copyright (C) 2008 Maarten Maathuis.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining
6  * a copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sublicense, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the
14  * next paragraph) shall be included in all copies or substantial
15  * portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24  *
25  */
26
27 #include "nv50_display.h"
28 #include "nouveau_crtc.h"
29 #include "nouveau_encoder.h"
30 #include "nouveau_connector.h"
31 #include "nouveau_fb.h"
32 #include "drm_crtc_helper.h"
33
34 static void
35 nv50_evo_channel_del(struct nouveau_channel **pchan)
36 {
37         struct nouveau_channel *chan = *pchan;
38
39         if (!chan)
40                 return;
41         *pchan = NULL;
42
43         nouveau_gpuobj_channel_takedown(chan);
44         nouveau_bo_ref(NULL, &chan->pushbuf_bo);
45
46         if (chan->user)
47                 iounmap(chan->user);
48
49         kfree(chan);
50 }
51
52 static int
53 nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
54                     uint32_t tile_flags, uint32_t magic_flags,
55                     uint32_t offset, uint32_t limit)
56 {
57         struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
58         struct drm_device *dev = evo->dev;
59         struct nouveau_gpuobj *obj = NULL;
60         int ret;
61
62         ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj);
63         if (ret)
64                 return ret;
65         obj->engine = NVOBJ_ENGINE_DISPLAY;
66
67         ret = nouveau_gpuobj_ref_add(dev, evo, name, obj, NULL);
68         if (ret) {
69                 nouveau_gpuobj_del(dev, &obj);
70                 return ret;
71         }
72
73         dev_priv->engine.instmem.prepare_access(dev, true);
74         nv_wo32(dev, obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
75         nv_wo32(dev, obj, 1, limit);
76         nv_wo32(dev, obj, 2, offset);
77         nv_wo32(dev, obj, 3, 0x00000000);
78         nv_wo32(dev, obj, 4, 0x00000000);
79         nv_wo32(dev, obj, 5, 0x00010000);
80         dev_priv->engine.instmem.finish_access(dev);
81
82         return 0;
83 }
84
85 static int
86 nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
87 {
88         struct drm_nouveau_private *dev_priv = dev->dev_private;
89         struct nouveau_channel *chan;
90         int ret;
91
92         chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
93         if (!chan)
94                 return -ENOMEM;
95         *pchan = chan;
96
97         chan->id = -1;
98         chan->dev = dev;
99         chan->user_get = 4;
100         chan->user_put = 0;
101
102         INIT_LIST_HEAD(&chan->ramht_refs);
103
104         ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 32768, 0x1000,
105                                      NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
106         if (ret) {
107                 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
108                 nv50_evo_channel_del(pchan);
109                 return ret;
110         }
111
112         ret = nouveau_mem_init_heap(&chan->ramin_heap, chan->ramin->gpuobj->
113                                     im_pramin->start, 32768);
114         if (ret) {
115                 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
116                 nv50_evo_channel_del(pchan);
117                 return ret;
118         }
119
120         ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 4096, 16,
121                                      0, &chan->ramht);
122         if (ret) {
123                 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
124                 nv50_evo_channel_del(pchan);
125                 return ret;
126         }
127
128         if (dev_priv->chipset != 0x50) {
129                 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
130                                           0, 0xffffffff);
131                 if (ret) {
132                         nv50_evo_channel_del(pchan);
133                         return ret;
134                 }
135
136
137                 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
138                                           0, 0xffffffff);
139                 if (ret) {
140                         nv50_evo_channel_del(pchan);
141                         return ret;
142                 }
143         }
144
145         ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
146                                   0, nouveau_mem_fb_amount(dev));
147         if (ret) {
148                 nv50_evo_channel_del(pchan);
149                 return ret;
150         }
151
152         ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
153                              false, true, &chan->pushbuf_bo);
154         if (ret == 0)
155                 ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM);
156         if (ret) {
157                 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
158                 nv50_evo_channel_del(pchan);
159                 return ret;
160         }
161
162         ret = nouveau_bo_map(chan->pushbuf_bo);
163         if (ret) {
164                 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
165                 nv50_evo_channel_del(pchan);
166                 return ret;
167         }
168
169         chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
170                                         NV50_PDISPLAY_USER(0), PAGE_SIZE);
171         if (!chan->user) {
172                 NV_ERROR(dev, "Error mapping EVO control regs.\n");
173                 nv50_evo_channel_del(pchan);
174                 return -ENOMEM;
175         }
176
177         return 0;
178 }
179
180 int
181 nv50_display_init(struct drm_device *dev)
182 {
183         struct drm_nouveau_private *dev_priv = dev->dev_private;
184         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
185         struct nouveau_channel *evo = dev_priv->evo;
186         struct drm_connector *connector;
187         uint32_t val, ram_amount, hpd_en[2];
188         uint64_t start;
189         int ret, i;
190
191         NV_DEBUG_KMS(dev, "\n");
192
193         nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
194         /*
195          * I think the 0x006101XX range is some kind of main control area
196          * that enables things.
197          */
198         /* CRTC? */
199         for (i = 0; i < 2; i++) {
200                 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
201                 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
202                 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
203                 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
204                 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
205                 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
206                 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
207                 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
208         }
209         /* DAC */
210         for (i = 0; i < 3; i++) {
211                 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
212                 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
213         }
214         /* SOR */
215         for (i = 0; i < 4; i++) {
216                 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
217                 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
218         }
219         /* Something not yet in use, tv-out maybe. */
220         for (i = 0; i < 3; i++) {
221                 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
222                 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
223         }
224
225         for (i = 0; i < 3; i++) {
226                 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
227                         NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
228                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
229         }
230
231         /* This used to be in crtc unblank, but seems out of place there. */
232         nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
233         /* RAM is clamped to 256 MiB. */
234         ram_amount = nouveau_mem_fb_amount(dev);
235         NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
236         if (ram_amount > 256*1024*1024)
237                 ram_amount = 256*1024*1024;
238         nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
239         nv_wr32(dev, NV50_PDISPLAY_UNK_388, 0x150000);
240         nv_wr32(dev, NV50_PDISPLAY_UNK_38C, 0);
241
242         /* The precise purpose is unknown, i suspect it has something to do
243          * with text mode.
244          */
245         if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
246                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
247                 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
248                 if (!nv_wait(0x006194e8, 2, 0)) {
249                         NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
250                         NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
251                                                 nv_rd32(dev, 0x6194e8));
252                         return -EBUSY;
253                 }
254         }
255
256         /* taken from nv bug #12637, attempts to un-wedge the hw if it's
257          * stuck in some unspecified state
258          */
259         start = ptimer->read(dev);
260         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00);
261         while ((val = nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) {
262                 if ((val & 0x9f0000) == 0x20000)
263                         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
264                                                         val | 0x800000);
265
266                 if ((val & 0x3f0000) == 0x30000)
267                         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
268                                                         val | 0x200000);
269
270                 if (ptimer->read(dev) - start > 1000000000ULL) {
271                         NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
272                         NV_ERROR(dev, "0x610200 = 0x%08x\n", val);
273                         return -EBUSY;
274                 }
275         }
276
277         nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
278         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03);
279         if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x40000000, 0x40000000)) {
280                 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
281                 NV_ERROR(dev, "0x610200 = 0x%08x\n",
282                           nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
283                 return -EBUSY;
284         }
285
286         for (i = 0; i < 2; i++) {
287                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
288                 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
289                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
290                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
291                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
292                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
293                         return -EBUSY;
294                 }
295
296                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
297                         NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
298                 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
299                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
300                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
301                         NV_ERROR(dev, "timeout: "
302                                       "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
303                         NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
304                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
305                         return -EBUSY;
306                 }
307         }
308
309         nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->instance >> 8) | 9);
310
311         /* initialise fifo */
312         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0),
313                 ((evo->pushbuf_bo->bo.mem.mm_node->start << PAGE_SHIFT) >> 8) |
314                 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM |
315                 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID);
316         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000);
317         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002);
318         if (!nv_wait(0x610200, 0x80000000, 0x00000000)) {
319                 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
320                 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
321                 return -EBUSY;
322         }
323         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
324                 (nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) |
325                  NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
326         nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
327         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 |
328                 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
329         nv_wr32(dev, 0x610300, nv_rd32(dev, 0x610300) & ~1);
330
331         evo->dma.max = (4096/4) - 2;
332         evo->dma.put = 0;
333         evo->dma.cur = evo->dma.put;
334         evo->dma.free = evo->dma.max - evo->dma.cur;
335
336         ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
337         if (ret)
338                 return ret;
339
340         for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
341                 OUT_RING(evo, 0);
342
343         ret = RING_SPACE(evo, 11);
344         if (ret)
345                 return ret;
346         BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
347         OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
348         OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE);
349         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
350         OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
351         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
352         OUT_RING(evo, 0);
353         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
354         OUT_RING(evo, 0);
355         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
356         OUT_RING(evo, 0);
357         FIRE_RING(evo);
358         if (!nv_wait(0x640004, 0xffffffff, evo->dma.put << 2))
359                 NV_ERROR(dev, "evo pushbuf stalled\n");
360
361         /* enable clock change interrupts. */
362         nv_wr32(dev, 0x610028, 0x00010001);
363         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, (NV50_PDISPLAY_INTR_EN_CLK_UNK10 |
364                                              NV50_PDISPLAY_INTR_EN_CLK_UNK20 |
365                                              NV50_PDISPLAY_INTR_EN_CLK_UNK40));
366
367         /* enable hotplug interrupts */
368         hpd_en[0] = hpd_en[1] = 0;
369         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
370                 struct nouveau_connector *conn = nouveau_connector(connector);
371                 struct dcb_gpio_entry *gpio;
372
373                 if (connector->connector_type != DRM_MODE_CONNECTOR_DVII &&
374                     connector->connector_type != DRM_MODE_CONNECTOR_DVID &&
375                     connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
376                         continue;
377
378                 gpio = nouveau_bios_gpio_entry(dev, conn->dcb->gpio_tag);
379                 if (!gpio)
380                         continue;
381
382                 hpd_en[gpio->line >> 4] |= (0x00010001 << (gpio->line & 0xf));
383         }
384
385         nv_wr32(dev, 0xe054, 0xffffffff);
386         nv_wr32(dev, 0xe050, hpd_en[0]);
387         if (dev_priv->chipset >= 0x90) {
388                 nv_wr32(dev, 0xe074, 0xffffffff);
389                 nv_wr32(dev, 0xe070, hpd_en[1]);
390         }
391
392         return 0;
393 }
394
395 static int nv50_display_disable(struct drm_device *dev)
396 {
397         struct drm_nouveau_private *dev_priv = dev->dev_private;
398         struct drm_crtc *drm_crtc;
399         int ret, i;
400
401         NV_DEBUG_KMS(dev, "\n");
402
403         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
404                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
405
406                 nv50_crtc_blank(crtc, true);
407         }
408
409         ret = RING_SPACE(dev_priv->evo, 2);
410         if (ret == 0) {
411                 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
412                 OUT_RING(dev_priv->evo, 0);
413         }
414         FIRE_RING(dev_priv->evo);
415
416         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
417          * cleaning up?
418          */
419         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
420                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
421                 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
422
423                 if (!crtc->base.enabled)
424                         continue;
425
426                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
427                 if (!nv_wait(NV50_PDISPLAY_INTR_1, mask, mask)) {
428                         NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
429                                       "0x%08x\n", mask, mask);
430                         NV_ERROR(dev, "0x610024 = 0x%08x\n",
431                                  nv_rd32(dev, NV50_PDISPLAY_INTR_1));
432                 }
433         }
434
435         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0);
436         nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, 0);
437         if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) {
438                 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
439                 NV_ERROR(dev, "0x610200 = 0x%08x\n",
440                           nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
441         }
442
443         for (i = 0; i < 3; i++) {
444                 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_STATE(i),
445                              NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
446                         NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
447                         NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
448                                   nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
449                 }
450         }
451
452         /* disable interrupts. */
453         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 0x00000000);
454
455         /* disable hotplug interrupts */
456         nv_wr32(dev, 0xe054, 0xffffffff);
457         nv_wr32(dev, 0xe050, 0x00000000);
458         if (dev_priv->chipset >= 0x90) {
459                 nv_wr32(dev, 0xe074, 0xffffffff);
460                 nv_wr32(dev, 0xe070, 0x00000000);
461         }
462         return 0;
463 }
464
465 int nv50_display_create(struct drm_device *dev)
466 {
467         struct drm_nouveau_private *dev_priv = dev->dev_private;
468         struct parsed_dcb *dcb = dev_priv->vbios->dcb;
469         uint32_t connector[16] = {};
470         int ret, i;
471
472         NV_DEBUG_KMS(dev, "\n");
473
474         /* init basic kernel modesetting */
475         drm_mode_config_init(dev);
476
477         /* Initialise some optional connector properties. */
478         drm_mode_create_scaling_mode_property(dev);
479         drm_mode_create_dithering_property(dev);
480
481         dev->mode_config.min_width = 0;
482         dev->mode_config.min_height = 0;
483
484         dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
485
486         dev->mode_config.max_width = 8192;
487         dev->mode_config.max_height = 8192;
488
489         dev->mode_config.fb_base = dev_priv->fb_phys;
490
491         /* Create EVO channel */
492         ret = nv50_evo_channel_new(dev, &dev_priv->evo);
493         if (ret) {
494                 NV_ERROR(dev, "Error creating EVO channel: %d\n", ret);
495                 return ret;
496         }
497
498         /* Create CRTC objects */
499         for (i = 0; i < 2; i++)
500                 nv50_crtc_create(dev, i);
501
502         /* We setup the encoders from the BIOS table */
503         for (i = 0 ; i < dcb->entries; i++) {
504                 struct dcb_entry *entry = &dcb->entry[i];
505
506                 if (entry->location != DCB_LOC_ON_CHIP) {
507                         NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
508                                 entry->type, ffs(entry->or) - 1);
509                         continue;
510                 }
511
512                 switch (entry->type) {
513                 case OUTPUT_TMDS:
514                 case OUTPUT_LVDS:
515                 case OUTPUT_DP:
516                         nv50_sor_create(dev, entry);
517                         break;
518                 case OUTPUT_ANALOG:
519                         nv50_dac_create(dev, entry);
520                         break;
521                 default:
522                         NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
523                         continue;
524                 }
525
526                 connector[entry->connector] |= (1 << entry->type);
527         }
528
529         /* It appears that DCB 3.0+ VBIOS has a connector table, however,
530          * I'm not 100% certain how to decode it correctly yet so just
531          * look at what encoders are present on each connector index and
532          * attempt to derive the connector type from that.
533          */
534         for (i = 0 ; i < dcb->entries; i++) {
535                 struct dcb_entry *entry = &dcb->entry[i];
536                 uint16_t encoders;
537                 int type;
538
539                 encoders = connector[entry->connector];
540                 if (!(encoders & (1 << entry->type)))
541                         continue;
542                 connector[entry->connector] = 0;
543
544                 if (encoders & (1 << OUTPUT_DP)) {
545                         type = DRM_MODE_CONNECTOR_DisplayPort;
546                 } else if (encoders & (1 << OUTPUT_TMDS)) {
547                         if (encoders & (1 << OUTPUT_ANALOG))
548                                 type = DRM_MODE_CONNECTOR_DVII;
549                         else
550                                 type = DRM_MODE_CONNECTOR_DVID;
551                 } else if (encoders & (1 << OUTPUT_ANALOG)) {
552                         type = DRM_MODE_CONNECTOR_VGA;
553                 } else if (encoders & (1 << OUTPUT_LVDS)) {
554                         type = DRM_MODE_CONNECTOR_LVDS;
555                 } else {
556                         type = DRM_MODE_CONNECTOR_Unknown;
557                 }
558
559                 if (type == DRM_MODE_CONNECTOR_Unknown)
560                         continue;
561
562                 nouveau_connector_create(dev, entry->connector, type);
563         }
564
565         ret = nv50_display_init(dev);
566         if (ret)
567                 return ret;
568
569         return 0;
570 }
571
572 int nv50_display_destroy(struct drm_device *dev)
573 {
574         struct drm_nouveau_private *dev_priv = dev->dev_private;
575
576         NV_DEBUG_KMS(dev, "\n");
577
578         drm_mode_config_cleanup(dev);
579
580         nv50_display_disable(dev);
581         nv50_evo_channel_del(&dev_priv->evo);
582
583         return 0;
584 }
585
586 static inline uint32_t
587 nv50_display_mode_ctrl(struct drm_device *dev, bool sor, int or)
588 {
589         struct drm_nouveau_private *dev_priv = dev->dev_private;
590         uint32_t mc;
591
592         if (sor) {
593                 if (dev_priv->chipset < 0x90 ||
594                     dev_priv->chipset == 0x92 || dev_priv->chipset == 0xa0)
595                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(or));
596                 else
597                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(or));
598         } else {
599                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(or));
600         }
601
602         return mc;
603 }
604
605 static int
606 nv50_display_irq_head(struct drm_device *dev, int *phead,
607                       struct dcb_entry **pdcbent)
608 {
609         struct drm_nouveau_private *dev_priv = dev->dev_private;
610         uint32_t unk30 = nv_rd32(dev, NV50_PDISPLAY_UNK30_CTRL);
611         uint32_t dac = 0, sor = 0;
612         int head, i, or = 0, type = OUTPUT_ANY;
613
614         /* We're assuming that head 0 *or* head 1 will be active here,
615          * and not both.  I'm not sure if the hw will even signal both
616          * ever, but it definitely shouldn't for us as we commit each
617          * CRTC separately, and submission will be blocked by the GPU
618          * until we handle each in turn.
619          */
620         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
621         head = ffs((unk30 >> 9) & 3) - 1;
622         if (head < 0)
623                 return -EINVAL;
624
625         /* This assumes CRTCs are never bound to multiple encoders, which
626          * should be the case.
627          */
628         for (i = 0; i < 3 && type == OUTPUT_ANY; i++) {
629                 uint32_t mc = nv50_display_mode_ctrl(dev, false, i);
630                 if (!(mc & (1 << head)))
631                         continue;
632
633                 switch ((mc >> 8) & 0xf) {
634                 case 0: type = OUTPUT_ANALOG; break;
635                 case 1: type = OUTPUT_TV; break;
636                 default:
637                         NV_ERROR(dev, "unknown dac mode_ctrl: 0x%08x\n", dac);
638                         return -1;
639                 }
640
641                 or = i;
642         }
643
644         for (i = 0; i < 4 && type == OUTPUT_ANY; i++) {
645                 uint32_t mc = nv50_display_mode_ctrl(dev, true, i);
646                 if (!(mc & (1 << head)))
647                         continue;
648
649                 switch ((mc >> 8) & 0xf) {
650                 case 0: type = OUTPUT_LVDS; break;
651                 case 1: type = OUTPUT_TMDS; break;
652                 case 2: type = OUTPUT_TMDS; break;
653                 case 5: type = OUTPUT_TMDS; break;
654                 case 8: type = OUTPUT_DP; break;
655                 case 9: type = OUTPUT_DP; break;
656                 default:
657                         NV_ERROR(dev, "unknown sor mode_ctrl: 0x%08x\n", sor);
658                         return -1;
659                 }
660
661                 or = i;
662         }
663
664         NV_DEBUG_KMS(dev, "type %d, or %d\n", type, or);
665         if (type == OUTPUT_ANY) {
666                 NV_ERROR(dev, "unknown encoder!!\n");
667                 return -1;
668         }
669
670         for (i = 0; i < dev_priv->vbios->dcb->entries; i++) {
671                 struct dcb_entry *dcbent = &dev_priv->vbios->dcb->entry[i];
672
673                 if (dcbent->type != type)
674                         continue;
675
676                 if (!(dcbent->or & (1 << or)))
677                         continue;
678
679                 *phead = head;
680                 *pdcbent = dcbent;
681                 return 0;
682         }
683
684         NV_ERROR(dev, "no DCB entry for %d %d\n", dac != 0, or);
685         return 0;
686 }
687
688 static uint32_t
689 nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcbent,
690                            int pxclk)
691 {
692         struct drm_nouveau_private *dev_priv = dev->dev_private;
693         struct nouveau_connector *nv_connector = NULL;
694         struct drm_encoder *encoder;
695         struct nvbios *bios = &dev_priv->VBIOS;
696         uint32_t mc, script = 0, or;
697
698         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
699                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
700
701                 if (nv_encoder->dcb != dcbent)
702                         continue;
703
704                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
705                 break;
706         }
707
708         or = ffs(dcbent->or) - 1;
709         mc = nv50_display_mode_ctrl(dev, dcbent->type != OUTPUT_ANALOG, or);
710         switch (dcbent->type) {
711         case OUTPUT_LVDS:
712                 script = (mc >> 8) & 0xf;
713                 if (bios->pub.fp_no_ddc) {
714                         if (bios->fp.dual_link)
715                                 script |= 0x0100;
716                         if (bios->fp.if_is_24bit)
717                                 script |= 0x0200;
718                 } else {
719                         if (pxclk >= bios->fp.duallink_transition_clk) {
720                                 script |= 0x0100;
721                                 if (bios->fp.strapless_is_24bit & 2)
722                                         script |= 0x0200;
723                         } else
724                         if (bios->fp.strapless_is_24bit & 1)
725                                 script |= 0x0200;
726
727                         if (nv_connector && nv_connector->edid &&
728                             (nv_connector->edid->revision >= 4) &&
729                             (nv_connector->edid->input & 0x70) >= 0x20)
730                                 script |= 0x0200;
731                 }
732
733                 if (nouveau_uscript_lvds >= 0) {
734                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
735                                      "for output LVDS-%d\n", script,
736                                      nouveau_uscript_lvds, or);
737                         script = nouveau_uscript_lvds;
738                 }
739                 break;
740         case OUTPUT_TMDS:
741                 script = (mc >> 8) & 0xf;
742                 if (pxclk >= 165000)
743                         script |= 0x0100;
744
745                 if (nouveau_uscript_tmds >= 0) {
746                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
747                                      "for output TMDS-%d\n", script,
748                                      nouveau_uscript_tmds, or);
749                         script = nouveau_uscript_tmds;
750                 }
751                 break;
752         case OUTPUT_DP:
753                 script = (mc >> 8) & 0xf;
754                 break;
755         case OUTPUT_ANALOG:
756                 script = 0xff;
757                 break;
758         default:
759                 NV_ERROR(dev, "modeset on unsupported output type!\n");
760                 break;
761         }
762
763         return script;
764 }
765
766 static void
767 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
768 {
769         struct drm_nouveau_private *dev_priv = dev->dev_private;
770         struct nouveau_channel *chan;
771         struct list_head *entry, *tmp;
772
773         list_for_each_safe(entry, tmp, &dev_priv->vbl_waiting) {
774                 chan = list_entry(entry, struct nouveau_channel, nvsw.vbl_wait);
775
776                 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
777                                                 chan->nvsw.vblsem_rval);
778                 list_del(&chan->nvsw.vbl_wait);
779         }
780 }
781
782 static void
783 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
784 {
785         intr &= NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
786
787         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
788                 nv50_display_vblank_crtc_handler(dev, 0);
789
790         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
791                 nv50_display_vblank_crtc_handler(dev, 1);
792
793         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
794                      NV50_PDISPLAY_INTR_EN) & ~intr);
795         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr);
796 }
797
798 static void
799 nv50_display_unk10_handler(struct drm_device *dev)
800 {
801         struct dcb_entry *dcbent;
802         int head, ret;
803
804         ret = nv50_display_irq_head(dev, &head, &dcbent);
805         if (ret)
806                 goto ack;
807
808         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
809
810         nouveau_bios_run_display_table(dev, dcbent, 0, -1);
811
812 ack:
813         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
814         nv_wr32(dev, 0x610030, 0x80000000);
815 }
816
817 static void
818 nv50_display_unk20_handler(struct drm_device *dev)
819 {
820         struct dcb_entry *dcbent;
821         uint32_t tmp, pclk, script;
822         int head, or, ret;
823
824         ret = nv50_display_irq_head(dev, &head, &dcbent);
825         if (ret)
826                 goto ack;
827         or = ffs(dcbent->or) - 1;
828         pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff;
829         script = nv50_display_script_select(dev, dcbent, pclk);
830
831         NV_DEBUG_KMS(dev, "head %d pxclk: %dKHz\n", head, pclk);
832
833         if (dcbent->type != OUTPUT_DP)
834                 nouveau_bios_run_display_table(dev, dcbent, 0, -2);
835
836         nv50_crtc_set_clock(dev, head, pclk);
837
838         nouveau_bios_run_display_table(dev, dcbent, script, pclk);
839
840         tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(head));
841         tmp &= ~0x000000f;
842         nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(head), tmp);
843
844         if (dcbent->type != OUTPUT_ANALOG) {
845                 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
846                 tmp &= ~0x00000f0f;
847                 if (script & 0x0100)
848                         tmp |= 0x00000101;
849                 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
850         } else {
851                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
852         }
853
854 ack:
855         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
856         nv_wr32(dev, 0x610030, 0x80000000);
857 }
858
859 static void
860 nv50_display_unk40_handler(struct drm_device *dev)
861 {
862         struct dcb_entry *dcbent;
863         int head, pclk, script, ret;
864
865         ret = nv50_display_irq_head(dev, &head, &dcbent);
866         if (ret)
867                 goto ack;
868         pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff;
869         script = nv50_display_script_select(dev, dcbent, pclk);
870
871         nouveau_bios_run_display_table(dev, dcbent, script, -pclk);
872
873 ack:
874         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
875         nv_wr32(dev, 0x610030, 0x80000000);
876         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
877 }
878
879 void
880 nv50_display_irq_handler_bh(struct work_struct *work)
881 {
882         struct drm_nouveau_private *dev_priv =
883                 container_of(work, struct drm_nouveau_private, irq_work);
884         struct drm_device *dev = dev_priv->dev;
885
886         for (;;) {
887                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
888                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
889
890                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
891
892                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
893                         nv50_display_unk10_handler(dev);
894                 else
895                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
896                         nv50_display_unk20_handler(dev);
897                 else
898                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
899                         nv50_display_unk40_handler(dev);
900                 else
901                         break;
902         }
903
904         nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
905 }
906
907 static void
908 nv50_display_error_handler(struct drm_device *dev)
909 {
910         uint32_t addr, data;
911
912         nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000);
913         addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR);
914         data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA);
915
916         NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)\n",
917                  0, addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
918
919         nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000);
920 }
921
922 static void
923 nv50_display_irq_hotplug(struct drm_device *dev)
924 {
925         struct drm_nouveau_private *dev_priv = dev->dev_private;
926         struct drm_connector *connector;
927         const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
928         uint32_t unplug_mask, plug_mask, change_mask;
929         uint32_t hpd0, hpd1 = 0;
930
931         hpd0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
932         if (dev_priv->chipset >= 0x90)
933                 hpd1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
934
935         plug_mask   = (hpd0 & 0x0000ffff) | (hpd1 << 16);
936         unplug_mask = (hpd0 >> 16) | (hpd1 & 0xffff0000);
937         change_mask = plug_mask | unplug_mask;
938
939         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
940                 struct drm_encoder_helper_funcs *helper;
941                 struct nouveau_connector *nv_connector =
942                         nouveau_connector(connector);
943                 struct nouveau_encoder *nv_encoder;
944                 struct dcb_gpio_entry *gpio;
945                 uint32_t reg;
946                 bool plugged;
947
948                 if (!nv_connector->dcb)
949                         continue;
950
951                 gpio = nouveau_bios_gpio_entry(dev, nv_connector->dcb->gpio_tag);
952                 if (!gpio || !(change_mask & (1 << gpio->line)))
953                         continue;
954
955                 reg = nv_rd32(dev, gpio_reg[gpio->line >> 3]);
956                 plugged = !!(reg & (4 << ((gpio->line & 7) << 2)));
957                 NV_INFO(dev, "%splugged %s\n", plugged ? "" : "un",
958                         drm_get_connector_name(connector)) ;
959
960                 if (!connector->encoder || !connector->encoder->crtc ||
961                     !connector->encoder->crtc->enabled)
962                         continue;
963                 nv_encoder = nouveau_encoder(connector->encoder);
964                 helper = connector->encoder->helper_private;
965
966                 if (nv_encoder->dcb->type != OUTPUT_DP)
967                         continue;
968
969                 if (plugged)
970                         helper->dpms(connector->encoder, DRM_MODE_DPMS_ON);
971                 else
972                         helper->dpms(connector->encoder, DRM_MODE_DPMS_OFF);
973         }
974
975         nv_wr32(dev, 0xe054, nv_rd32(dev, 0xe054));
976         if (dev_priv->chipset >= 0x90)
977                 nv_wr32(dev, 0xe074, nv_rd32(dev, 0xe074));
978 }
979
980 void
981 nv50_display_irq_handler(struct drm_device *dev)
982 {
983         struct drm_nouveau_private *dev_priv = dev->dev_private;
984         uint32_t delayed = 0;
985
986         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG)
987                 nv50_display_irq_hotplug(dev);
988
989         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
990                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
991                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
992                 uint32_t clock;
993
994                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
995
996                 if (!intr0 && !(intr1 & ~delayed))
997                         break;
998
999                 if (intr0 & 0x00010000) {
1000                         nv50_display_error_handler(dev);
1001                         intr0 &= ~0x00010000;
1002                 }
1003
1004                 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
1005                         nv50_display_vblank_handler(dev, intr1);
1006                         intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
1007                 }
1008
1009                 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
1010                                   NV50_PDISPLAY_INTR_1_CLK_UNK20 |
1011                                   NV50_PDISPLAY_INTR_1_CLK_UNK40));
1012                 if (clock) {
1013                         nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
1014                         if (!work_pending(&dev_priv->irq_work))
1015                                 queue_work(dev_priv->wq, &dev_priv->irq_work);
1016                         delayed |= clock;
1017                         intr1 &= ~clock;
1018                 }
1019
1020                 if (intr0) {
1021                         NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
1022                         nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
1023                 }
1024
1025                 if (intr1) {
1026                         NV_ERROR(dev,
1027                                  "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1028                         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1029                 }
1030         }
1031 }
1032