2 * Copyright 2011 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/dma-mapping.h>
26 #include <linux/hdmi.h>
29 #include <drm/drm_atomic.h>
30 #include <drm/drm_atomic_helper.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/drm_dp_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include <drm/drm_plane_helper.h>
35 #include <drm/drm_edid.h>
37 #include <nvif/class.h>
38 #include <nvif/cl0002.h>
39 #include <nvif/cl5070.h>
40 #include <nvif/cl507a.h>
41 #include <nvif/cl507b.h>
42 #include <nvif/cl507c.h>
43 #include <nvif/cl507d.h>
44 #include <nvif/cl507e.h>
45 #include <nvif/event.h>
47 #include "nouveau_drv.h"
48 #include "nouveau_dma.h"
49 #include "nouveau_gem.h"
50 #include "nouveau_connector.h"
51 #include "nouveau_encoder.h"
52 #include "nouveau_crtc.h"
53 #include "nouveau_fence.h"
54 #include "nouveau_fbcon.h"
55 #include "nv50_display.h"
59 #define EVO_MASTER (0x00)
60 #define EVO_FLIP(c) (0x01 + (c))
61 #define EVO_OVLY(c) (0x05 + (c))
62 #define EVO_OIMM(c) (0x09 + (c))
63 #define EVO_CURS(c) (0x0d + (c))
65 /* offsets in shared sync bo of various structures */
66 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
67 #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
68 #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
69 #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
70 #define EVO_FLIP_NTFY0(c) EVO_SYNC((c) + 1, 0x20)
71 #define EVO_FLIP_NTFY1(c) EVO_SYNC((c) + 1, 0x30)
73 /******************************************************************************
75 *****************************************************************************/
76 #define nv50_atom(p) container_of((p), struct nv50_atom, state)
79 struct drm_atomic_state state;
81 struct list_head outp;
86 struct nv50_outp_atom {
87 struct list_head head;
89 struct drm_encoder *encoder;
107 #define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)
109 struct nv50_head_atom {
110 struct drm_crtc_state state;
119 struct nv50_head_mode {
216 static inline struct nv50_head_atom *
217 nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc)
219 struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc);
221 return (void *)statec;
222 return nv50_head_atom(statec);
225 #define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state)
227 struct nv50_wndw_atom {
228 struct drm_plane_state state;
231 struct drm_rect clip;
292 /******************************************************************************
294 *****************************************************************************/
297 struct nvif_object user;
298 struct nvif_device *device;
302 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
303 const s32 *oclass, u8 head, void *data, u32 size,
304 struct nv50_chan *chan)
306 struct nvif_sclass *sclass;
309 chan->device = device;
311 ret = n = nvif_object_sclass_get(disp, &sclass);
316 for (i = 0; i < n; i++) {
317 if (sclass[i].oclass == oclass[0]) {
318 ret = nvif_object_init(disp, 0, oclass[0],
319 data, size, &chan->user);
321 nvif_object_map(&chan->user, NULL, 0);
322 nvif_object_sclass_put(&sclass);
329 nvif_object_sclass_put(&sclass);
334 nv50_chan_destroy(struct nv50_chan *chan)
336 nvif_object_fini(&chan->user);
339 /******************************************************************************
341 *****************************************************************************/
344 struct nv50_chan base;
348 nv50_pioc_destroy(struct nv50_pioc *pioc)
350 nv50_chan_destroy(&pioc->base);
354 nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp,
355 const s32 *oclass, u8 head, void *data, u32 size,
356 struct nv50_pioc *pioc)
358 return nv50_chan_create(device, disp, oclass, head, data, size,
362 /******************************************************************************
364 *****************************************************************************/
367 struct nv50_pioc base;
371 nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp,
372 int head, struct nv50_oimm *oimm)
374 struct nv50_disp_cursor_v0 args = {
377 static const s32 oclass[] = {
386 return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
390 /******************************************************************************
392 *****************************************************************************/
394 struct nv50_dmac_ctxdma {
395 struct list_head head;
396 struct nvif_object object;
400 struct nv50_chan base;
404 struct nvif_object sync;
405 struct nvif_object vram;
406 struct list_head ctxdma;
408 /* Protects against concurrent pushbuf access to this channel, lock is
409 * grabbed by evo_wait (if the pushbuf reservation is successful) and
410 * dropped again by evo_kick. */
415 nv50_dmac_ctxdma_del(struct nv50_dmac_ctxdma *ctxdma)
417 nvif_object_fini(&ctxdma->object);
418 list_del(&ctxdma->head);
422 static struct nv50_dmac_ctxdma *
423 nv50_dmac_ctxdma_new(struct nv50_dmac *dmac, struct nouveau_framebuffer *fb)
425 struct nouveau_drm *drm = nouveau_drm(fb->base.dev);
426 struct nv50_dmac_ctxdma *ctxdma;
427 const u8 kind = fb->nvbo->kind;
428 const u32 handle = 0xfb000000 | kind;
430 struct nv_dma_v0 base;
432 struct nv50_dma_v0 nv50;
433 struct gf100_dma_v0 gf100;
434 struct gf119_dma_v0 gf119;
437 u32 argc = sizeof(args.base);
440 list_for_each_entry(ctxdma, &dmac->ctxdma, head) {
441 if (ctxdma->object.handle == handle)
445 if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL)))
446 return ERR_PTR(-ENOMEM);
447 list_add(&ctxdma->head, &dmac->ctxdma);
449 args.base.target = NV_DMA_V0_TARGET_VRAM;
450 args.base.access = NV_DMA_V0_ACCESS_RDWR;
452 args.base.limit = drm->client.device.info.ram_user - 1;
454 if (drm->client.device.info.chipset < 0x80) {
455 args.nv50.part = NV50_DMA_V0_PART_256;
456 argc += sizeof(args.nv50);
458 if (drm->client.device.info.chipset < 0xc0) {
459 args.nv50.part = NV50_DMA_V0_PART_256;
460 args.nv50.kind = kind;
461 argc += sizeof(args.nv50);
463 if (drm->client.device.info.chipset < 0xd0) {
464 args.gf100.kind = kind;
465 argc += sizeof(args.gf100);
467 args.gf119.page = GF119_DMA_V0_PAGE_LP;
468 args.gf119.kind = kind;
469 argc += sizeof(args.gf119);
472 ret = nvif_object_init(&dmac->base.user, handle, NV_DMA_IN_MEMORY,
473 &args, argc, &ctxdma->object);
475 nv50_dmac_ctxdma_del(ctxdma);
483 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
485 struct nvif_device *device = dmac->base.device;
486 struct nv50_dmac_ctxdma *ctxdma, *ctxtmp;
488 list_for_each_entry_safe(ctxdma, ctxtmp, &dmac->ctxdma, head) {
489 nv50_dmac_ctxdma_del(ctxdma);
492 nvif_object_fini(&dmac->vram);
493 nvif_object_fini(&dmac->sync);
495 nv50_chan_destroy(&dmac->base);
498 struct device *dev = nvxx_device(device)->dev;
499 dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle);
504 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
505 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
506 struct nv50_dmac *dmac)
508 struct nv50_disp_core_channel_dma_v0 *args = data;
509 struct nvif_object pushbuf;
512 mutex_init(&dmac->lock);
513 INIT_LIST_HEAD(&dmac->ctxdma);
515 dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE,
516 &dmac->handle, GFP_KERNEL);
520 ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
521 &(struct nv_dma_v0) {
522 .target = NV_DMA_V0_TARGET_PCI_US,
523 .access = NV_DMA_V0_ACCESS_RD,
524 .start = dmac->handle + 0x0000,
525 .limit = dmac->handle + 0x0fff,
526 }, sizeof(struct nv_dma_v0), &pushbuf);
530 args->pushbuf = nvif_handle(&pushbuf);
532 ret = nv50_chan_create(device, disp, oclass, head, data, size,
534 nvif_object_fini(&pushbuf);
538 ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
539 &(struct nv_dma_v0) {
540 .target = NV_DMA_V0_TARGET_VRAM,
541 .access = NV_DMA_V0_ACCESS_RDWR,
542 .start = syncbuf + 0x0000,
543 .limit = syncbuf + 0x0fff,
544 }, sizeof(struct nv_dma_v0),
549 ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
550 &(struct nv_dma_v0) {
551 .target = NV_DMA_V0_TARGET_VRAM,
552 .access = NV_DMA_V0_ACCESS_RDWR,
554 .limit = device->info.ram_user - 1,
555 }, sizeof(struct nv_dma_v0),
563 /******************************************************************************
565 *****************************************************************************/
568 struct nv50_dmac base;
572 nv50_core_create(struct nvif_device *device, struct nvif_object *disp,
573 u64 syncbuf, struct nv50_mast *core)
575 struct nv50_disp_core_channel_dma_v0 args = {
576 .pushbuf = 0xb0007d00,
578 static const s32 oclass[] = {
579 GP102_DISP_CORE_CHANNEL_DMA,
580 GP100_DISP_CORE_CHANNEL_DMA,
581 GM200_DISP_CORE_CHANNEL_DMA,
582 GM107_DISP_CORE_CHANNEL_DMA,
583 GK110_DISP_CORE_CHANNEL_DMA,
584 GK104_DISP_CORE_CHANNEL_DMA,
585 GF110_DISP_CORE_CHANNEL_DMA,
586 GT214_DISP_CORE_CHANNEL_DMA,
587 GT206_DISP_CORE_CHANNEL_DMA,
588 GT200_DISP_CORE_CHANNEL_DMA,
589 G82_DISP_CORE_CHANNEL_DMA,
590 NV50_DISP_CORE_CHANNEL_DMA,
594 return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args),
595 syncbuf, &core->base);
598 /******************************************************************************
600 *****************************************************************************/
603 struct nv50_dmac base;
609 nv50_base_create(struct nvif_device *device, struct nvif_object *disp,
610 int head, u64 syncbuf, struct nv50_sync *base)
612 struct nv50_disp_base_channel_dma_v0 args = {
613 .pushbuf = 0xb0007c00 | head,
616 static const s32 oclass[] = {
617 GK110_DISP_BASE_CHANNEL_DMA,
618 GK104_DISP_BASE_CHANNEL_DMA,
619 GF110_DISP_BASE_CHANNEL_DMA,
620 GT214_DISP_BASE_CHANNEL_DMA,
621 GT200_DISP_BASE_CHANNEL_DMA,
622 G82_DISP_BASE_CHANNEL_DMA,
623 NV50_DISP_BASE_CHANNEL_DMA,
627 return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
628 syncbuf, &base->base);
631 /******************************************************************************
633 *****************************************************************************/
636 struct nv50_dmac base;
640 nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp,
641 int head, u64 syncbuf, struct nv50_ovly *ovly)
643 struct nv50_disp_overlay_channel_dma_v0 args = {
644 .pushbuf = 0xb0007e00 | head,
647 static const s32 oclass[] = {
648 GK104_DISP_OVERLAY_CONTROL_DMA,
649 GF110_DISP_OVERLAY_CONTROL_DMA,
650 GT214_DISP_OVERLAY_CHANNEL_DMA,
651 GT200_DISP_OVERLAY_CHANNEL_DMA,
652 G82_DISP_OVERLAY_CHANNEL_DMA,
653 NV50_DISP_OVERLAY_CHANNEL_DMA,
657 return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
658 syncbuf, &ovly->base);
662 struct nouveau_crtc base;
663 struct nv50_ovly ovly;
664 struct nv50_oimm oimm;
667 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
668 #define nv50_ovly(c) (&nv50_head(c)->ovly)
669 #define nv50_oimm(c) (&nv50_head(c)->oimm)
670 #define nv50_chan(c) (&(c)->base.base)
671 #define nv50_vers(c) nv50_chan(c)->user.oclass
674 struct nvif_object *disp;
675 struct nv50_mast mast;
677 struct nouveau_bo *sync;
682 static struct nv50_disp *
683 nv50_disp(struct drm_device *dev)
685 return nouveau_display(dev)->priv;
688 #define nv50_mast(d) (&nv50_disp(d)->mast)
690 /******************************************************************************
691 * EVO channel helpers
692 *****************************************************************************/
694 evo_wait(void *evoc, int nr)
696 struct nv50_dmac *dmac = evoc;
697 struct nvif_device *device = dmac->base.device;
698 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
700 mutex_lock(&dmac->lock);
701 if (put + nr >= (PAGE_SIZE / 4) - 8) {
702 dmac->ptr[put] = 0x20000000;
704 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
705 if (nvif_msec(device, 2000,
706 if (!nvif_rd32(&dmac->base.user, 0x0004))
709 mutex_unlock(&dmac->lock);
710 pr_err("nouveau: evo channel stalled\n");
717 return dmac->ptr + put;
721 evo_kick(u32 *push, void *evoc)
723 struct nv50_dmac *dmac = evoc;
724 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
725 mutex_unlock(&dmac->lock);
728 #define evo_mthd(p, m, s) do { \
729 const u32 _m = (m), _s = (s); \
730 if (drm_debug & DRM_UT_KMS) \
731 pr_err("%04x %d %s\n", _m, _s, __func__); \
732 *((p)++) = ((_s << 18) | _m); \
735 #define evo_data(p, d) do { \
736 const u32 _d = (d); \
737 if (drm_debug & DRM_UT_KMS) \
738 pr_err("\t%08x\n", _d); \
742 /******************************************************************************
744 *****************************************************************************/
745 #define nv50_wndw(p) container_of((p), struct nv50_wndw, plane)
748 const struct nv50_wndw_func *func;
749 struct nv50_dmac *dmac;
751 struct drm_plane plane;
753 struct nvif_notify notify;
759 struct nv50_wndw_func {
760 void *(*dtor)(struct nv50_wndw *);
761 int (*acquire)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
762 struct nv50_head_atom *asyh);
763 void (*release)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
764 struct nv50_head_atom *asyh);
765 void (*prepare)(struct nv50_wndw *, struct nv50_head_atom *asyh,
766 struct nv50_wndw_atom *asyw);
768 void (*sema_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
769 void (*sema_clr)(struct nv50_wndw *);
770 void (*ntfy_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
771 void (*ntfy_clr)(struct nv50_wndw *);
772 int (*ntfy_wait_begun)(struct nv50_wndw *, struct nv50_wndw_atom *);
773 void (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
774 void (*image_clr)(struct nv50_wndw *);
775 void (*lut)(struct nv50_wndw *, struct nv50_wndw_atom *);
776 void (*point)(struct nv50_wndw *, struct nv50_wndw_atom *);
778 u32 (*update)(struct nv50_wndw *, u32 interlock);
782 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
785 return wndw->func->ntfy_wait_begun(wndw, asyw);
790 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 interlock, bool flush,
791 struct nv50_wndw_atom *asyw)
793 if (asyw->clr.sema && (!asyw->set.sema || flush))
794 wndw->func->sema_clr(wndw);
795 if (asyw->clr.ntfy && (!asyw->set.ntfy || flush))
796 wndw->func->ntfy_clr(wndw);
797 if (asyw->clr.image && (!asyw->set.image || flush))
798 wndw->func->image_clr(wndw);
800 return flush ? wndw->func->update(wndw, interlock) : 0;
804 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 interlock,
805 struct nv50_wndw_atom *asyw)
808 asyw->image.mode = 0;
809 asyw->image.interval = 1;
812 if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw);
813 if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw);
814 if (asyw->set.image) wndw->func->image_set(wndw, asyw);
815 if (asyw->set.lut ) wndw->func->lut (wndw, asyw);
816 if (asyw->set.point) wndw->func->point (wndw, asyw);
818 return wndw->func->update(wndw, interlock);
822 nv50_wndw_atomic_check_release(struct nv50_wndw *wndw,
823 struct nv50_wndw_atom *asyw,
824 struct nv50_head_atom *asyh)
826 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
827 NV_ATOMIC(drm, "%s release\n", wndw->plane.name);
828 wndw->func->release(wndw, asyw, asyh);
829 asyw->ntfy.handle = 0;
830 asyw->sema.handle = 0;
834 nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw,
835 struct nv50_wndw_atom *asyw,
836 struct nv50_head_atom *asyh)
838 struct nouveau_framebuffer *fb = nouveau_framebuffer(asyw->state.fb);
839 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
842 NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name);
845 asyw->clip.x2 = asyh->state.mode.hdisplay;
846 asyw->clip.y2 = asyh->state.mode.vdisplay;
848 asyw->image.w = fb->base.width;
849 asyw->image.h = fb->base.height;
850 asyw->image.kind = fb->nvbo->kind;
852 if (asyh->state.pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
857 if (asyw->image.kind) {
858 asyw->image.layout = 0;
859 if (drm->client.device.info.chipset >= 0xc0)
860 asyw->image.block = fb->nvbo->mode >> 4;
862 asyw->image.block = fb->nvbo->mode;
863 asyw->image.pitch = (fb->base.pitches[0] / 4) << 4;
865 asyw->image.layout = 1;
866 asyw->image.block = 0;
867 asyw->image.pitch = fb->base.pitches[0];
870 ret = wndw->func->acquire(wndw, asyw, asyh);
874 if (asyw->set.image) {
875 if (!(asyw->image.mode = asyw->interval ? 0 : 1))
876 asyw->image.interval = asyw->interval;
878 asyw->image.interval = 0;
885 nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state)
887 struct nouveau_drm *drm = nouveau_drm(plane->dev);
888 struct nv50_wndw *wndw = nv50_wndw(plane);
889 struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state);
890 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
891 struct nv50_head_atom *harm = NULL, *asyh = NULL;
892 bool varm = false, asyv = false, asym = false;
895 NV_ATOMIC(drm, "%s atomic_check\n", plane->name);
896 if (asyw->state.crtc) {
897 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
899 return PTR_ERR(asyh);
900 asym = drm_atomic_crtc_needs_modeset(&asyh->state);
901 asyv = asyh->state.active;
904 if (armw->state.crtc) {
905 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc);
907 return PTR_ERR(harm);
908 varm = harm->state.crtc->state->active;
912 asyw->point.x = asyw->state.crtc_x;
913 asyw->point.y = asyw->state.crtc_y;
914 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point)))
915 asyw->set.point = true;
917 ret = nv50_wndw_atomic_check_acquire(wndw, asyw, asyh);
922 nv50_wndw_atomic_check_release(wndw, asyw, harm);
928 asyw->clr.ntfy = armw->ntfy.handle != 0;
929 asyw->clr.sema = armw->sema.handle != 0;
930 if (wndw->func->image_clr)
931 asyw->clr.image = armw->image.handle != 0;
932 asyw->set.lut = wndw->func->lut && asyv;
939 nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state)
941 struct nouveau_framebuffer *fb = nouveau_framebuffer(old_state->fb);
942 struct nouveau_drm *drm = nouveau_drm(plane->dev);
944 NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb);
948 nouveau_bo_unpin(fb->nvbo);
952 nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state)
954 struct nouveau_framebuffer *fb = nouveau_framebuffer(state->fb);
955 struct nouveau_drm *drm = nouveau_drm(plane->dev);
956 struct nv50_wndw *wndw = nv50_wndw(plane);
957 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
958 struct nv50_head_atom *asyh;
959 struct nv50_dmac_ctxdma *ctxdma;
962 NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, state->fb);
966 ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM, true);
970 ctxdma = nv50_dmac_ctxdma_new(wndw->dmac, fb);
971 if (IS_ERR(ctxdma)) {
972 nouveau_bo_unpin(fb->nvbo);
973 return PTR_ERR(ctxdma);
976 asyw->state.fence = reservation_object_get_excl_rcu(fb->nvbo->bo.resv);
977 asyw->image.handle = ctxdma->object.handle;
978 asyw->image.offset = fb->nvbo->bo.offset;
980 if (wndw->func->prepare) {
981 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
983 return PTR_ERR(asyh);
985 wndw->func->prepare(wndw, asyh, asyw);
991 static const struct drm_plane_helper_funcs
993 .prepare_fb = nv50_wndw_prepare_fb,
994 .cleanup_fb = nv50_wndw_cleanup_fb,
995 .atomic_check = nv50_wndw_atomic_check,
999 nv50_wndw_atomic_destroy_state(struct drm_plane *plane,
1000 struct drm_plane_state *state)
1002 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
1003 __drm_atomic_helper_plane_destroy_state(&asyw->state);
1007 static struct drm_plane_state *
1008 nv50_wndw_atomic_duplicate_state(struct drm_plane *plane)
1010 struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state);
1011 struct nv50_wndw_atom *asyw;
1012 if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL)))
1014 __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state);
1016 asyw->sema = armw->sema;
1017 asyw->ntfy = armw->ntfy;
1018 asyw->image = armw->image;
1019 asyw->point = armw->point;
1020 asyw->lut = armw->lut;
1023 return &asyw->state;
1027 nv50_wndw_reset(struct drm_plane *plane)
1029 struct nv50_wndw_atom *asyw;
1031 if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL))))
1035 plane->funcs->atomic_destroy_state(plane, plane->state);
1036 plane->state = &asyw->state;
1037 plane->state->plane = plane;
1038 plane->state->rotation = DRM_MODE_ROTATE_0;
1042 nv50_wndw_destroy(struct drm_plane *plane)
1044 struct nv50_wndw *wndw = nv50_wndw(plane);
1046 nvif_notify_fini(&wndw->notify);
1047 data = wndw->func->dtor(wndw);
1048 drm_plane_cleanup(&wndw->plane);
1052 static const struct drm_plane_funcs
1054 .update_plane = drm_atomic_helper_update_plane,
1055 .disable_plane = drm_atomic_helper_disable_plane,
1056 .destroy = nv50_wndw_destroy,
1057 .reset = nv50_wndw_reset,
1058 .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state,
1059 .atomic_destroy_state = nv50_wndw_atomic_destroy_state,
1063 nv50_wndw_fini(struct nv50_wndw *wndw)
1065 nvif_notify_put(&wndw->notify);
1069 nv50_wndw_init(struct nv50_wndw *wndw)
1071 nvif_notify_get(&wndw->notify);
1075 nv50_wndw_ctor(const struct nv50_wndw_func *func, struct drm_device *dev,
1076 enum drm_plane_type type, const char *name, int index,
1077 struct nv50_dmac *dmac, const u32 *format, int nformat,
1078 struct nv50_wndw *wndw)
1085 ret = drm_universal_plane_init(dev, &wndw->plane, 0, &nv50_wndw,
1086 format, nformat, NULL,
1087 type, "%s-%d", name, index);
1091 drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);
1095 /******************************************************************************
1097 *****************************************************************************/
1098 #define nv50_curs(p) container_of((p), struct nv50_curs, wndw)
1101 struct nv50_wndw wndw;
1102 struct nvif_object chan;
1106 nv50_curs_update(struct nv50_wndw *wndw, u32 interlock)
1108 struct nv50_curs *curs = nv50_curs(wndw);
1109 nvif_wr32(&curs->chan, 0x0080, 0x00000000);
1114 nv50_curs_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1116 struct nv50_curs *curs = nv50_curs(wndw);
1117 nvif_wr32(&curs->chan, 0x0084, (asyw->point.y << 16) | asyw->point.x);
1121 nv50_curs_prepare(struct nv50_wndw *wndw, struct nv50_head_atom *asyh,
1122 struct nv50_wndw_atom *asyw)
1124 u32 handle = nv50_disp(wndw->plane.dev)->mast.base.vram.handle;
1125 u32 offset = asyw->image.offset;
1126 if (asyh->curs.handle != handle || asyh->curs.offset != offset) {
1127 asyh->curs.handle = handle;
1128 asyh->curs.offset = offset;
1129 asyh->set.curs = asyh->curs.visible;
1134 nv50_curs_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1135 struct nv50_head_atom *asyh)
1137 asyh->curs.visible = false;
1141 nv50_curs_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1142 struct nv50_head_atom *asyh)
1146 ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state,
1148 DRM_PLANE_HELPER_NO_SCALING,
1149 DRM_PLANE_HELPER_NO_SCALING,
1151 asyh->curs.visible = asyw->state.visible;
1152 if (ret || !asyh->curs.visible)
1155 switch (asyw->state.fb->width) {
1156 case 32: asyh->curs.layout = 0; break;
1157 case 64: asyh->curs.layout = 1; break;
1162 if (asyw->state.fb->width != asyw->state.fb->height)
1165 switch (asyw->state.fb->format->format) {
1166 case DRM_FORMAT_ARGB8888: asyh->curs.format = 1; break;
1176 nv50_curs_dtor(struct nv50_wndw *wndw)
1178 struct nv50_curs *curs = nv50_curs(wndw);
1179 nvif_object_fini(&curs->chan);
1184 nv50_curs_format[] = {
1185 DRM_FORMAT_ARGB8888,
1188 static const struct nv50_wndw_func
1190 .dtor = nv50_curs_dtor,
1191 .acquire = nv50_curs_acquire,
1192 .release = nv50_curs_release,
1193 .prepare = nv50_curs_prepare,
1194 .point = nv50_curs_point,
1195 .update = nv50_curs_update,
1199 nv50_curs_new(struct nouveau_drm *drm, struct nv50_head *head,
1200 struct nv50_curs **pcurs)
1202 static const struct nvif_mclass curses[] = {
1203 { GK104_DISP_CURSOR, 0 },
1204 { GF110_DISP_CURSOR, 0 },
1205 { GT214_DISP_CURSOR, 0 },
1206 { G82_DISP_CURSOR, 0 },
1207 { NV50_DISP_CURSOR, 0 },
1210 struct nv50_disp_cursor_v0 args = {
1211 .head = head->base.index,
1213 struct nv50_disp *disp = nv50_disp(drm->dev);
1214 struct nv50_curs *curs;
1217 cid = nvif_mclass(disp->disp, curses);
1219 NV_ERROR(drm, "No supported cursor immediate class\n");
1223 if (!(curs = *pcurs = kzalloc(sizeof(*curs), GFP_KERNEL)))
1226 ret = nv50_wndw_ctor(&nv50_curs, drm->dev, DRM_PLANE_TYPE_CURSOR,
1227 "curs", head->base.index, &disp->mast.base,
1228 nv50_curs_format, ARRAY_SIZE(nv50_curs_format),
1235 ret = nvif_object_init(disp->disp, 0, curses[cid].oclass, &args,
1236 sizeof(args), &curs->chan);
1238 NV_ERROR(drm, "curs%04x allocation failed: %d\n",
1239 curses[cid].oclass, ret);
1246 /******************************************************************************
1248 *****************************************************************************/
1249 #define nv50_base(p) container_of((p), struct nv50_base, wndw)
1252 struct nv50_wndw wndw;
1253 struct nv50_sync chan;
1258 nv50_base_notify(struct nvif_notify *notify)
1260 return NVIF_NOTIFY_KEEP;
1264 nv50_base_lut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1266 struct nv50_base *base = nv50_base(wndw);
1268 if ((push = evo_wait(&base->chan, 2))) {
1269 evo_mthd(push, 0x00e0, 1);
1270 evo_data(push, asyw->lut.enable << 30);
1271 evo_kick(push, &base->chan);
1276 nv50_base_image_clr(struct nv50_wndw *wndw)
1278 struct nv50_base *base = nv50_base(wndw);
1280 if ((push = evo_wait(&base->chan, 4))) {
1281 evo_mthd(push, 0x0084, 1);
1282 evo_data(push, 0x00000000);
1283 evo_mthd(push, 0x00c0, 1);
1284 evo_data(push, 0x00000000);
1285 evo_kick(push, &base->chan);
1290 nv50_base_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1292 struct nv50_base *base = nv50_base(wndw);
1293 const s32 oclass = base->chan.base.base.user.oclass;
1295 if ((push = evo_wait(&base->chan, 10))) {
1296 evo_mthd(push, 0x0084, 1);
1297 evo_data(push, (asyw->image.mode << 8) |
1298 (asyw->image.interval << 4));
1299 evo_mthd(push, 0x00c0, 1);
1300 evo_data(push, asyw->image.handle);
1301 if (oclass < G82_DISP_BASE_CHANNEL_DMA) {
1302 evo_mthd(push, 0x0800, 5);
1303 evo_data(push, asyw->image.offset >> 8);
1304 evo_data(push, 0x00000000);
1305 evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1306 evo_data(push, (asyw->image.layout << 20) |
1309 evo_data(push, (asyw->image.kind << 16) |
1310 (asyw->image.format << 8));
1312 if (oclass < GF110_DISP_BASE_CHANNEL_DMA) {
1313 evo_mthd(push, 0x0800, 5);
1314 evo_data(push, asyw->image.offset >> 8);
1315 evo_data(push, 0x00000000);
1316 evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1317 evo_data(push, (asyw->image.layout << 20) |
1320 evo_data(push, asyw->image.format << 8);
1322 evo_mthd(push, 0x0400, 5);
1323 evo_data(push, asyw->image.offset >> 8);
1324 evo_data(push, 0x00000000);
1325 evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1326 evo_data(push, (asyw->image.layout << 24) |
1329 evo_data(push, asyw->image.format << 8);
1331 evo_kick(push, &base->chan);
1336 nv50_base_ntfy_clr(struct nv50_wndw *wndw)
1338 struct nv50_base *base = nv50_base(wndw);
1340 if ((push = evo_wait(&base->chan, 2))) {
1341 evo_mthd(push, 0x00a4, 1);
1342 evo_data(push, 0x00000000);
1343 evo_kick(push, &base->chan);
1348 nv50_base_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1350 struct nv50_base *base = nv50_base(wndw);
1352 if ((push = evo_wait(&base->chan, 3))) {
1353 evo_mthd(push, 0x00a0, 2);
1354 evo_data(push, (asyw->ntfy.awaken << 30) | asyw->ntfy.offset);
1355 evo_data(push, asyw->ntfy.handle);
1356 evo_kick(push, &base->chan);
1361 nv50_base_sema_clr(struct nv50_wndw *wndw)
1363 struct nv50_base *base = nv50_base(wndw);
1365 if ((push = evo_wait(&base->chan, 2))) {
1366 evo_mthd(push, 0x0094, 1);
1367 evo_data(push, 0x00000000);
1368 evo_kick(push, &base->chan);
1373 nv50_base_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1375 struct nv50_base *base = nv50_base(wndw);
1377 if ((push = evo_wait(&base->chan, 5))) {
1378 evo_mthd(push, 0x0088, 4);
1379 evo_data(push, asyw->sema.offset);
1380 evo_data(push, asyw->sema.acquire);
1381 evo_data(push, asyw->sema.release);
1382 evo_data(push, asyw->sema.handle);
1383 evo_kick(push, &base->chan);
1388 nv50_base_update(struct nv50_wndw *wndw, u32 interlock)
1390 struct nv50_base *base = nv50_base(wndw);
1393 if (!(push = evo_wait(&base->chan, 2)))
1395 evo_mthd(push, 0x0080, 1);
1396 evo_data(push, interlock);
1397 evo_kick(push, &base->chan);
1399 if (base->chan.base.base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA)
1400 return interlock ? 2 << (base->id * 8) : 0;
1401 return interlock ? 2 << (base->id * 4) : 0;
1405 nv50_base_ntfy_wait_begun(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1407 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
1408 struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
1409 if (nvif_msec(&drm->client.device, 2000ULL,
1410 u32 data = nouveau_bo_rd32(disp->sync, asyw->ntfy.offset / 4);
1411 if ((data & 0xc0000000) == 0x40000000)
1420 nv50_base_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1421 struct nv50_head_atom *asyh)
1427 nv50_base_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1428 struct nv50_head_atom *asyh)
1430 const struct drm_framebuffer *fb = asyw->state.fb;
1433 if (!fb->format->depth)
1436 ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state,
1438 DRM_PLANE_HELPER_NO_SCALING,
1439 DRM_PLANE_HELPER_NO_SCALING,
1444 asyh->base.depth = fb->format->depth;
1445 asyh->base.cpp = fb->format->cpp[0];
1446 asyh->base.x = asyw->state.src.x1 >> 16;
1447 asyh->base.y = asyw->state.src.y1 >> 16;
1448 asyh->base.w = asyw->state.fb->width;
1449 asyh->base.h = asyw->state.fb->height;
1451 switch (fb->format->format) {
1452 case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break;
1453 case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break;
1454 case DRM_FORMAT_XRGB1555 :
1455 case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break;
1456 case DRM_FORMAT_XRGB8888 :
1457 case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break;
1458 case DRM_FORMAT_XBGR2101010:
1459 case DRM_FORMAT_ABGR2101010: asyw->image.format = 0xd1; break;
1460 case DRM_FORMAT_XBGR8888 :
1461 case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break;
1467 asyw->lut.enable = 1;
1468 asyw->set.image = true;
1473 nv50_base_dtor(struct nv50_wndw *wndw)
1475 struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
1476 struct nv50_base *base = nv50_base(wndw);
1477 nv50_dmac_destroy(&base->chan.base, disp->disp);
1482 nv50_base_format[] = {
1485 DRM_FORMAT_XRGB1555,
1486 DRM_FORMAT_ARGB1555,
1487 DRM_FORMAT_XRGB8888,
1488 DRM_FORMAT_ARGB8888,
1489 DRM_FORMAT_XBGR2101010,
1490 DRM_FORMAT_ABGR2101010,
1491 DRM_FORMAT_XBGR8888,
1492 DRM_FORMAT_ABGR8888,
1495 static const struct nv50_wndw_func
1497 .dtor = nv50_base_dtor,
1498 .acquire = nv50_base_acquire,
1499 .release = nv50_base_release,
1500 .sema_set = nv50_base_sema_set,
1501 .sema_clr = nv50_base_sema_clr,
1502 .ntfy_set = nv50_base_ntfy_set,
1503 .ntfy_clr = nv50_base_ntfy_clr,
1504 .ntfy_wait_begun = nv50_base_ntfy_wait_begun,
1505 .image_set = nv50_base_image_set,
1506 .image_clr = nv50_base_image_clr,
1507 .lut = nv50_base_lut,
1508 .update = nv50_base_update,
1512 nv50_base_new(struct nouveau_drm *drm, struct nv50_head *head,
1513 struct nv50_base **pbase)
1515 struct nv50_disp *disp = nv50_disp(drm->dev);
1516 struct nv50_base *base;
1519 if (!(base = *pbase = kzalloc(sizeof(*base), GFP_KERNEL)))
1521 base->id = head->base.index;
1522 base->wndw.ntfy = EVO_FLIP_NTFY0(base->id);
1523 base->wndw.sema = EVO_FLIP_SEM0(base->id);
1524 base->wndw.data = 0x00000000;
1526 ret = nv50_wndw_ctor(&nv50_base, drm->dev, DRM_PLANE_TYPE_PRIMARY,
1527 "base", base->id, &base->chan.base,
1528 nv50_base_format, ARRAY_SIZE(nv50_base_format),
1535 ret = nv50_base_create(&drm->client.device, disp->disp, base->id,
1536 disp->sync->bo.offset, &base->chan);
1540 return nvif_notify_init(&base->chan.base.base.user, nv50_base_notify,
1542 NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT,
1543 &(struct nvif_notify_uevent_req) {},
1544 sizeof(struct nvif_notify_uevent_req),
1545 sizeof(struct nvif_notify_uevent_rep),
1546 &base->wndw.notify);
1549 /******************************************************************************
1551 *****************************************************************************/
1553 nv50_head_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
1555 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1557 if ((push = evo_wait(core, 2))) {
1558 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1559 evo_mthd(push, 0x08a8 + (head->base.index * 0x400), 1);
1561 evo_mthd(push, 0x0498 + (head->base.index * 0x300), 1);
1562 evo_data(push, (asyh->procamp.sat.sin << 20) |
1563 (asyh->procamp.sat.cos << 8));
1564 evo_kick(push, core);
1569 nv50_head_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
1571 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1573 if ((push = evo_wait(core, 2))) {
1574 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1575 evo_mthd(push, 0x08a0 + (head->base.index * 0x0400), 1);
1577 if (core->base.user.oclass < GK104_DISP_CORE_CHANNEL_DMA)
1578 evo_mthd(push, 0x0490 + (head->base.index * 0x0300), 1);
1580 evo_mthd(push, 0x04a0 + (head->base.index * 0x0300), 1);
1581 evo_data(push, (asyh->dither.mode << 3) |
1582 (asyh->dither.bits << 1) |
1583 asyh->dither.enable);
1584 evo_kick(push, core);
1589 nv50_head_ovly(struct nv50_head *head, struct nv50_head_atom *asyh)
1591 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1595 if (asyh->base.cpp) {
1596 switch (asyh->base.cpp) {
1597 case 8: bounds |= 0x00000500; break;
1598 case 4: bounds |= 0x00000300; break;
1599 case 2: bounds |= 0x00000100; break;
1604 bounds |= 0x00000001;
1607 if ((push = evo_wait(core, 2))) {
1608 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1609 evo_mthd(push, 0x0904 + head->base.index * 0x400, 1);
1611 evo_mthd(push, 0x04d4 + head->base.index * 0x300, 1);
1612 evo_data(push, bounds);
1613 evo_kick(push, core);
1618 nv50_head_base(struct nv50_head *head, struct nv50_head_atom *asyh)
1620 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1624 if (asyh->base.cpp) {
1625 switch (asyh->base.cpp) {
1626 case 8: bounds |= 0x00000500; break;
1627 case 4: bounds |= 0x00000300; break;
1628 case 2: bounds |= 0x00000100; break;
1629 case 1: bounds |= 0x00000000; break;
1634 bounds |= 0x00000001;
1637 if ((push = evo_wait(core, 2))) {
1638 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1639 evo_mthd(push, 0x0900 + head->base.index * 0x400, 1);
1641 evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1);
1642 evo_data(push, bounds);
1643 evo_kick(push, core);
1648 nv50_head_curs_clr(struct nv50_head *head)
1650 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1652 if ((push = evo_wait(core, 4))) {
1653 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1654 evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
1655 evo_data(push, 0x05000000);
1657 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1658 evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
1659 evo_data(push, 0x05000000);
1660 evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
1661 evo_data(push, 0x00000000);
1663 evo_mthd(push, 0x0480 + head->base.index * 0x300, 1);
1664 evo_data(push, 0x05000000);
1665 evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
1666 evo_data(push, 0x00000000);
1668 evo_kick(push, core);
1673 nv50_head_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1675 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1677 if ((push = evo_wait(core, 5))) {
1678 if (core->base.user.oclass < G82_DISP_BASE_CHANNEL_DMA) {
1679 evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
1680 evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1681 (asyh->curs.format << 24));
1682 evo_data(push, asyh->curs.offset >> 8);
1684 if (core->base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA) {
1685 evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
1686 evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1687 (asyh->curs.format << 24));
1688 evo_data(push, asyh->curs.offset >> 8);
1689 evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
1690 evo_data(push, asyh->curs.handle);
1692 evo_mthd(push, 0x0480 + head->base.index * 0x300, 2);
1693 evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1694 (asyh->curs.format << 24));
1695 evo_data(push, asyh->curs.offset >> 8);
1696 evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
1697 evo_data(push, asyh->curs.handle);
1699 evo_kick(push, core);
1704 nv50_head_core_clr(struct nv50_head *head)
1706 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1708 if ((push = evo_wait(core, 2))) {
1709 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1710 evo_mthd(push, 0x0874 + head->base.index * 0x400, 1);
1712 evo_mthd(push, 0x0474 + head->base.index * 0x300, 1);
1713 evo_data(push, 0x00000000);
1714 evo_kick(push, core);
1719 nv50_head_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1721 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1723 if ((push = evo_wait(core, 9))) {
1724 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1725 evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
1726 evo_data(push, asyh->core.offset >> 8);
1727 evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
1728 evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1729 evo_data(push, asyh->core.layout << 20 |
1730 (asyh->core.pitch >> 8) << 8 |
1732 evo_data(push, asyh->core.kind << 16 |
1733 asyh->core.format << 8);
1734 evo_data(push, asyh->core.handle);
1735 evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
1736 evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1737 /* EVO will complain with INVALID_STATE if we have an
1738 * active cursor and (re)specify HeadSetContextDmaIso
1739 * without also updating HeadSetOffsetCursor.
1741 asyh->set.curs = asyh->curs.visible;
1743 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1744 evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
1745 evo_data(push, asyh->core.offset >> 8);
1746 evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
1747 evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1748 evo_data(push, asyh->core.layout << 20 |
1749 (asyh->core.pitch >> 8) << 8 |
1751 evo_data(push, asyh->core.format << 8);
1752 evo_data(push, asyh->core.handle);
1753 evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
1754 evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1756 evo_mthd(push, 0x0460 + head->base.index * 0x300, 1);
1757 evo_data(push, asyh->core.offset >> 8);
1758 evo_mthd(push, 0x0468 + head->base.index * 0x300, 4);
1759 evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1760 evo_data(push, asyh->core.layout << 24 |
1761 (asyh->core.pitch >> 8) << 8 |
1763 evo_data(push, asyh->core.format << 8);
1764 evo_data(push, asyh->core.handle);
1765 evo_mthd(push, 0x04b0 + head->base.index * 0x300, 1);
1766 evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1768 evo_kick(push, core);
1773 nv50_head_lut_clr(struct nv50_head *head)
1775 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1777 if ((push = evo_wait(core, 4))) {
1778 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1779 evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
1780 evo_data(push, 0x40000000);
1782 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1783 evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
1784 evo_data(push, 0x40000000);
1785 evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
1786 evo_data(push, 0x00000000);
1788 evo_mthd(push, 0x0440 + (head->base.index * 0x300), 1);
1789 evo_data(push, 0x03000000);
1790 evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
1791 evo_data(push, 0x00000000);
1793 evo_kick(push, core);
1798 nv50_head_lut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1800 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1802 if ((push = evo_wait(core, 7))) {
1803 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1804 evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1805 evo_data(push, 0xc0000000);
1806 evo_data(push, asyh->lut.offset >> 8);
1808 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1809 evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1810 evo_data(push, 0xc0000000);
1811 evo_data(push, asyh->lut.offset >> 8);
1812 evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
1813 evo_data(push, asyh->lut.handle);
1815 evo_mthd(push, 0x0440 + (head->base.index * 0x300), 4);
1816 evo_data(push, 0x83000000);
1817 evo_data(push, asyh->lut.offset >> 8);
1818 evo_data(push, 0x00000000);
1819 evo_data(push, 0x00000000);
1820 evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
1821 evo_data(push, asyh->lut.handle);
1823 evo_kick(push, core);
1828 nv50_head_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
1830 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1831 struct nv50_head_mode *m = &asyh->mode;
1833 if ((push = evo_wait(core, 14))) {
1834 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1835 evo_mthd(push, 0x0804 + (head->base.index * 0x400), 2);
1836 evo_data(push, 0x00800000 | m->clock);
1837 evo_data(push, m->interlace ? 0x00000002 : 0x00000000);
1838 evo_mthd(push, 0x0810 + (head->base.index * 0x400), 7);
1839 evo_data(push, 0x00000000);
1840 evo_data(push, (m->v.active << 16) | m->h.active );
1841 evo_data(push, (m->v.synce << 16) | m->h.synce );
1842 evo_data(push, (m->v.blanke << 16) | m->h.blanke );
1843 evo_data(push, (m->v.blanks << 16) | m->h.blanks );
1844 evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1845 evo_data(push, asyh->mode.v.blankus);
1846 evo_mthd(push, 0x082c + (head->base.index * 0x400), 1);
1847 evo_data(push, 0x00000000);
1849 evo_mthd(push, 0x0410 + (head->base.index * 0x300), 6);
1850 evo_data(push, 0x00000000);
1851 evo_data(push, (m->v.active << 16) | m->h.active );
1852 evo_data(push, (m->v.synce << 16) | m->h.synce );
1853 evo_data(push, (m->v.blanke << 16) | m->h.blanke );
1854 evo_data(push, (m->v.blanks << 16) | m->h.blanks );
1855 evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1856 evo_mthd(push, 0x042c + (head->base.index * 0x300), 2);
1857 evo_data(push, 0x00000000); /* ??? */
1858 evo_data(push, 0xffffff00);
1859 evo_mthd(push, 0x0450 + (head->base.index * 0x300), 3);
1860 evo_data(push, m->clock * 1000);
1861 evo_data(push, 0x00200000); /* ??? */
1862 evo_data(push, m->clock * 1000);
1864 evo_kick(push, core);
1869 nv50_head_view(struct nv50_head *head, struct nv50_head_atom *asyh)
1871 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1873 if ((push = evo_wait(core, 10))) {
1874 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1875 evo_mthd(push, 0x08a4 + (head->base.index * 0x400), 1);
1876 evo_data(push, 0x00000000);
1877 evo_mthd(push, 0x08c8 + (head->base.index * 0x400), 1);
1878 evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1879 evo_mthd(push, 0x08d8 + (head->base.index * 0x400), 2);
1880 evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1881 evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1883 evo_mthd(push, 0x0494 + (head->base.index * 0x300), 1);
1884 evo_data(push, 0x00000000);
1885 evo_mthd(push, 0x04b8 + (head->base.index * 0x300), 1);
1886 evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1887 evo_mthd(push, 0x04c0 + (head->base.index * 0x300), 3);
1888 evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1889 evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1890 evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1892 evo_kick(push, core);
1897 nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool y)
1899 if (asyh->clr.core && (!asyh->set.core || y))
1900 nv50_head_lut_clr(head);
1901 if (asyh->clr.core && (!asyh->set.core || y))
1902 nv50_head_core_clr(head);
1903 if (asyh->clr.curs && (!asyh->set.curs || y))
1904 nv50_head_curs_clr(head);
1908 nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1910 if (asyh->set.view ) nv50_head_view (head, asyh);
1911 if (asyh->set.mode ) nv50_head_mode (head, asyh);
1912 if (asyh->set.core ) nv50_head_lut_set (head, asyh);
1913 if (asyh->set.core ) nv50_head_core_set(head, asyh);
1914 if (asyh->set.curs ) nv50_head_curs_set(head, asyh);
1915 if (asyh->set.base ) nv50_head_base (head, asyh);
1916 if (asyh->set.ovly ) nv50_head_ovly (head, asyh);
1917 if (asyh->set.dither ) nv50_head_dither (head, asyh);
1918 if (asyh->set.procamp) nv50_head_procamp (head, asyh);
1922 nv50_head_atomic_check_procamp(struct nv50_head_atom *armh,
1923 struct nv50_head_atom *asyh,
1924 struct nouveau_conn_atom *asyc)
1926 const int vib = asyc->procamp.color_vibrance - 100;
1927 const int hue = asyc->procamp.vibrant_hue - 90;
1928 const int adj = (vib > 0) ? 50 : 0;
1929 asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff;
1930 asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff;
1931 asyh->set.procamp = true;
1935 nv50_head_atomic_check_dither(struct nv50_head_atom *armh,
1936 struct nv50_head_atom *asyh,
1937 struct nouveau_conn_atom *asyc)
1939 struct drm_connector *connector = asyc->state.connector;
1942 if (asyc->dither.mode == DITHERING_MODE_AUTO) {
1943 if (asyh->base.depth > connector->display_info.bpc * 3)
1944 mode = DITHERING_MODE_DYNAMIC2X2;
1946 mode = asyc->dither.mode;
1949 if (asyc->dither.depth == DITHERING_DEPTH_AUTO) {
1950 if (connector->display_info.bpc >= 8)
1951 mode |= DITHERING_DEPTH_8BPC;
1953 mode |= asyc->dither.depth;
1956 asyh->dither.enable = mode;
1957 asyh->dither.bits = mode >> 1;
1958 asyh->dither.mode = mode >> 3;
1959 asyh->set.dither = true;
1963 nv50_head_atomic_check_view(struct nv50_head_atom *armh,
1964 struct nv50_head_atom *asyh,
1965 struct nouveau_conn_atom *asyc)
1967 struct drm_connector *connector = asyc->state.connector;
1968 struct drm_display_mode *omode = &asyh->state.adjusted_mode;
1969 struct drm_display_mode *umode = &asyh->state.mode;
1970 int mode = asyc->scaler.mode;
1972 int umode_vdisplay, omode_hdisplay, omode_vdisplay;
1974 if (connector->edid_blob_ptr)
1975 edid = (struct edid *)connector->edid_blob_ptr->data;
1979 if (!asyc->scaler.full) {
1980 if (mode == DRM_MODE_SCALE_NONE)
1983 /* Non-EDID LVDS/eDP mode. */
1984 mode = DRM_MODE_SCALE_FULLSCREEN;
1987 /* For the user-specified mode, we must ignore doublescan and
1988 * the like, but honor frame packing.
1990 umode_vdisplay = umode->vdisplay;
1991 if ((umode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1992 umode_vdisplay += umode->vtotal;
1993 asyh->view.iW = umode->hdisplay;
1994 asyh->view.iH = umode_vdisplay;
1995 /* For the output mode, we can just use the stock helper. */
1996 drm_mode_get_hv_timing(omode, &omode_hdisplay, &omode_vdisplay);
1997 asyh->view.oW = omode_hdisplay;
1998 asyh->view.oH = omode_vdisplay;
2000 /* Add overscan compensation if necessary, will keep the aspect
2001 * ratio the same as the backend mode unless overridden by the
2002 * user setting both hborder and vborder properties.
2004 if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
2005 (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
2006 drm_detect_hdmi_monitor(edid)))) {
2007 u32 bX = asyc->scaler.underscan.hborder;
2008 u32 bY = asyc->scaler.underscan.vborder;
2009 u32 r = (asyh->view.oH << 19) / asyh->view.oW;
2012 asyh->view.oW -= (bX * 2);
2013 if (bY) asyh->view.oH -= (bY * 2);
2014 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
2016 asyh->view.oW -= (asyh->view.oW >> 4) + 32;
2017 if (bY) asyh->view.oH -= (bY * 2);
2018 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
2022 /* Handle CENTER/ASPECT scaling, taking into account the areas
2023 * removed already for overscan compensation.
2026 case DRM_MODE_SCALE_CENTER:
2027 asyh->view.oW = min((u16)umode->hdisplay, asyh->view.oW);
2028 asyh->view.oH = min((u16)umode_vdisplay, asyh->view.oH);
2030 case DRM_MODE_SCALE_ASPECT:
2031 if (asyh->view.oH < asyh->view.oW) {
2032 u32 r = (asyh->view.iW << 19) / asyh->view.iH;
2033 asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
2035 u32 r = (asyh->view.iH << 19) / asyh->view.iW;
2036 asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
2043 asyh->set.view = true;
2047 nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
2049 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
2050 struct nv50_head_mode *m = &asyh->mode;
2053 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
2056 * DRM modes are defined in terms of a repeating interval
2057 * starting with the active display area. The hardware modes
2058 * are defined in terms of a repeating interval starting one
2059 * unit (pixel or line) into the sync pulse. So, add bias.
2062 m->h.active = mode->crtc_htotal;
2063 m->h.synce = mode->crtc_hsync_end - mode->crtc_hsync_start - 1;
2064 m->h.blanke = mode->crtc_hblank_end - mode->crtc_hsync_start - 1;
2065 m->h.blanks = m->h.blanke + mode->crtc_hdisplay;
2067 m->v.active = mode->crtc_vtotal;
2068 m->v.synce = mode->crtc_vsync_end - mode->crtc_vsync_start - 1;
2069 m->v.blanke = mode->crtc_vblank_end - mode->crtc_vsync_start - 1;
2070 m->v.blanks = m->v.blanke + mode->crtc_vdisplay;
2072 /*XXX: Safe underestimate, even "0" works */
2073 blankus = (m->v.active - mode->crtc_vdisplay - 2) * m->h.active;
2075 blankus /= mode->crtc_clock;
2076 m->v.blankus = blankus;
2078 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2079 m->v.blank2e = m->v.active + m->v.blanke;
2080 m->v.blank2s = m->v.blank2e + mode->crtc_vdisplay;
2081 m->v.active = (m->v.active * 2) + 1;
2082 m->interlace = true;
2086 m->interlace = false;
2088 m->clock = mode->crtc_clock;
2090 asyh->set.mode = true;
2094 nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
2096 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
2097 struct nv50_disp *disp = nv50_disp(crtc->dev);
2098 struct nv50_head *head = nv50_head(crtc);
2099 struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
2100 struct nv50_head_atom *asyh = nv50_head_atom(state);
2101 struct nouveau_conn_atom *asyc = NULL;
2102 struct drm_connector_state *conns;
2103 struct drm_connector *conn;
2106 NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
2107 if (asyh->state.active) {
2108 for_each_new_connector_in_state(asyh->state.state, conn, conns, i) {
2109 if (conns->crtc == crtc) {
2110 asyc = nouveau_conn_atom(conns);
2115 if (armh->state.active) {
2117 if (asyh->state.mode_changed)
2118 asyc->set.scaler = true;
2119 if (armh->base.depth != asyh->base.depth)
2120 asyc->set.dither = true;
2124 asyc->set.mask = ~0;
2125 asyh->set.mask = ~0;
2128 if (asyh->state.mode_changed)
2129 nv50_head_atomic_check_mode(head, asyh);
2132 if (asyc->set.scaler)
2133 nv50_head_atomic_check_view(armh, asyh, asyc);
2134 if (asyc->set.dither)
2135 nv50_head_atomic_check_dither(armh, asyh, asyc);
2136 if (asyc->set.procamp)
2137 nv50_head_atomic_check_procamp(armh, asyh, asyc);
2140 if ((asyh->core.visible = (asyh->base.cpp != 0))) {
2141 asyh->core.x = asyh->base.x;
2142 asyh->core.y = asyh->base.y;
2143 asyh->core.w = asyh->base.w;
2144 asyh->core.h = asyh->base.h;
2146 if ((asyh->core.visible = asyh->curs.visible)) {
2147 /*XXX: We need to either find some way of having the
2148 * primary base layer appear black, while still
2149 * being able to display the other layers, or we
2150 * need to allocate a dummy black surface here.
2154 asyh->core.w = asyh->state.mode.hdisplay;
2155 asyh->core.h = asyh->state.mode.vdisplay;
2157 asyh->core.handle = disp->mast.base.vram.handle;
2158 asyh->core.offset = 0;
2159 asyh->core.format = 0xcf;
2160 asyh->core.kind = 0;
2161 asyh->core.layout = 1;
2162 asyh->core.block = 0;
2163 asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4;
2164 asyh->lut.handle = disp->mast.base.vram.handle;
2165 asyh->lut.offset = head->base.lut.nvbo->bo.offset;
2166 asyh->set.base = armh->base.cpp != asyh->base.cpp;
2167 asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
2169 asyh->core.visible = false;
2170 asyh->curs.visible = false;
2175 if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
2176 if (asyh->core.visible) {
2177 if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
2178 asyh->set.core = true;
2180 if (armh->core.visible) {
2181 asyh->clr.core = true;
2184 if (asyh->curs.visible) {
2185 if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))
2186 asyh->set.curs = true;
2188 if (armh->curs.visible) {
2189 asyh->clr.curs = true;
2192 asyh->clr.core = armh->core.visible;
2193 asyh->clr.curs = armh->curs.visible;
2194 asyh->set.core = asyh->core.visible;
2195 asyh->set.curs = asyh->curs.visible;
2198 if (asyh->clr.mask || asyh->set.mask)
2199 nv50_atom(asyh->state.state)->lock_core = true;
2204 nv50_head_lut_load(struct drm_crtc *crtc)
2206 struct nv50_disp *disp = nv50_disp(crtc->dev);
2207 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
2208 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
2212 r = crtc->gamma_store;
2213 g = r + crtc->gamma_size;
2214 b = g + crtc->gamma_size;
2216 for (i = 0; i < 256; i++) {
2217 if (disp->disp->oclass < GF110_DISP) {
2218 writew((*r++ >> 2) + 0x0000, lut + (i * 0x08) + 0);
2219 writew((*g++ >> 2) + 0x0000, lut + (i * 0x08) + 2);
2220 writew((*b++ >> 2) + 0x0000, lut + (i * 0x08) + 4);
2222 /* 0x6000 interferes with the 14-bit color??? */
2223 writew((*r++ >> 2) + 0x6000, lut + (i * 0x20) + 0);
2224 writew((*g++ >> 2) + 0x6000, lut + (i * 0x20) + 2);
2225 writew((*b++ >> 2) + 0x6000, lut + (i * 0x20) + 4);
2230 static const struct drm_crtc_helper_funcs
2232 .atomic_check = nv50_head_atomic_check,
2236 nv50_head_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
2238 struct drm_modeset_acquire_ctx *ctx)
2240 nv50_head_lut_load(crtc);
2245 nv50_head_atomic_destroy_state(struct drm_crtc *crtc,
2246 struct drm_crtc_state *state)
2248 struct nv50_head_atom *asyh = nv50_head_atom(state);
2249 __drm_atomic_helper_crtc_destroy_state(&asyh->state);
2253 static struct drm_crtc_state *
2254 nv50_head_atomic_duplicate_state(struct drm_crtc *crtc)
2256 struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
2257 struct nv50_head_atom *asyh;
2258 if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL)))
2260 __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state);
2261 asyh->view = armh->view;
2262 asyh->mode = armh->mode;
2263 asyh->lut = armh->lut;
2264 asyh->core = armh->core;
2265 asyh->curs = armh->curs;
2266 asyh->base = armh->base;
2267 asyh->ovly = armh->ovly;
2268 asyh->dither = armh->dither;
2269 asyh->procamp = armh->procamp;
2272 return &asyh->state;
2276 __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc,
2277 struct drm_crtc_state *state)
2280 crtc->funcs->atomic_destroy_state(crtc, crtc->state);
2281 crtc->state = state;
2282 crtc->state->crtc = crtc;
2286 nv50_head_reset(struct drm_crtc *crtc)
2288 struct nv50_head_atom *asyh;
2290 if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL))))
2293 __drm_atomic_helper_crtc_reset(crtc, &asyh->state);
2297 nv50_head_destroy(struct drm_crtc *crtc)
2299 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
2300 struct nv50_disp *disp = nv50_disp(crtc->dev);
2301 struct nv50_head *head = nv50_head(crtc);
2303 nv50_dmac_destroy(&head->ovly.base, disp->disp);
2304 nv50_pioc_destroy(&head->oimm.base);
2306 nouveau_bo_unmap(nv_crtc->lut.nvbo);
2307 if (nv_crtc->lut.nvbo)
2308 nouveau_bo_unpin(nv_crtc->lut.nvbo);
2309 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
2311 drm_crtc_cleanup(crtc);
2315 static const struct drm_crtc_funcs
2317 .reset = nv50_head_reset,
2318 .gamma_set = nv50_head_gamma_set,
2319 .destroy = nv50_head_destroy,
2320 .set_config = drm_atomic_helper_set_config,
2321 .page_flip = drm_atomic_helper_page_flip,
2322 .atomic_duplicate_state = nv50_head_atomic_duplicate_state,
2323 .atomic_destroy_state = nv50_head_atomic_destroy_state,
2327 nv50_head_create(struct drm_device *dev, int index)
2329 struct nouveau_drm *drm = nouveau_drm(dev);
2330 struct nvif_device *device = &drm->client.device;
2331 struct nv50_disp *disp = nv50_disp(dev);
2332 struct nv50_head *head;
2333 struct nv50_base *base;
2334 struct nv50_curs *curs;
2335 struct drm_crtc *crtc;
2338 head = kzalloc(sizeof(*head), GFP_KERNEL);
2342 head->base.index = index;
2343 ret = nv50_base_new(drm, head, &base);
2345 ret = nv50_curs_new(drm, head, &curs);
2351 crtc = &head->base.base;
2352 drm_crtc_init_with_planes(dev, crtc, &base->wndw.plane,
2353 &curs->wndw.plane, &nv50_head_func,
2354 "head-%d", head->base.index);
2355 drm_crtc_helper_add(crtc, &nv50_head_help);
2356 drm_mode_crtc_set_gamma_size(crtc, 256);
2358 ret = nouveau_bo_new(&drm->client, 8192, 0x100, TTM_PL_FLAG_VRAM,
2359 0, 0x0000, NULL, NULL, &head->base.lut.nvbo);
2361 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true);
2363 ret = nouveau_bo_map(head->base.lut.nvbo);
2365 nouveau_bo_unpin(head->base.lut.nvbo);
2368 nouveau_bo_ref(NULL, &head->base.lut.nvbo);
2374 /* allocate overlay resources */
2375 ret = nv50_oimm_create(device, disp->disp, index, &head->oimm);
2379 ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset,
2386 nv50_head_destroy(crtc);
2390 /******************************************************************************
2391 * Output path helpers
2392 *****************************************************************************/
2394 nv50_outp_release(struct nouveau_encoder *nv_encoder)
2396 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
2398 struct nv50_disp_mthd_v1 base;
2401 .base.method = NV50_DISP_MTHD_V1_RELEASE,
2402 .base.hasht = nv_encoder->dcb->hasht,
2403 .base.hashm = nv_encoder->dcb->hashm,
2406 nvif_mthd(disp->disp, 0, &args, sizeof(args));
2407 nv_encoder->or = -1;
2408 nv_encoder->link = 0;
2412 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
2414 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
2415 struct nv50_disp *disp = nv50_disp(drm->dev);
2417 struct nv50_disp_mthd_v1 base;
2418 struct nv50_disp_acquire_v0 info;
2421 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
2422 .base.hasht = nv_encoder->dcb->hasht,
2423 .base.hashm = nv_encoder->dcb->hashm,
2427 ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
2429 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
2433 nv_encoder->or = args.info.or;
2434 nv_encoder->link = args.info.link;
2439 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
2440 struct drm_crtc_state *crtc_state,
2441 struct drm_connector_state *conn_state,
2442 struct drm_display_mode *native_mode)
2444 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
2445 struct drm_display_mode *mode = &crtc_state->mode;
2446 struct drm_connector *connector = conn_state->connector;
2447 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
2448 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
2450 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
2451 asyc->scaler.full = false;
2455 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
2456 switch (connector->connector_type) {
2457 case DRM_MODE_CONNECTOR_LVDS:
2458 case DRM_MODE_CONNECTOR_eDP:
2459 /* Force use of scaler for non-EDID modes. */
2460 if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
2463 asyc->scaler.full = true;
2472 if (!drm_mode_equal(adjusted_mode, mode)) {
2473 drm_mode_copy(adjusted_mode, mode);
2474 crtc_state->mode_changed = true;
2481 nv50_outp_atomic_check(struct drm_encoder *encoder,
2482 struct drm_crtc_state *crtc_state,
2483 struct drm_connector_state *conn_state)
2485 struct nouveau_connector *nv_connector =
2486 nouveau_connector(conn_state->connector);
2487 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
2488 nv_connector->native_mode);
2491 /******************************************************************************
2493 *****************************************************************************/
2495 nv50_dac_disable(struct drm_encoder *encoder)
2497 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2498 struct nv50_mast *mast = nv50_mast(encoder->dev);
2499 const int or = nv_encoder->or;
2502 if (nv_encoder->crtc) {
2503 push = evo_wait(mast, 4);
2505 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2506 evo_mthd(push, 0x0400 + (or * 0x080), 1);
2507 evo_data(push, 0x00000000);
2509 evo_mthd(push, 0x0180 + (or * 0x020), 1);
2510 evo_data(push, 0x00000000);
2512 evo_kick(push, mast);
2516 nv_encoder->crtc = NULL;
2517 nv50_outp_release(nv_encoder);
2521 nv50_dac_enable(struct drm_encoder *encoder)
2523 struct nv50_mast *mast = nv50_mast(encoder->dev);
2524 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2525 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2526 struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
2529 nv50_outp_acquire(nv_encoder);
2531 push = evo_wait(mast, 8);
2533 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2534 u32 syncs = 0x00000000;
2536 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2537 syncs |= 0x00000001;
2538 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2539 syncs |= 0x00000002;
2541 evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
2542 evo_data(push, 1 << nv_crtc->index);
2543 evo_data(push, syncs);
2545 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
2546 u32 syncs = 0x00000001;
2548 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2549 syncs |= 0x00000008;
2550 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2551 syncs |= 0x00000010;
2553 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2554 magic |= 0x00000001;
2556 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
2557 evo_data(push, syncs);
2558 evo_data(push, magic);
2559 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
2560 evo_data(push, 1 << nv_crtc->index);
2563 evo_kick(push, mast);
2566 nv_encoder->crtc = encoder->crtc;
2569 static enum drm_connector_status
2570 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2572 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2573 struct nv50_disp *disp = nv50_disp(encoder->dev);
2575 struct nv50_disp_mthd_v1 base;
2576 struct nv50_disp_dac_load_v0 load;
2579 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
2580 .base.hasht = nv_encoder->dcb->hasht,
2581 .base.hashm = nv_encoder->dcb->hashm,
2585 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
2586 if (args.load.data == 0)
2587 args.load.data = 340;
2589 ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
2590 if (ret || !args.load.load)
2591 return connector_status_disconnected;
2593 return connector_status_connected;
2596 static const struct drm_encoder_helper_funcs
2598 .atomic_check = nv50_outp_atomic_check,
2599 .enable = nv50_dac_enable,
2600 .disable = nv50_dac_disable,
2601 .detect = nv50_dac_detect
2605 nv50_dac_destroy(struct drm_encoder *encoder)
2607 drm_encoder_cleanup(encoder);
2611 static const struct drm_encoder_funcs
2613 .destroy = nv50_dac_destroy,
2617 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
2619 struct nouveau_drm *drm = nouveau_drm(connector->dev);
2620 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
2621 struct nvkm_i2c_bus *bus;
2622 struct nouveau_encoder *nv_encoder;
2623 struct drm_encoder *encoder;
2624 int type = DRM_MODE_ENCODER_DAC;
2626 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2629 nv_encoder->dcb = dcbe;
2631 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
2633 nv_encoder->i2c = &bus->i2c;
2635 encoder = to_drm_encoder(nv_encoder);
2636 encoder->possible_crtcs = dcbe->heads;
2637 encoder->possible_clones = 0;
2638 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
2639 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
2640 drm_encoder_helper_add(encoder, &nv50_dac_help);
2642 drm_mode_connector_attach_encoder(connector, encoder);
2646 /******************************************************************************
2648 *****************************************************************************/
2650 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2652 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2653 struct nv50_disp *disp = nv50_disp(encoder->dev);
2655 struct nv50_disp_mthd_v1 base;
2656 struct nv50_disp_sor_hda_eld_v0 eld;
2659 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2660 .base.hasht = nv_encoder->dcb->hasht,
2661 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
2662 (0x0100 << nv_crtc->index),
2665 nvif_mthd(disp->disp, 0, &args, sizeof(args));
2669 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
2671 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2672 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2673 struct nouveau_connector *nv_connector;
2674 struct nv50_disp *disp = nv50_disp(encoder->dev);
2677 struct nv50_disp_mthd_v1 mthd;
2678 struct nv50_disp_sor_hda_eld_v0 eld;
2680 u8 data[sizeof(nv_connector->base.eld)];
2682 .base.mthd.version = 1,
2683 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2684 .base.mthd.hasht = nv_encoder->dcb->hasht,
2685 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
2686 (0x0100 << nv_crtc->index),
2689 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2690 if (!drm_detect_monitor_audio(nv_connector->edid))
2693 memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
2695 nvif_mthd(disp->disp, 0, &args,
2696 sizeof(args.base) + drm_eld_size(args.data));
2699 /******************************************************************************
2701 *****************************************************************************/
2703 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2705 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2706 struct nv50_disp *disp = nv50_disp(encoder->dev);
2708 struct nv50_disp_mthd_v1 base;
2709 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2712 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2713 .base.hasht = nv_encoder->dcb->hasht,
2714 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
2715 (0x0100 << nv_crtc->index),
2718 nvif_mthd(disp->disp, 0, &args, sizeof(args));
2722 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
2724 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2725 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2726 struct nv50_disp *disp = nv50_disp(encoder->dev);
2728 struct nv50_disp_mthd_v1 base;
2729 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2730 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
2733 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2734 .base.hasht = nv_encoder->dcb->hasht,
2735 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
2736 (0x0100 << nv_crtc->index),
2738 .pwr.rekey = 56, /* binary driver, and tegra, constant */
2740 struct nouveau_connector *nv_connector;
2742 union hdmi_infoframe avi_frame;
2743 union hdmi_infoframe vendor_frame;
2747 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2748 if (!drm_detect_hdmi_monitor(nv_connector->edid))
2751 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode,
2754 /* We have an AVI InfoFrame, populate it to the display */
2755 args.pwr.avi_infoframe_length
2756 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
2759 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
2760 &nv_connector->base, mode);
2762 /* We have a Vendor InfoFrame, populate it to the display */
2763 args.pwr.vendor_infoframe_length
2764 = hdmi_infoframe_pack(&vendor_frame,
2766 + args.pwr.avi_infoframe_length,
2770 max_ac_packet = mode->htotal - mode->hdisplay;
2771 max_ac_packet -= args.pwr.rekey;
2772 max_ac_packet -= 18; /* constant from tegra */
2773 args.pwr.max_ac_packet = max_ac_packet / 32;
2775 size = sizeof(args.base)
2777 + args.pwr.avi_infoframe_length
2778 + args.pwr.vendor_infoframe_length;
2779 nvif_mthd(disp->disp, 0, &args, size);
2780 nv50_audio_enable(encoder, mode);
2783 /******************************************************************************
2785 *****************************************************************************/
2786 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
2787 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
2788 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
2791 struct nouveau_encoder *outp;
2793 struct drm_dp_mst_topology_mgr mgr;
2794 struct nv50_msto *msto[4];
2802 struct nv50_mstm *mstm;
2803 struct drm_dp_mst_port *port;
2804 struct drm_connector connector;
2806 struct drm_display_mode *native;
2813 struct drm_encoder encoder;
2815 struct nv50_head *head;
2816 struct nv50_mstc *mstc;
2820 static struct drm_dp_payload *
2821 nv50_msto_payload(struct nv50_msto *msto)
2823 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2824 struct nv50_mstc *mstc = msto->mstc;
2825 struct nv50_mstm *mstm = mstc->mstm;
2826 int vcpi = mstc->port->vcpi.vcpi, i;
2828 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
2829 for (i = 0; i < mstm->mgr.max_payloads; i++) {
2830 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
2831 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
2832 mstm->outp->base.base.name, i, payload->vcpi,
2833 payload->start_slot, payload->num_slots);
2836 for (i = 0; i < mstm->mgr.max_payloads; i++) {
2837 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
2838 if (payload->vcpi == vcpi)
2846 nv50_msto_cleanup(struct nv50_msto *msto)
2848 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2849 struct nv50_mstc *mstc = msto->mstc;
2850 struct nv50_mstm *mstm = mstc->mstm;
2852 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
2853 if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
2854 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
2855 if (msto->disabled) {
2858 msto->disabled = false;
2863 nv50_msto_prepare(struct nv50_msto *msto)
2865 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2866 struct nv50_mstc *mstc = msto->mstc;
2867 struct nv50_mstm *mstm = mstc->mstm;
2869 struct nv50_disp_mthd_v1 base;
2870 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
2873 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
2874 .base.hasht = mstm->outp->dcb->hasht,
2875 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) |
2876 (0x0100 << msto->head->base.index),
2879 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
2880 if (mstc->port && mstc->port->vcpi.vcpi > 0) {
2881 struct drm_dp_payload *payload = nv50_msto_payload(msto);
2883 args.vcpi.start_slot = payload->start_slot;
2884 args.vcpi.num_slots = payload->num_slots;
2885 args.vcpi.pbn = mstc->port->vcpi.pbn;
2886 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
2890 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
2891 msto->encoder.name, msto->head->base.base.name,
2892 args.vcpi.start_slot, args.vcpi.num_slots,
2893 args.vcpi.pbn, args.vcpi.aligned_pbn);
2894 nvif_mthd(&drm->display->disp, 0, &args, sizeof(args));
2898 nv50_msto_atomic_check(struct drm_encoder *encoder,
2899 struct drm_crtc_state *crtc_state,
2900 struct drm_connector_state *conn_state)
2902 struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
2903 struct nv50_mstm *mstm = mstc->mstm;
2904 int bpp = conn_state->connector->display_info.bpc * 3;
2907 mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
2909 slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
2913 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
2918 nv50_msto_enable(struct drm_encoder *encoder)
2920 struct nv50_head *head = nv50_head(encoder->crtc);
2921 struct nv50_msto *msto = nv50_msto(encoder);
2922 struct nv50_mstc *mstc = NULL;
2923 struct nv50_mstm *mstm = NULL;
2924 struct drm_connector *connector;
2925 struct drm_connector_list_iter conn_iter;
2930 drm_connector_list_iter_begin(encoder->dev, &conn_iter);
2931 drm_for_each_connector_iter(connector, &conn_iter) {
2932 if (connector->state->best_encoder == &msto->encoder) {
2933 mstc = nv50_mstc(connector);
2938 drm_connector_list_iter_end(&conn_iter);
2943 slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
2944 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
2948 nv50_outp_acquire(mstm->outp);
2950 if (mstm->outp->link & 1)
2955 switch (mstc->connector.display_info.bpc) {
2956 case 6: depth = 0x2; break;
2957 case 8: depth = 0x5; break;
2959 default: depth = 0x6; break;
2962 mstm->outp->update(mstm->outp, head->base.index,
2963 &head->base.base.state->adjusted_mode, proto, depth);
2967 mstm->modified = true;
2971 nv50_msto_disable(struct drm_encoder *encoder)
2973 struct nv50_msto *msto = nv50_msto(encoder);
2974 struct nv50_mstc *mstc = msto->mstc;
2975 struct nv50_mstm *mstm = mstc->mstm;
2978 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
2980 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
2981 mstm->modified = true;
2983 mstm->disabled = true;
2984 msto->disabled = true;
2987 static const struct drm_encoder_helper_funcs
2989 .disable = nv50_msto_disable,
2990 .enable = nv50_msto_enable,
2991 .atomic_check = nv50_msto_atomic_check,
2995 nv50_msto_destroy(struct drm_encoder *encoder)
2997 struct nv50_msto *msto = nv50_msto(encoder);
2998 drm_encoder_cleanup(&msto->encoder);
3002 static const struct drm_encoder_funcs
3004 .destroy = nv50_msto_destroy,
3008 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
3009 struct nv50_msto **pmsto)
3011 struct nv50_msto *msto;
3014 if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
3017 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
3018 DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
3025 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
3026 msto->encoder.possible_crtcs = heads;
3030 static struct drm_encoder *
3031 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
3032 struct drm_connector_state *connector_state)
3034 struct nv50_head *head = nv50_head(connector_state->crtc);
3035 struct nv50_mstc *mstc = nv50_mstc(connector);
3037 struct nv50_mstm *mstm = mstc->mstm;
3038 return &mstm->msto[head->base.index]->encoder;
3043 static struct drm_encoder *
3044 nv50_mstc_best_encoder(struct drm_connector *connector)
3046 struct nv50_mstc *mstc = nv50_mstc(connector);
3048 struct nv50_mstm *mstm = mstc->mstm;
3049 return &mstm->msto[0]->encoder;
3054 static enum drm_mode_status
3055 nv50_mstc_mode_valid(struct drm_connector *connector,
3056 struct drm_display_mode *mode)
3062 nv50_mstc_get_modes(struct drm_connector *connector)
3064 struct nv50_mstc *mstc = nv50_mstc(connector);
3067 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
3068 drm_mode_connector_update_edid_property(&mstc->connector, mstc->edid);
3070 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
3072 if (!mstc->connector.display_info.bpc)
3073 mstc->connector.display_info.bpc = 8;
3076 drm_mode_destroy(mstc->connector.dev, mstc->native);
3077 mstc->native = nouveau_conn_native_mode(&mstc->connector);
3081 static const struct drm_connector_helper_funcs
3083 .get_modes = nv50_mstc_get_modes,
3084 .mode_valid = nv50_mstc_mode_valid,
3085 .best_encoder = nv50_mstc_best_encoder,
3086 .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
3089 static enum drm_connector_status
3090 nv50_mstc_detect(struct drm_connector *connector, bool force)
3092 struct nv50_mstc *mstc = nv50_mstc(connector);
3094 return connector_status_disconnected;
3095 return drm_dp_mst_detect_port(connector, mstc->port->mgr, mstc->port);
3099 nv50_mstc_destroy(struct drm_connector *connector)
3101 struct nv50_mstc *mstc = nv50_mstc(connector);
3102 drm_connector_cleanup(&mstc->connector);
3106 static const struct drm_connector_funcs
3108 .reset = nouveau_conn_reset,
3109 .detect = nv50_mstc_detect,
3110 .fill_modes = drm_helper_probe_single_connector_modes,
3111 .destroy = nv50_mstc_destroy,
3112 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
3113 .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
3114 .atomic_set_property = nouveau_conn_atomic_set_property,
3115 .atomic_get_property = nouveau_conn_atomic_get_property,
3119 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
3120 const char *path, struct nv50_mstc **pmstc)
3122 struct drm_device *dev = mstm->outp->base.base.dev;
3123 struct nv50_mstc *mstc;
3126 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
3131 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
3132 DRM_MODE_CONNECTOR_DisplayPort);
3139 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
3141 mstc->connector.funcs->reset(&mstc->connector);
3142 nouveau_conn_attach_properties(&mstc->connector);
3144 for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
3145 drm_mode_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
3147 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
3148 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
3149 drm_mode_connector_set_path_property(&mstc->connector, path);
3154 nv50_mstm_cleanup(struct nv50_mstm *mstm)
3156 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
3157 struct drm_encoder *encoder;
3160 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
3161 ret = drm_dp_check_act_status(&mstm->mgr);
3163 ret = drm_dp_update_payload_part2(&mstm->mgr);
3165 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
3166 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
3167 struct nv50_msto *msto = nv50_msto(encoder);
3168 struct nv50_mstc *mstc = msto->mstc;
3169 if (mstc && mstc->mstm == mstm)
3170 nv50_msto_cleanup(msto);
3174 mstm->modified = false;
3178 nv50_mstm_prepare(struct nv50_mstm *mstm)
3180 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
3181 struct drm_encoder *encoder;
3184 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
3185 ret = drm_dp_update_payload_part1(&mstm->mgr);
3187 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
3188 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
3189 struct nv50_msto *msto = nv50_msto(encoder);
3190 struct nv50_mstc *mstc = msto->mstc;
3191 if (mstc && mstc->mstm == mstm)
3192 nv50_msto_prepare(msto);
3196 if (mstm->disabled) {
3198 nv50_outp_release(mstm->outp);
3199 mstm->disabled = false;
3204 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr)
3206 struct nv50_mstm *mstm = nv50_mstm(mgr);
3207 drm_kms_helper_hotplug_event(mstm->outp->base.base.dev);
3211 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
3212 struct drm_connector *connector)
3214 struct nouveau_drm *drm = nouveau_drm(connector->dev);
3215 struct nv50_mstc *mstc = nv50_mstc(connector);
3217 drm_connector_unregister(&mstc->connector);
3219 drm_modeset_lock_all(drm->dev);
3220 drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
3222 drm_modeset_unlock_all(drm->dev);
3224 drm_connector_unreference(&mstc->connector);
3228 nv50_mstm_register_connector(struct drm_connector *connector)
3230 struct nouveau_drm *drm = nouveau_drm(connector->dev);
3232 drm_modeset_lock_all(drm->dev);
3233 drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
3234 drm_modeset_unlock_all(drm->dev);
3236 drm_connector_register(connector);
3239 static struct drm_connector *
3240 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
3241 struct drm_dp_mst_port *port, const char *path)
3243 struct nv50_mstm *mstm = nv50_mstm(mgr);
3244 struct nv50_mstc *mstc;
3247 ret = nv50_mstc_new(mstm, port, path, &mstc);
3250 mstc->connector.funcs->destroy(&mstc->connector);
3254 return &mstc->connector;
3257 static const struct drm_dp_mst_topology_cbs
3259 .add_connector = nv50_mstm_add_connector,
3260 .register_connector = nv50_mstm_register_connector,
3261 .destroy_connector = nv50_mstm_destroy_connector,
3262 .hotplug = nv50_mstm_hotplug,
3266 nv50_mstm_service(struct nv50_mstm *mstm)
3268 struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
3269 bool handled = true;
3277 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
3279 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
3283 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
3287 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
3292 nv50_mstm_remove(struct nv50_mstm *mstm)
3295 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
3299 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
3301 struct nouveau_encoder *outp = mstm->outp;
3303 struct nv50_disp_mthd_v1 base;
3304 struct nv50_disp_sor_dp_mst_link_v0 mst;
3307 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
3308 .base.hasht = outp->dcb->hasht,
3309 .base.hashm = outp->dcb->hashm,
3312 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
3313 struct nvif_object *disp = &drm->display->disp;
3317 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CTRL, &dpcd);
3325 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, dpcd);
3330 return nvif_mthd(disp, 0, &args, sizeof(args));
3334 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
3341 if (dpcd[0] >= 0x12) {
3342 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CAP, &dpcd[1]);
3346 if (!(dpcd[1] & DP_MST_CAP))
3352 ret = nv50_mstm_enable(mstm, dpcd[0], state);
3356 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, state);
3358 return nv50_mstm_enable(mstm, dpcd[0], 0);
3360 return mstm->mgr.mst_state;
3364 nv50_mstm_fini(struct nv50_mstm *mstm)
3366 if (mstm && mstm->mgr.mst_state)
3367 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
3371 nv50_mstm_init(struct nv50_mstm *mstm)
3373 if (mstm && mstm->mgr.mst_state)
3374 drm_dp_mst_topology_mgr_resume(&mstm->mgr);
3378 nv50_mstm_del(struct nv50_mstm **pmstm)
3380 struct nv50_mstm *mstm = *pmstm;
3388 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
3389 int conn_base_id, struct nv50_mstm **pmstm)
3391 const int max_payloads = hweight8(outp->dcb->heads);
3392 struct drm_device *dev = outp->base.base.dev;
3393 struct nv50_mstm *mstm;
3397 /* This is a workaround for some monitors not functioning
3398 * correctly in MST mode on initial module load. I think
3399 * some bad interaction with the VBIOS may be responsible.
3401 * A good ol' off and on again seems to work here ;)
3403 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
3404 if (ret >= 0 && dpcd >= 0x12)
3405 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
3407 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
3410 mstm->mgr.cbs = &nv50_mstm;
3412 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
3413 max_payloads, conn_base_id);
3417 for (i = 0; i < max_payloads; i++) {
3418 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
3427 /******************************************************************************
3429 *****************************************************************************/
3431 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
3432 struct drm_display_mode *mode, u8 proto, u8 depth)
3434 struct nv50_dmac *core = &nv50_mast(nv_encoder->base.base.dev)->base;
3438 nv_encoder->ctrl &= ~BIT(head);
3439 if (!(nv_encoder->ctrl & 0x0000000f))
3440 nv_encoder->ctrl = 0;
3442 nv_encoder->ctrl |= proto << 8;
3443 nv_encoder->ctrl |= BIT(head);
3446 if ((push = evo_wait(core, 6))) {
3447 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
3449 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3450 nv_encoder->ctrl |= 0x00001000;
3451 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3452 nv_encoder->ctrl |= 0x00002000;
3453 nv_encoder->ctrl |= depth << 16;
3455 evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
3458 u32 magic = 0x31ec6000 | (head << 25);
3459 u32 syncs = 0x00000001;
3460 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3461 syncs |= 0x00000008;
3462 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3463 syncs |= 0x00000010;
3464 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
3465 magic |= 0x00000001;
3467 evo_mthd(push, 0x0404 + (head * 0x300), 2);
3468 evo_data(push, syncs | (depth << 6));
3469 evo_data(push, magic);
3471 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
3473 evo_data(push, nv_encoder->ctrl);
3474 evo_kick(push, core);
3479 nv50_sor_disable(struct drm_encoder *encoder)
3481 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3482 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
3484 nv_encoder->crtc = NULL;
3487 struct nvkm_i2c_aux *aux = nv_encoder->aux;
3491 int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
3493 pwr &= ~DP_SET_POWER_MASK;
3494 pwr |= DP_SET_POWER_D3;
3495 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
3499 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
3500 nv50_audio_disable(encoder, nv_crtc);
3501 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
3502 nv50_outp_release(nv_encoder);
3507 nv50_sor_enable(struct drm_encoder *encoder)
3509 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3510 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3511 struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
3513 struct nv50_disp_mthd_v1 base;
3514 struct nv50_disp_sor_lvds_script_v0 lvds;
3517 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
3518 .base.hasht = nv_encoder->dcb->hasht,
3519 .base.hashm = nv_encoder->dcb->hashm,
3521 struct nv50_disp *disp = nv50_disp(encoder->dev);
3522 struct drm_device *dev = encoder->dev;
3523 struct nouveau_drm *drm = nouveau_drm(dev);
3524 struct nouveau_connector *nv_connector;
3525 struct nvbios *bios = &drm->vbios;
3529 nv_connector = nouveau_encoder_connector_get(nv_encoder);
3530 nv_encoder->crtc = encoder->crtc;
3531 nv50_outp_acquire(nv_encoder);
3533 switch (nv_encoder->dcb->type) {
3534 case DCB_OUTPUT_TMDS:
3535 if (nv_encoder->link & 1) {
3537 /* Only enable dual-link if:
3538 * - Need to (i.e. rate > 165MHz)
3540 * - Not an HDMI monitor, since there's no dual-link
3543 if (mode->clock >= 165000 &&
3544 nv_encoder->dcb->duallink_possible &&
3545 !drm_detect_hdmi_monitor(nv_connector->edid))
3551 nv50_hdmi_enable(&nv_encoder->base.base, mode);
3553 case DCB_OUTPUT_LVDS:
3556 if (bios->fp_no_ddc) {
3557 if (bios->fp.dual_link)
3558 lvds.lvds.script |= 0x0100;
3559 if (bios->fp.if_is_24bit)
3560 lvds.lvds.script |= 0x0200;
3562 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
3563 if (((u8 *)nv_connector->edid)[121] == 2)
3564 lvds.lvds.script |= 0x0100;
3566 if (mode->clock >= bios->fp.duallink_transition_clk) {
3567 lvds.lvds.script |= 0x0100;
3570 if (lvds.lvds.script & 0x0100) {
3571 if (bios->fp.strapless_is_24bit & 2)
3572 lvds.lvds.script |= 0x0200;
3574 if (bios->fp.strapless_is_24bit & 1)
3575 lvds.lvds.script |= 0x0200;
3578 if (nv_connector->base.display_info.bpc == 8)
3579 lvds.lvds.script |= 0x0200;
3582 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
3585 if (nv_connector->base.display_info.bpc == 6)
3588 if (nv_connector->base.display_info.bpc == 8)
3593 if (nv_encoder->link & 1)
3598 nv50_audio_enable(encoder, mode);
3605 nv_encoder->update(nv_encoder, nv_crtc->index, mode, proto, depth);
3608 static const struct drm_encoder_helper_funcs
3610 .atomic_check = nv50_outp_atomic_check,
3611 .enable = nv50_sor_enable,
3612 .disable = nv50_sor_disable,
3616 nv50_sor_destroy(struct drm_encoder *encoder)
3618 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3619 nv50_mstm_del(&nv_encoder->dp.mstm);
3620 drm_encoder_cleanup(encoder);
3624 static const struct drm_encoder_funcs
3626 .destroy = nv50_sor_destroy,
3630 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
3632 struct nouveau_connector *nv_connector = nouveau_connector(connector);
3633 struct nouveau_drm *drm = nouveau_drm(connector->dev);
3634 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
3635 struct nouveau_encoder *nv_encoder;
3636 struct drm_encoder *encoder;
3639 switch (dcbe->type) {
3640 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
3641 case DCB_OUTPUT_TMDS:
3644 type = DRM_MODE_ENCODER_TMDS;
3648 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
3651 nv_encoder->dcb = dcbe;
3652 nv_encoder->update = nv50_sor_update;
3654 encoder = to_drm_encoder(nv_encoder);
3655 encoder->possible_crtcs = dcbe->heads;
3656 encoder->possible_clones = 0;
3657 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
3658 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
3659 drm_encoder_helper_add(encoder, &nv50_sor_help);
3661 drm_mode_connector_attach_encoder(connector, encoder);
3663 if (dcbe->type == DCB_OUTPUT_DP) {
3664 struct nv50_disp *disp = nv50_disp(encoder->dev);
3665 struct nvkm_i2c_aux *aux =
3666 nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
3668 if (disp->disp->oclass < GF110_DISP) {
3669 /* HW has no support for address-only
3670 * transactions, so we're required to
3671 * use custom I2C-over-AUX code.
3673 nv_encoder->i2c = &aux->i2c;
3675 nv_encoder->i2c = &nv_connector->aux.ddc;
3677 nv_encoder->aux = aux;
3680 /*TODO: Use DP Info Table to check for support. */
3681 if (disp->disp->oclass >= GF110_DISP) {
3682 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
3683 nv_connector->base.base.id,
3684 &nv_encoder->dp.mstm);
3689 struct nvkm_i2c_bus *bus =
3690 nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
3692 nv_encoder->i2c = &bus->i2c;
3698 /******************************************************************************
3700 *****************************************************************************/
3702 nv50_pior_atomic_check(struct drm_encoder *encoder,
3703 struct drm_crtc_state *crtc_state,
3704 struct drm_connector_state *conn_state)
3706 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
3709 crtc_state->adjusted_mode.clock *= 2;
3714 nv50_pior_disable(struct drm_encoder *encoder)
3716 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3717 struct nv50_mast *mast = nv50_mast(encoder->dev);
3718 const int or = nv_encoder->or;
3721 if (nv_encoder->crtc) {
3722 push = evo_wait(mast, 4);
3724 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
3725 evo_mthd(push, 0x0700 + (or * 0x040), 1);
3726 evo_data(push, 0x00000000);
3728 evo_kick(push, mast);
3732 nv_encoder->crtc = NULL;
3733 nv50_outp_release(nv_encoder);
3737 nv50_pior_enable(struct drm_encoder *encoder)
3739 struct nv50_mast *mast = nv50_mast(encoder->dev);
3740 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3741 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3742 struct nouveau_connector *nv_connector;
3743 struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
3744 u8 owner = 1 << nv_crtc->index;
3748 nv50_outp_acquire(nv_encoder);
3750 nv_connector = nouveau_encoder_connector_get(nv_encoder);
3751 switch (nv_connector->base.display_info.bpc) {
3752 case 10: depth = 0x6; break;
3753 case 8: depth = 0x5; break;
3754 case 6: depth = 0x2; break;
3755 default: depth = 0x0; break;
3758 switch (nv_encoder->dcb->type) {
3759 case DCB_OUTPUT_TMDS:
3768 push = evo_wait(mast, 8);
3770 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
3771 u32 ctrl = (depth << 16) | (proto << 8) | owner;
3772 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3774 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3776 evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
3777 evo_data(push, ctrl);
3780 evo_kick(push, mast);
3783 nv_encoder->crtc = encoder->crtc;
3786 static const struct drm_encoder_helper_funcs
3788 .atomic_check = nv50_pior_atomic_check,
3789 .enable = nv50_pior_enable,
3790 .disable = nv50_pior_disable,
3794 nv50_pior_destroy(struct drm_encoder *encoder)
3796 drm_encoder_cleanup(encoder);
3800 static const struct drm_encoder_funcs
3802 .destroy = nv50_pior_destroy,
3806 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
3808 struct nouveau_connector *nv_connector = nouveau_connector(connector);
3809 struct nouveau_drm *drm = nouveau_drm(connector->dev);
3810 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
3811 struct nvkm_i2c_bus *bus = NULL;
3812 struct nvkm_i2c_aux *aux = NULL;
3813 struct i2c_adapter *ddc;
3814 struct nouveau_encoder *nv_encoder;
3815 struct drm_encoder *encoder;
3818 switch (dcbe->type) {
3819 case DCB_OUTPUT_TMDS:
3820 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
3821 ddc = bus ? &bus->i2c : NULL;
3822 type = DRM_MODE_ENCODER_TMDS;
3825 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
3826 ddc = aux ? &nv_connector->aux.ddc : NULL;
3827 type = DRM_MODE_ENCODER_TMDS;
3833 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
3836 nv_encoder->dcb = dcbe;
3837 nv_encoder->i2c = ddc;
3838 nv_encoder->aux = aux;
3840 encoder = to_drm_encoder(nv_encoder);
3841 encoder->possible_crtcs = dcbe->heads;
3842 encoder->possible_clones = 0;
3843 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
3844 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
3845 drm_encoder_helper_add(encoder, &nv50_pior_help);
3847 drm_mode_connector_attach_encoder(connector, encoder);
3851 /******************************************************************************
3853 *****************************************************************************/
3856 nv50_disp_atomic_commit_core(struct nouveau_drm *drm, u32 interlock)
3858 struct nv50_disp *disp = nv50_disp(drm->dev);
3859 struct nv50_dmac *core = &disp->mast.base;
3860 struct nv50_mstm *mstm;
3861 struct drm_encoder *encoder;
3864 NV_ATOMIC(drm, "commit core %08x\n", interlock);
3866 drm_for_each_encoder(encoder, drm->dev) {
3867 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
3868 mstm = nouveau_encoder(encoder)->dp.mstm;
3869 if (mstm && mstm->modified)
3870 nv50_mstm_prepare(mstm);
3874 if ((push = evo_wait(core, 5))) {
3875 evo_mthd(push, 0x0084, 1);
3876 evo_data(push, 0x80000000);
3877 evo_mthd(push, 0x0080, 2);
3878 evo_data(push, interlock);
3879 evo_data(push, 0x00000000);
3880 nouveau_bo_wr32(disp->sync, 0, 0x00000000);
3881 evo_kick(push, core);
3882 if (nvif_msec(&drm->client.device, 2000ULL,
3883 if (nouveau_bo_rd32(disp->sync, 0))
3887 NV_ERROR(drm, "EVO timeout\n");
3890 drm_for_each_encoder(encoder, drm->dev) {
3891 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
3892 mstm = nouveau_encoder(encoder)->dp.mstm;
3893 if (mstm && mstm->modified)
3894 nv50_mstm_cleanup(mstm);
3900 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
3902 struct drm_device *dev = state->dev;
3903 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
3904 struct drm_crtc *crtc;
3905 struct drm_plane_state *new_plane_state;
3906 struct drm_plane *plane;
3907 struct nouveau_drm *drm = nouveau_drm(dev);
3908 struct nv50_disp *disp = nv50_disp(dev);
3909 struct nv50_atom *atom = nv50_atom(state);
3910 struct nv50_outp_atom *outp, *outt;
3911 u32 interlock_core = 0;
3912 u32 interlock_chan = 0;
3915 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
3916 drm_atomic_helper_wait_for_fences(dev, state, false);
3917 drm_atomic_helper_wait_for_dependencies(state);
3918 drm_atomic_helper_update_legacy_modeset_state(dev, state);
3920 if (atom->lock_core)
3921 mutex_lock(&disp->mutex);
3923 /* Disable head(s). */
3924 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
3925 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
3926 struct nv50_head *head = nv50_head(crtc);
3928 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
3929 asyh->clr.mask, asyh->set.mask);
3930 if (old_crtc_state->active && !new_crtc_state->active)
3931 drm_crtc_vblank_off(crtc);
3933 if (asyh->clr.mask) {
3934 nv50_head_flush_clr(head, asyh, atom->flush_disable);
3935 interlock_core |= 1;
3939 /* Disable plane(s). */
3940 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
3941 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
3942 struct nv50_wndw *wndw = nv50_wndw(plane);
3944 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
3945 asyw->clr.mask, asyw->set.mask);
3946 if (!asyw->clr.mask)
3949 interlock_chan |= nv50_wndw_flush_clr(wndw, interlock_core,
3950 atom->flush_disable,
3954 /* Disable output path(s). */
3955 list_for_each_entry(outp, &atom->outp, head) {
3956 const struct drm_encoder_helper_funcs *help;
3957 struct drm_encoder *encoder;
3959 encoder = outp->encoder;
3960 help = encoder->helper_private;
3962 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
3963 outp->clr.mask, outp->set.mask);
3965 if (outp->clr.mask) {
3966 help->disable(encoder);
3967 interlock_core |= 1;
3968 if (outp->flush_disable) {
3969 nv50_disp_atomic_commit_core(drm, interlock_chan);
3976 /* Flush disable. */
3977 if (interlock_core) {
3978 if (atom->flush_disable) {
3979 nv50_disp_atomic_commit_core(drm, interlock_chan);
3985 /* Update output path(s). */
3986 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
3987 const struct drm_encoder_helper_funcs *help;
3988 struct drm_encoder *encoder;
3990 encoder = outp->encoder;
3991 help = encoder->helper_private;
3993 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
3994 outp->set.mask, outp->clr.mask);
3996 if (outp->set.mask) {
3997 help->enable(encoder);
4001 list_del(&outp->head);
4005 /* Update head(s). */
4006 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4007 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
4008 struct nv50_head *head = nv50_head(crtc);
4010 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
4011 asyh->set.mask, asyh->clr.mask);
4013 if (asyh->set.mask) {
4014 nv50_head_flush_set(head, asyh);
4018 if (new_crtc_state->active) {
4019 if (!old_crtc_state->active)
4020 drm_crtc_vblank_on(crtc);
4021 if (new_crtc_state->event)
4022 drm_crtc_vblank_get(crtc);
4026 /* Update plane(s). */
4027 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
4028 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
4029 struct nv50_wndw *wndw = nv50_wndw(plane);
4031 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
4032 asyw->set.mask, asyw->clr.mask);
4033 if ( !asyw->set.mask &&
4034 (!asyw->clr.mask || atom->flush_disable))
4037 interlock_chan |= nv50_wndw_flush_set(wndw, interlock_core, asyw);
4041 if (interlock_core) {
4042 if (!interlock_chan && atom->state.legacy_cursor_update) {
4043 u32 *push = evo_wait(&disp->mast, 2);
4045 evo_mthd(push, 0x0080, 1);
4046 evo_data(push, 0x00000000);
4047 evo_kick(push, &disp->mast);
4050 nv50_disp_atomic_commit_core(drm, interlock_chan);
4054 if (atom->lock_core)
4055 mutex_unlock(&disp->mutex);
4057 /* Wait for HW to signal completion. */
4058 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
4059 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
4060 struct nv50_wndw *wndw = nv50_wndw(plane);
4061 int ret = nv50_wndw_wait_armed(wndw, asyw);
4063 NV_ERROR(drm, "%s: timeout\n", plane->name);
4066 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4067 if (new_crtc_state->event) {
4068 unsigned long flags;
4069 /* Get correct count/ts if racing with vblank irq */
4070 if (new_crtc_state->active)
4071 drm_crtc_accurate_vblank_count(crtc);
4072 spin_lock_irqsave(&crtc->dev->event_lock, flags);
4073 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
4074 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4076 new_crtc_state->event = NULL;
4077 if (new_crtc_state->active)
4078 drm_crtc_vblank_put(crtc);
4082 drm_atomic_helper_commit_hw_done(state);
4083 drm_atomic_helper_cleanup_planes(dev, state);
4084 drm_atomic_helper_commit_cleanup_done(state);
4085 drm_atomic_state_put(state);
4089 nv50_disp_atomic_commit_work(struct work_struct *work)
4091 struct drm_atomic_state *state =
4092 container_of(work, typeof(*state), commit_work);
4093 nv50_disp_atomic_commit_tail(state);
4097 nv50_disp_atomic_commit(struct drm_device *dev,
4098 struct drm_atomic_state *state, bool nonblock)
4100 struct nouveau_drm *drm = nouveau_drm(dev);
4101 struct nv50_disp *disp = nv50_disp(dev);
4102 struct drm_plane_state *old_plane_state;
4103 struct drm_plane *plane;
4104 struct drm_crtc *crtc;
4105 bool active = false;
4108 ret = pm_runtime_get_sync(dev->dev);
4109 if (ret < 0 && ret != -EACCES)
4112 ret = drm_atomic_helper_setup_commit(state, nonblock);
4116 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
4118 ret = drm_atomic_helper_prepare_planes(dev, state);
4123 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
4128 ret = drm_atomic_helper_swap_state(state, true);
4132 for_each_old_plane_in_state(state, plane, old_plane_state, i) {
4133 struct nv50_wndw_atom *asyw = nv50_wndw_atom(old_plane_state);
4134 struct nv50_wndw *wndw = nv50_wndw(plane);
4136 if (asyw->set.image) {
4137 asyw->ntfy.handle = wndw->dmac->sync.handle;
4138 asyw->ntfy.offset = wndw->ntfy;
4139 asyw->ntfy.awaken = false;
4140 asyw->set.ntfy = true;
4141 nouveau_bo_wr32(disp->sync, wndw->ntfy / 4, 0x00000000);
4146 drm_atomic_state_get(state);
4149 queue_work(system_unbound_wq, &state->commit_work);
4151 nv50_disp_atomic_commit_tail(state);
4153 drm_for_each_crtc(crtc, dev) {
4154 if (crtc->state->enable) {
4155 if (!drm->have_disp_power_ref) {
4156 drm->have_disp_power_ref = true;
4164 if (!active && drm->have_disp_power_ref) {
4165 pm_runtime_put_autosuspend(dev->dev);
4166 drm->have_disp_power_ref = false;
4171 drm_atomic_helper_cleanup_planes(dev, state);
4173 pm_runtime_put_autosuspend(dev->dev);
4177 static struct nv50_outp_atom *
4178 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
4180 struct nv50_outp_atom *outp;
4182 list_for_each_entry(outp, &atom->outp, head) {
4183 if (outp->encoder == encoder)
4187 outp = kzalloc(sizeof(*outp), GFP_KERNEL);
4189 return ERR_PTR(-ENOMEM);
4191 list_add(&outp->head, &atom->outp);
4192 outp->encoder = encoder;
4197 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
4198 struct drm_connector_state *old_connector_state)
4200 struct drm_encoder *encoder = old_connector_state->best_encoder;
4201 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4202 struct drm_crtc *crtc;
4203 struct nv50_outp_atom *outp;
4205 if (!(crtc = old_connector_state->crtc))
4208 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
4209 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
4210 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
4211 outp = nv50_disp_outp_atomic_add(atom, encoder);
4213 return PTR_ERR(outp);
4215 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
4216 outp->flush_disable = true;
4217 atom->flush_disable = true;
4219 outp->clr.ctrl = true;
4220 atom->lock_core = true;
4227 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
4228 struct drm_connector_state *connector_state)
4230 struct drm_encoder *encoder = connector_state->best_encoder;
4231 struct drm_crtc_state *new_crtc_state;
4232 struct drm_crtc *crtc;
4233 struct nv50_outp_atom *outp;
4235 if (!(crtc = connector_state->crtc))
4238 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
4239 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
4240 outp = nv50_disp_outp_atomic_add(atom, encoder);
4242 return PTR_ERR(outp);
4244 outp->set.ctrl = true;
4245 atom->lock_core = true;
4252 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
4254 struct nv50_atom *atom = nv50_atom(state);
4255 struct drm_connector_state *old_connector_state, *new_connector_state;
4256 struct drm_connector *connector;
4259 ret = drm_atomic_helper_check(dev, state);
4263 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
4264 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
4268 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
4277 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
4279 struct nv50_atom *atom = nv50_atom(state);
4280 struct nv50_outp_atom *outp, *outt;
4282 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
4283 list_del(&outp->head);
4287 drm_atomic_state_default_clear(state);
4291 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
4293 struct nv50_atom *atom = nv50_atom(state);
4294 drm_atomic_state_default_release(&atom->state);
4298 static struct drm_atomic_state *
4299 nv50_disp_atomic_state_alloc(struct drm_device *dev)
4301 struct nv50_atom *atom;
4302 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
4303 drm_atomic_state_init(dev, &atom->state) < 0) {
4307 INIT_LIST_HEAD(&atom->outp);
4308 return &atom->state;
4311 static const struct drm_mode_config_funcs
4313 .fb_create = nouveau_user_framebuffer_create,
4314 .output_poll_changed = nouveau_fbcon_output_poll_changed,
4315 .atomic_check = nv50_disp_atomic_check,
4316 .atomic_commit = nv50_disp_atomic_commit,
4317 .atomic_state_alloc = nv50_disp_atomic_state_alloc,
4318 .atomic_state_clear = nv50_disp_atomic_state_clear,
4319 .atomic_state_free = nv50_disp_atomic_state_free,
4322 /******************************************************************************
4324 *****************************************************************************/
4327 nv50_display_fini(struct drm_device *dev)
4329 struct nouveau_encoder *nv_encoder;
4330 struct drm_encoder *encoder;
4331 struct drm_plane *plane;
4333 drm_for_each_plane(plane, dev) {
4334 struct nv50_wndw *wndw = nv50_wndw(plane);
4335 if (plane->funcs != &nv50_wndw)
4337 nv50_wndw_fini(wndw);
4340 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4341 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
4342 nv_encoder = nouveau_encoder(encoder);
4343 nv50_mstm_fini(nv_encoder->dp.mstm);
4349 nv50_display_init(struct drm_device *dev)
4351 struct drm_encoder *encoder;
4352 struct drm_plane *plane;
4353 struct drm_crtc *crtc;
4356 push = evo_wait(nv50_mast(dev), 32);
4360 evo_mthd(push, 0x0088, 1);
4361 evo_data(push, nv50_mast(dev)->base.sync.handle);
4362 evo_kick(push, nv50_mast(dev));
4364 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4365 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
4366 struct nouveau_encoder *nv_encoder =
4367 nouveau_encoder(encoder);
4368 nv50_mstm_init(nv_encoder->dp.mstm);
4372 drm_for_each_crtc(crtc, dev) {
4373 nv50_head_lut_load(crtc);
4376 drm_for_each_plane(plane, dev) {
4377 struct nv50_wndw *wndw = nv50_wndw(plane);
4378 if (plane->funcs != &nv50_wndw)
4380 nv50_wndw_init(wndw);
4387 nv50_display_destroy(struct drm_device *dev)
4389 struct nv50_disp *disp = nv50_disp(dev);
4391 nv50_dmac_destroy(&disp->mast.base, disp->disp);
4393 nouveau_bo_unmap(disp->sync);
4395 nouveau_bo_unpin(disp->sync);
4396 nouveau_bo_ref(NULL, &disp->sync);
4398 nouveau_display(dev)->priv = NULL;
4402 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
4403 static int nouveau_atomic = 0;
4404 module_param_named(atomic, nouveau_atomic, int, 0400);
4407 nv50_display_create(struct drm_device *dev)
4409 struct nvif_device *device = &nouveau_drm(dev)->client.device;
4410 struct nouveau_drm *drm = nouveau_drm(dev);
4411 struct dcb_table *dcb = &drm->vbios.dcb;
4412 struct drm_connector *connector, *tmp;
4413 struct nv50_disp *disp;
4414 struct dcb_output *dcbe;
4417 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
4421 mutex_init(&disp->mutex);
4423 nouveau_display(dev)->priv = disp;
4424 nouveau_display(dev)->dtor = nv50_display_destroy;
4425 nouveau_display(dev)->init = nv50_display_init;
4426 nouveau_display(dev)->fini = nv50_display_fini;
4427 disp->disp = &nouveau_display(dev)->disp;
4428 dev->mode_config.funcs = &nv50_disp_func;
4430 dev->driver->driver_features |= DRIVER_ATOMIC;
4432 /* small shared memory area we use for notifiers and semaphores */
4433 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
4434 0, 0x0000, NULL, NULL, &disp->sync);
4436 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
4438 ret = nouveau_bo_map(disp->sync);
4440 nouveau_bo_unpin(disp->sync);
4443 nouveau_bo_ref(NULL, &disp->sync);
4449 /* allocate master evo channel */
4450 ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset,
4455 /* create crtc objects to represent the hw heads */
4456 if (disp->disp->oclass >= GF110_DISP)
4457 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
4461 for (i = 0; i < fls(crtcs); i++) {
4462 if (!(crtcs & (1 << i)))
4464 ret = nv50_head_create(dev, i);
4469 /* create encoder/connector objects based on VBIOS DCB table */
4470 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
4471 connector = nouveau_connector_create(dev, dcbe->connector);
4472 if (IS_ERR(connector))
4475 if (dcbe->location == DCB_LOC_ON_CHIP) {
4476 switch (dcbe->type) {
4477 case DCB_OUTPUT_TMDS:
4478 case DCB_OUTPUT_LVDS:
4480 ret = nv50_sor_create(connector, dcbe);
4482 case DCB_OUTPUT_ANALOG:
4483 ret = nv50_dac_create(connector, dcbe);
4490 ret = nv50_pior_create(connector, dcbe);
4494 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
4495 dcbe->location, dcbe->type,
4496 ffs(dcbe->or) - 1, ret);
4501 /* cull any connectors we created that don't have an encoder */
4502 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
4503 if (connector->encoder_ids[0])
4506 NV_WARN(drm, "%s has no encoders, removing\n",
4508 connector->funcs->destroy(connector);
4513 nv50_display_destroy(dev);