drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26 #include <linux/hdmi.h>
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_atomic.h>
  30 #include <drm/drm_atomic_helper.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/drm_dp_helper.h>
  33 #include <drm/drm_fb_helper.h>
  34 #include <drm/drm_plane_helper.h>
  35 #include <drm/drm_edid.h>
  36
  37 #include <nvif/class.h>
  38 #include <nvif/cl0002.h>
  39 #include <nvif/cl5070.h>
  40 #include <nvif/cl507a.h>
  41 #include <nvif/cl507b.h>
  42 #include <nvif/cl507c.h>
  43 #include <nvif/cl507d.h>
  44 #include <nvif/cl507e.h>
  45 #include <nvif/event.h>
  46
  47 #include "nouveau_drv.h"
  48 #include "nouveau_dma.h"
  49 #include "nouveau_gem.h"
  50 #include "nouveau_connector.h"
  51 #include "nouveau_encoder.h"
  52 #include "nouveau_crtc.h"
  53 #include "nouveau_fence.h"
  54 #include "nouveau_fbcon.h"
  55 #include "nv50_display.h"
  56
  57 #define EVO_DMA_NR 9
  58
  59 #define EVO_MASTER  (0x00)
  60 #define EVO_FLIP(c) (0x01 + (c))
  61 #define EVO_OVLY(c) (0x05 + (c))
  62 #define EVO_OIMM(c) (0x09 + (c))
  63 #define EVO_CURS(c) (0x0d + (c))
  64
  65 /* offsets in shared sync bo of various structures */
  66 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
  67 #define EVO_MAST_NTFY     EVO_SYNC(      0, 0x00)
  68 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c) + 1, 0x00)
  69 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c) + 1, 0x10)
  70 #define EVO_FLIP_NTFY0(c) EVO_SYNC((c) + 1, 0x20)
  71 #define EVO_FLIP_NTFY1(c) EVO_SYNC((c) + 1, 0x30)
  72
  73 /******************************************************************************
  74  * Atomic state
  75  *****************************************************************************/
  76 #define nv50_atom(p) container_of((p), struct nv50_atom, state)
  77
  78 struct nv50_atom {
  79         struct drm_atomic_state state;
  80
  81         struct list_head outp;
  82         bool lock_core;
  83         bool flush_disable;
  84 };
  85
  86 struct nv50_outp_atom {
  87         struct list_head head;
  88
  89         struct drm_encoder *encoder;
  90         bool flush_disable;
  91
  92         union {
  93                 struct {
  94                         bool ctrl:1;
  95                 };
  96                 u8 mask;
  97         } clr;
  98
  99         union {
 100                 struct {
 101                         bool ctrl:1;
 102                 };
 103                 u8 mask;
 104         } set;
 105 };
 106
 107 #define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)
 108
 109 struct nv50_head_atom {
 110         struct drm_crtc_state state;
 111
 112         struct {
 113                 u16 iW;
 114                 u16 iH;
 115                 u16 oW;
 116                 u16 oH;
 117         } view;
 118
 119         struct nv50_head_mode {
 120                 bool interlace;
 121                 u32 clock;
 122                 struct {
 123                         u16 active;
 124                         u16 synce;
 125                         u16 blanke;
 126                         u16 blanks;
 127                 } h;
 128                 struct {
 129                         u32 active;
 130                         u16 synce;
 131                         u16 blanke;
 132                         u16 blanks;
 133                         u16 blank2s;
 134                         u16 blank2e;
 135                         u16 blankus;
 136                 } v;
 137         } mode;
 138
 139         struct {
 140                 bool visible;
 141                 u32 handle;
 142                 u64 offset:40;
 143                 u8  mode:4;
 144         } lut;
 145
 146         struct {
 147                 bool visible;
 148                 u32 handle;
 149                 u64 offset:40;
 150                 u8  format;
 151                 u8  kind:7;
 152                 u8  layout:1;
 153                 u8  block:4;
 154                 u32 pitch:20;
 155                 u16 x;
 156                 u16 y;
 157                 u16 w;
 158                 u16 h;
 159         } core;
 160
 161         struct {
 162                 bool visible;
 163                 u32 handle;
 164                 u64 offset:40;
 165                 u8  layout:1;
 166                 u8  format:1;
 167         } curs;
 168
 169         struct {
 170                 u8  depth;
 171                 u8  cpp;
 172                 u16 x;
 173                 u16 y;
 174                 u16 w;
 175                 u16 h;
 176         } base;
 177
 178         struct {
 179                 u8 cpp;
 180         } ovly;
 181
 182         struct {
 183                 bool enable:1;
 184                 u8 bits:2;
 185                 u8 mode:4;
 186         } dither;
 187
 188         struct {
 189                 struct {
 190                         u16 cos:12;
 191                         u16 sin:12;
 192                 } sat;
 193         } procamp;
 194
 195         union {
 196                 struct {
 197                         bool ilut:1;
 198                         bool core:1;
 199                         bool curs:1;
 200                 };
 201                 u8 mask;
 202         } clr;
 203
 204         union {
 205                 struct {
 206                         bool ilut:1;
 207                         bool core:1;
 208                         bool curs:1;
 209                         bool view:1;
 210                         bool mode:1;
 211                         bool base:1;
 212                         bool ovly:1;
 213                         bool dither:1;
 214                         bool procamp:1;
 215                 };
 216                 u16 mask;
 217         } set;
 218 };
 219
 220 static inline struct nv50_head_atom *
 221 nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc)
 222 {
 223         struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc);
 224         if (IS_ERR(statec))
 225                 return (void *)statec;
 226         return nv50_head_atom(statec);
 227 }
 228
 229 #define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state)
 230
 231 struct nv50_wndw_atom {
 232         struct drm_plane_state state;
 233         u8 interval;
 234
 235         struct {
 236                 u32  handle;
 237                 u16  offset:12;
 238                 bool awaken:1;
 239         } ntfy;
 240
 241         struct {
 242                 u32 handle;
 243                 u16 offset:12;
 244                 u32 acquire;
 245                 u32 release;
 246         } sema;
 247
 248         struct {
 249                 u8 enable:2;
 250         } lut;
 251
 252         struct {
 253                 u8  mode:2;
 254                 u8  interval:4;
 255
 256                 u8  format;
 257                 u8  kind:7;
 258                 u8  layout:1;
 259                 u8  block:4;
 260                 u32 pitch:20;
 261                 u16 w;
 262                 u16 h;
 263
 264                 u32 handle;
 265                 u64 offset;
 266         } image;
 267
 268         struct {
 269                 u16 x;
 270                 u16 y;
 271         } point;
 272
 273         union {
 274                 struct {
 275                         bool ntfy:1;
 276                         bool sema:1;
 277                         bool image:1;
 278                 };
 279                 u8 mask;
 280         } clr;
 281
 282         union {
 283                 struct {
 284                         bool ntfy:1;
 285                         bool sema:1;
 286                         bool image:1;
 287                         bool lut:1;
 288                         bool point:1;
 289                 };
 290                 u8 mask;
 291         } set;
 292 };
 293
 294 /******************************************************************************
 295  * EVO channel
 296  *****************************************************************************/
 297
 298 struct nv50_chan {
 299         struct nvif_object user;
 300         struct nvif_device *device;
 301 };
 302
 303 static int
 304 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
 305                  const s32 *oclass, u8 head, void *data, u32 size,
 306                  struct nv50_chan *chan)
 307 {
 308         struct nvif_sclass *sclass;
 309         int ret, i, n;
 310
 311         chan->device = device;
 312
 313         ret = n = nvif_object_sclass_get(disp, &sclass);
 314         if (ret < 0)
 315                 return ret;
 316
 317         while (oclass[0]) {
 318                 for (i = 0; i < n; i++) {
 319                         if (sclass[i].oclass == oclass[0]) {
 320                                 ret = nvif_object_init(disp, 0, oclass[0],
 321                                                        data, size, &chan->user);
 322                                 if (ret == 0)
 323                                         nvif_object_map(&chan->user, NULL, 0);
 324                                 nvif_object_sclass_put(&sclass);
 325                                 return ret;
 326                         }
 327                 }
 328                 oclass++;
 329         }
 330
 331         nvif_object_sclass_put(&sclass);
 332         return -ENOSYS;
 333 }
 334
 335 static void
 336 nv50_chan_destroy(struct nv50_chan *chan)
 337 {
 338         nvif_object_fini(&chan->user);
 339 }
 340
 341 /******************************************************************************
 342  * PIO EVO channel
 343  *****************************************************************************/
 344
 345 struct nv50_pioc {
 346         struct nv50_chan base;
 347 };
 348
 349 static void
 350 nv50_pioc_destroy(struct nv50_pioc *pioc)
 351 {
 352         nv50_chan_destroy(&pioc->base);
 353 }
 354
 355 static int
 356 nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp,
 357                  const s32 *oclass, u8 head, void *data, u32 size,
 358                  struct nv50_pioc *pioc)
 359 {
 360         return nv50_chan_create(device, disp, oclass, head, data, size,
 361                                 &pioc->base);
 362 }
 363
 364 /******************************************************************************
 365  * Overlay Immediate
 366  *****************************************************************************/
 367
 368 struct nv50_oimm {
 369         struct nv50_pioc base;
 370 };
 371
 372 static int
 373 nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp,
 374                  int head, struct nv50_oimm *oimm)
 375 {
 376         struct nv50_disp_cursor_v0 args = {
 377                 .head = head,
 378         };
 379         static const s32 oclass[] = {
 380                 GK104_DISP_OVERLAY,
 381                 GF110_DISP_OVERLAY,
 382                 GT214_DISP_OVERLAY,
 383                 G82_DISP_OVERLAY,
 384                 NV50_DISP_OVERLAY,
 385                 0
 386         };
 387
 388         return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
 389                                 &oimm->base);
 390 }
 391
 392 /******************************************************************************
 393  * DMA EVO channel
 394  *****************************************************************************/
 395
 396 struct nv50_dmac_ctxdma {
 397         struct list_head head;
 398         struct nvif_object object;
 399 };
 400
 401 struct nv50_dmac {
 402         struct nv50_chan base;
 403         dma_addr_t handle;
 404         u32 *ptr;
 405
 406         struct nvif_object sync;
 407         struct nvif_object vram;
 408         struct list_head ctxdma;
 409
 410         /* Protects against concurrent pushbuf access to this channel, lock is
 411          * grabbed by evo_wait (if the pushbuf reservation is successful) and
 412          * dropped again by evo_kick. */
 413         struct mutex lock;
 414 };
 415
 416 static void
 417 nv50_dmac_ctxdma_del(struct nv50_dmac_ctxdma *ctxdma)
 418 {
 419         nvif_object_fini(&ctxdma->object);
 420         list_del(&ctxdma->head);
 421         kfree(ctxdma);
 422 }
 423
 424 static struct nv50_dmac_ctxdma *
 425 nv50_dmac_ctxdma_new(struct nv50_dmac *dmac, struct nouveau_framebuffer *fb)
 426 {
 427         struct nouveau_drm *drm = nouveau_drm(fb->base.dev);
 428         struct nv50_dmac_ctxdma *ctxdma;
 429         const u8    kind = fb->nvbo->kind;
 430         const u32 handle = 0xfb000000 | kind;
 431         struct {
 432                 struct nv_dma_v0 base;
 433                 union {
 434                         struct nv50_dma_v0 nv50;
 435                         struct gf100_dma_v0 gf100;
 436                         struct gf119_dma_v0 gf119;
 437                 };
 438         } args = {};
 439         u32 argc = sizeof(args.base);
 440         int ret;
 441
 442         list_for_each_entry(ctxdma, &dmac->ctxdma, head) {
 443                 if (ctxdma->object.handle == handle)
 444                         return ctxdma;
 445         }
 446
 447         if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL)))
 448                 return ERR_PTR(-ENOMEM);
 449         list_add(&ctxdma->head, &dmac->ctxdma);
 450
 451         args.base.target = NV_DMA_V0_TARGET_VRAM;
 452         args.base.access = NV_DMA_V0_ACCESS_RDWR;
 453         args.base.start  = 0;
 454         args.base.limit  = drm->client.device.info.ram_user - 1;
 455
 456         if (drm->client.device.info.chipset < 0x80) {
 457                 args.nv50.part = NV50_DMA_V0_PART_256;
 458                 argc += sizeof(args.nv50);
 459         } else
 460         if (drm->client.device.info.chipset < 0xc0) {
 461                 args.nv50.part = NV50_DMA_V0_PART_256;
 462                 args.nv50.kind = kind;
 463                 argc += sizeof(args.nv50);
 464         } else
 465         if (drm->client.device.info.chipset < 0xd0) {
 466                 args.gf100.kind = kind;
 467                 argc += sizeof(args.gf100);
 468         } else {
 469                 args.gf119.page = GF119_DMA_V0_PAGE_LP;
 470                 args.gf119.kind = kind;
 471                 argc += sizeof(args.gf119);
 472         }
 473
 474         ret = nvif_object_init(&dmac->base.user, handle, NV_DMA_IN_MEMORY,
 475                                &args, argc, &ctxdma->object);
 476         if (ret) {
 477                 nv50_dmac_ctxdma_del(ctxdma);
 478                 return ERR_PTR(ret);
 479         }
 480
 481         return ctxdma;
 482 }
 483
 484 static void
 485 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
 486 {
 487         struct nvif_device *device = dmac->base.device;
 488         struct nv50_dmac_ctxdma *ctxdma, *ctxtmp;
 489
 490         list_for_each_entry_safe(ctxdma, ctxtmp, &dmac->ctxdma, head) {
 491                 nv50_dmac_ctxdma_del(ctxdma);
 492         }
 493
 494         nvif_object_fini(&dmac->vram);
 495         nvif_object_fini(&dmac->sync);
 496
 497         nv50_chan_destroy(&dmac->base);
 498
 499         if (dmac->ptr) {
 500                 struct device *dev = nvxx_device(device)->dev;
 501                 dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle);
 502         }
 503 }
 504
 505 static int
 506 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 507                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 508                  struct nv50_dmac *dmac)
 509 {
 510         struct nv50_disp_core_channel_dma_v0 *args = data;
 511         struct nvif_object pushbuf;
 512         int ret;
 513
 514         mutex_init(&dmac->lock);
 515         INIT_LIST_HEAD(&dmac->ctxdma);
 516
 517         dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE,
 518                                        &dmac->handle, GFP_KERNEL);
 519         if (!dmac->ptr)
 520                 return -ENOMEM;
 521
 522         ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
 523                                &(struct nv_dma_v0) {
 524                                         .target = NV_DMA_V0_TARGET_PCI_US,
 525                                         .access = NV_DMA_V0_ACCESS_RD,
 526                                         .start = dmac->handle + 0x0000,
 527                                         .limit = dmac->handle + 0x0fff,
 528                                }, sizeof(struct nv_dma_v0), &pushbuf);
 529         if (ret)
 530                 return ret;
 531
 532         args->pushbuf = nvif_handle(&pushbuf);
 533
 534         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 535                                &dmac->base);
 536         nvif_object_fini(&pushbuf);
 537         if (ret)
 538                 return ret;
 539
 540         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 541                                &(struct nv_dma_v0) {
 542                                         .target = NV_DMA_V0_TARGET_VRAM,
 543                                         .access = NV_DMA_V0_ACCESS_RDWR,
 544                                         .start = syncbuf + 0x0000,
 545                                         .limit = syncbuf + 0x0fff,
 546                                }, sizeof(struct nv_dma_v0),
 547                                &dmac->sync);
 548         if (ret)
 549                 return ret;
 550
 551         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 552                                &(struct nv_dma_v0) {
 553                                         .target = NV_DMA_V0_TARGET_VRAM,
 554                                         .access = NV_DMA_V0_ACCESS_RDWR,
 555                                         .start = 0,
 556                                         .limit = device->info.ram_user - 1,
 557                                }, sizeof(struct nv_dma_v0),
 558                                &dmac->vram);
 559         if (ret)
 560                 return ret;
 561
 562         return ret;
 563 }
 564
 565 /******************************************************************************
 566  * Core
 567  *****************************************************************************/
 568
 569 struct nv50_mast {
 570         struct nv50_dmac base;
 571 };
 572
 573 static int
 574 nv50_core_create(struct nvif_device *device, struct nvif_object *disp,
 575                  u64 syncbuf, struct nv50_mast *core)
 576 {
 577         struct nv50_disp_core_channel_dma_v0 args = {
 578                 .pushbuf = 0xb0007d00,
 579         };
 580         static const s32 oclass[] = {
 581                 GP102_DISP_CORE_CHANNEL_DMA,
 582                 GP100_DISP_CORE_CHANNEL_DMA,
 583                 GM200_DISP_CORE_CHANNEL_DMA,
 584                 GM107_DISP_CORE_CHANNEL_DMA,
 585                 GK110_DISP_CORE_CHANNEL_DMA,
 586                 GK104_DISP_CORE_CHANNEL_DMA,
 587                 GF110_DISP_CORE_CHANNEL_DMA,
 588                 GT214_DISP_CORE_CHANNEL_DMA,
 589                 GT206_DISP_CORE_CHANNEL_DMA,
 590                 GT200_DISP_CORE_CHANNEL_DMA,
 591                 G82_DISP_CORE_CHANNEL_DMA,
 592                 NV50_DISP_CORE_CHANNEL_DMA,
 593                 0
 594         };
 595
 596         return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args),
 597                                 syncbuf, &core->base);
 598 }
 599
 600 /******************************************************************************
 601  * Base
 602  *****************************************************************************/
 603
 604 struct nv50_sync {
 605         struct nv50_dmac base;
 606         u32 addr;
 607         u32 data;
 608 };
 609
 610 static int
 611 nv50_base_create(struct nvif_device *device, struct nvif_object *disp,
 612                  int head, u64 syncbuf, struct nv50_sync *base)
 613 {
 614         struct nv50_disp_base_channel_dma_v0 args = {
 615                 .pushbuf = 0xb0007c00 | head,
 616                 .head = head,
 617         };
 618         static const s32 oclass[] = {
 619                 GK110_DISP_BASE_CHANNEL_DMA,
 620                 GK104_DISP_BASE_CHANNEL_DMA,
 621                 GF110_DISP_BASE_CHANNEL_DMA,
 622                 GT214_DISP_BASE_CHANNEL_DMA,
 623                 GT200_DISP_BASE_CHANNEL_DMA,
 624                 G82_DISP_BASE_CHANNEL_DMA,
 625                 NV50_DISP_BASE_CHANNEL_DMA,
 626                 0
 627         };
 628
 629         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 630                                 syncbuf, &base->base);
 631 }
 632
 633 /******************************************************************************
 634  * Overlay
 635  *****************************************************************************/
 636
 637 struct nv50_ovly {
 638         struct nv50_dmac base;
 639 };
 640
 641 static int
 642 nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp,
 643                  int head, u64 syncbuf, struct nv50_ovly *ovly)
 644 {
 645         struct nv50_disp_overlay_channel_dma_v0 args = {
 646                 .pushbuf = 0xb0007e00 | head,
 647                 .head = head,
 648         };
 649         static const s32 oclass[] = {
 650                 GK104_DISP_OVERLAY_CONTROL_DMA,
 651                 GF110_DISP_OVERLAY_CONTROL_DMA,
 652                 GT214_DISP_OVERLAY_CHANNEL_DMA,
 653                 GT200_DISP_OVERLAY_CHANNEL_DMA,
 654                 G82_DISP_OVERLAY_CHANNEL_DMA,
 655                 NV50_DISP_OVERLAY_CHANNEL_DMA,
 656                 0
 657         };
 658
 659         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 660                                 syncbuf, &ovly->base);
 661 }
 662
 663 struct nv50_head {
 664         struct nouveau_crtc base;
 665         struct {
 666                 struct nouveau_bo *nvbo[2];
 667                 int next;
 668         } lut;
 669         struct nv50_ovly ovly;
 670         struct nv50_oimm oimm;
 671 };
 672
 673 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
 674 #define nv50_ovly(c) (&nv50_head(c)->ovly)
 675 #define nv50_oimm(c) (&nv50_head(c)->oimm)
 676 #define nv50_chan(c) (&(c)->base.base)
 677 #define nv50_vers(c) nv50_chan(c)->user.oclass
 678
 679 struct nv50_disp {
 680         struct nvif_object *disp;
 681         struct nv50_mast mast;
 682
 683         struct nouveau_bo *sync;
 684
 685         struct mutex mutex;
 686 };
 687
 688 static struct nv50_disp *
 689 nv50_disp(struct drm_device *dev)
 690 {
 691         return nouveau_display(dev)->priv;
 692 }
 693
 694 #define nv50_mast(d) (&nv50_disp(d)->mast)
 695
 696 /******************************************************************************
 697  * EVO channel helpers
 698  *****************************************************************************/
 699 static u32 *
 700 evo_wait(void *evoc, int nr)
 701 {
 702         struct nv50_dmac *dmac = evoc;
 703         struct nvif_device *device = dmac->base.device;
 704         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 705
 706         mutex_lock(&dmac->lock);
 707         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 708                 dmac->ptr[put] = 0x20000000;
 709
 710                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 711                 if (nvif_msec(device, 2000,
 712                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 713                                 break;
 714                 ) < 0) {
 715                         mutex_unlock(&dmac->lock);
 716                         pr_err("nouveau: evo channel stalled\n");
 717                         return NULL;
 718                 }
 719
 720                 put = 0;
 721         }
 722
 723         return dmac->ptr + put;
 724 }
 725
 726 static void
 727 evo_kick(u32 *push, void *evoc)
 728 {
 729         struct nv50_dmac *dmac = evoc;
 730         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 731         mutex_unlock(&dmac->lock);
 732 }
 733
 734 #define evo_mthd(p, m, s) do {                                          \
 735         const u32 _m = (m), _s = (s);                                   \
 736         if (drm_debug & DRM_UT_KMS)                                     \
 737                 pr_err("%04x %d %s\n", _m, _s, __func__);               \
 738         *((p)++) = ((_s << 18) | _m);                                   \
 739 } while(0)
 740
 741 #define evo_data(p, d) do {                                             \
 742         const u32 _d = (d);                                             \
 743         if (drm_debug & DRM_UT_KMS)                                     \
 744                 pr_err("\t%08x\n", _d);                                 \
 745         *((p)++) = _d;                                                  \
 746 } while(0)
 747
 748 /******************************************************************************
 749  * Plane
 750  *****************************************************************************/
 751 #define nv50_wndw(p) container_of((p), struct nv50_wndw, plane)
 752
 753 struct nv50_wndw {
 754         const struct nv50_wndw_func *func;
 755         struct nv50_dmac *dmac;
 756
 757         struct drm_plane plane;
 758
 759         struct nvif_notify notify;
 760         u16 ntfy;
 761         u16 sema;
 762         u32 data;
 763 };
 764
 765 struct nv50_wndw_func {
 766         void *(*dtor)(struct nv50_wndw *);
 767         int (*acquire)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
 768                        struct nv50_head_atom *asyh);
 769         void (*release)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
 770                         struct nv50_head_atom *asyh);
 771         void (*prepare)(struct nv50_wndw *, struct nv50_head_atom *asyh,
 772                         struct nv50_wndw_atom *asyw);
 773
 774         void (*sema_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 775         void (*sema_clr)(struct nv50_wndw *);
 776         void (*ntfy_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 777         void (*ntfy_clr)(struct nv50_wndw *);
 778         int (*ntfy_wait_begun)(struct nv50_wndw *, struct nv50_wndw_atom *);
 779         void (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 780         void (*image_clr)(struct nv50_wndw *);
 781         void (*lut)(struct nv50_wndw *, struct nv50_wndw_atom *);
 782         void (*point)(struct nv50_wndw *, struct nv50_wndw_atom *);
 783
 784         u32 (*update)(struct nv50_wndw *, u32 interlock);
 785 };
 786
 787 static int
 788 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
 789 {
 790         if (asyw->set.ntfy)
 791                 return wndw->func->ntfy_wait_begun(wndw, asyw);
 792         return 0;
 793 }
 794
 795 static u32
 796 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 interlock, bool flush,
 797                     struct nv50_wndw_atom *asyw)
 798 {
 799         if (asyw->clr.sema && (!asyw->set.sema || flush))
 800                 wndw->func->sema_clr(wndw);
 801         if (asyw->clr.ntfy && (!asyw->set.ntfy || flush))
 802                 wndw->func->ntfy_clr(wndw);
 803         if (asyw->clr.image && (!asyw->set.image || flush))
 804                 wndw->func->image_clr(wndw);
 805
 806         return flush ? wndw->func->update(wndw, interlock) : 0;
 807 }
 808
 809 static u32
 810 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 interlock,
 811                     struct nv50_wndw_atom *asyw)
 812 {
 813         if (interlock) {
 814                 asyw->image.mode = 0;
 815                 asyw->image.interval = 1;
 816         }
 817
 818         if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw);
 819         if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw);
 820         if (asyw->set.image) wndw->func->image_set(wndw, asyw);
 821         if (asyw->set.lut  ) wndw->func->lut      (wndw, asyw);
 822         if (asyw->set.point) wndw->func->point    (wndw, asyw);
 823
 824         return wndw->func->update(wndw, interlock);
 825 }
 826
 827 static void
 828 nv50_wndw_atomic_check_release(struct nv50_wndw *wndw,
 829                                struct nv50_wndw_atom *asyw,
 830                                struct nv50_head_atom *asyh)
 831 {
 832         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
 833         NV_ATOMIC(drm, "%s release\n", wndw->plane.name);
 834         wndw->func->release(wndw, asyw, asyh);
 835         asyw->ntfy.handle = 0;
 836         asyw->sema.handle = 0;
 837 }
 838
 839 static int
 840 nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw,
 841                                struct nv50_wndw_atom *asyw,
 842                                struct nv50_head_atom *asyh)
 843 {
 844         struct nouveau_framebuffer *fb = nouveau_framebuffer(asyw->state.fb);
 845         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
 846         int ret;
 847
 848         NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name);
 849
 850         asyw->image.w = fb->base.width;
 851         asyw->image.h = fb->base.height;
 852         asyw->image.kind = fb->nvbo->kind;
 853
 854         if (asyh->state.pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
 855                 asyw->interval = 0;
 856         else
 857                 asyw->interval = 1;
 858
 859         if (asyw->image.kind) {
 860                 asyw->image.layout = 0;
 861                 if (drm->client.device.info.chipset >= 0xc0)
 862                         asyw->image.block = fb->nvbo->mode >> 4;
 863                 else
 864                         asyw->image.block = fb->nvbo->mode;
 865                 asyw->image.pitch = (fb->base.pitches[0] / 4) << 4;
 866         } else {
 867                 asyw->image.layout = 1;
 868                 asyw->image.block  = 0;
 869                 asyw->image.pitch  = fb->base.pitches[0];
 870         }
 871
 872         ret = wndw->func->acquire(wndw, asyw, asyh);
 873         if (ret)
 874                 return ret;
 875
 876         if (asyw->set.image) {
 877                 if (!(asyw->image.mode = asyw->interval ? 0 : 1))
 878                         asyw->image.interval = asyw->interval;
 879                 else
 880                         asyw->image.interval = 0;
 881         }
 882
 883         return 0;
 884 }
 885
 886 static int
 887 nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state)
 888 {
 889         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 890         struct nv50_wndw *wndw = nv50_wndw(plane);
 891         struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state);
 892         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
 893         struct nv50_head_atom *harm = NULL, *asyh = NULL;
 894         bool varm = false, asyv = false, asym = false;
 895         int ret;
 896
 897         NV_ATOMIC(drm, "%s atomic_check\n", plane->name);
 898         if (asyw->state.crtc) {
 899                 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
 900                 if (IS_ERR(asyh))
 901                         return PTR_ERR(asyh);
 902                 asym = drm_atomic_crtc_needs_modeset(&asyh->state);
 903                 asyv = asyh->state.active;
 904         }
 905
 906         if (armw->state.crtc) {
 907                 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc);
 908                 if (IS_ERR(harm))
 909                         return PTR_ERR(harm);
 910                 varm = harm->state.crtc->state->active;
 911         }
 912
 913         if (asyv) {
 914                 asyw->point.x = asyw->state.crtc_x;
 915                 asyw->point.y = asyw->state.crtc_y;
 916                 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point)))
 917                         asyw->set.point = true;
 918
 919                 ret = nv50_wndw_atomic_check_acquire(wndw, asyw, asyh);
 920                 if (ret)
 921                         return ret;
 922         } else
 923         if (varm) {
 924                 nv50_wndw_atomic_check_release(wndw, asyw, harm);
 925         } else {
 926                 return 0;
 927         }
 928
 929         if (!asyv || asym) {
 930                 asyw->clr.ntfy = armw->ntfy.handle != 0;
 931                 asyw->clr.sema = armw->sema.handle != 0;
 932                 if (wndw->func->image_clr)
 933                         asyw->clr.image = armw->image.handle != 0;
 934                 asyw->set.lut = wndw->func->lut && asyv;
 935         }
 936
 937         return 0;
 938 }
 939
 940 static void
 941 nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state)
 942 {
 943         struct nouveau_framebuffer *fb = nouveau_framebuffer(old_state->fb);
 944         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 945
 946         NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb);
 947         if (!old_state->fb)
 948                 return;
 949
 950         nouveau_bo_unpin(fb->nvbo);
 951 }
 952
 953 static int
 954 nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state)
 955 {
 956         struct nouveau_framebuffer *fb = nouveau_framebuffer(state->fb);
 957         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 958         struct nv50_wndw *wndw = nv50_wndw(plane);
 959         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
 960         struct nv50_head_atom *asyh;
 961         struct nv50_dmac_ctxdma *ctxdma;
 962         int ret;
 963
 964         NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, state->fb);
 965         if (!asyw->state.fb)
 966                 return 0;
 967
 968         ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM, true);
 969         if (ret)
 970                 return ret;
 971
 972         ctxdma = nv50_dmac_ctxdma_new(wndw->dmac, fb);
 973         if (IS_ERR(ctxdma)) {
 974                 nouveau_bo_unpin(fb->nvbo);
 975                 return PTR_ERR(ctxdma);
 976         }
 977
 978         asyw->state.fence = reservation_object_get_excl_rcu(fb->nvbo->bo.resv);
 979         asyw->image.handle = ctxdma->object.handle;
 980         asyw->image.offset = fb->nvbo->bo.offset;
 981
 982         if (wndw->func->prepare) {
 983                 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
 984                 if (IS_ERR(asyh))
 985                         return PTR_ERR(asyh);
 986
 987                 wndw->func->prepare(wndw, asyh, asyw);
 988         }
 989
 990         return 0;
 991 }
 992
 993 static const struct drm_plane_helper_funcs
 994 nv50_wndw_helper = {
 995         .prepare_fb = nv50_wndw_prepare_fb,
 996         .cleanup_fb = nv50_wndw_cleanup_fb,
 997         .atomic_check = nv50_wndw_atomic_check,
 998 };
 999
1000 static void
1001 nv50_wndw_atomic_destroy_state(struct drm_plane *plane,
1002                                struct drm_plane_state *state)
1003 {
1004         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
1005         __drm_atomic_helper_plane_destroy_state(&asyw->state);
1006         kfree(asyw);
1007 }
1008
1009 static struct drm_plane_state *
1010 nv50_wndw_atomic_duplicate_state(struct drm_plane *plane)
1011 {
1012         struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state);
1013         struct nv50_wndw_atom *asyw;
1014         if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL)))
1015                 return NULL;
1016         __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state);
1017         asyw->interval = 1;
1018         asyw->sema = armw->sema;
1019         asyw->ntfy = armw->ntfy;
1020         asyw->image = armw->image;
1021         asyw->point = armw->point;
1022         asyw->lut = armw->lut;
1023         asyw->clr.mask = 0;
1024         asyw->set.mask = 0;
1025         return &asyw->state;
1026 }
1027
1028 static void
1029 nv50_wndw_reset(struct drm_plane *plane)
1030 {
1031         struct nv50_wndw_atom *asyw;
1032
1033         if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL))))
1034                 return;
1035
1036         if (plane->state)
1037                 plane->funcs->atomic_destroy_state(plane, plane->state);
1038         plane->state = &asyw->state;
1039         plane->state->plane = plane;
1040         plane->state->rotation = DRM_MODE_ROTATE_0;
1041 }
1042
1043 static void
1044 nv50_wndw_destroy(struct drm_plane *plane)
1045 {
1046         struct nv50_wndw *wndw = nv50_wndw(plane);
1047         void *data;
1048         nvif_notify_fini(&wndw->notify);
1049         data = wndw->func->dtor(wndw);
1050         drm_plane_cleanup(&wndw->plane);
1051         kfree(data);
1052 }
1053
1054 static const struct drm_plane_funcs
1055 nv50_wndw = {
1056         .update_plane = drm_atomic_helper_update_plane,
1057         .disable_plane = drm_atomic_helper_disable_plane,
1058         .destroy = nv50_wndw_destroy,
1059         .reset = nv50_wndw_reset,
1060         .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state,
1061         .atomic_destroy_state = nv50_wndw_atomic_destroy_state,
1062 };
1063
1064 static void
1065 nv50_wndw_fini(struct nv50_wndw *wndw)
1066 {
1067         nvif_notify_put(&wndw->notify);
1068 }
1069
1070 static void
1071 nv50_wndw_init(struct nv50_wndw *wndw)
1072 {
1073         nvif_notify_get(&wndw->notify);
1074 }
1075
1076 static int
1077 nv50_wndw_ctor(const struct nv50_wndw_func *func, struct drm_device *dev,
1078                enum drm_plane_type type, const char *name, int index,
1079                struct nv50_dmac *dmac, const u32 *format, int nformat,
1080                struct nv50_wndw *wndw)
1081 {
1082         int ret;
1083
1084         wndw->func = func;
1085         wndw->dmac = dmac;
1086
1087         ret = drm_universal_plane_init(dev, &wndw->plane, 0, &nv50_wndw,
1088                                        format, nformat, NULL,
1089                                        type, "%s-%d", name, index);
1090         if (ret)
1091                 return ret;
1092
1093         drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);
1094         return 0;
1095 }
1096
1097 /******************************************************************************
1098  * Cursor plane
1099  *****************************************************************************/
1100 #define nv50_curs(p) container_of((p), struct nv50_curs, wndw)
1101
1102 struct nv50_curs {
1103         struct nv50_wndw wndw;
1104         struct nvif_object chan;
1105 };
1106
1107 static u32
1108 nv50_curs_update(struct nv50_wndw *wndw, u32 interlock)
1109 {
1110         struct nv50_curs *curs = nv50_curs(wndw);
1111         nvif_wr32(&curs->chan, 0x0080, 0x00000000);
1112         return 0;
1113 }
1114
1115 static void
1116 nv50_curs_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1117 {
1118         struct nv50_curs *curs = nv50_curs(wndw);
1119         nvif_wr32(&curs->chan, 0x0084, (asyw->point.y << 16) | asyw->point.x);
1120 }
1121
1122 static void
1123 nv50_curs_prepare(struct nv50_wndw *wndw, struct nv50_head_atom *asyh,
1124                   struct nv50_wndw_atom *asyw)
1125 {
1126         u32 handle = nv50_disp(wndw->plane.dev)->mast.base.vram.handle;
1127         u32 offset = asyw->image.offset;
1128         if (asyh->curs.handle != handle || asyh->curs.offset != offset) {
1129                 asyh->curs.handle = handle;
1130                 asyh->curs.offset = offset;
1131                 asyh->set.curs = asyh->curs.visible;
1132         }
1133 }
1134
1135 static void
1136 nv50_curs_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1137                   struct nv50_head_atom *asyh)
1138 {
1139         asyh->curs.visible = false;
1140 }
1141
1142 static int
1143 nv50_curs_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1144                   struct nv50_head_atom *asyh)
1145 {
1146         int ret;
1147
1148         ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state,
1149                                                   DRM_PLANE_HELPER_NO_SCALING,
1150                                                   DRM_PLANE_HELPER_NO_SCALING,
1151                                                   true, true);
1152         asyh->curs.visible = asyw->state.visible;
1153         if (ret || !asyh->curs.visible)
1154                 return ret;
1155
1156         switch (asyw->state.fb->width) {
1157         case 32: asyh->curs.layout = 0; break;
1158         case 64: asyh->curs.layout = 1; break;
1159         default:
1160                 return -EINVAL;
1161         }
1162
1163         if (asyw->state.fb->width != asyw->state.fb->height)
1164                 return -EINVAL;
1165
1166         switch (asyw->state.fb->format->format) {
1167         case DRM_FORMAT_ARGB8888: asyh->curs.format = 1; break;
1168         default:
1169                 WARN_ON(1);
1170                 return -EINVAL;
1171         }
1172
1173         return 0;
1174 }
1175
1176 static void *
1177 nv50_curs_dtor(struct nv50_wndw *wndw)
1178 {
1179         struct nv50_curs *curs = nv50_curs(wndw);
1180         nvif_object_fini(&curs->chan);
1181         return curs;
1182 }
1183
1184 static const u32
1185 nv50_curs_format[] = {
1186         DRM_FORMAT_ARGB8888,
1187 };
1188
1189 static const struct nv50_wndw_func
1190 nv50_curs = {
1191         .dtor = nv50_curs_dtor,
1192         .acquire = nv50_curs_acquire,
1193         .release = nv50_curs_release,
1194         .prepare = nv50_curs_prepare,
1195         .point = nv50_curs_point,
1196         .update = nv50_curs_update,
1197 };
1198
1199 static int
1200 nv50_curs_new(struct nouveau_drm *drm, struct nv50_head *head,
1201               struct nv50_curs **pcurs)
1202 {
1203         static const struct nvif_mclass curses[] = {
1204                 { GK104_DISP_CURSOR, 0 },
1205                 { GF110_DISP_CURSOR, 0 },
1206                 { GT214_DISP_CURSOR, 0 },
1207                 {   G82_DISP_CURSOR, 0 },
1208                 {  NV50_DISP_CURSOR, 0 },
1209                 {}
1210         };
1211         struct nv50_disp_cursor_v0 args = {
1212                 .head = head->base.index,
1213         };
1214         struct nv50_disp *disp = nv50_disp(drm->dev);
1215         struct nv50_curs *curs;
1216         int cid, ret;
1217
1218         cid = nvif_mclass(disp->disp, curses);
1219         if (cid < 0) {
1220                 NV_ERROR(drm, "No supported cursor immediate class\n");
1221                 return cid;
1222         }
1223
1224         if (!(curs = *pcurs = kzalloc(sizeof(*curs), GFP_KERNEL)))
1225                 return -ENOMEM;
1226
1227         ret = nv50_wndw_ctor(&nv50_curs, drm->dev, DRM_PLANE_TYPE_CURSOR,
1228                              "curs", head->base.index, &disp->mast.base,
1229                              nv50_curs_format, ARRAY_SIZE(nv50_curs_format),
1230                              &curs->wndw);
1231         if (ret) {
1232                 kfree(curs);
1233                 return ret;
1234         }
1235
1236         ret = nvif_object_init(disp->disp, 0, curses[cid].oclass, &args,
1237                                sizeof(args), &curs->chan);
1238         if (ret) {
1239                 NV_ERROR(drm, "curs%04x allocation failed: %d\n",
1240                          curses[cid].oclass, ret);
1241                 return ret;
1242         }
1243
1244         return 0;
1245 }
1246
1247 /******************************************************************************
1248  * Primary plane
1249  *****************************************************************************/
1250 #define nv50_base(p) container_of((p), struct nv50_base, wndw)
1251
1252 struct nv50_base {
1253         struct nv50_wndw wndw;
1254         struct nv50_sync chan;
1255         int id;
1256 };
1257
1258 static int
1259 nv50_base_notify(struct nvif_notify *notify)
1260 {
1261         return NVIF_NOTIFY_KEEP;
1262 }
1263
1264 static void
1265 nv50_base_lut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1266 {
1267         struct nv50_base *base = nv50_base(wndw);
1268         u32 *push;
1269         if ((push = evo_wait(&base->chan, 2))) {
1270                 evo_mthd(push, 0x00e0, 1);
1271                 evo_data(push, asyw->lut.enable << 30);
1272                 evo_kick(push, &base->chan);
1273         }
1274 }
1275
1276 static void
1277 nv50_base_image_clr(struct nv50_wndw *wndw)
1278 {
1279         struct nv50_base *base = nv50_base(wndw);
1280         u32 *push;
1281         if ((push = evo_wait(&base->chan, 4))) {
1282                 evo_mthd(push, 0x0084, 1);
1283                 evo_data(push, 0x00000000);
1284                 evo_mthd(push, 0x00c0, 1);
1285                 evo_data(push, 0x00000000);
1286                 evo_kick(push, &base->chan);
1287         }
1288 }
1289
1290 static void
1291 nv50_base_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1292 {
1293         struct nv50_base *base = nv50_base(wndw);
1294         const s32 oclass = base->chan.base.base.user.oclass;
1295         u32 *push;
1296         if ((push = evo_wait(&base->chan, 10))) {
1297                 evo_mthd(push, 0x0084, 1);
1298                 evo_data(push, (asyw->image.mode << 8) |
1299                                (asyw->image.interval << 4));
1300                 evo_mthd(push, 0x00c0, 1);
1301                 evo_data(push, asyw->image.handle);
1302                 if (oclass < G82_DISP_BASE_CHANNEL_DMA) {
1303                         evo_mthd(push, 0x0800, 5);
1304                         evo_data(push, asyw->image.offset >> 8);
1305                         evo_data(push, 0x00000000);
1306                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1307                         evo_data(push, (asyw->image.layout << 20) |
1308                                         asyw->image.pitch |
1309                                         asyw->image.block);
1310                         evo_data(push, (asyw->image.kind << 16) |
1311                                        (asyw->image.format << 8));
1312                 } else
1313                 if (oclass < GF110_DISP_BASE_CHANNEL_DMA) {
1314                         evo_mthd(push, 0x0800, 5);
1315                         evo_data(push, asyw->image.offset >> 8);
1316                         evo_data(push, 0x00000000);
1317                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1318                         evo_data(push, (asyw->image.layout << 20) |
1319                                         asyw->image.pitch |
1320                                         asyw->image.block);
1321                         evo_data(push, asyw->image.format << 8);
1322                 } else {
1323                         evo_mthd(push, 0x0400, 5);
1324                         evo_data(push, asyw->image.offset >> 8);
1325                         evo_data(push, 0x00000000);
1326                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1327                         evo_data(push, (asyw->image.layout << 24) |
1328                                         asyw->image.pitch |
1329                                         asyw->image.block);
1330                         evo_data(push, asyw->image.format << 8);
1331                 }
1332                 evo_kick(push, &base->chan);
1333         }
1334 }
1335
1336 static void
1337 nv50_base_ntfy_clr(struct nv50_wndw *wndw)
1338 {
1339         struct nv50_base *base = nv50_base(wndw);
1340         u32 *push;
1341         if ((push = evo_wait(&base->chan, 2))) {
1342                 evo_mthd(push, 0x00a4, 1);
1343                 evo_data(push, 0x00000000);
1344                 evo_kick(push, &base->chan);
1345         }
1346 }
1347
1348 static void
1349 nv50_base_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1350 {
1351         struct nv50_base *base = nv50_base(wndw);
1352         u32 *push;
1353         if ((push = evo_wait(&base->chan, 3))) {
1354                 evo_mthd(push, 0x00a0, 2);
1355                 evo_data(push, (asyw->ntfy.awaken << 30) | asyw->ntfy.offset);
1356                 evo_data(push, asyw->ntfy.handle);
1357                 evo_kick(push, &base->chan);
1358         }
1359 }
1360
1361 static void
1362 nv50_base_sema_clr(struct nv50_wndw *wndw)
1363 {
1364         struct nv50_base *base = nv50_base(wndw);
1365         u32 *push;
1366         if ((push = evo_wait(&base->chan, 2))) {
1367                 evo_mthd(push, 0x0094, 1);
1368                 evo_data(push, 0x00000000);
1369                 evo_kick(push, &base->chan);
1370         }
1371 }
1372
1373 static void
1374 nv50_base_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1375 {
1376         struct nv50_base *base = nv50_base(wndw);
1377         u32 *push;
1378         if ((push = evo_wait(&base->chan, 5))) {
1379                 evo_mthd(push, 0x0088, 4);
1380                 evo_data(push, asyw->sema.offset);
1381                 evo_data(push, asyw->sema.acquire);
1382                 evo_data(push, asyw->sema.release);
1383                 evo_data(push, asyw->sema.handle);
1384                 evo_kick(push, &base->chan);
1385         }
1386 }
1387
1388 static u32
1389 nv50_base_update(struct nv50_wndw *wndw, u32 interlock)
1390 {
1391         struct nv50_base *base = nv50_base(wndw);
1392         u32 *push;
1393
1394         if (!(push = evo_wait(&base->chan, 2)))
1395                 return 0;
1396         evo_mthd(push, 0x0080, 1);
1397         evo_data(push, interlock);
1398         evo_kick(push, &base->chan);
1399
1400         if (base->chan.base.base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA)
1401                 return interlock ? 2 << (base->id * 8) : 0;
1402         return interlock ? 2 << (base->id * 4) : 0;
1403 }
1404
1405 static int
1406 nv50_base_ntfy_wait_begun(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1407 {
1408         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
1409         struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
1410         if (nvif_msec(&drm->client.device, 2000ULL,
1411                 u32 data = nouveau_bo_rd32(disp->sync, asyw->ntfy.offset / 4);
1412                 if ((data & 0xc0000000) == 0x40000000)
1413                         break;
1414                 usleep_range(1, 2);
1415         ) < 0)
1416                 return -ETIMEDOUT;
1417         return 0;
1418 }
1419
1420 static void
1421 nv50_base_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1422                   struct nv50_head_atom *asyh)
1423 {
1424         asyh->base.cpp = 0;
1425 }
1426
1427 static int
1428 nv50_base_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1429                   struct nv50_head_atom *asyh)
1430 {
1431         const struct drm_framebuffer *fb = asyw->state.fb;
1432         int ret;
1433
1434         if (!fb->format->depth)
1435                 return -EINVAL;
1436
1437         ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state,
1438                                                   DRM_PLANE_HELPER_NO_SCALING,
1439                                                   DRM_PLANE_HELPER_NO_SCALING,
1440                                                   false, true);
1441         if (ret)
1442                 return ret;
1443
1444         asyh->base.depth = fb->format->depth;
1445         asyh->base.cpp = fb->format->cpp[0];
1446         asyh->base.x = asyw->state.src.x1 >> 16;
1447         asyh->base.y = asyw->state.src.y1 >> 16;
1448         asyh->base.w = asyw->state.fb->width;
1449         asyh->base.h = asyw->state.fb->height;
1450
1451         switch (fb->format->format) {
1452         case DRM_FORMAT_C8         : asyw->image.format = 0x1e; break;
1453         case DRM_FORMAT_RGB565     : asyw->image.format = 0xe8; break;
1454         case DRM_FORMAT_XRGB1555   :
1455         case DRM_FORMAT_ARGB1555   : asyw->image.format = 0xe9; break;
1456         case DRM_FORMAT_XRGB8888   :
1457         case DRM_FORMAT_ARGB8888   : asyw->image.format = 0xcf; break;
1458         case DRM_FORMAT_XBGR2101010:
1459         case DRM_FORMAT_ABGR2101010: asyw->image.format = 0xd1; break;
1460         case DRM_FORMAT_XBGR8888   :
1461         case DRM_FORMAT_ABGR8888   : asyw->image.format = 0xd5; break;
1462         default:
1463                 WARN_ON(1);
1464                 return -EINVAL;
1465         }
1466
1467         asyw->lut.enable = 1;
1468         asyw->set.image = true;
1469         return 0;
1470 }
1471
1472 static void *
1473 nv50_base_dtor(struct nv50_wndw *wndw)
1474 {
1475         struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
1476         struct nv50_base *base = nv50_base(wndw);
1477         nv50_dmac_destroy(&base->chan.base, disp->disp);
1478         return base;
1479 }
1480
1481 static const u32
1482 nv50_base_format[] = {
1483         DRM_FORMAT_C8,
1484         DRM_FORMAT_RGB565,
1485         DRM_FORMAT_XRGB1555,
1486         DRM_FORMAT_ARGB1555,
1487         DRM_FORMAT_XRGB8888,
1488         DRM_FORMAT_ARGB8888,
1489         DRM_FORMAT_XBGR2101010,
1490         DRM_FORMAT_ABGR2101010,
1491         DRM_FORMAT_XBGR8888,
1492         DRM_FORMAT_ABGR8888,
1493 };
1494
1495 static const struct nv50_wndw_func
1496 nv50_base = {
1497         .dtor = nv50_base_dtor,
1498         .acquire = nv50_base_acquire,
1499         .release = nv50_base_release,
1500         .sema_set = nv50_base_sema_set,
1501         .sema_clr = nv50_base_sema_clr,
1502         .ntfy_set = nv50_base_ntfy_set,
1503         .ntfy_clr = nv50_base_ntfy_clr,
1504         .ntfy_wait_begun = nv50_base_ntfy_wait_begun,
1505         .image_set = nv50_base_image_set,
1506         .image_clr = nv50_base_image_clr,
1507         .lut = nv50_base_lut,
1508         .update = nv50_base_update,
1509 };
1510
1511 static int
1512 nv50_base_new(struct nouveau_drm *drm, struct nv50_head *head,
1513               struct nv50_base **pbase)
1514 {
1515         struct nv50_disp *disp = nv50_disp(drm->dev);
1516         struct nv50_base *base;
1517         int ret;
1518
1519         if (!(base = *pbase = kzalloc(sizeof(*base), GFP_KERNEL)))
1520                 return -ENOMEM;
1521         base->id = head->base.index;
1522         base->wndw.ntfy = EVO_FLIP_NTFY0(base->id);
1523         base->wndw.sema = EVO_FLIP_SEM0(base->id);
1524         base->wndw.data = 0x00000000;
1525
1526         ret = nv50_wndw_ctor(&nv50_base, drm->dev, DRM_PLANE_TYPE_PRIMARY,
1527                              "base", base->id, &base->chan.base,
1528                              nv50_base_format, ARRAY_SIZE(nv50_base_format),
1529                              &base->wndw);
1530         if (ret) {
1531                 kfree(base);
1532                 return ret;
1533         }
1534
1535         ret = nv50_base_create(&drm->client.device, disp->disp, base->id,
1536                                disp->sync->bo.offset, &base->chan);
1537         if (ret)
1538                 return ret;
1539
1540         return nvif_notify_init(&base->chan.base.base.user, nv50_base_notify,
1541                                 false,
1542                                 NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT,
1543                                 &(struct nvif_notify_uevent_req) {},
1544                                 sizeof(struct nvif_notify_uevent_req),
1545                                 sizeof(struct nvif_notify_uevent_rep),
1546                                 &base->wndw.notify);
1547 }
1548
1549 /******************************************************************************
1550  * Head
1551  *****************************************************************************/
1552 static void
1553 nv50_head_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
1554 {
1555         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1556         u32 *push;
1557         if ((push = evo_wait(core, 2))) {
1558                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1559                         evo_mthd(push, 0x08a8 + (head->base.index * 0x400), 1);
1560                 else
1561                         evo_mthd(push, 0x0498 + (head->base.index * 0x300), 1);
1562                 evo_data(push, (asyh->procamp.sat.sin << 20) |
1563                                (asyh->procamp.sat.cos << 8));
1564                 evo_kick(push, core);
1565         }
1566 }
1567
1568 static void
1569 nv50_head_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
1570 {
1571         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1572         u32 *push;
1573         if ((push = evo_wait(core, 2))) {
1574                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1575                         evo_mthd(push, 0x08a0 + (head->base.index * 0x0400), 1);
1576                 else
1577                 if (core->base.user.oclass < GK104_DISP_CORE_CHANNEL_DMA)
1578                         evo_mthd(push, 0x0490 + (head->base.index * 0x0300), 1);
1579                 else
1580                         evo_mthd(push, 0x04a0 + (head->base.index * 0x0300), 1);
1581                 evo_data(push, (asyh->dither.mode << 3) |
1582                                (asyh->dither.bits << 1) |
1583                                 asyh->dither.enable);
1584                 evo_kick(push, core);
1585         }
1586 }
1587
1588 static void
1589 nv50_head_ovly(struct nv50_head *head, struct nv50_head_atom *asyh)
1590 {
1591         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1592         u32 bounds = 0;
1593         u32 *push;
1594
1595         if (asyh->base.cpp) {
1596                 switch (asyh->base.cpp) {
1597                 case 8: bounds |= 0x00000500; break;
1598                 case 4: bounds |= 0x00000300; break;
1599                 case 2: bounds |= 0x00000100; break;
1600                 default:
1601                         WARN_ON(1);
1602                         break;
1603                 }
1604                 bounds |= 0x00000001;
1605         }
1606
1607         if ((push = evo_wait(core, 2))) {
1608                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1609                         evo_mthd(push, 0x0904 + head->base.index * 0x400, 1);
1610                 else
1611                         evo_mthd(push, 0x04d4 + head->base.index * 0x300, 1);
1612                 evo_data(push, bounds);
1613                 evo_kick(push, core);
1614         }
1615 }
1616
1617 static void
1618 nv50_head_base(struct nv50_head *head, struct nv50_head_atom *asyh)
1619 {
1620         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1621         u32 bounds = 0;
1622         u32 *push;
1623
1624         if (asyh->base.cpp) {
1625                 switch (asyh->base.cpp) {
1626                 case 8: bounds |= 0x00000500; break;
1627                 case 4: bounds |= 0x00000300; break;
1628                 case 2: bounds |= 0x00000100; break;
1629                 case 1: bounds |= 0x00000000; break;
1630                 default:
1631                         WARN_ON(1);
1632                         break;
1633                 }
1634                 bounds |= 0x00000001;
1635         }
1636
1637         if ((push = evo_wait(core, 2))) {
1638                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1639                         evo_mthd(push, 0x0900 + head->base.index * 0x400, 1);
1640                 else
1641                         evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1);
1642                 evo_data(push, bounds);
1643                 evo_kick(push, core);
1644         }
1645 }
1646
1647 static void
1648 nv50_head_curs_clr(struct nv50_head *head)
1649 {
1650         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1651         u32 *push;
1652         if ((push = evo_wait(core, 4))) {
1653                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1654                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
1655                         evo_data(push, 0x05000000);
1656                 } else
1657                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1658                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
1659                         evo_data(push, 0x05000000);
1660                         evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
1661                         evo_data(push, 0x00000000);
1662                 } else {
1663                         evo_mthd(push, 0x0480 + head->base.index * 0x300, 1);
1664                         evo_data(push, 0x05000000);
1665                         evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
1666                         evo_data(push, 0x00000000);
1667                 }
1668                 evo_kick(push, core);
1669         }
1670 }
1671
1672 static void
1673 nv50_head_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1674 {
1675         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1676         u32 *push;
1677         if ((push = evo_wait(core, 5))) {
1678                 if (core->base.user.oclass < G82_DISP_BASE_CHANNEL_DMA) {
1679                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
1680                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1681                                                     (asyh->curs.format << 24));
1682                         evo_data(push, asyh->curs.offset >> 8);
1683                 } else
1684                 if (core->base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA) {
1685                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
1686                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1687                                                     (asyh->curs.format << 24));
1688                         evo_data(push, asyh->curs.offset >> 8);
1689                         evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
1690                         evo_data(push, asyh->curs.handle);
1691                 } else {
1692                         evo_mthd(push, 0x0480 + head->base.index * 0x300, 2);
1693                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1694                                                     (asyh->curs.format << 24));
1695                         evo_data(push, asyh->curs.offset >> 8);
1696                         evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
1697                         evo_data(push, asyh->curs.handle);
1698                 }
1699                 evo_kick(push, core);
1700         }
1701 }
1702
1703 static void
1704 nv50_head_core_clr(struct nv50_head *head)
1705 {
1706         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1707         u32 *push;
1708         if ((push = evo_wait(core, 2))) {
1709                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1710                         evo_mthd(push, 0x0874 + head->base.index * 0x400, 1);
1711                 else
1712                         evo_mthd(push, 0x0474 + head->base.index * 0x300, 1);
1713                 evo_data(push, 0x00000000);
1714                 evo_kick(push, core);
1715         }
1716 }
1717
1718 static void
1719 nv50_head_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1720 {
1721         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1722         u32 *push;
1723         if ((push = evo_wait(core, 9))) {
1724                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1725                         evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
1726                         evo_data(push, asyh->core.offset >> 8);
1727                         evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
1728                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1729                         evo_data(push, asyh->core.layout << 20 |
1730                                        (asyh->core.pitch >> 8) << 8 |
1731                                        asyh->core.block);
1732                         evo_data(push, asyh->core.kind << 16 |
1733                                        asyh->core.format << 8);
1734                         evo_data(push, asyh->core.handle);
1735                         evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
1736                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1737                         /* EVO will complain with INVALID_STATE if we have an
1738                          * active cursor and (re)specify HeadSetContextDmaIso
1739                          * without also updating HeadSetOffsetCursor.
1740                          */
1741                         asyh->set.curs = asyh->curs.visible;
1742                 } else
1743                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1744                         evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
1745                         evo_data(push, asyh->core.offset >> 8);
1746                         evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
1747                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1748                         evo_data(push, asyh->core.layout << 20 |
1749                                        (asyh->core.pitch >> 8) << 8 |
1750                                        asyh->core.block);
1751                         evo_data(push, asyh->core.format << 8);
1752                         evo_data(push, asyh->core.handle);
1753                         evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
1754                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1755                 } else {
1756                         evo_mthd(push, 0x0460 + head->base.index * 0x300, 1);
1757                         evo_data(push, asyh->core.offset >> 8);
1758                         evo_mthd(push, 0x0468 + head->base.index * 0x300, 4);
1759                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1760                         evo_data(push, asyh->core.layout << 24 |
1761                                        (asyh->core.pitch >> 8) << 8 |
1762                                        asyh->core.block);
1763                         evo_data(push, asyh->core.format << 8);
1764                         evo_data(push, asyh->core.handle);
1765                         evo_mthd(push, 0x04b0 + head->base.index * 0x300, 1);
1766                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1767                 }
1768                 evo_kick(push, core);
1769         }
1770 }
1771
1772 static void
1773 nv50_head_lut_clr(struct nv50_head *head)
1774 {
1775         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1776         u32 *push;
1777         if ((push = evo_wait(core, 4))) {
1778                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1779                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
1780                         evo_data(push, 0x40000000);
1781                 } else
1782                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1783                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
1784                         evo_data(push, 0x40000000);
1785                         evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
1786                         evo_data(push, 0x00000000);
1787                 } else {
1788                         evo_mthd(push, 0x0440 + (head->base.index * 0x300), 1);
1789                         evo_data(push, 0x03000000);
1790                         evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
1791                         evo_data(push, 0x00000000);
1792                 }
1793                 evo_kick(push, core);
1794         }
1795 }
1796
1797 static void
1798 nv50_head_lut_load(struct drm_property_blob *blob, int mode,
1799                    struct nouveau_bo *nvbo)
1800 {
1801         struct drm_color_lut *in = (struct drm_color_lut *)blob->data;
1802         void __iomem *lut = (u8 *)nvbo_kmap_obj_iovirtual(nvbo);
1803         const int size = blob->length / sizeof(*in);
1804         int bits, shift, i;
1805         u16 zero, r, g, b;
1806
1807         /* This can't happen.. But it shuts the compiler up. */
1808         if (WARN_ON(size != 256))
1809                 return;
1810
1811         switch (mode) {
1812         case 0: /* LORES. */
1813         case 1: /* HIRES. */
1814                 bits = 11;
1815                 shift = 3;
1816                 zero = 0x0000;
1817                 break;
1818         case 7: /* INTERPOLATE_257_UNITY_RANGE. */
1819                 bits = 14;
1820                 shift = 0;
1821                 zero = 0x6000;
1822                 break;
1823         default:
1824                 WARN_ON(1);
1825                 return;
1826         }
1827
1828         for (i = 0; i < size; i++) {
1829                 r = (drm_color_lut_extract(in[i].  red, bits) + zero) << shift;
1830                 g = (drm_color_lut_extract(in[i].green, bits) + zero) << shift;
1831                 b = (drm_color_lut_extract(in[i]. blue, bits) + zero) << shift;
1832                 writew(r, lut + (i * 0x08) + 0);
1833                 writew(g, lut + (i * 0x08) + 2);
1834                 writew(b, lut + (i * 0x08) + 4);
1835         }
1836
1837         /* INTERPOLATE modes require a "next" entry to interpolate with,
1838          * so we replicate the last entry to deal with this for now.
1839          */
1840         writew(r, lut + (i * 0x08) + 0);
1841         writew(g, lut + (i * 0x08) + 2);
1842         writew(b, lut + (i * 0x08) + 4);
1843 }
1844
1845 static void
1846 nv50_head_lut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1847 {
1848         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1849         u32 *push;
1850         if ((push = evo_wait(core, 7))) {
1851                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1852                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1853                         evo_data(push, 0x80000000 | asyh->lut.mode << 30);
1854                         evo_data(push, asyh->lut.offset >> 8);
1855                 } else
1856                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1857                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1858                         evo_data(push, 0x80000000 | asyh->lut.mode << 30);
1859                         evo_data(push, asyh->lut.offset >> 8);
1860                         evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
1861                         evo_data(push, asyh->lut.handle);
1862                 } else {
1863                         evo_mthd(push, 0x0440 + (head->base.index * 0x300), 4);
1864                         evo_data(push, 0x80000000 | asyh->lut.mode << 24);
1865                         evo_data(push, asyh->lut.offset >> 8);
1866                         evo_data(push, 0x00000000);
1867                         evo_data(push, 0x00000000);
1868                         evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
1869                         evo_data(push, asyh->lut.handle);
1870                 }
1871                 evo_kick(push, core);
1872         }
1873 }
1874
1875 static void
1876 nv50_head_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
1877 {
1878         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1879         struct nv50_head_mode *m = &asyh->mode;
1880         u32 *push;
1881         if ((push = evo_wait(core, 14))) {
1882                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1883                         evo_mthd(push, 0x0804 + (head->base.index * 0x400), 2);
1884                         evo_data(push, 0x00800000 | m->clock);
1885                         evo_data(push, m->interlace ? 0x00000002 : 0x00000000);
1886                         evo_mthd(push, 0x0810 + (head->base.index * 0x400), 7);
1887                         evo_data(push, 0x00000000);
1888                         evo_data(push, (m->v.active  << 16) | m->h.active );
1889                         evo_data(push, (m->v.synce   << 16) | m->h.synce  );
1890                         evo_data(push, (m->v.blanke  << 16) | m->h.blanke );
1891                         evo_data(push, (m->v.blanks  << 16) | m->h.blanks );
1892                         evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1893                         evo_data(push, asyh->mode.v.blankus);
1894                         evo_mthd(push, 0x082c + (head->base.index * 0x400), 1);
1895                         evo_data(push, 0x00000000);
1896                 } else {
1897                         evo_mthd(push, 0x0410 + (head->base.index * 0x300), 6);
1898                         evo_data(push, 0x00000000);
1899                         evo_data(push, (m->v.active  << 16) | m->h.active );
1900                         evo_data(push, (m->v.synce   << 16) | m->h.synce  );
1901                         evo_data(push, (m->v.blanke  << 16) | m->h.blanke );
1902                         evo_data(push, (m->v.blanks  << 16) | m->h.blanks );
1903                         evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1904                         evo_mthd(push, 0x042c + (head->base.index * 0x300), 2);
1905                         evo_data(push, 0x00000000); /* ??? */
1906                         evo_data(push, 0xffffff00);
1907                         evo_mthd(push, 0x0450 + (head->base.index * 0x300), 3);
1908                         evo_data(push, m->clock * 1000);
1909                         evo_data(push, 0x00200000); /* ??? */
1910                         evo_data(push, m->clock * 1000);
1911                 }
1912                 evo_kick(push, core);
1913         }
1914 }
1915
1916 static void
1917 nv50_head_view(struct nv50_head *head, struct nv50_head_atom *asyh)
1918 {
1919         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1920         u32 *push;
1921         if ((push = evo_wait(core, 10))) {
1922                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1923                         evo_mthd(push, 0x08a4 + (head->base.index * 0x400), 1);
1924                         evo_data(push, 0x00000000);
1925                         evo_mthd(push, 0x08c8 + (head->base.index * 0x400), 1);
1926                         evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1927                         evo_mthd(push, 0x08d8 + (head->base.index * 0x400), 2);
1928                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1929                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1930                 } else {
1931                         evo_mthd(push, 0x0494 + (head->base.index * 0x300), 1);
1932                         evo_data(push, 0x00000000);
1933                         evo_mthd(push, 0x04b8 + (head->base.index * 0x300), 1);
1934                         evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1935                         evo_mthd(push, 0x04c0 + (head->base.index * 0x300), 3);
1936                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1937                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1938                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1939                 }
1940                 evo_kick(push, core);
1941         }
1942 }
1943
1944 static void
1945 nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool y)
1946 {
1947         if (asyh->clr.ilut && (!asyh->set.ilut || y))
1948                 nv50_head_lut_clr(head);
1949         if (asyh->clr.core && (!asyh->set.core || y))
1950                 nv50_head_core_clr(head);
1951         if (asyh->clr.curs && (!asyh->set.curs || y))
1952                 nv50_head_curs_clr(head);
1953 }
1954
1955 static void
1956 nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1957 {
1958         if (asyh->set.view   ) nv50_head_view    (head, asyh);
1959         if (asyh->set.mode   ) nv50_head_mode    (head, asyh);
1960         if (asyh->set.ilut   ) {
1961                 struct nouveau_bo *nvbo = head->lut.nvbo[head->lut.next];
1962                 struct drm_property_blob *blob = asyh->state.gamma_lut;
1963                 if (blob)
1964                         nv50_head_lut_load(blob, asyh->lut.mode, nvbo);
1965                 asyh->lut.offset = nvbo->bo.offset;
1966                 head->lut.next ^= 1;
1967                 nv50_head_lut_set(head, asyh);
1968         }
1969         if (asyh->set.core   ) nv50_head_core_set(head, asyh);
1970         if (asyh->set.curs   ) nv50_head_curs_set(head, asyh);
1971         if (asyh->set.base   ) nv50_head_base    (head, asyh);
1972         if (asyh->set.ovly   ) nv50_head_ovly    (head, asyh);
1973         if (asyh->set.dither ) nv50_head_dither  (head, asyh);
1974         if (asyh->set.procamp) nv50_head_procamp (head, asyh);
1975 }
1976
1977 static void
1978 nv50_head_atomic_check_procamp(struct nv50_head_atom *armh,
1979                                struct nv50_head_atom *asyh,
1980                                struct nouveau_conn_atom *asyc)
1981 {
1982         const int vib = asyc->procamp.color_vibrance - 100;
1983         const int hue = asyc->procamp.vibrant_hue - 90;
1984         const int adj = (vib > 0) ? 50 : 0;
1985         asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff;
1986         asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff;
1987         asyh->set.procamp = true;
1988 }
1989
1990 static void
1991 nv50_head_atomic_check_dither(struct nv50_head_atom *armh,
1992                               struct nv50_head_atom *asyh,
1993                               struct nouveau_conn_atom *asyc)
1994 {
1995         struct drm_connector *connector = asyc->state.connector;
1996         u32 mode = 0x00;
1997
1998         if (asyc->dither.mode == DITHERING_MODE_AUTO) {
1999                 if (asyh->base.depth > connector->display_info.bpc * 3)
2000                         mode = DITHERING_MODE_DYNAMIC2X2;
2001         } else {
2002                 mode = asyc->dither.mode;
2003         }
2004
2005         if (asyc->dither.depth == DITHERING_DEPTH_AUTO) {
2006                 if (connector->display_info.bpc >= 8)
2007                         mode |= DITHERING_DEPTH_8BPC;
2008         } else {
2009                 mode |= asyc->dither.depth;
2010         }
2011
2012         asyh->dither.enable = mode;
2013         asyh->dither.bits = mode >> 1;
2014         asyh->dither.mode = mode >> 3;
2015         asyh->set.dither = true;
2016 }
2017
2018 static void
2019 nv50_head_atomic_check_view(struct nv50_head_atom *armh,
2020                             struct nv50_head_atom *asyh,
2021                             struct nouveau_conn_atom *asyc)
2022 {
2023         struct drm_connector *connector = asyc->state.connector;
2024         struct drm_display_mode *omode = &asyh->state.adjusted_mode;
2025         struct drm_display_mode *umode = &asyh->state.mode;
2026         int mode = asyc->scaler.mode;
2027         struct edid *edid;
2028         int umode_vdisplay, omode_hdisplay, omode_vdisplay;
2029
2030         if (connector->edid_blob_ptr)
2031                 edid = (struct edid *)connector->edid_blob_ptr->data;
2032         else
2033                 edid = NULL;
2034
2035         if (!asyc->scaler.full) {
2036                 if (mode == DRM_MODE_SCALE_NONE)
2037                         omode = umode;
2038         } else {
2039                 /* Non-EDID LVDS/eDP mode. */
2040                 mode = DRM_MODE_SCALE_FULLSCREEN;
2041         }
2042
2043         /* For the user-specified mode, we must ignore doublescan and
2044          * the like, but honor frame packing.
2045          */
2046         umode_vdisplay = umode->vdisplay;
2047         if ((umode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2048                 umode_vdisplay += umode->vtotal;
2049         asyh->view.iW = umode->hdisplay;
2050         asyh->view.iH = umode_vdisplay;
2051         /* For the output mode, we can just use the stock helper. */
2052         drm_mode_get_hv_timing(omode, &omode_hdisplay, &omode_vdisplay);
2053         asyh->view.oW = omode_hdisplay;
2054         asyh->view.oH = omode_vdisplay;
2055
2056         /* Add overscan compensation if necessary, will keep the aspect
2057          * ratio the same as the backend mode unless overridden by the
2058          * user setting both hborder and vborder properties.
2059          */
2060         if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
2061             (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
2062              drm_detect_hdmi_monitor(edid)))) {
2063                 u32 bX = asyc->scaler.underscan.hborder;
2064                 u32 bY = asyc->scaler.underscan.vborder;
2065                 u32 r = (asyh->view.oH << 19) / asyh->view.oW;
2066
2067                 if (bX) {
2068                         asyh->view.oW -= (bX * 2);
2069                         if (bY) asyh->view.oH -= (bY * 2);
2070                         else    asyh->view.oH  = ((asyh->view.oW * r) + (r / 2)) >> 19;
2071                 } else {
2072                         asyh->view.oW -= (asyh->view.oW >> 4) + 32;
2073                         if (bY) asyh->view.oH -= (bY * 2);
2074                         else    asyh->view.oH  = ((asyh->view.oW * r) + (r / 2)) >> 19;
2075                 }
2076         }
2077
2078         /* Handle CENTER/ASPECT scaling, taking into account the areas
2079          * removed already for overscan compensation.
2080          */
2081         switch (mode) {
2082         case DRM_MODE_SCALE_CENTER:
2083                 asyh->view.oW = min((u16)umode->hdisplay, asyh->view.oW);
2084                 asyh->view.oH = min((u16)umode_vdisplay, asyh->view.oH);
2085                 /* fall-through */
2086         case DRM_MODE_SCALE_ASPECT:
2087                 if (asyh->view.oH < asyh->view.oW) {
2088                         u32 r = (asyh->view.iW << 19) / asyh->view.iH;
2089                         asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
2090                 } else {
2091                         u32 r = (asyh->view.iH << 19) / asyh->view.iW;
2092                         asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
2093                 }
2094                 break;
2095         default:
2096                 break;
2097         }
2098
2099         asyh->set.view = true;
2100 }
2101
2102 static void
2103 nv50_head_atomic_check_lut(struct nv50_head *head,
2104                            struct nv50_head_atom *armh,
2105                            struct nv50_head_atom *asyh)
2106 {
2107         struct nv50_disp *disp = nv50_disp(head->base.base.dev);
2108
2109         /* An I8 surface without an input LUT makes no sense, and
2110          * EVO will throw an error if you try.
2111          *
2112          * Legacy clients actually cause this due to the order in
2113          * which they call ioctls, so we will enable the LUT with
2114          * whatever contents the buffer already contains to avoid
2115          * triggering the error check.
2116          */
2117         if (!asyh->state.gamma_lut && asyh->base.cpp != 1) {
2118                 asyh->lut.handle = 0;
2119                 asyh->clr.ilut = armh->lut.visible;
2120                 return;
2121         }
2122
2123         if (disp->disp->oclass < GF110_DISP) {
2124                 asyh->lut.mode = (asyh->base.cpp == 1) ? 0 : 1;
2125                 asyh->set.ilut = true;
2126         } else {
2127                 asyh->lut.mode = 7;
2128                 asyh->set.ilut = asyh->state.color_mgmt_changed;
2129         }
2130         asyh->lut.handle = disp->mast.base.vram.handle;
2131 }
2132
2133 static void
2134 nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
2135 {
2136         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
2137         struct nv50_head_mode *m = &asyh->mode;
2138         u32 blankus;
2139
2140         drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
2141
2142         /*
2143          * DRM modes are defined in terms of a repeating interval
2144          * starting with the active display area.  The hardware modes
2145          * are defined in terms of a repeating interval starting one
2146          * unit (pixel or line) into the sync pulse.  So, add bias.
2147          */
2148
2149         m->h.active = mode->crtc_htotal;
2150         m->h.synce  = mode->crtc_hsync_end - mode->crtc_hsync_start - 1;
2151         m->h.blanke = mode->crtc_hblank_end - mode->crtc_hsync_start - 1;
2152         m->h.blanks = m->h.blanke + mode->crtc_hdisplay;
2153
2154         m->v.active = mode->crtc_vtotal;
2155         m->v.synce  = mode->crtc_vsync_end - mode->crtc_vsync_start - 1;
2156         m->v.blanke = mode->crtc_vblank_end - mode->crtc_vsync_start - 1;
2157         m->v.blanks = m->v.blanke + mode->crtc_vdisplay;
2158
2159         /*XXX: Safe underestimate, even "0" works */
2160         blankus = (m->v.active - mode->crtc_vdisplay - 2) * m->h.active;
2161         blankus *= 1000;
2162         blankus /= mode->crtc_clock;
2163         m->v.blankus = blankus;
2164
2165         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2166                 m->v.blank2e =  m->v.active + m->v.blanke;
2167                 m->v.blank2s =  m->v.blank2e + mode->crtc_vdisplay;
2168                 m->v.active  = (m->v.active * 2) + 1;
2169                 m->interlace = true;
2170         } else {
2171                 m->v.blank2e = 0;
2172                 m->v.blank2s = 1;
2173                 m->interlace = false;
2174         }
2175         m->clock = mode->crtc_clock;
2176
2177         asyh->set.mode = true;
2178 }
2179
2180 static int
2181 nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
2182 {
2183         struct nouveau_drm *drm = nouveau_drm(crtc->dev);
2184         struct nv50_disp *disp = nv50_disp(crtc->dev);
2185         struct nv50_head *head = nv50_head(crtc);
2186         struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
2187         struct nv50_head_atom *asyh = nv50_head_atom(state);
2188         struct nouveau_conn_atom *asyc = NULL;
2189         struct drm_connector_state *conns;
2190         struct drm_connector *conn;
2191         int i;
2192
2193         NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
2194         if (asyh->state.active) {
2195                 for_each_new_connector_in_state(asyh->state.state, conn, conns, i) {
2196                         if (conns->crtc == crtc) {
2197                                 asyc = nouveau_conn_atom(conns);
2198                                 break;
2199                         }
2200                 }
2201
2202                 if (armh->state.active) {
2203                         if (asyc) {
2204                                 if (asyh->state.mode_changed)
2205                                         asyc->set.scaler = true;
2206                                 if (armh->base.depth != asyh->base.depth)
2207                                         asyc->set.dither = true;
2208                         }
2209                 } else {
2210                         if (asyc)
2211                                 asyc->set.mask = ~0;
2212                         asyh->set.mask = ~0;
2213                 }
2214
2215                 if (asyh->state.mode_changed)
2216                         nv50_head_atomic_check_mode(head, asyh);
2217
2218                 if (asyh->state.color_mgmt_changed ||
2219                     asyh->base.cpp != armh->base.cpp)
2220                         nv50_head_atomic_check_lut(head, armh, asyh);
2221                 asyh->lut.visible = asyh->lut.handle != 0;
2222
2223                 if (asyc) {
2224                         if (asyc->set.scaler)
2225                                 nv50_head_atomic_check_view(armh, asyh, asyc);
2226                         if (asyc->set.dither)
2227                                 nv50_head_atomic_check_dither(armh, asyh, asyc);
2228                         if (asyc->set.procamp)
2229                                 nv50_head_atomic_check_procamp(armh, asyh, asyc);
2230                 }
2231
2232                 if ((asyh->core.visible = (asyh->base.cpp != 0))) {
2233                         asyh->core.x = asyh->base.x;
2234                         asyh->core.y = asyh->base.y;
2235                         asyh->core.w = asyh->base.w;
2236                         asyh->core.h = asyh->base.h;
2237                 } else
2238                 if ((asyh->core.visible = asyh->curs.visible) ||
2239                     (asyh->core.visible = asyh->lut.visible)) {
2240                         /*XXX: We need to either find some way of having the
2241                          *     primary base layer appear black, while still
2242                          *     being able to display the other layers, or we
2243                          *     need to allocate a dummy black surface here.
2244                          */
2245                         asyh->core.x = 0;
2246                         asyh->core.y = 0;
2247                         asyh->core.w = asyh->state.mode.hdisplay;
2248                         asyh->core.h = asyh->state.mode.vdisplay;
2249                 }
2250                 asyh->core.handle = disp->mast.base.vram.handle;
2251                 asyh->core.offset = 0;
2252                 asyh->core.format = 0xcf;
2253                 asyh->core.kind = 0;
2254                 asyh->core.layout = 1;
2255                 asyh->core.block = 0;
2256                 asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4;
2257                 asyh->set.base = armh->base.cpp != asyh->base.cpp;
2258                 asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
2259         } else {
2260                 asyh->lut.visible = false;
2261                 asyh->core.visible = false;
2262                 asyh->curs.visible = false;
2263                 asyh->base.cpp = 0;
2264                 asyh->ovly.cpp = 0;
2265         }
2266
2267         if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
2268                 if (asyh->core.visible) {
2269                         if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
2270                                 asyh->set.core = true;
2271                 } else
2272                 if (armh->core.visible) {
2273                         asyh->clr.core = true;
2274                 }
2275
2276                 if (asyh->curs.visible) {
2277                         if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))
2278                                 asyh->set.curs = true;
2279                 } else
2280                 if (armh->curs.visible) {
2281                         asyh->clr.curs = true;
2282                 }
2283         } else {
2284                 asyh->clr.ilut = armh->lut.visible;
2285                 asyh->clr.core = armh->core.visible;
2286                 asyh->clr.curs = armh->curs.visible;
2287                 asyh->set.ilut = asyh->lut.visible;
2288                 asyh->set.core = asyh->core.visible;
2289                 asyh->set.curs = asyh->curs.visible;
2290         }
2291
2292         if (asyh->clr.mask || asyh->set.mask)
2293                 nv50_atom(asyh->state.state)->lock_core = true;
2294         return 0;
2295 }
2296
2297 static const struct drm_crtc_helper_funcs
2298 nv50_head_help = {
2299         .atomic_check = nv50_head_atomic_check,
2300 };
2301
2302 static void
2303 nv50_head_atomic_destroy_state(struct drm_crtc *crtc,
2304                                struct drm_crtc_state *state)
2305 {
2306         struct nv50_head_atom *asyh = nv50_head_atom(state);
2307         __drm_atomic_helper_crtc_destroy_state(&asyh->state);
2308         kfree(asyh);
2309 }
2310
2311 static struct drm_crtc_state *
2312 nv50_head_atomic_duplicate_state(struct drm_crtc *crtc)
2313 {
2314         struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
2315         struct nv50_head_atom *asyh;
2316         if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL)))
2317                 return NULL;
2318         __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state);
2319         asyh->view = armh->view;
2320         asyh->mode = armh->mode;
2321         asyh->lut  = armh->lut;
2322         asyh->core = armh->core;
2323         asyh->curs = armh->curs;
2324         asyh->base = armh->base;
2325         asyh->ovly = armh->ovly;
2326         asyh->dither = armh->dither;
2327         asyh->procamp = armh->procamp;
2328         asyh->clr.mask = 0;
2329         asyh->set.mask = 0;
2330         return &asyh->state;
2331 }
2332
2333 static void
2334 __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc,
2335                                struct drm_crtc_state *state)
2336 {
2337         if (crtc->state)
2338                 crtc->funcs->atomic_destroy_state(crtc, crtc->state);
2339         crtc->state = state;
2340         crtc->state->crtc = crtc;
2341 }
2342
2343 static void
2344 nv50_head_reset(struct drm_crtc *crtc)
2345 {
2346         struct nv50_head_atom *asyh;
2347
2348         if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL))))
2349                 return;
2350
2351         __drm_atomic_helper_crtc_reset(crtc, &asyh->state);
2352 }
2353
2354 static void
2355 nv50_head_destroy(struct drm_crtc *crtc)
2356 {
2357         struct nv50_disp *disp = nv50_disp(crtc->dev);
2358         struct nv50_head *head = nv50_head(crtc);
2359         int i;
2360
2361         nv50_dmac_destroy(&head->ovly.base, disp->disp);
2362         nv50_pioc_destroy(&head->oimm.base);
2363
2364         for (i = 0; i < ARRAY_SIZE(head->lut.nvbo); i++)
2365                 nouveau_bo_unmap_unpin_unref(&head->lut.nvbo[i]);
2366
2367         drm_crtc_cleanup(crtc);
2368         kfree(crtc);
2369 }
2370
2371 static const struct drm_crtc_funcs
2372 nv50_head_func = {
2373         .reset = nv50_head_reset,
2374         .gamma_set = drm_atomic_helper_legacy_gamma_set,
2375         .destroy = nv50_head_destroy,
2376         .set_config = drm_atomic_helper_set_config,
2377         .page_flip = drm_atomic_helper_page_flip,
2378         .atomic_duplicate_state = nv50_head_atomic_duplicate_state,
2379         .atomic_destroy_state = nv50_head_atomic_destroy_state,
2380 };
2381
2382 static int
2383 nv50_head_create(struct drm_device *dev, int index)
2384 {
2385         struct nouveau_drm *drm = nouveau_drm(dev);
2386         struct nvif_device *device = &drm->client.device;
2387         struct nv50_disp *disp = nv50_disp(dev);
2388         struct nv50_head *head;
2389         struct nv50_base *base;
2390         struct nv50_curs *curs;
2391         struct drm_crtc *crtc;
2392         int ret, i;
2393
2394         head = kzalloc(sizeof(*head), GFP_KERNEL);
2395         if (!head)
2396                 return -ENOMEM;
2397
2398         head->base.index = index;
2399         ret = nv50_base_new(drm, head, &base);
2400         if (ret == 0)
2401                 ret = nv50_curs_new(drm, head, &curs);
2402         if (ret) {
2403                 kfree(head);
2404                 return ret;
2405         }
2406
2407         crtc = &head->base.base;
2408         drm_crtc_init_with_planes(dev, crtc, &base->wndw.plane,
2409                                   &curs->wndw.plane, &nv50_head_func,
2410                                   "head-%d", head->base.index);
2411         drm_crtc_helper_add(crtc, &nv50_head_help);
2412         drm_mode_crtc_set_gamma_size(crtc, 256);
2413
2414         for (i = 0; i < ARRAY_SIZE(head->lut.nvbo); i++) {
2415                 ret = nouveau_bo_new_pin_map(&drm->client, 1025 * 8, 0x100,
2416                                              TTM_PL_FLAG_VRAM,
2417                                              &head->lut.nvbo[i]);
2418                 if (ret)
2419                         goto out;
2420         }
2421
2422         /* allocate overlay resources */
2423         ret = nv50_oimm_create(device, disp->disp, index, &head->oimm);
2424         if (ret)
2425                 goto out;
2426
2427         ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset,
2428                                &head->ovly);
2429         if (ret)
2430                 goto out;
2431
2432 out:
2433         if (ret)
2434                 nv50_head_destroy(crtc);
2435         return ret;
2436 }
2437
2438 /******************************************************************************
2439  * Output path helpers
2440  *****************************************************************************/
2441 static void
2442 nv50_outp_release(struct nouveau_encoder *nv_encoder)
2443 {
2444         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
2445         struct {
2446                 struct nv50_disp_mthd_v1 base;
2447         } args = {
2448                 .base.version = 1,
2449                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
2450                 .base.hasht  = nv_encoder->dcb->hasht,
2451                 .base.hashm  = nv_encoder->dcb->hashm,
2452         };
2453
2454         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2455         nv_encoder->or = -1;
2456         nv_encoder->link = 0;
2457 }
2458
2459 static int
2460 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
2461 {
2462         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
2463         struct nv50_disp *disp = nv50_disp(drm->dev);
2464         struct {
2465                 struct nv50_disp_mthd_v1 base;
2466                 struct nv50_disp_acquire_v0 info;
2467         } args = {
2468                 .base.version = 1,
2469                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
2470                 .base.hasht  = nv_encoder->dcb->hasht,
2471                 .base.hashm  = nv_encoder->dcb->hashm,
2472         };
2473         int ret;
2474
2475         ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
2476         if (ret) {
2477                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
2478                 return ret;
2479         }
2480
2481         nv_encoder->or = args.info.or;
2482         nv_encoder->link = args.info.link;
2483         return 0;
2484 }
2485
2486 static int
2487 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
2488                             struct drm_crtc_state *crtc_state,
2489                             struct drm_connector_state *conn_state,
2490                             struct drm_display_mode *native_mode)
2491 {
2492         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
2493         struct drm_display_mode *mode = &crtc_state->mode;
2494         struct drm_connector *connector = conn_state->connector;
2495         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
2496         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
2497
2498         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
2499         asyc->scaler.full = false;
2500         if (!native_mode)
2501                 return 0;
2502
2503         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
2504                 switch (connector->connector_type) {
2505                 case DRM_MODE_CONNECTOR_LVDS:
2506                 case DRM_MODE_CONNECTOR_eDP:
2507                         /* Force use of scaler for non-EDID modes. */
2508                         if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
2509                                 break;
2510                         mode = native_mode;
2511                         asyc->scaler.full = true;
2512                         break;
2513                 default:
2514                         break;
2515                 }
2516         } else {
2517                 mode = native_mode;
2518         }
2519
2520         if (!drm_mode_equal(adjusted_mode, mode)) {
2521                 drm_mode_copy(adjusted_mode, mode);
2522                 crtc_state->mode_changed = true;
2523         }
2524
2525         return 0;
2526 }
2527
2528 static int
2529 nv50_outp_atomic_check(struct drm_encoder *encoder,
2530                        struct drm_crtc_state *crtc_state,
2531                        struct drm_connector_state *conn_state)
2532 {
2533         struct nouveau_connector *nv_connector =
2534                 nouveau_connector(conn_state->connector);
2535         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
2536                                            nv_connector->native_mode);
2537 }
2538
2539 /******************************************************************************
2540  * DAC
2541  *****************************************************************************/
2542 static void
2543 nv50_dac_disable(struct drm_encoder *encoder)
2544 {
2545         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2546         struct nv50_mast *mast = nv50_mast(encoder->dev);
2547         const int or = nv_encoder->or;
2548         u32 *push;
2549
2550         if (nv_encoder->crtc) {
2551                 push = evo_wait(mast, 4);
2552                 if (push) {
2553                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2554                                 evo_mthd(push, 0x0400 + (or * 0x080), 1);
2555                                 evo_data(push, 0x00000000);
2556                         } else {
2557                                 evo_mthd(push, 0x0180 + (or * 0x020), 1);
2558                                 evo_data(push, 0x00000000);
2559                         }
2560                         evo_kick(push, mast);
2561                 }
2562         }
2563
2564         nv_encoder->crtc = NULL;
2565         nv50_outp_release(nv_encoder);
2566 }
2567
2568 static void
2569 nv50_dac_enable(struct drm_encoder *encoder)
2570 {
2571         struct nv50_mast *mast = nv50_mast(encoder->dev);
2572         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2573         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2574         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
2575         u32 *push;
2576
2577         nv50_outp_acquire(nv_encoder);
2578
2579         push = evo_wait(mast, 8);
2580         if (push) {
2581                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2582                         u32 syncs = 0x00000000;
2583
2584                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2585                                 syncs |= 0x00000001;
2586                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2587                                 syncs |= 0x00000002;
2588
2589                         evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
2590                         evo_data(push, 1 << nv_crtc->index);
2591                         evo_data(push, syncs);
2592                 } else {
2593                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
2594                         u32 syncs = 0x00000001;
2595
2596                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2597                                 syncs |= 0x00000008;
2598                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2599                                 syncs |= 0x00000010;
2600
2601                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2602                                 magic |= 0x00000001;
2603
2604                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
2605                         evo_data(push, syncs);
2606                         evo_data(push, magic);
2607                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
2608                         evo_data(push, 1 << nv_crtc->index);
2609                 }
2610
2611                 evo_kick(push, mast);
2612         }
2613
2614         nv_encoder->crtc = encoder->crtc;
2615 }
2616
2617 static enum drm_connector_status
2618 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2619 {
2620         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2621         struct nv50_disp *disp = nv50_disp(encoder->dev);
2622         struct {
2623                 struct nv50_disp_mthd_v1 base;
2624                 struct nv50_disp_dac_load_v0 load;
2625         } args = {
2626                 .base.version = 1,
2627                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
2628                 .base.hasht  = nv_encoder->dcb->hasht,
2629                 .base.hashm  = nv_encoder->dcb->hashm,
2630         };
2631         int ret;
2632
2633         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
2634         if (args.load.data == 0)
2635                 args.load.data = 340;
2636
2637         ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
2638         if (ret || !args.load.load)
2639                 return connector_status_disconnected;
2640
2641         return connector_status_connected;
2642 }
2643
2644 static const struct drm_encoder_helper_funcs
2645 nv50_dac_help = {
2646         .atomic_check = nv50_outp_atomic_check,
2647         .enable = nv50_dac_enable,
2648         .disable = nv50_dac_disable,
2649         .detect = nv50_dac_detect
2650 };
2651
2652 static void
2653 nv50_dac_destroy(struct drm_encoder *encoder)
2654 {
2655         drm_encoder_cleanup(encoder);
2656         kfree(encoder);
2657 }
2658
2659 static const struct drm_encoder_funcs
2660 nv50_dac_func = {
2661         .destroy = nv50_dac_destroy,
2662 };
2663
2664 static int
2665 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
2666 {
2667         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2668         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
2669         struct nvkm_i2c_bus *bus;
2670         struct nouveau_encoder *nv_encoder;
2671         struct drm_encoder *encoder;
2672         int type = DRM_MODE_ENCODER_DAC;
2673
2674         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2675         if (!nv_encoder)
2676                 return -ENOMEM;
2677         nv_encoder->dcb = dcbe;
2678
2679         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
2680         if (bus)
2681                 nv_encoder->i2c = &bus->i2c;
2682
2683         encoder = to_drm_encoder(nv_encoder);
2684         encoder->possible_crtcs = dcbe->heads;
2685         encoder->possible_clones = 0;
2686         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
2687                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
2688         drm_encoder_helper_add(encoder, &nv50_dac_help);
2689
2690         drm_mode_connector_attach_encoder(connector, encoder);
2691         return 0;
2692 }
2693
2694 /******************************************************************************
2695  * Audio
2696  *****************************************************************************/
2697 static void
2698 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2699 {
2700         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2701         struct nv50_disp *disp = nv50_disp(encoder->dev);
2702         struct {
2703                 struct nv50_disp_mthd_v1 base;
2704                 struct nv50_disp_sor_hda_eld_v0 eld;
2705         } args = {
2706                 .base.version = 1,
2707                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2708                 .base.hasht   = nv_encoder->dcb->hasht,
2709                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
2710                                 (0x0100 << nv_crtc->index),
2711         };
2712
2713         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2714 }
2715
2716 static void
2717 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
2718 {
2719         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2720         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2721         struct nouveau_connector *nv_connector;
2722         struct nv50_disp *disp = nv50_disp(encoder->dev);
2723         struct __packed {
2724                 struct {
2725                         struct nv50_disp_mthd_v1 mthd;
2726                         struct nv50_disp_sor_hda_eld_v0 eld;
2727                 } base;
2728                 u8 data[sizeof(nv_connector->base.eld)];
2729         } args = {
2730                 .base.mthd.version = 1,
2731                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2732                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
2733                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
2734                                      (0x0100 << nv_crtc->index),
2735         };
2736
2737         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2738         if (!drm_detect_monitor_audio(nv_connector->edid))
2739                 return;
2740
2741         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
2742
2743         nvif_mthd(disp->disp, 0, &args,
2744                   sizeof(args.base) + drm_eld_size(args.data));
2745 }
2746
2747 /******************************************************************************
2748  * HDMI
2749  *****************************************************************************/
2750 static void
2751 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2752 {
2753         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2754         struct nv50_disp *disp = nv50_disp(encoder->dev);
2755         struct {
2756                 struct nv50_disp_mthd_v1 base;
2757                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2758         } args = {
2759                 .base.version = 1,
2760                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2761                 .base.hasht  = nv_encoder->dcb->hasht,
2762                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
2763                                (0x0100 << nv_crtc->index),
2764         };
2765
2766         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2767 }
2768
2769 static void
2770 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
2771 {
2772         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2773         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2774         struct nv50_disp *disp = nv50_disp(encoder->dev);
2775         struct {
2776                 struct nv50_disp_mthd_v1 base;
2777                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2778                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
2779         } args = {
2780                 .base.version = 1,
2781                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2782                 .base.hasht  = nv_encoder->dcb->hasht,
2783                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
2784                                (0x0100 << nv_crtc->index),
2785                 .pwr.state = 1,
2786                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
2787         };
2788         struct nouveau_connector *nv_connector;
2789         u32 max_ac_packet;
2790         union hdmi_infoframe avi_frame;
2791         union hdmi_infoframe vendor_frame;
2792         int ret;
2793         int size;
2794
2795         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2796         if (!drm_detect_hdmi_monitor(nv_connector->edid))
2797                 return;
2798
2799         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode,
2800                                                        false);
2801         if (!ret) {
2802                 /* We have an AVI InfoFrame, populate it to the display */
2803                 args.pwr.avi_infoframe_length
2804                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
2805         }
2806
2807         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
2808                                                           &nv_connector->base, mode);
2809         if (!ret) {
2810                 /* We have a Vendor InfoFrame, populate it to the display */
2811                 args.pwr.vendor_infoframe_length
2812                         = hdmi_infoframe_pack(&vendor_frame,
2813                                               args.infoframes
2814                                               + args.pwr.avi_infoframe_length,
2815                                               17);
2816         }
2817
2818         max_ac_packet  = mode->htotal - mode->hdisplay;
2819         max_ac_packet -= args.pwr.rekey;
2820         max_ac_packet -= 18; /* constant from tegra */
2821         args.pwr.max_ac_packet = max_ac_packet / 32;
2822
2823         size = sizeof(args.base)
2824                 + sizeof(args.pwr)
2825                 + args.pwr.avi_infoframe_length
2826                 + args.pwr.vendor_infoframe_length;
2827         nvif_mthd(disp->disp, 0, &args, size);
2828         nv50_audio_enable(encoder, mode);
2829 }
2830
2831 /******************************************************************************
2832  * MST
2833  *****************************************************************************/
2834 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
2835 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
2836 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
2837
2838 struct nv50_mstm {
2839         struct nouveau_encoder *outp;
2840
2841         struct drm_dp_mst_topology_mgr mgr;
2842         struct nv50_msto *msto[4];
2843
2844         bool modified;
2845         bool disabled;
2846         int links;
2847 };
2848
2849 struct nv50_mstc {
2850         struct nv50_mstm *mstm;
2851         struct drm_dp_mst_port *port;
2852         struct drm_connector connector;
2853
2854         struct drm_display_mode *native;
2855         struct edid *edid;
2856
2857         int pbn;
2858 };
2859
2860 struct nv50_msto {
2861         struct drm_encoder encoder;
2862
2863         struct nv50_head *head;
2864         struct nv50_mstc *mstc;
2865         bool disabled;
2866 };
2867
2868 static struct drm_dp_payload *
2869 nv50_msto_payload(struct nv50_msto *msto)
2870 {
2871         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2872         struct nv50_mstc *mstc = msto->mstc;
2873         struct nv50_mstm *mstm = mstc->mstm;
2874         int vcpi = mstc->port->vcpi.vcpi, i;
2875
2876         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
2877         for (i = 0; i < mstm->mgr.max_payloads; i++) {
2878                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
2879                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
2880                           mstm->outp->base.base.name, i, payload->vcpi,
2881                           payload->start_slot, payload->num_slots);
2882         }
2883
2884         for (i = 0; i < mstm->mgr.max_payloads; i++) {
2885                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
2886                 if (payload->vcpi == vcpi)
2887                         return payload;
2888         }
2889
2890         return NULL;
2891 }
2892
2893 static void
2894 nv50_msto_cleanup(struct nv50_msto *msto)
2895 {
2896         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2897         struct nv50_mstc *mstc = msto->mstc;
2898         struct nv50_mstm *mstm = mstc->mstm;
2899
2900         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
2901         if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
2902                 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
2903         if (msto->disabled) {
2904                 msto->mstc = NULL;
2905                 msto->head = NULL;
2906                 msto->disabled = false;
2907         }
2908 }
2909
2910 static void
2911 nv50_msto_prepare(struct nv50_msto *msto)
2912 {
2913         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2914         struct nv50_mstc *mstc = msto->mstc;
2915         struct nv50_mstm *mstm = mstc->mstm;
2916         struct {
2917                 struct nv50_disp_mthd_v1 base;
2918                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
2919         } args = {
2920                 .base.version = 1,
2921                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
2922                 .base.hasht  = mstm->outp->dcb->hasht,
2923                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
2924                                (0x0100 << msto->head->base.index),
2925         };
2926
2927         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
2928         if (mstc->port && mstc->port->vcpi.vcpi > 0) {
2929                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
2930                 if (payload) {
2931                         args.vcpi.start_slot = payload->start_slot;
2932                         args.vcpi.num_slots = payload->num_slots;
2933                         args.vcpi.pbn = mstc->port->vcpi.pbn;
2934                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
2935                 }
2936         }
2937
2938         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
2939                   msto->encoder.name, msto->head->base.base.name,
2940                   args.vcpi.start_slot, args.vcpi.num_slots,
2941                   args.vcpi.pbn, args.vcpi.aligned_pbn);
2942         nvif_mthd(&drm->display->disp, 0, &args, sizeof(args));
2943 }
2944
2945 static int
2946 nv50_msto_atomic_check(struct drm_encoder *encoder,
2947                        struct drm_crtc_state *crtc_state,
2948                        struct drm_connector_state *conn_state)
2949 {
2950         struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
2951         struct nv50_mstm *mstm = mstc->mstm;
2952         int bpp = conn_state->connector->display_info.bpc * 3;
2953         int slots;
2954
2955         mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
2956
2957         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
2958         if (slots < 0)
2959                 return slots;
2960
2961         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
2962                                            mstc->native);
2963 }
2964
2965 static void
2966 nv50_msto_enable(struct drm_encoder *encoder)
2967 {
2968         struct nv50_head *head = nv50_head(encoder->crtc);
2969         struct nv50_msto *msto = nv50_msto(encoder);
2970         struct nv50_mstc *mstc = NULL;
2971         struct nv50_mstm *mstm = NULL;
2972         struct drm_connector *connector;
2973         struct drm_connector_list_iter conn_iter;
2974         u8 proto, depth;
2975         int slots;
2976         bool r;
2977
2978         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
2979         drm_for_each_connector_iter(connector, &conn_iter) {
2980                 if (connector->state->best_encoder == &msto->encoder) {
2981                         mstc = nv50_mstc(connector);
2982                         mstm = mstc->mstm;
2983                         break;
2984                 }
2985         }
2986         drm_connector_list_iter_end(&conn_iter);
2987
2988         if (WARN_ON(!mstc))
2989                 return;
2990
2991         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
2992         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
2993         WARN_ON(!r);
2994
2995         if (!mstm->links++)
2996                 nv50_outp_acquire(mstm->outp);
2997
2998         if (mstm->outp->link & 1)
2999                 proto = 0x8;
3000         else
3001                 proto = 0x9;
3002
3003         switch (mstc->connector.display_info.bpc) {
3004         case  6: depth = 0x2; break;
3005         case  8: depth = 0x5; break;
3006         case 10:
3007         default: depth = 0x6; break;
3008         }
3009
3010         mstm->outp->update(mstm->outp, head->base.index,
3011                            &head->base.base.state->adjusted_mode, proto, depth);
3012
3013         msto->head = head;
3014         msto->mstc = mstc;
3015         mstm->modified = true;
3016 }
3017
3018 static void
3019 nv50_msto_disable(struct drm_encoder *encoder)
3020 {
3021         struct nv50_msto *msto = nv50_msto(encoder);
3022         struct nv50_mstc *mstc = msto->mstc;
3023         struct nv50_mstm *mstm = mstc->mstm;
3024
3025         if (mstc->port)
3026                 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
3027
3028         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
3029         mstm->modified = true;
3030         if (!--mstm->links)
3031                 mstm->disabled = true;
3032         msto->disabled = true;
3033 }
3034
3035 static const struct drm_encoder_helper_funcs
3036 nv50_msto_help = {
3037         .disable = nv50_msto_disable,
3038         .enable = nv50_msto_enable,
3039         .atomic_check = nv50_msto_atomic_check,
3040 };
3041
3042 static void
3043 nv50_msto_destroy(struct drm_encoder *encoder)
3044 {
3045         struct nv50_msto *msto = nv50_msto(encoder);
3046         drm_encoder_cleanup(&msto->encoder);
3047         kfree(msto);
3048 }
3049
3050 static const struct drm_encoder_funcs
3051 nv50_msto = {
3052         .destroy = nv50_msto_destroy,
3053 };
3054
3055 static int
3056 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
3057               struct nv50_msto **pmsto)
3058 {
3059         struct nv50_msto *msto;
3060         int ret;
3061
3062         if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
3063                 return -ENOMEM;
3064
3065         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
3066                                DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
3067         if (ret) {
3068                 kfree(*pmsto);
3069                 *pmsto = NULL;
3070                 return ret;
3071         }
3072
3073         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
3074         msto->encoder.possible_crtcs = heads;
3075         return 0;
3076 }
3077
3078 static struct drm_encoder *
3079 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
3080                               struct drm_connector_state *connector_state)
3081 {
3082         struct nv50_head *head = nv50_head(connector_state->crtc);
3083         struct nv50_mstc *mstc = nv50_mstc(connector);
3084         if (mstc->port) {
3085                 struct nv50_mstm *mstm = mstc->mstm;
3086                 return &mstm->msto[head->base.index]->encoder;
3087         }
3088         return NULL;
3089 }
3090
3091 static struct drm_encoder *
3092 nv50_mstc_best_encoder(struct drm_connector *connector)
3093 {
3094         struct nv50_mstc *mstc = nv50_mstc(connector);
3095         if (mstc->port) {
3096                 struct nv50_mstm *mstm = mstc->mstm;
3097                 return &mstm->msto[0]->encoder;
3098         }
3099         return NULL;
3100 }
3101
3102 static enum drm_mode_status
3103 nv50_mstc_mode_valid(struct drm_connector *connector,
3104                      struct drm_display_mode *mode)
3105 {
3106         return MODE_OK;
3107 }
3108
3109 static int
3110 nv50_mstc_get_modes(struct drm_connector *connector)
3111 {
3112         struct nv50_mstc *mstc = nv50_mstc(connector);
3113         int ret = 0;
3114
3115         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
3116         drm_mode_connector_update_edid_property(&mstc->connector, mstc->edid);
3117         if (mstc->edid)
3118                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
3119
3120         if (!mstc->connector.display_info.bpc)
3121                 mstc->connector.display_info.bpc = 8;
3122
3123         if (mstc->native)
3124                 drm_mode_destroy(mstc->connector.dev, mstc->native);
3125         mstc->native = nouveau_conn_native_mode(&mstc->connector);
3126         return ret;
3127 }
3128
3129 static const struct drm_connector_helper_funcs
3130 nv50_mstc_help = {
3131         .get_modes = nv50_mstc_get_modes,
3132         .mode_valid = nv50_mstc_mode_valid,
3133         .best_encoder = nv50_mstc_best_encoder,
3134         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
3135 };
3136
3137 static enum drm_connector_status
3138 nv50_mstc_detect(struct drm_connector *connector, bool force)
3139 {
3140         struct nv50_mstc *mstc = nv50_mstc(connector);
3141         if (!mstc->port)
3142                 return connector_status_disconnected;
3143         return drm_dp_mst_detect_port(connector, mstc->port->mgr, mstc->port);
3144 }
3145
3146 static void
3147 nv50_mstc_destroy(struct drm_connector *connector)
3148 {
3149         struct nv50_mstc *mstc = nv50_mstc(connector);
3150         drm_connector_cleanup(&mstc->connector);
3151         kfree(mstc);
3152 }
3153
3154 static const struct drm_connector_funcs
3155 nv50_mstc = {
3156         .reset = nouveau_conn_reset,
3157         .detect = nv50_mstc_detect,
3158         .fill_modes = drm_helper_probe_single_connector_modes,
3159         .destroy = nv50_mstc_destroy,
3160         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
3161         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
3162         .atomic_set_property = nouveau_conn_atomic_set_property,
3163         .atomic_get_property = nouveau_conn_atomic_get_property,
3164 };
3165
3166 static int
3167 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
3168               const char *path, struct nv50_mstc **pmstc)
3169 {
3170         struct drm_device *dev = mstm->outp->base.base.dev;
3171         struct nv50_mstc *mstc;
3172         int ret, i;
3173
3174         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
3175                 return -ENOMEM;
3176         mstc->mstm = mstm;
3177         mstc->port = port;
3178
3179         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
3180                                  DRM_MODE_CONNECTOR_DisplayPort);
3181         if (ret) {
3182                 kfree(*pmstc);
3183                 *pmstc = NULL;
3184                 return ret;
3185         }
3186
3187         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
3188
3189         mstc->connector.funcs->reset(&mstc->connector);
3190         nouveau_conn_attach_properties(&mstc->connector);
3191
3192         for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
3193                 drm_mode_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
3194
3195         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
3196         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
3197         drm_mode_connector_set_path_property(&mstc->connector, path);
3198         return 0;
3199 }
3200
3201 static void
3202 nv50_mstm_cleanup(struct nv50_mstm *mstm)
3203 {
3204         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
3205         struct drm_encoder *encoder;
3206         int ret;
3207
3208         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
3209         ret = drm_dp_check_act_status(&mstm->mgr);
3210
3211         ret = drm_dp_update_payload_part2(&mstm->mgr);
3212
3213         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
3214                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
3215                         struct nv50_msto *msto = nv50_msto(encoder);
3216                         struct nv50_mstc *mstc = msto->mstc;
3217                         if (mstc && mstc->mstm == mstm)
3218                                 nv50_msto_cleanup(msto);
3219                 }
3220         }
3221
3222         mstm->modified = false;
3223 }
3224
3225 static void
3226 nv50_mstm_prepare(struct nv50_mstm *mstm)
3227 {
3228         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
3229         struct drm_encoder *encoder;
3230         int ret;
3231
3232         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
3233         ret = drm_dp_update_payload_part1(&mstm->mgr);
3234
3235         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
3236                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
3237                         struct nv50_msto *msto = nv50_msto(encoder);
3238                         struct nv50_mstc *mstc = msto->mstc;
3239                         if (mstc && mstc->mstm == mstm)
3240                                 nv50_msto_prepare(msto);
3241                 }
3242         }
3243
3244         if (mstm->disabled) {
3245                 if (!mstm->links)
3246                         nv50_outp_release(mstm->outp);
3247                 mstm->disabled = false;
3248         }
3249 }
3250
3251 static void
3252 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr)
3253 {
3254         struct nv50_mstm *mstm = nv50_mstm(mgr);
3255         drm_kms_helper_hotplug_event(mstm->outp->base.base.dev);
3256 }
3257
3258 static void
3259 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
3260                             struct drm_connector *connector)
3261 {
3262         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3263         struct nv50_mstc *mstc = nv50_mstc(connector);
3264
3265         drm_connector_unregister(&mstc->connector);
3266
3267         drm_modeset_lock_all(drm->dev);
3268         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
3269         mstc->port = NULL;
3270         drm_modeset_unlock_all(drm->dev);
3271
3272         drm_connector_unreference(&mstc->connector);
3273 }
3274
3275 static void
3276 nv50_mstm_register_connector(struct drm_connector *connector)
3277 {
3278         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3279
3280         drm_modeset_lock_all(drm->dev);
3281         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
3282         drm_modeset_unlock_all(drm->dev);
3283
3284         drm_connector_register(connector);
3285 }
3286
3287 static struct drm_connector *
3288 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
3289                         struct drm_dp_mst_port *port, const char *path)
3290 {
3291         struct nv50_mstm *mstm = nv50_mstm(mgr);
3292         struct nv50_mstc *mstc;
3293         int ret;
3294
3295         ret = nv50_mstc_new(mstm, port, path, &mstc);
3296         if (ret) {
3297                 if (mstc)
3298                         mstc->connector.funcs->destroy(&mstc->connector);
3299                 return NULL;
3300         }
3301
3302         return &mstc->connector;
3303 }
3304
3305 static const struct drm_dp_mst_topology_cbs
3306 nv50_mstm = {
3307         .add_connector = nv50_mstm_add_connector,
3308         .register_connector = nv50_mstm_register_connector,
3309         .destroy_connector = nv50_mstm_destroy_connector,
3310         .hotplug = nv50_mstm_hotplug,
3311 };
3312
3313 void
3314 nv50_mstm_service(struct nv50_mstm *mstm)
3315 {
3316         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
3317         bool handled = true;
3318         int ret;
3319         u8 esi[8] = {};
3320
3321         if (!aux)
3322                 return;
3323
3324         while (handled) {
3325                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
3326                 if (ret != 8) {
3327                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
3328                         return;
3329                 }
3330
3331                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
3332                 if (!handled)
3333                         break;
3334
3335                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
3336         }
3337 }
3338
3339 void
3340 nv50_mstm_remove(struct nv50_mstm *mstm)
3341 {
3342         if (mstm)
3343                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
3344 }
3345
3346 static int
3347 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
3348 {
3349         struct nouveau_encoder *outp = mstm->outp;
3350         struct {
3351                 struct nv50_disp_mthd_v1 base;
3352                 struct nv50_disp_sor_dp_mst_link_v0 mst;
3353         } args = {
3354                 .base.version = 1,
3355                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
3356                 .base.hasht = outp->dcb->hasht,
3357                 .base.hashm = outp->dcb->hashm,
3358                 .mst.state = state,
3359         };
3360         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
3361         struct nvif_object *disp = &drm->display->disp;
3362         int ret;
3363
3364         if (dpcd >= 0x12) {
3365                 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CTRL, &dpcd);
3366                 if (ret < 0)
3367                         return ret;
3368
3369                 dpcd &= ~DP_MST_EN;
3370                 if (state)
3371                         dpcd |= DP_MST_EN;
3372
3373                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, dpcd);
3374                 if (ret < 0)
3375                         return ret;
3376         }
3377
3378         return nvif_mthd(disp, 0, &args, sizeof(args));
3379 }
3380
3381 int
3382 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
3383 {
3384         int ret, state = 0;
3385
3386         if (!mstm)
3387                 return 0;
3388
3389         if (dpcd[0] >= 0x12) {
3390                 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CAP, &dpcd[1]);
3391                 if (ret < 0)
3392                         return ret;
3393
3394                 if (!(dpcd[1] & DP_MST_CAP))
3395                         dpcd[0] = 0x11;
3396                 else
3397                         state = allow;
3398         }
3399
3400         ret = nv50_mstm_enable(mstm, dpcd[0], state);
3401         if (ret)
3402                 return ret;
3403
3404         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, state);
3405         if (ret)
3406                 return nv50_mstm_enable(mstm, dpcd[0], 0);
3407
3408         return mstm->mgr.mst_state;
3409 }
3410
3411 static void
3412 nv50_mstm_fini(struct nv50_mstm *mstm)
3413 {
3414         if (mstm && mstm->mgr.mst_state)
3415                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
3416 }
3417
3418 static void
3419 nv50_mstm_init(struct nv50_mstm *mstm)
3420 {
3421         if (mstm && mstm->mgr.mst_state)
3422                 drm_dp_mst_topology_mgr_resume(&mstm->mgr);
3423 }
3424
3425 static void
3426 nv50_mstm_del(struct nv50_mstm **pmstm)
3427 {
3428         struct nv50_mstm *mstm = *pmstm;
3429         if (mstm) {
3430                 kfree(*pmstm);
3431                 *pmstm = NULL;
3432         }
3433 }
3434
3435 static int
3436 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
3437               int conn_base_id, struct nv50_mstm **pmstm)
3438 {
3439         const int max_payloads = hweight8(outp->dcb->heads);
3440         struct drm_device *dev = outp->base.base.dev;
3441         struct nv50_mstm *mstm;
3442         int ret, i;
3443         u8 dpcd;
3444
3445         /* This is a workaround for some monitors not functioning
3446          * correctly in MST mode on initial module load.  I think
3447          * some bad interaction with the VBIOS may be responsible.
3448          *
3449          * A good ol' off and on again seems to work here ;)
3450          */
3451         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
3452         if (ret >= 0 && dpcd >= 0x12)
3453                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
3454
3455         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
3456                 return -ENOMEM;
3457         mstm->outp = outp;
3458         mstm->mgr.cbs = &nv50_mstm;
3459
3460         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
3461                                            max_payloads, conn_base_id);
3462         if (ret)
3463                 return ret;
3464
3465         for (i = 0; i < max_payloads; i++) {
3466                 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
3467                                     i, &mstm->msto[i]);
3468                 if (ret)
3469                         return ret;
3470         }
3471
3472         return 0;
3473 }
3474
3475 /******************************************************************************
3476  * SOR
3477  *****************************************************************************/
3478 static void
3479 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
3480                 struct drm_display_mode *mode, u8 proto, u8 depth)
3481 {
3482         struct nv50_dmac *core = &nv50_mast(nv_encoder->base.base.dev)->base;
3483         u32 *push;
3484
3485         if (!mode) {
3486                 nv_encoder->ctrl &= ~BIT(head);
3487                 if (!(nv_encoder->ctrl & 0x0000000f))
3488                         nv_encoder->ctrl = 0;
3489         } else {
3490                 nv_encoder->ctrl |= proto << 8;
3491                 nv_encoder->ctrl |= BIT(head);
3492         }
3493
3494         if ((push = evo_wait(core, 6))) {
3495                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
3496                         if (mode) {
3497                                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3498                                         nv_encoder->ctrl |= 0x00001000;
3499                                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3500                                         nv_encoder->ctrl |= 0x00002000;
3501                                 nv_encoder->ctrl |= depth << 16;
3502                         }
3503                         evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
3504                 } else {
3505                         if (mode) {
3506                                 u32 magic = 0x31ec6000 | (head << 25);
3507                                 u32 syncs = 0x00000001;
3508                                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3509                                         syncs |= 0x00000008;
3510                                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3511                                         syncs |= 0x00000010;
3512                                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
3513                                         magic |= 0x00000001;
3514
3515                                 evo_mthd(push, 0x0404 + (head * 0x300), 2);
3516                                 evo_data(push, syncs | (depth << 6));
3517                                 evo_data(push, magic);
3518                         }
3519                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
3520                 }
3521                 evo_data(push, nv_encoder->ctrl);
3522                 evo_kick(push, core);
3523         }
3524 }
3525
3526 static void
3527 nv50_sor_disable(struct drm_encoder *encoder)
3528 {
3529         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3530         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
3531
3532         nv_encoder->crtc = NULL;
3533
3534         if (nv_crtc) {
3535                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
3536                 u8 pwr;
3537
3538                 if (aux) {
3539                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
3540                         if (ret == 0) {
3541                                 pwr &= ~DP_SET_POWER_MASK;
3542                                 pwr |=  DP_SET_POWER_D3;
3543                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
3544                         }
3545                 }
3546
3547                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
3548                 nv50_audio_disable(encoder, nv_crtc);
3549                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
3550                 nv50_outp_release(nv_encoder);
3551         }
3552 }
3553
3554 static void
3555 nv50_sor_enable(struct drm_encoder *encoder)
3556 {
3557         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3558         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3559         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
3560         struct {
3561                 struct nv50_disp_mthd_v1 base;
3562                 struct nv50_disp_sor_lvds_script_v0 lvds;
3563         } lvds = {
3564                 .base.version = 1,
3565                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
3566                 .base.hasht   = nv_encoder->dcb->hasht,
3567                 .base.hashm   = nv_encoder->dcb->hashm,
3568         };
3569         struct nv50_disp *disp = nv50_disp(encoder->dev);
3570         struct drm_device *dev = encoder->dev;
3571         struct nouveau_drm *drm = nouveau_drm(dev);
3572         struct nouveau_connector *nv_connector;
3573         struct nvbios *bios = &drm->vbios;
3574         u8 proto = 0xf;
3575         u8 depth = 0x0;
3576
3577         nv_connector = nouveau_encoder_connector_get(nv_encoder);
3578         nv_encoder->crtc = encoder->crtc;
3579         nv50_outp_acquire(nv_encoder);
3580
3581         switch (nv_encoder->dcb->type) {
3582         case DCB_OUTPUT_TMDS:
3583                 if (nv_encoder->link & 1) {
3584                         proto = 0x1;
3585                         /* Only enable dual-link if:
3586                          *  - Need to (i.e. rate > 165MHz)
3587                          *  - DCB says we can
3588                          *  - Not an HDMI monitor, since there's no dual-link
3589                          *    on HDMI.
3590                          */
3591                         if (mode->clock >= 165000 &&
3592                             nv_encoder->dcb->duallink_possible &&
3593                             !drm_detect_hdmi_monitor(nv_connector->edid))
3594                                 proto |= 0x4;
3595                 } else {
3596                         proto = 0x2;
3597                 }
3598
3599                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
3600                 break;
3601         case DCB_OUTPUT_LVDS:
3602                 proto = 0x0;
3603
3604                 if (bios->fp_no_ddc) {
3605                         if (bios->fp.dual_link)
3606                                 lvds.lvds.script |= 0x0100;
3607                         if (bios->fp.if_is_24bit)
3608                                 lvds.lvds.script |= 0x0200;
3609                 } else {
3610                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
3611                                 if (((u8 *)nv_connector->edid)[121] == 2)
3612                                         lvds.lvds.script |= 0x0100;
3613                         } else
3614                         if (mode->clock >= bios->fp.duallink_transition_clk) {
3615                                 lvds.lvds.script |= 0x0100;
3616                         }
3617
3618                         if (lvds.lvds.script & 0x0100) {
3619                                 if (bios->fp.strapless_is_24bit & 2)
3620                                         lvds.lvds.script |= 0x0200;
3621                         } else {
3622                                 if (bios->fp.strapless_is_24bit & 1)
3623                                         lvds.lvds.script |= 0x0200;
3624                         }
3625
3626                         if (nv_connector->base.display_info.bpc == 8)
3627                                 lvds.lvds.script |= 0x0200;
3628                 }
3629
3630                 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
3631                 break;
3632         case DCB_OUTPUT_DP:
3633                 if (nv_connector->base.display_info.bpc == 6)
3634                         depth = 0x2;
3635                 else
3636                 if (nv_connector->base.display_info.bpc == 8)
3637                         depth = 0x5;
3638                 else
3639                         depth = 0x6;
3640
3641                 if (nv_encoder->link & 1)
3642                         proto = 0x8;
3643                 else
3644                         proto = 0x9;
3645
3646                 nv50_audio_enable(encoder, mode);
3647                 break;
3648         default:
3649                 BUG();
3650                 break;
3651         }
3652
3653         nv_encoder->update(nv_encoder, nv_crtc->index, mode, proto, depth);
3654 }
3655
3656 static const struct drm_encoder_helper_funcs
3657 nv50_sor_help = {
3658         .atomic_check = nv50_outp_atomic_check,
3659         .enable = nv50_sor_enable,
3660         .disable = nv50_sor_disable,
3661 };
3662
3663 static void
3664 nv50_sor_destroy(struct drm_encoder *encoder)
3665 {
3666         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3667         nv50_mstm_del(&nv_encoder->dp.mstm);
3668         drm_encoder_cleanup(encoder);
3669         kfree(encoder);
3670 }
3671
3672 static const struct drm_encoder_funcs
3673 nv50_sor_func = {
3674         .destroy = nv50_sor_destroy,
3675 };
3676
3677 static int
3678 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
3679 {
3680         struct nouveau_connector *nv_connector = nouveau_connector(connector);
3681         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3682         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
3683         struct nouveau_encoder *nv_encoder;
3684         struct drm_encoder *encoder;
3685         int type, ret;
3686
3687         switch (dcbe->type) {
3688         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
3689         case DCB_OUTPUT_TMDS:
3690         case DCB_OUTPUT_DP:
3691         default:
3692                 type = DRM_MODE_ENCODER_TMDS;
3693                 break;
3694         }
3695
3696         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
3697         if (!nv_encoder)
3698                 return -ENOMEM;
3699         nv_encoder->dcb = dcbe;
3700         nv_encoder->update = nv50_sor_update;
3701
3702         encoder = to_drm_encoder(nv_encoder);
3703         encoder->possible_crtcs = dcbe->heads;
3704         encoder->possible_clones = 0;
3705         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
3706                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
3707         drm_encoder_helper_add(encoder, &nv50_sor_help);
3708
3709         drm_mode_connector_attach_encoder(connector, encoder);
3710
3711         if (dcbe->type == DCB_OUTPUT_DP) {
3712                 struct nv50_disp *disp = nv50_disp(encoder->dev);
3713                 struct nvkm_i2c_aux *aux =
3714                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
3715                 if (aux) {
3716                         if (disp->disp->oclass < GF110_DISP) {
3717                                 /* HW has no support for address-only
3718                                  * transactions, so we're required to
3719                                  * use custom I2C-over-AUX code.
3720                                  */
3721                                 nv_encoder->i2c = &aux->i2c;
3722                         } else {
3723                                 nv_encoder->i2c = &nv_connector->aux.ddc;
3724                         }
3725                         nv_encoder->aux = aux;
3726                 }
3727
3728                 /*TODO: Use DP Info Table to check for support. */
3729                 if (disp->disp->oclass >= GF110_DISP) {
3730                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
3731                                             nv_connector->base.base.id,
3732                                             &nv_encoder->dp.mstm);
3733                         if (ret)
3734                                 return ret;
3735                 }
3736         } else {
3737                 struct nvkm_i2c_bus *bus =
3738                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
3739                 if (bus)
3740                         nv_encoder->i2c = &bus->i2c;
3741         }
3742
3743         return 0;
3744 }
3745
3746 /******************************************************************************
3747  * PIOR
3748  *****************************************************************************/
3749 static int
3750 nv50_pior_atomic_check(struct drm_encoder *encoder,
3751                        struct drm_crtc_state *crtc_state,
3752                        struct drm_connector_state *conn_state)
3753 {
3754         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
3755         if (ret)
3756                 return ret;
3757         crtc_state->adjusted_mode.clock *= 2;
3758         return 0;
3759 }
3760
3761 static void
3762 nv50_pior_disable(struct drm_encoder *encoder)
3763 {
3764         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3765         struct nv50_mast *mast = nv50_mast(encoder->dev);
3766         const int or = nv_encoder->or;
3767         u32 *push;
3768
3769         if (nv_encoder->crtc) {
3770                 push = evo_wait(mast, 4);
3771                 if (push) {
3772                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
3773                                 evo_mthd(push, 0x0700 + (or * 0x040), 1);
3774                                 evo_data(push, 0x00000000);
3775                         }
3776                         evo_kick(push, mast);
3777                 }
3778         }
3779
3780         nv_encoder->crtc = NULL;
3781         nv50_outp_release(nv_encoder);
3782 }
3783
3784 static void
3785 nv50_pior_enable(struct drm_encoder *encoder)
3786 {
3787         struct nv50_mast *mast = nv50_mast(encoder->dev);
3788         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3789         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3790         struct nouveau_connector *nv_connector;
3791         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
3792         u8 owner = 1 << nv_crtc->index;
3793         u8 proto, depth;
3794         u32 *push;
3795
3796         nv50_outp_acquire(nv_encoder);
3797
3798         nv_connector = nouveau_encoder_connector_get(nv_encoder);
3799         switch (nv_connector->base.display_info.bpc) {
3800         case 10: depth = 0x6; break;
3801         case  8: depth = 0x5; break;
3802         case  6: depth = 0x2; break;
3803         default: depth = 0x0; break;
3804         }
3805
3806         switch (nv_encoder->dcb->type) {
3807         case DCB_OUTPUT_TMDS:
3808         case DCB_OUTPUT_DP:
3809                 proto = 0x0;
3810                 break;
3811         default:
3812                 BUG();
3813                 break;
3814         }
3815
3816         push = evo_wait(mast, 8);
3817         if (push) {
3818                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
3819                         u32 ctrl = (depth << 16) | (proto << 8) | owner;
3820                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3821                                 ctrl |= 0x00001000;
3822                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3823                                 ctrl |= 0x00002000;
3824                         evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
3825                         evo_data(push, ctrl);
3826                 }
3827
3828                 evo_kick(push, mast);
3829         }
3830
3831         nv_encoder->crtc = encoder->crtc;
3832 }
3833
3834 static const struct drm_encoder_helper_funcs
3835 nv50_pior_help = {
3836         .atomic_check = nv50_pior_atomic_check,
3837         .enable = nv50_pior_enable,
3838         .disable = nv50_pior_disable,
3839 };
3840
3841 static void
3842 nv50_pior_destroy(struct drm_encoder *encoder)
3843 {
3844         drm_encoder_cleanup(encoder);
3845         kfree(encoder);
3846 }
3847
3848 static const struct drm_encoder_funcs
3849 nv50_pior_func = {
3850         .destroy = nv50_pior_destroy,
3851 };
3852
3853 static int
3854 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
3855 {
3856         struct nouveau_connector *nv_connector = nouveau_connector(connector);
3857         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3858         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
3859         struct nvkm_i2c_bus *bus = NULL;
3860         struct nvkm_i2c_aux *aux = NULL;
3861         struct i2c_adapter *ddc;
3862         struct nouveau_encoder *nv_encoder;
3863         struct drm_encoder *encoder;
3864         int type;
3865
3866         switch (dcbe->type) {
3867         case DCB_OUTPUT_TMDS:
3868                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
3869                 ddc  = bus ? &bus->i2c : NULL;
3870                 type = DRM_MODE_ENCODER_TMDS;
3871                 break;
3872         case DCB_OUTPUT_DP:
3873                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
3874                 ddc  = aux ? &nv_connector->aux.ddc : NULL;
3875                 type = DRM_MODE_ENCODER_TMDS;
3876                 break;
3877         default:
3878                 return -ENODEV;
3879         }
3880
3881         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
3882         if (!nv_encoder)
3883                 return -ENOMEM;
3884         nv_encoder->dcb = dcbe;
3885         nv_encoder->i2c = ddc;
3886         nv_encoder->aux = aux;
3887
3888         encoder = to_drm_encoder(nv_encoder);
3889         encoder->possible_crtcs = dcbe->heads;
3890         encoder->possible_clones = 0;
3891         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
3892                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
3893         drm_encoder_helper_add(encoder, &nv50_pior_help);
3894
3895         drm_mode_connector_attach_encoder(connector, encoder);
3896         return 0;
3897 }
3898
3899 /******************************************************************************
3900  * Atomic
3901  *****************************************************************************/
3902
3903 static void
3904 nv50_disp_atomic_commit_core(struct nouveau_drm *drm, u32 interlock)
3905 {
3906         struct nv50_disp *disp = nv50_disp(drm->dev);
3907         struct nv50_dmac *core = &disp->mast.base;
3908         struct nv50_mstm *mstm;
3909         struct drm_encoder *encoder;
3910         u32 *push;
3911
3912         NV_ATOMIC(drm, "commit core %08x\n", interlock);
3913
3914         drm_for_each_encoder(encoder, drm->dev) {
3915                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
3916                         mstm = nouveau_encoder(encoder)->dp.mstm;
3917                         if (mstm && mstm->modified)
3918                                 nv50_mstm_prepare(mstm);
3919                 }
3920         }
3921
3922         if ((push = evo_wait(core, 5))) {
3923                 evo_mthd(push, 0x0084, 1);
3924                 evo_data(push, 0x80000000);
3925                 evo_mthd(push, 0x0080, 2);
3926                 evo_data(push, interlock);
3927                 evo_data(push, 0x00000000);
3928                 nouveau_bo_wr32(disp->sync, 0, 0x00000000);
3929                 evo_kick(push, core);
3930                 if (nvif_msec(&drm->client.device, 2000ULL,
3931                         if (nouveau_bo_rd32(disp->sync, 0))
3932                                 break;
3933                         usleep_range(1, 2);
3934                 ) < 0)
3935                         NV_ERROR(drm, "EVO timeout\n");
3936         }
3937
3938         drm_for_each_encoder(encoder, drm->dev) {
3939                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
3940                         mstm = nouveau_encoder(encoder)->dp.mstm;
3941                         if (mstm && mstm->modified)
3942                                 nv50_mstm_cleanup(mstm);
3943                 }
3944         }
3945 }
3946
3947 static void
3948 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
3949 {
3950         struct drm_device *dev = state->dev;
3951         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
3952         struct drm_crtc *crtc;
3953         struct drm_plane_state *new_plane_state;
3954         struct drm_plane *plane;
3955         struct nouveau_drm *drm = nouveau_drm(dev);
3956         struct nv50_disp *disp = nv50_disp(dev);
3957         struct nv50_atom *atom = nv50_atom(state);
3958         struct nv50_outp_atom *outp, *outt;
3959         u32 interlock_core = 0;
3960         u32 interlock_chan = 0;
3961         int i;
3962
3963         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
3964         drm_atomic_helper_wait_for_fences(dev, state, false);
3965         drm_atomic_helper_wait_for_dependencies(state);
3966         drm_atomic_helper_update_legacy_modeset_state(dev, state);
3967
3968         if (atom->lock_core)
3969                 mutex_lock(&disp->mutex);
3970
3971         /* Disable head(s). */
3972         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
3973                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
3974                 struct nv50_head *head = nv50_head(crtc);
3975
3976                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
3977                           asyh->clr.mask, asyh->set.mask);
3978                 if (old_crtc_state->active && !new_crtc_state->active)
3979                         drm_crtc_vblank_off(crtc);
3980
3981                 if (asyh->clr.mask) {
3982                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
3983                         interlock_core |= 1;
3984                 }
3985         }
3986
3987         /* Disable plane(s). */
3988         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
3989                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
3990                 struct nv50_wndw *wndw = nv50_wndw(plane);
3991
3992                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
3993                           asyw->clr.mask, asyw->set.mask);
3994                 if (!asyw->clr.mask)
3995                         continue;
3996
3997                 interlock_chan |= nv50_wndw_flush_clr(wndw, interlock_core,
3998                                                       atom->flush_disable,
3999                                                       asyw);
4000         }
4001
4002         /* Disable output path(s). */
4003         list_for_each_entry(outp, &atom->outp, head) {
4004                 const struct drm_encoder_helper_funcs *help;
4005                 struct drm_encoder *encoder;
4006
4007                 encoder = outp->encoder;
4008                 help = encoder->helper_private;
4009
4010                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
4011                           outp->clr.mask, outp->set.mask);
4012
4013                 if (outp->clr.mask) {
4014                         help->disable(encoder);
4015                         interlock_core |= 1;
4016                         if (outp->flush_disable) {
4017                                 nv50_disp_atomic_commit_core(drm, interlock_chan);
4018                                 interlock_core = 0;
4019                                 interlock_chan = 0;
4020                         }
4021                 }
4022         }
4023
4024         /* Flush disable. */
4025         if (interlock_core) {
4026                 if (atom->flush_disable) {
4027                         nv50_disp_atomic_commit_core(drm, interlock_chan);
4028                         interlock_core = 0;
4029                         interlock_chan = 0;
4030                 }
4031         }
4032
4033         /* Update output path(s). */
4034         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
4035                 const struct drm_encoder_helper_funcs *help;
4036                 struct drm_encoder *encoder;
4037
4038                 encoder = outp->encoder;
4039                 help = encoder->helper_private;
4040
4041                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
4042                           outp->set.mask, outp->clr.mask);
4043
4044                 if (outp->set.mask) {
4045                         help->enable(encoder);
4046                         interlock_core = 1;
4047                 }
4048
4049                 list_del(&outp->head);
4050                 kfree(outp);
4051         }
4052
4053         /* Update head(s). */
4054         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4055                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
4056                 struct nv50_head *head = nv50_head(crtc);
4057
4058                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
4059                           asyh->set.mask, asyh->clr.mask);
4060
4061                 if (asyh->set.mask) {
4062                         nv50_head_flush_set(head, asyh);
4063                         interlock_core = 1;
4064                 }
4065
4066                 if (new_crtc_state->active) {
4067                         if (!old_crtc_state->active)
4068                                 drm_crtc_vblank_on(crtc);
4069                         if (new_crtc_state->event)
4070                                 drm_crtc_vblank_get(crtc);
4071                 }
4072         }
4073
4074         /* Update plane(s). */
4075         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
4076                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
4077                 struct nv50_wndw *wndw = nv50_wndw(plane);
4078
4079                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
4080                           asyw->set.mask, asyw->clr.mask);
4081                 if ( !asyw->set.mask &&
4082                     (!asyw->clr.mask || atom->flush_disable))
4083                         continue;
4084
4085                 interlock_chan |= nv50_wndw_flush_set(wndw, interlock_core, asyw);
4086         }
4087
4088         /* Flush update. */
4089         if (interlock_core) {
4090                 if (!interlock_chan && atom->state.legacy_cursor_update) {
4091                         u32 *push = evo_wait(&disp->mast, 2);
4092                         if (push) {
4093                                 evo_mthd(push, 0x0080, 1);
4094                                 evo_data(push, 0x00000000);
4095                                 evo_kick(push, &disp->mast);
4096                         }
4097                 } else {
4098                         nv50_disp_atomic_commit_core(drm, interlock_chan);
4099                 }
4100         }
4101
4102         if (atom->lock_core)
4103                 mutex_unlock(&disp->mutex);
4104
4105         /* Wait for HW to signal completion. */
4106         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
4107                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
4108                 struct nv50_wndw *wndw = nv50_wndw(plane);
4109                 int ret = nv50_wndw_wait_armed(wndw, asyw);
4110                 if (ret)
4111                         NV_ERROR(drm, "%s: timeout\n", plane->name);
4112         }
4113
4114         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4115                 if (new_crtc_state->event) {
4116                         unsigned long flags;
4117                         /* Get correct count/ts if racing with vblank irq */
4118                         if (new_crtc_state->active)
4119                                 drm_crtc_accurate_vblank_count(crtc);
4120                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
4121                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
4122                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4123
4124                         new_crtc_state->event = NULL;
4125                         if (new_crtc_state->active)
4126                                 drm_crtc_vblank_put(crtc);
4127                 }
4128         }
4129
4130         drm_atomic_helper_commit_hw_done(state);
4131         drm_atomic_helper_cleanup_planes(dev, state);
4132         drm_atomic_helper_commit_cleanup_done(state);
4133         drm_atomic_state_put(state);
4134 }
4135
4136 static void
4137 nv50_disp_atomic_commit_work(struct work_struct *work)
4138 {
4139         struct drm_atomic_state *state =
4140                 container_of(work, typeof(*state), commit_work);
4141         nv50_disp_atomic_commit_tail(state);
4142 }
4143
4144 static int
4145 nv50_disp_atomic_commit(struct drm_device *dev,
4146                         struct drm_atomic_state *state, bool nonblock)
4147 {
4148         struct nouveau_drm *drm = nouveau_drm(dev);
4149         struct nv50_disp *disp = nv50_disp(dev);
4150         struct drm_plane_state *new_plane_state;
4151         struct drm_plane *plane;
4152         struct drm_crtc *crtc;
4153         bool active = false;
4154         int ret, i;
4155
4156         ret = pm_runtime_get_sync(dev->dev);
4157         if (ret < 0 && ret != -EACCES)
4158                 return ret;
4159
4160         ret = drm_atomic_helper_setup_commit(state, nonblock);
4161         if (ret)
4162                 goto done;
4163
4164         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
4165
4166         ret = drm_atomic_helper_prepare_planes(dev, state);
4167         if (ret)
4168                 goto done;
4169
4170         if (!nonblock) {
4171                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
4172                 if (ret)
4173                         goto err_cleanup;
4174         }
4175
4176         ret = drm_atomic_helper_swap_state(state, true);
4177         if (ret)
4178                 goto err_cleanup;
4179
4180         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
4181                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
4182                 struct nv50_wndw *wndw = nv50_wndw(plane);
4183
4184                 if (asyw->set.image) {
4185                         asyw->ntfy.handle = wndw->dmac->sync.handle;
4186                         asyw->ntfy.offset = wndw->ntfy;
4187                         asyw->ntfy.awaken = false;
4188                         asyw->set.ntfy = true;
4189                         nouveau_bo_wr32(disp->sync, wndw->ntfy / 4, 0x00000000);
4190                         wndw->ntfy ^= 0x10;
4191                 }
4192         }
4193
4194         drm_atomic_state_get(state);
4195
4196         if (nonblock)
4197                 queue_work(system_unbound_wq, &state->commit_work);
4198         else
4199                 nv50_disp_atomic_commit_tail(state);
4200
4201         drm_for_each_crtc(crtc, dev) {
4202                 if (crtc->state->enable) {
4203                         if (!drm->have_disp_power_ref) {
4204                                 drm->have_disp_power_ref = true;
4205                                 return 0;
4206                         }
4207                         active = true;
4208                         break;
4209                 }
4210         }
4211
4212         if (!active && drm->have_disp_power_ref) {
4213                 pm_runtime_put_autosuspend(dev->dev);
4214                 drm->have_disp_power_ref = false;
4215         }
4216
4217 err_cleanup:
4218         if (ret)
4219                 drm_atomic_helper_cleanup_planes(dev, state);
4220 done:
4221         pm_runtime_put_autosuspend(dev->dev);
4222         return ret;
4223 }
4224
4225 static struct nv50_outp_atom *
4226 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
4227 {
4228         struct nv50_outp_atom *outp;
4229
4230         list_for_each_entry(outp, &atom->outp, head) {
4231                 if (outp->encoder == encoder)
4232                         return outp;
4233         }
4234
4235         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
4236         if (!outp)
4237                 return ERR_PTR(-ENOMEM);
4238
4239         list_add(&outp->head, &atom->outp);
4240         outp->encoder = encoder;
4241         return outp;
4242 }
4243
4244 static int
4245 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
4246                                 struct drm_connector_state *old_connector_state)
4247 {
4248         struct drm_encoder *encoder = old_connector_state->best_encoder;
4249         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4250         struct drm_crtc *crtc;
4251         struct nv50_outp_atom *outp;
4252
4253         if (!(crtc = old_connector_state->crtc))
4254                 return 0;
4255
4256         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
4257         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
4258         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
4259                 outp = nv50_disp_outp_atomic_add(atom, encoder);
4260                 if (IS_ERR(outp))
4261                         return PTR_ERR(outp);
4262
4263                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
4264                         outp->flush_disable = true;
4265                         atom->flush_disable = true;
4266                 }
4267                 outp->clr.ctrl = true;
4268                 atom->lock_core = true;
4269         }
4270
4271         return 0;
4272 }
4273
4274 static int
4275 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
4276                                 struct drm_connector_state *connector_state)
4277 {
4278         struct drm_encoder *encoder = connector_state->best_encoder;
4279         struct drm_crtc_state *new_crtc_state;
4280         struct drm_crtc *crtc;
4281         struct nv50_outp_atom *outp;
4282
4283         if (!(crtc = connector_state->crtc))
4284                 return 0;
4285
4286         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
4287         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
4288                 outp = nv50_disp_outp_atomic_add(atom, encoder);
4289                 if (IS_ERR(outp))
4290                         return PTR_ERR(outp);
4291
4292                 outp->set.ctrl = true;
4293                 atom->lock_core = true;
4294         }
4295
4296         return 0;
4297 }
4298
4299 static int
4300 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
4301 {
4302         struct nv50_atom *atom = nv50_atom(state);
4303         struct drm_connector_state *old_connector_state, *new_connector_state;
4304         struct drm_connector *connector;
4305         int ret, i;
4306
4307         ret = drm_atomic_helper_check(dev, state);
4308         if (ret)
4309                 return ret;
4310
4311         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
4312                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
4313                 if (ret)
4314                         return ret;
4315
4316                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
4317                 if (ret)
4318                         return ret;
4319         }
4320
4321         return 0;
4322 }
4323
4324 static void
4325 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
4326 {
4327         struct nv50_atom *atom = nv50_atom(state);
4328         struct nv50_outp_atom *outp, *outt;
4329
4330         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
4331                 list_del(&outp->head);
4332                 kfree(outp);
4333         }
4334
4335         drm_atomic_state_default_clear(state);
4336 }
4337
4338 static void
4339 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
4340 {
4341         struct nv50_atom *atom = nv50_atom(state);
4342         drm_atomic_state_default_release(&atom->state);
4343         kfree(atom);
4344 }
4345
4346 static struct drm_atomic_state *
4347 nv50_disp_atomic_state_alloc(struct drm_device *dev)
4348 {
4349         struct nv50_atom *atom;
4350         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
4351             drm_atomic_state_init(dev, &atom->state) < 0) {
4352                 kfree(atom);
4353                 return NULL;
4354         }
4355         INIT_LIST_HEAD(&atom->outp);
4356         return &atom->state;
4357 }
4358
4359 static const struct drm_mode_config_funcs
4360 nv50_disp_func = {
4361         .fb_create = nouveau_user_framebuffer_create,
4362         .output_poll_changed = drm_fb_helper_output_poll_changed,
4363         .atomic_check = nv50_disp_atomic_check,
4364         .atomic_commit = nv50_disp_atomic_commit,
4365         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
4366         .atomic_state_clear = nv50_disp_atomic_state_clear,
4367         .atomic_state_free = nv50_disp_atomic_state_free,
4368 };
4369
4370 /******************************************************************************
4371  * Init
4372  *****************************************************************************/
4373
4374 void
4375 nv50_display_fini(struct drm_device *dev)
4376 {
4377         struct nouveau_encoder *nv_encoder;
4378         struct drm_encoder *encoder;
4379         struct drm_plane *plane;
4380
4381         drm_for_each_plane(plane, dev) {
4382                 struct nv50_wndw *wndw = nv50_wndw(plane);
4383                 if (plane->funcs != &nv50_wndw)
4384                         continue;
4385                 nv50_wndw_fini(wndw);
4386         }
4387
4388         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4389                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
4390                         nv_encoder = nouveau_encoder(encoder);
4391                         nv50_mstm_fini(nv_encoder->dp.mstm);
4392                 }
4393         }
4394 }
4395
4396 int
4397 nv50_display_init(struct drm_device *dev)
4398 {
4399         struct drm_encoder *encoder;
4400         struct drm_plane *plane;
4401         u32 *push;
4402
4403         push = evo_wait(nv50_mast(dev), 32);
4404         if (!push)
4405                 return -EBUSY;
4406
4407         evo_mthd(push, 0x0088, 1);
4408         evo_data(push, nv50_mast(dev)->base.sync.handle);
4409         evo_kick(push, nv50_mast(dev));
4410
4411         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4412                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
4413                         struct nouveau_encoder *nv_encoder =
4414                                 nouveau_encoder(encoder);
4415                         nv50_mstm_init(nv_encoder->dp.mstm);
4416                 }
4417         }
4418
4419         drm_for_each_plane(plane, dev) {
4420                 struct nv50_wndw *wndw = nv50_wndw(plane);
4421                 if (plane->funcs != &nv50_wndw)
4422                         continue;
4423                 nv50_wndw_init(wndw);
4424         }
4425
4426         return 0;
4427 }
4428
4429 void
4430 nv50_display_destroy(struct drm_device *dev)
4431 {
4432         struct nv50_disp *disp = nv50_disp(dev);
4433
4434         nv50_dmac_destroy(&disp->mast.base, disp->disp);
4435
4436         nouveau_bo_unmap(disp->sync);
4437         if (disp->sync)
4438                 nouveau_bo_unpin(disp->sync);
4439         nouveau_bo_ref(NULL, &disp->sync);
4440
4441         nouveau_display(dev)->priv = NULL;
4442         kfree(disp);
4443 }
4444
4445 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
4446 static int nouveau_atomic = 0;
4447 module_param_named(atomic, nouveau_atomic, int, 0400);
4448
4449 int
4450 nv50_display_create(struct drm_device *dev)
4451 {
4452         struct nvif_device *device = &nouveau_drm(dev)->client.device;
4453         struct nouveau_drm *drm = nouveau_drm(dev);
4454         struct dcb_table *dcb = &drm->vbios.dcb;
4455         struct drm_connector *connector, *tmp;
4456         struct nv50_disp *disp;
4457         struct dcb_output *dcbe;
4458         int crtcs, ret, i;
4459
4460         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
4461         if (!disp)
4462                 return -ENOMEM;
4463
4464         mutex_init(&disp->mutex);
4465
4466         nouveau_display(dev)->priv = disp;
4467         nouveau_display(dev)->dtor = nv50_display_destroy;
4468         nouveau_display(dev)->init = nv50_display_init;
4469         nouveau_display(dev)->fini = nv50_display_fini;
4470         disp->disp = &nouveau_display(dev)->disp;
4471         dev->mode_config.funcs = &nv50_disp_func;
4472         dev->driver->driver_features |= DRIVER_PREFER_XBGR_30BPP;
4473         if (nouveau_atomic)
4474                 dev->driver->driver_features |= DRIVER_ATOMIC;
4475
4476         /* small shared memory area we use for notifiers and semaphores */
4477         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
4478                              0, 0x0000, NULL, NULL, &disp->sync);
4479         if (!ret) {
4480                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
4481                 if (!ret) {
4482                         ret = nouveau_bo_map(disp->sync);
4483                         if (ret)
4484                                 nouveau_bo_unpin(disp->sync);
4485                 }
4486                 if (ret)
4487                         nouveau_bo_ref(NULL, &disp->sync);
4488         }
4489
4490         if (ret)
4491                 goto out;
4492
4493         /* allocate master evo channel */
4494         ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset,
4495                               &disp->mast);
4496         if (ret)
4497                 goto out;
4498
4499         /* create crtc objects to represent the hw heads */
4500         if (disp->disp->oclass >= GF110_DISP)
4501                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
4502         else
4503                 crtcs = 0x3;
4504
4505         for (i = 0; i < fls(crtcs); i++) {
4506                 if (!(crtcs & (1 << i)))
4507                         continue;
4508                 ret = nv50_head_create(dev, i);
4509                 if (ret)
4510                         goto out;
4511         }
4512
4513         /* create encoder/connector objects based on VBIOS DCB table */
4514         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
4515                 connector = nouveau_connector_create(dev, dcbe->connector);
4516                 if (IS_ERR(connector))
4517                         continue;
4518
4519                 if (dcbe->location == DCB_LOC_ON_CHIP) {
4520                         switch (dcbe->type) {
4521                         case DCB_OUTPUT_TMDS:
4522                         case DCB_OUTPUT_LVDS:
4523                         case DCB_OUTPUT_DP:
4524                                 ret = nv50_sor_create(connector, dcbe);
4525                                 break;
4526                         case DCB_OUTPUT_ANALOG:
4527                                 ret = nv50_dac_create(connector, dcbe);
4528                                 break;
4529                         default:
4530                                 ret = -ENODEV;
4531                                 break;
4532                         }
4533                 } else {
4534                         ret = nv50_pior_create(connector, dcbe);
4535                 }
4536
4537                 if (ret) {
4538                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
4539                                      dcbe->location, dcbe->type,
4540                                      ffs(dcbe->or) - 1, ret);
4541                         ret = 0;
4542                 }
4543         }
4544
4545         /* cull any connectors we created that don't have an encoder */
4546         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
4547                 if (connector->encoder_ids[0])
4548                         continue;
4549
4550                 NV_WARN(drm, "%s has no encoders, removing\n",
4551                         connector->name);
4552                 connector->funcs->destroy(connector);
4553         }
4554
4555 out:
4556         if (ret)
4557                 nv50_display_destroy(dev);
4558         return ret;
4559 }