2 * Copyright 2011 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/dma-mapping.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <drm/drm_plane_helper.h>
30 #include <drm/drm_dp_helper.h>
32 #include <nvif/class.h>
34 #include "nouveau_drm.h"
35 #include "nouveau_dma.h"
36 #include "nouveau_gem.h"
37 #include "nouveau_connector.h"
38 #include "nouveau_encoder.h"
39 #include "nouveau_crtc.h"
40 #include "nouveau_fence.h"
41 #include "nv50_display.h"
45 #define EVO_MASTER (0x00)
46 #define EVO_FLIP(c) (0x01 + (c))
47 #define EVO_OVLY(c) (0x05 + (c))
48 #define EVO_OIMM(c) (0x09 + (c))
49 #define EVO_CURS(c) (0x0d + (c))
51 /* offsets in shared sync bo of various structures */
52 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
53 #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
54 #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
55 #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
57 /******************************************************************************
59 *****************************************************************************/
62 struct nvif_object user;
66 nv50_chan_create(struct nvif_object *disp, const u32 *oclass, u8 head,
67 void *data, u32 size, struct nv50_chan *chan)
69 const u32 handle = (oclass[0] << 16) | head;
73 ret = nvif_object_sclass(disp, sclass, ARRAY_SIZE(sclass));
74 WARN_ON(ret > ARRAY_SIZE(sclass));
79 for (i = 0; i < ARRAY_SIZE(sclass); i++) {
80 if (sclass[i] == oclass[0]) {
81 ret = nvif_object_init(disp, NULL, handle,
82 oclass[0], data, size,
85 nvif_object_map(&chan->user);
96 nv50_chan_destroy(struct nv50_chan *chan)
98 nvif_object_fini(&chan->user);
101 /******************************************************************************
103 *****************************************************************************/
106 struct nv50_chan base;
110 nv50_pioc_destroy(struct nv50_pioc *pioc)
112 nv50_chan_destroy(&pioc->base);
116 nv50_pioc_create(struct nvif_object *disp, const u32 *oclass, u8 head,
117 void *data, u32 size, struct nv50_pioc *pioc)
119 return nv50_chan_create(disp, oclass, head, data, size, &pioc->base);
122 /******************************************************************************
124 *****************************************************************************/
127 struct nv50_pioc base;
128 struct nouveau_bo *image;
132 nv50_curs_create(struct nvif_object *disp, int head, struct nv50_curs *curs)
134 struct nv50_disp_cursor_v0 args = {
137 static const u32 oclass[] = {
146 return nv50_pioc_create(disp, oclass, head, &args, sizeof(args),
150 /******************************************************************************
152 *****************************************************************************/
155 struct nv50_pioc base;
159 nv50_oimm_create(struct nvif_object *disp, int head, struct nv50_oimm *oimm)
161 struct nv50_disp_cursor_v0 args = {
164 static const u32 oclass[] = {
173 return nv50_pioc_create(disp, oclass, head, &args, sizeof(args),
177 /******************************************************************************
179 *****************************************************************************/
182 struct nv50_chan base;
186 struct nvif_object sync;
187 struct nvif_object vram;
189 /* Protects against concurrent pushbuf access to this channel, lock is
190 * grabbed by evo_wait (if the pushbuf reservation is successful) and
191 * dropped again by evo_kick. */
196 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
198 nvif_object_fini(&dmac->vram);
199 nvif_object_fini(&dmac->sync);
201 nv50_chan_destroy(&dmac->base);
204 struct pci_dev *pdev = nvkm_device(nvif_device(disp))->pdev;
205 pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
210 nv50_dmac_create(struct nvif_object *disp, const u32 *oclass, u8 head,
211 void *data, u32 size, u64 syncbuf,
212 struct nv50_dmac *dmac)
214 struct nvif_device *device = nvif_device(disp);
215 struct nv50_disp_core_channel_dma_v0 *args = data;
216 struct nvif_object pushbuf;
219 mutex_init(&dmac->lock);
221 dmac->ptr = pci_alloc_consistent(nvkm_device(device)->pdev,
222 PAGE_SIZE, &dmac->handle);
226 ret = nvif_object_init(nvif_object(device), NULL,
227 args->pushbuf, NV_DMA_FROM_MEMORY,
228 &(struct nv_dma_v0) {
229 .target = NV_DMA_V0_TARGET_PCI_US,
230 .access = NV_DMA_V0_ACCESS_RD,
231 .start = dmac->handle + 0x0000,
232 .limit = dmac->handle + 0x0fff,
233 }, sizeof(struct nv_dma_v0), &pushbuf);
237 ret = nv50_chan_create(disp, oclass, head, data, size, &dmac->base);
238 nvif_object_fini(&pushbuf);
242 ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000000,
244 &(struct nv_dma_v0) {
245 .target = NV_DMA_V0_TARGET_VRAM,
246 .access = NV_DMA_V0_ACCESS_RDWR,
247 .start = syncbuf + 0x0000,
248 .limit = syncbuf + 0x0fff,
249 }, sizeof(struct nv_dma_v0),
254 ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000001,
256 &(struct nv_dma_v0) {
257 .target = NV_DMA_V0_TARGET_VRAM,
258 .access = NV_DMA_V0_ACCESS_RDWR,
260 .limit = device->info.ram_user - 1,
261 }, sizeof(struct nv_dma_v0),
269 /******************************************************************************
271 *****************************************************************************/
274 struct nv50_dmac base;
278 nv50_core_create(struct nvif_object *disp, u64 syncbuf, struct nv50_mast *core)
280 struct nv50_disp_core_channel_dma_v0 args = {
281 .pushbuf = 0xb0007d00,
283 static const u32 oclass[] = {
284 GM204_DISP_CORE_CHANNEL_DMA,
285 GM107_DISP_CORE_CHANNEL_DMA,
286 GK110_DISP_CORE_CHANNEL_DMA,
287 GK104_DISP_CORE_CHANNEL_DMA,
288 GF110_DISP_CORE_CHANNEL_DMA,
289 GT214_DISP_CORE_CHANNEL_DMA,
290 GT206_DISP_CORE_CHANNEL_DMA,
291 GT200_DISP_CORE_CHANNEL_DMA,
292 G82_DISP_CORE_CHANNEL_DMA,
293 NV50_DISP_CORE_CHANNEL_DMA,
297 return nv50_dmac_create(disp, oclass, 0, &args, sizeof(args), syncbuf,
301 /******************************************************************************
303 *****************************************************************************/
306 struct nv50_dmac base;
312 nv50_base_create(struct nvif_object *disp, int head, u64 syncbuf,
313 struct nv50_sync *base)
315 struct nv50_disp_base_channel_dma_v0 args = {
316 .pushbuf = 0xb0007c00 | head,
319 static const u32 oclass[] = {
320 GK110_DISP_BASE_CHANNEL_DMA,
321 GK104_DISP_BASE_CHANNEL_DMA,
322 GF110_DISP_BASE_CHANNEL_DMA,
323 GT214_DISP_BASE_CHANNEL_DMA,
324 GT200_DISP_BASE_CHANNEL_DMA,
325 G82_DISP_BASE_CHANNEL_DMA,
326 NV50_DISP_BASE_CHANNEL_DMA,
330 return nv50_dmac_create(disp, oclass, head, &args, sizeof(args),
331 syncbuf, &base->base);
334 /******************************************************************************
336 *****************************************************************************/
339 struct nv50_dmac base;
343 nv50_ovly_create(struct nvif_object *disp, int head, u64 syncbuf,
344 struct nv50_ovly *ovly)
346 struct nv50_disp_overlay_channel_dma_v0 args = {
347 .pushbuf = 0xb0007e00 | head,
350 static const u32 oclass[] = {
351 GK104_DISP_OVERLAY_CONTROL_DMA,
352 GF110_DISP_OVERLAY_CONTROL_DMA,
353 GT214_DISP_OVERLAY_CHANNEL_DMA,
354 GT200_DISP_OVERLAY_CHANNEL_DMA,
355 G82_DISP_OVERLAY_CHANNEL_DMA,
356 NV50_DISP_OVERLAY_CHANNEL_DMA,
360 return nv50_dmac_create(disp, oclass, head, &args, sizeof(args),
361 syncbuf, &ovly->base);
365 struct nouveau_crtc base;
366 struct nouveau_bo *image;
367 struct nv50_curs curs;
368 struct nv50_sync sync;
369 struct nv50_ovly ovly;
370 struct nv50_oimm oimm;
373 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
374 #define nv50_curs(c) (&nv50_head(c)->curs)
375 #define nv50_sync(c) (&nv50_head(c)->sync)
376 #define nv50_ovly(c) (&nv50_head(c)->ovly)
377 #define nv50_oimm(c) (&nv50_head(c)->oimm)
378 #define nv50_chan(c) (&(c)->base.base)
379 #define nv50_vers(c) nv50_chan(c)->user.oclass
382 struct list_head head;
383 struct nvif_object core;
384 struct nvif_object base[4];
388 struct nvif_object *disp;
389 struct nv50_mast mast;
391 struct list_head fbdma;
393 struct nouveau_bo *sync;
396 static struct nv50_disp *
397 nv50_disp(struct drm_device *dev)
399 return nouveau_display(dev)->priv;
402 #define nv50_mast(d) (&nv50_disp(d)->mast)
404 static struct drm_crtc *
405 nv50_display_crtc_get(struct drm_encoder *encoder)
407 return nouveau_encoder(encoder)->crtc;
410 /******************************************************************************
411 * EVO channel helpers
412 *****************************************************************************/
414 evo_wait(void *evoc, int nr)
416 struct nv50_dmac *dmac = evoc;
417 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
419 mutex_lock(&dmac->lock);
420 if (put + nr >= (PAGE_SIZE / 4) - 8) {
421 dmac->ptr[put] = 0x20000000;
423 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
424 if (!nvkm_wait(&dmac->base.user, 0x0004, ~0, 0x00000000)) {
425 mutex_unlock(&dmac->lock);
426 nv_error(nvkm_object(&dmac->base.user), "channel stalled\n");
433 return dmac->ptr + put;
437 evo_kick(u32 *push, void *evoc)
439 struct nv50_dmac *dmac = evoc;
440 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
441 mutex_unlock(&dmac->lock);
445 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
446 #define evo_data(p,d) *((p)++) = (d)
448 #define evo_mthd(p,m,s) do { \
449 const u32 _m = (m), _s = (s); \
450 printk(KERN_ERR "%04x %d %s\n", _m, _s, __func__); \
451 *((p)++) = ((_s << 18) | _m); \
453 #define evo_data(p,d) do { \
454 const u32 _d = (d); \
455 printk(KERN_ERR "\t%08x\n", _d); \
461 evo_sync_wait(void *data)
463 if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
470 evo_sync(struct drm_device *dev)
472 struct nvif_device *device = &nouveau_drm(dev)->device;
473 struct nv50_disp *disp = nv50_disp(dev);
474 struct nv50_mast *mast = nv50_mast(dev);
475 u32 *push = evo_wait(mast, 8);
477 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
478 evo_mthd(push, 0x0084, 1);
479 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
480 evo_mthd(push, 0x0080, 2);
481 evo_data(push, 0x00000000);
482 evo_data(push, 0x00000000);
483 evo_kick(push, mast);
484 if (nv_wait_cb(nvkm_device(device), evo_sync_wait, disp->sync))
491 /******************************************************************************
492 * Page flipping channel
493 *****************************************************************************/
495 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
497 return nv50_disp(dev)->sync;
500 struct nv50_display_flip {
501 struct nv50_disp *disp;
502 struct nv50_sync *chan;
506 nv50_display_flip_wait(void *data)
508 struct nv50_display_flip *flip = data;
509 if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
517 nv50_display_flip_stop(struct drm_crtc *crtc)
519 struct nvif_device *device = &nouveau_drm(crtc->dev)->device;
520 struct nv50_display_flip flip = {
521 .disp = nv50_disp(crtc->dev),
522 .chan = nv50_sync(crtc),
526 push = evo_wait(flip.chan, 8);
528 evo_mthd(push, 0x0084, 1);
529 evo_data(push, 0x00000000);
530 evo_mthd(push, 0x0094, 1);
531 evo_data(push, 0x00000000);
532 evo_mthd(push, 0x00c0, 1);
533 evo_data(push, 0x00000000);
534 evo_mthd(push, 0x0080, 1);
535 evo_data(push, 0x00000000);
536 evo_kick(push, flip.chan);
539 nv_wait_cb(nvkm_device(device), nv50_display_flip_wait, &flip);
543 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
544 struct nouveau_channel *chan, u32 swap_interval)
546 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
547 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
548 struct nv50_head *head = nv50_head(crtc);
549 struct nv50_sync *sync = nv50_sync(crtc);
554 if (swap_interval == 0)
555 swap_interval |= 0x100;
559 push = evo_wait(sync, 128);
560 if (unlikely(push == NULL))
563 if (chan && chan->object->oclass < G82_CHANNEL_GPFIFO) {
564 ret = RING_SPACE(chan, 8);
568 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
569 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
570 OUT_RING (chan, sync->addr ^ 0x10);
571 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
572 OUT_RING (chan, sync->data + 1);
573 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
574 OUT_RING (chan, sync->addr);
575 OUT_RING (chan, sync->data);
577 if (chan && chan->object->oclass < FERMI_CHANNEL_GPFIFO) {
578 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
579 ret = RING_SPACE(chan, 12);
583 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
584 OUT_RING (chan, chan->vram.handle);
585 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
586 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
587 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
588 OUT_RING (chan, sync->data + 1);
589 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
590 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
591 OUT_RING (chan, upper_32_bits(addr));
592 OUT_RING (chan, lower_32_bits(addr));
593 OUT_RING (chan, sync->data);
594 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
597 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
598 ret = RING_SPACE(chan, 10);
602 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
603 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
604 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
605 OUT_RING (chan, sync->data + 1);
606 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
607 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
608 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
609 OUT_RING (chan, upper_32_bits(addr));
610 OUT_RING (chan, lower_32_bits(addr));
611 OUT_RING (chan, sync->data);
612 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
613 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
623 evo_mthd(push, 0x0100, 1);
624 evo_data(push, 0xfffe0000);
625 evo_mthd(push, 0x0084, 1);
626 evo_data(push, swap_interval);
627 if (!(swap_interval & 0x00000100)) {
628 evo_mthd(push, 0x00e0, 1);
629 evo_data(push, 0x40000000);
631 evo_mthd(push, 0x0088, 4);
632 evo_data(push, sync->addr);
633 evo_data(push, sync->data++);
634 evo_data(push, sync->data);
635 evo_data(push, sync->base.sync.handle);
636 evo_mthd(push, 0x00a0, 2);
637 evo_data(push, 0x00000000);
638 evo_data(push, 0x00000000);
639 evo_mthd(push, 0x00c0, 1);
640 evo_data(push, nv_fb->r_handle);
641 evo_mthd(push, 0x0110, 2);
642 evo_data(push, 0x00000000);
643 evo_data(push, 0x00000000);
644 if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) {
645 evo_mthd(push, 0x0800, 5);
646 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
648 evo_data(push, (fb->height << 16) | fb->width);
649 evo_data(push, nv_fb->r_pitch);
650 evo_data(push, nv_fb->r_format);
652 evo_mthd(push, 0x0400, 5);
653 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
655 evo_data(push, (fb->height << 16) | fb->width);
656 evo_data(push, nv_fb->r_pitch);
657 evo_data(push, nv_fb->r_format);
659 evo_mthd(push, 0x0080, 1);
660 evo_data(push, 0x00000000);
661 evo_kick(push, sync);
663 nouveau_bo_ref(nv_fb->nvbo, &head->image);
667 /******************************************************************************
669 *****************************************************************************/
671 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
673 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
674 struct nouveau_connector *nv_connector;
675 struct drm_connector *connector;
676 u32 *push, mode = 0x00;
678 nv_connector = nouveau_crtc_connector_get(nv_crtc);
679 connector = &nv_connector->base;
680 if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
681 if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3)
682 mode = DITHERING_MODE_DYNAMIC2X2;
684 mode = nv_connector->dithering_mode;
687 if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
688 if (connector->display_info.bpc >= 8)
689 mode |= DITHERING_DEPTH_8BPC;
691 mode |= nv_connector->dithering_depth;
694 push = evo_wait(mast, 4);
696 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
697 evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
698 evo_data(push, mode);
700 if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) {
701 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
702 evo_data(push, mode);
704 evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
705 evo_data(push, mode);
709 evo_mthd(push, 0x0080, 1);
710 evo_data(push, 0x00000000);
712 evo_kick(push, mast);
719 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
721 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
722 struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
723 struct drm_crtc *crtc = &nv_crtc->base;
724 struct nouveau_connector *nv_connector;
725 int mode = DRM_MODE_SCALE_NONE;
728 /* start off at the resolution we programmed the crtc for, this
729 * effectively handles NONE/FULL scaling
731 nv_connector = nouveau_crtc_connector_get(nv_crtc);
732 if (nv_connector && nv_connector->native_mode)
733 mode = nv_connector->scaling_mode;
735 if (mode != DRM_MODE_SCALE_NONE)
736 omode = nv_connector->native_mode;
740 oX = omode->hdisplay;
741 oY = omode->vdisplay;
742 if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
745 /* add overscan compensation if necessary, will keep the aspect
746 * ratio the same as the backend mode unless overridden by the
747 * user setting both hborder and vborder properties.
749 if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
750 (nv_connector->underscan == UNDERSCAN_AUTO &&
751 nv_connector->edid &&
752 drm_detect_hdmi_monitor(nv_connector->edid)))) {
753 u32 bX = nv_connector->underscan_hborder;
754 u32 bY = nv_connector->underscan_vborder;
755 u32 aspect = (oY << 19) / oX;
759 if (bY) oY -= (bY * 2);
760 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
762 oX -= (oX >> 4) + 32;
763 if (bY) oY -= (bY * 2);
764 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
768 /* handle CENTER/ASPECT scaling, taking into account the areas
769 * removed already for overscan compensation
772 case DRM_MODE_SCALE_CENTER:
773 oX = min((u32)umode->hdisplay, oX);
774 oY = min((u32)umode->vdisplay, oY);
776 case DRM_MODE_SCALE_ASPECT:
778 u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
779 oX = ((oY * aspect) + (aspect / 2)) >> 19;
781 u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
782 oY = ((oX * aspect) + (aspect / 2)) >> 19;
789 push = evo_wait(mast, 8);
791 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
792 /*XXX: SCALE_CTRL_ACTIVE??? */
793 evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
794 evo_data(push, (oY << 16) | oX);
795 evo_data(push, (oY << 16) | oX);
796 evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
797 evo_data(push, 0x00000000);
798 evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
799 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
801 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
802 evo_data(push, (oY << 16) | oX);
803 evo_data(push, (oY << 16) | oX);
804 evo_data(push, (oY << 16) | oX);
805 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
806 evo_data(push, 0x00000000);
807 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
808 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
811 evo_kick(push, mast);
814 nv50_display_flip_stop(crtc);
815 nv50_display_flip_next(crtc, crtc->primary->fb,
824 nv50_crtc_set_raster_vblank_dmi(struct nouveau_crtc *nv_crtc, u32 usec)
826 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
829 push = evo_wait(mast, 8);
833 evo_mthd(push, 0x0828 + (nv_crtc->index * 0x400), 1);
834 evo_data(push, usec);
835 evo_kick(push, mast);
840 nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
842 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
846 adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
847 vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
848 hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
850 push = evo_wait(mast, 16);
852 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
853 evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
854 evo_data(push, (hue << 20) | (vib << 8));
856 evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
857 evo_data(push, (hue << 20) | (vib << 8));
861 evo_mthd(push, 0x0080, 1);
862 evo_data(push, 0x00000000);
864 evo_kick(push, mast);
871 nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
872 int x, int y, bool update)
874 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
875 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
878 push = evo_wait(mast, 16);
880 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
881 evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
882 evo_data(push, nvfb->nvbo->bo.offset >> 8);
883 evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
884 evo_data(push, (fb->height << 16) | fb->width);
885 evo_data(push, nvfb->r_pitch);
886 evo_data(push, nvfb->r_format);
887 evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
888 evo_data(push, (y << 16) | x);
889 if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) {
890 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
891 evo_data(push, nvfb->r_handle);
894 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
895 evo_data(push, nvfb->nvbo->bo.offset >> 8);
896 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
897 evo_data(push, (fb->height << 16) | fb->width);
898 evo_data(push, nvfb->r_pitch);
899 evo_data(push, nvfb->r_format);
900 evo_data(push, nvfb->r_handle);
901 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
902 evo_data(push, (y << 16) | x);
906 evo_mthd(push, 0x0080, 1);
907 evo_data(push, 0x00000000);
909 evo_kick(push, mast);
912 nv_crtc->fb.handle = nvfb->r_handle;
917 nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
919 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
920 struct nv50_curs *curs = nv50_curs(&nv_crtc->base);
921 u32 *push = evo_wait(mast, 16);
923 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
924 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
925 evo_data(push, 0x85000000);
926 evo_data(push, curs->image->bo.offset >> 8);
928 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
929 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
930 evo_data(push, 0x85000000);
931 evo_data(push, curs->image->bo.offset >> 8);
932 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
933 evo_data(push, mast->base.vram.handle);
935 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
936 evo_data(push, 0x85000000);
937 evo_data(push, curs->image->bo.offset >> 8);
938 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
939 evo_data(push, mast->base.vram.handle);
941 evo_kick(push, mast);
946 nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
948 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
949 u32 *push = evo_wait(mast, 16);
951 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
952 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
953 evo_data(push, 0x05000000);
955 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
956 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
957 evo_data(push, 0x05000000);
958 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
959 evo_data(push, 0x00000000);
961 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
962 evo_data(push, 0x05000000);
963 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
964 evo_data(push, 0x00000000);
966 evo_kick(push, mast);
971 nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
973 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
974 struct nv50_curs *curs = nv50_curs(&nv_crtc->base);
976 if (show && curs->image)
977 nv50_crtc_cursor_show(nv_crtc);
979 nv50_crtc_cursor_hide(nv_crtc);
982 u32 *push = evo_wait(mast, 2);
984 evo_mthd(push, 0x0080, 1);
985 evo_data(push, 0x00000000);
986 evo_kick(push, mast);
992 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
997 nv50_crtc_prepare(struct drm_crtc *crtc)
999 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1000 struct nv50_mast *mast = nv50_mast(crtc->dev);
1003 nv50_display_flip_stop(crtc);
1005 push = evo_wait(mast, 6);
1007 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
1008 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1009 evo_data(push, 0x00000000);
1010 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
1011 evo_data(push, 0x40000000);
1013 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1014 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1015 evo_data(push, 0x00000000);
1016 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
1017 evo_data(push, 0x40000000);
1018 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1019 evo_data(push, 0x00000000);
1021 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1022 evo_data(push, 0x00000000);
1023 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
1024 evo_data(push, 0x03000000);
1025 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1026 evo_data(push, 0x00000000);
1029 evo_kick(push, mast);
1032 nv50_crtc_cursor_show_hide(nv_crtc, false, false);
1036 nv50_crtc_commit(struct drm_crtc *crtc)
1038 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1039 struct nv50_mast *mast = nv50_mast(crtc->dev);
1042 push = evo_wait(mast, 32);
1044 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
1045 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1046 evo_data(push, nv_crtc->fb.handle);
1047 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1048 evo_data(push, 0xc0000000);
1049 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1051 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1052 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1053 evo_data(push, nv_crtc->fb.handle);
1054 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1055 evo_data(push, 0xc0000000);
1056 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1057 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1058 evo_data(push, mast->base.vram.handle);
1060 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1061 evo_data(push, nv_crtc->fb.handle);
1062 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
1063 evo_data(push, 0x83000000);
1064 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1065 evo_data(push, 0x00000000);
1066 evo_data(push, 0x00000000);
1067 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1068 evo_data(push, mast->base.vram.handle);
1069 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
1070 evo_data(push, 0xffffff00);
1073 evo_kick(push, mast);
1076 nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1077 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1081 nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1082 struct drm_display_mode *adjusted_mode)
1084 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
1089 nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
1091 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
1092 struct nv50_head *head = nv50_head(crtc);
1095 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, true);
1098 nouveau_bo_unpin(head->image);
1099 nouveau_bo_ref(nvfb->nvbo, &head->image);
1106 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1107 struct drm_display_mode *mode, int x, int y,
1108 struct drm_framebuffer *old_fb)
1110 struct nv50_mast *mast = nv50_mast(crtc->dev);
1111 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1112 struct nouveau_connector *nv_connector;
1113 u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1114 u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1115 u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1116 u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1117 u32 vblan2e = 0, vblan2s = 1, vblankus = 0;
1121 hactive = mode->htotal;
1122 hsynce = mode->hsync_end - mode->hsync_start - 1;
1123 hbackp = mode->htotal - mode->hsync_end;
1124 hblanke = hsynce + hbackp;
1125 hfrontp = mode->hsync_start - mode->hdisplay;
1126 hblanks = mode->htotal - hfrontp - 1;
1128 vactive = mode->vtotal * vscan / ilace;
1129 vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1130 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1131 vblanke = vsynce + vbackp;
1132 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1133 vblanks = vactive - vfrontp - 1;
1134 /* XXX: Safe underestimate, even "0" works */
1135 vblankus = (vactive - mode->vdisplay - 2) * hactive;
1137 vblankus /= mode->clock;
1139 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1140 vblan2e = vactive + vsynce + vbackp;
1141 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1142 vactive = (vactive * 2) + 1;
1145 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1149 push = evo_wait(mast, 64);
1151 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1152 evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1153 evo_data(push, 0x00800000 | mode->clock);
1154 evo_data(push, (ilace == 2) ? 2 : 0);
1155 evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
1156 evo_data(push, 0x00000000);
1157 evo_data(push, (vactive << 16) | hactive);
1158 evo_data(push, ( vsynce << 16) | hsynce);
1159 evo_data(push, (vblanke << 16) | hblanke);
1160 evo_data(push, (vblanks << 16) | hblanks);
1161 evo_data(push, (vblan2e << 16) | vblan2s);
1162 evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
1163 evo_data(push, 0x00000000);
1164 evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1165 evo_data(push, 0x00000311);
1166 evo_data(push, 0x00000100);
1168 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1169 evo_data(push, 0x00000000);
1170 evo_data(push, (vactive << 16) | hactive);
1171 evo_data(push, ( vsynce << 16) | hsynce);
1172 evo_data(push, (vblanke << 16) | hblanke);
1173 evo_data(push, (vblanks << 16) | hblanks);
1174 evo_data(push, (vblan2e << 16) | vblan2s);
1175 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1176 evo_data(push, 0x00000000); /* ??? */
1177 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1178 evo_data(push, mode->clock * 1000);
1179 evo_data(push, 0x00200000); /* ??? */
1180 evo_data(push, mode->clock * 1000);
1181 evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1182 evo_data(push, 0x00000311);
1183 evo_data(push, 0x00000100);
1186 evo_kick(push, mast);
1189 nv_connector = nouveau_crtc_connector_get(nv_crtc);
1190 nv50_crtc_set_dither(nv_crtc, false);
1191 nv50_crtc_set_scale(nv_crtc, false);
1193 /* G94 only accepts this after setting scale */
1194 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA)
1195 nv50_crtc_set_raster_vblank_dmi(nv_crtc, vblankus);
1197 nv50_crtc_set_color_vibrance(nv_crtc, false);
1198 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false);
1203 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1204 struct drm_framebuffer *old_fb)
1206 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1207 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1210 if (!crtc->primary->fb) {
1211 NV_DEBUG(drm, "No FB bound\n");
1215 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1219 nv50_display_flip_stop(crtc);
1220 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true);
1221 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1226 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1227 struct drm_framebuffer *fb, int x, int y,
1228 enum mode_set_atomic state)
1230 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1231 nv50_display_flip_stop(crtc);
1232 nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1237 nv50_crtc_lut_load(struct drm_crtc *crtc)
1239 struct nv50_disp *disp = nv50_disp(crtc->dev);
1240 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1241 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1244 for (i = 0; i < 256; i++) {
1245 u16 r = nv_crtc->lut.r[i] >> 2;
1246 u16 g = nv_crtc->lut.g[i] >> 2;
1247 u16 b = nv_crtc->lut.b[i] >> 2;
1249 if (disp->disp->oclass < GF110_DISP) {
1250 writew(r + 0x0000, lut + (i * 0x08) + 0);
1251 writew(g + 0x0000, lut + (i * 0x08) + 2);
1252 writew(b + 0x0000, lut + (i * 0x08) + 4);
1254 writew(r + 0x6000, lut + (i * 0x20) + 0);
1255 writew(g + 0x6000, lut + (i * 0x20) + 2);
1256 writew(b + 0x6000, lut + (i * 0x20) + 4);
1262 nv50_crtc_disable(struct drm_crtc *crtc)
1264 struct nv50_head *head = nv50_head(crtc);
1265 evo_sync(crtc->dev);
1267 nouveau_bo_unpin(head->image);
1268 nouveau_bo_ref(NULL, &head->image);
1272 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1273 uint32_t handle, uint32_t width, uint32_t height)
1275 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1276 struct nv50_curs *curs = nv50_curs(crtc);
1277 struct drm_device *dev = crtc->dev;
1278 struct drm_gem_object *gem = NULL;
1279 struct nouveau_bo *nvbo = NULL;
1283 if (width != 64 || height != 64)
1286 gem = drm_gem_object_lookup(dev, file_priv, handle);
1289 nvbo = nouveau_gem_object(gem);
1291 ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, true);
1296 nouveau_bo_unpin(curs->image);
1297 nouveau_bo_ref(nvbo, &curs->image);
1299 drm_gem_object_unreference_unlocked(gem);
1301 nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1306 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1308 struct nv50_curs *curs = nv50_curs(crtc);
1309 struct nv50_chan *chan = nv50_chan(curs);
1310 nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff));
1311 nvif_wr32(&chan->user, 0x0080, 0x00000000);
1316 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1317 uint32_t start, uint32_t size)
1319 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1320 u32 end = min_t(u32, start + size, 256);
1323 for (i = start; i < end; i++) {
1324 nv_crtc->lut.r[i] = r[i];
1325 nv_crtc->lut.g[i] = g[i];
1326 nv_crtc->lut.b[i] = b[i];
1329 nv50_crtc_lut_load(crtc);
1333 nv50_crtc_destroy(struct drm_crtc *crtc)
1335 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1336 struct nv50_disp *disp = nv50_disp(crtc->dev);
1337 struct nv50_head *head = nv50_head(crtc);
1338 struct nv50_fbdma *fbdma;
1340 list_for_each_entry(fbdma, &disp->fbdma, head) {
1341 nvif_object_fini(&fbdma->base[nv_crtc->index]);
1344 nv50_dmac_destroy(&head->ovly.base, disp->disp);
1345 nv50_pioc_destroy(&head->oimm.base);
1346 nv50_dmac_destroy(&head->sync.base, disp->disp);
1347 nv50_pioc_destroy(&head->curs.base);
1349 /*XXX: this shouldn't be necessary, but the core doesn't call
1350 * disconnect() during the cleanup paths
1353 nouveau_bo_unpin(head->image);
1354 nouveau_bo_ref(NULL, &head->image);
1357 if (head->curs.image)
1358 nouveau_bo_unpin(head->curs.image);
1359 nouveau_bo_ref(NULL, &head->curs.image);
1361 nouveau_bo_unmap(nv_crtc->lut.nvbo);
1362 if (nv_crtc->lut.nvbo)
1363 nouveau_bo_unpin(nv_crtc->lut.nvbo);
1364 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
1366 drm_crtc_cleanup(crtc);
1370 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1371 .dpms = nv50_crtc_dpms,
1372 .prepare = nv50_crtc_prepare,
1373 .commit = nv50_crtc_commit,
1374 .mode_fixup = nv50_crtc_mode_fixup,
1375 .mode_set = nv50_crtc_mode_set,
1376 .mode_set_base = nv50_crtc_mode_set_base,
1377 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1378 .load_lut = nv50_crtc_lut_load,
1379 .disable = nv50_crtc_disable,
1382 static const struct drm_crtc_funcs nv50_crtc_func = {
1383 .cursor_set = nv50_crtc_cursor_set,
1384 .cursor_move = nv50_crtc_cursor_move,
1385 .gamma_set = nv50_crtc_gamma_set,
1386 .set_config = nouveau_crtc_set_config,
1387 .destroy = nv50_crtc_destroy,
1388 .page_flip = nouveau_crtc_page_flip,
1392 nv50_crtc_create(struct drm_device *dev, int index)
1394 struct nv50_disp *disp = nv50_disp(dev);
1395 struct nv50_head *head;
1396 struct drm_crtc *crtc;
1399 head = kzalloc(sizeof(*head), GFP_KERNEL);
1403 head->base.index = index;
1404 head->base.set_dither = nv50_crtc_set_dither;
1405 head->base.set_scale = nv50_crtc_set_scale;
1406 head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
1407 head->base.color_vibrance = 50;
1408 head->base.vibrant_hue = 0;
1409 for (i = 0; i < 256; i++) {
1410 head->base.lut.r[i] = i << 8;
1411 head->base.lut.g[i] = i << 8;
1412 head->base.lut.b[i] = i << 8;
1415 crtc = &head->base.base;
1416 drm_crtc_init(dev, crtc, &nv50_crtc_func);
1417 drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1418 drm_mode_crtc_set_gamma_size(crtc, 256);
1420 ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1421 0, 0x0000, NULL, NULL, &head->base.lut.nvbo);
1423 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true);
1425 ret = nouveau_bo_map(head->base.lut.nvbo);
1427 nouveau_bo_unpin(head->base.lut.nvbo);
1430 nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1436 nv50_crtc_lut_load(crtc);
1438 /* allocate cursor resources */
1439 ret = nv50_curs_create(disp->disp, index, &head->curs);
1443 /* allocate page flip / sync resources */
1444 ret = nv50_base_create(disp->disp, index, disp->sync->bo.offset,
1449 head->sync.addr = EVO_FLIP_SEM0(index);
1450 head->sync.data = 0x00000000;
1452 /* allocate overlay resources */
1453 ret = nv50_oimm_create(disp->disp, index, &head->oimm);
1457 ret = nv50_ovly_create(disp->disp, index, disp->sync->bo.offset,
1464 nv50_crtc_destroy(crtc);
1468 /******************************************************************************
1470 *****************************************************************************/
1472 nv50_encoder_mode_fixup(struct drm_encoder *encoder,
1473 const struct drm_display_mode *mode,
1474 struct drm_display_mode *adjusted_mode)
1476 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1477 struct nouveau_connector *nv_connector;
1479 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1480 if (nv_connector && nv_connector->native_mode) {
1481 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE)
1482 drm_mode_copy(adjusted_mode, nv_connector->native_mode);
1488 /******************************************************************************
1490 *****************************************************************************/
1492 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1494 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1495 struct nv50_disp *disp = nv50_disp(encoder->dev);
1497 struct nv50_disp_mthd_v1 base;
1498 struct nv50_disp_dac_pwr_v0 pwr;
1501 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
1502 .base.hasht = nv_encoder->dcb->hasht,
1503 .base.hashm = nv_encoder->dcb->hashm,
1506 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
1507 mode != DRM_MODE_DPMS_OFF),
1508 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
1509 mode != DRM_MODE_DPMS_OFF),
1512 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1516 nv50_dac_commit(struct drm_encoder *encoder)
1521 nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1522 struct drm_display_mode *adjusted_mode)
1524 struct nv50_mast *mast = nv50_mast(encoder->dev);
1525 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1526 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1529 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1531 push = evo_wait(mast, 8);
1533 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1534 u32 syncs = 0x00000000;
1536 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1537 syncs |= 0x00000001;
1538 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1539 syncs |= 0x00000002;
1541 evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1542 evo_data(push, 1 << nv_crtc->index);
1543 evo_data(push, syncs);
1545 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1546 u32 syncs = 0x00000001;
1548 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1549 syncs |= 0x00000008;
1550 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1551 syncs |= 0x00000010;
1553 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1554 magic |= 0x00000001;
1556 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1557 evo_data(push, syncs);
1558 evo_data(push, magic);
1559 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1560 evo_data(push, 1 << nv_crtc->index);
1563 evo_kick(push, mast);
1566 nv_encoder->crtc = encoder->crtc;
1570 nv50_dac_disconnect(struct drm_encoder *encoder)
1572 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1573 struct nv50_mast *mast = nv50_mast(encoder->dev);
1574 const int or = nv_encoder->or;
1577 if (nv_encoder->crtc) {
1578 nv50_crtc_prepare(nv_encoder->crtc);
1580 push = evo_wait(mast, 4);
1582 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1583 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1584 evo_data(push, 0x00000000);
1586 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1587 evo_data(push, 0x00000000);
1589 evo_kick(push, mast);
1593 nv_encoder->crtc = NULL;
1596 static enum drm_connector_status
1597 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1599 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1600 struct nv50_disp *disp = nv50_disp(encoder->dev);
1602 struct nv50_disp_mthd_v1 base;
1603 struct nv50_disp_dac_load_v0 load;
1606 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
1607 .base.hasht = nv_encoder->dcb->hasht,
1608 .base.hashm = nv_encoder->dcb->hashm,
1612 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
1613 if (args.load.data == 0)
1614 args.load.data = 340;
1616 ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
1617 if (ret || !args.load.load)
1618 return connector_status_disconnected;
1620 return connector_status_connected;
1624 nv50_dac_destroy(struct drm_encoder *encoder)
1626 drm_encoder_cleanup(encoder);
1630 static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1631 .dpms = nv50_dac_dpms,
1632 .mode_fixup = nv50_encoder_mode_fixup,
1633 .prepare = nv50_dac_disconnect,
1634 .commit = nv50_dac_commit,
1635 .mode_set = nv50_dac_mode_set,
1636 .disable = nv50_dac_disconnect,
1637 .get_crtc = nv50_display_crtc_get,
1638 .detect = nv50_dac_detect
1641 static const struct drm_encoder_funcs nv50_dac_func = {
1642 .destroy = nv50_dac_destroy,
1646 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1648 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1649 struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
1650 struct nouveau_encoder *nv_encoder;
1651 struct drm_encoder *encoder;
1652 int type = DRM_MODE_ENCODER_DAC;
1654 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1657 nv_encoder->dcb = dcbe;
1658 nv_encoder->or = ffs(dcbe->or) - 1;
1659 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1661 encoder = to_drm_encoder(nv_encoder);
1662 encoder->possible_crtcs = dcbe->heads;
1663 encoder->possible_clones = 0;
1664 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type);
1665 drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
1667 drm_mode_connector_attach_encoder(connector, encoder);
1671 /******************************************************************************
1673 *****************************************************************************/
1675 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1677 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1678 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1679 struct nouveau_connector *nv_connector;
1680 struct nv50_disp *disp = nv50_disp(encoder->dev);
1683 struct nv50_disp_mthd_v1 mthd;
1684 struct nv50_disp_sor_hda_eld_v0 eld;
1686 u8 data[sizeof(nv_connector->base.eld)];
1688 .base.mthd.version = 1,
1689 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1690 .base.mthd.hasht = nv_encoder->dcb->hasht,
1691 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1692 (0x0100 << nv_crtc->index),
1695 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1696 if (!drm_detect_monitor_audio(nv_connector->edid))
1699 drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1700 memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
1702 nvif_mthd(disp->disp, 0, &args,
1703 sizeof(args.base) + drm_eld_size(args.data));
1707 nv50_audio_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1709 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1710 struct nv50_disp *disp = nv50_disp(encoder->dev);
1712 struct nv50_disp_mthd_v1 base;
1713 struct nv50_disp_sor_hda_eld_v0 eld;
1716 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1717 .base.hasht = nv_encoder->dcb->hasht,
1718 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1719 (0x0100 << nv_crtc->index),
1722 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1725 /******************************************************************************
1727 *****************************************************************************/
1729 nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1731 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1732 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1733 struct nv50_disp *disp = nv50_disp(encoder->dev);
1735 struct nv50_disp_mthd_v1 base;
1736 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1739 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1740 .base.hasht = nv_encoder->dcb->hasht,
1741 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1742 (0x0100 << nv_crtc->index),
1744 .pwr.rekey = 56, /* binary driver, and tegra, constant */
1746 struct nouveau_connector *nv_connector;
1749 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1750 if (!drm_detect_hdmi_monitor(nv_connector->edid))
1753 max_ac_packet = mode->htotal - mode->hdisplay;
1754 max_ac_packet -= args.pwr.rekey;
1755 max_ac_packet -= 18; /* constant from tegra */
1756 args.pwr.max_ac_packet = max_ac_packet / 32;
1758 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1759 nv50_audio_mode_set(encoder, mode);
1763 nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1765 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1766 struct nv50_disp *disp = nv50_disp(encoder->dev);
1768 struct nv50_disp_mthd_v1 base;
1769 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1772 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1773 .base.hasht = nv_encoder->dcb->hasht,
1774 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1775 (0x0100 << nv_crtc->index),
1778 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1781 /******************************************************************************
1783 *****************************************************************************/
1785 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
1787 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1788 struct nv50_disp *disp = nv50_disp(encoder->dev);
1790 struct nv50_disp_mthd_v1 base;
1791 struct nv50_disp_sor_pwr_v0 pwr;
1794 .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
1795 .base.hasht = nv_encoder->dcb->hasht,
1796 .base.hashm = nv_encoder->dcb->hashm,
1797 .pwr.state = mode == DRM_MODE_DPMS_ON,
1800 struct nv50_disp_mthd_v1 base;
1801 struct nv50_disp_sor_dp_pwr_v0 pwr;
1804 .base.method = NV50_DISP_MTHD_V1_SOR_DP_PWR,
1805 .base.hasht = nv_encoder->dcb->hasht,
1806 .base.hashm = nv_encoder->dcb->hashm,
1807 .pwr.state = mode == DRM_MODE_DPMS_ON,
1809 struct drm_device *dev = encoder->dev;
1810 struct drm_encoder *partner;
1812 nv_encoder->last_dpms = mode;
1814 list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1815 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1817 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1820 if (nv_partner != nv_encoder &&
1821 nv_partner->dcb->or == nv_encoder->dcb->or) {
1822 if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1828 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1830 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1831 nvif_mthd(disp->disp, 0, &link, sizeof(link));
1833 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1838 nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data)
1840 struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev);
1841 u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push;
1842 if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) {
1843 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1844 evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
1845 evo_data(push, (nv_encoder->ctrl = temp));
1847 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
1848 evo_data(push, (nv_encoder->ctrl = temp));
1850 evo_kick(push, mast);
1855 nv50_sor_disconnect(struct drm_encoder *encoder)
1857 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1858 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1860 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1861 nv_encoder->crtc = NULL;
1864 nv50_crtc_prepare(&nv_crtc->base);
1865 nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0);
1866 nv50_audio_disconnect(encoder, nv_crtc);
1867 nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc);
1872 nv50_sor_commit(struct drm_encoder *encoder)
1877 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1878 struct drm_display_mode *mode)
1880 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1881 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1883 struct nv50_disp_mthd_v1 base;
1884 struct nv50_disp_sor_lvds_script_v0 lvds;
1887 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1888 .base.hasht = nv_encoder->dcb->hasht,
1889 .base.hashm = nv_encoder->dcb->hashm,
1891 struct nv50_disp *disp = nv50_disp(encoder->dev);
1892 struct nv50_mast *mast = nv50_mast(encoder->dev);
1893 struct drm_device *dev = encoder->dev;
1894 struct nouveau_drm *drm = nouveau_drm(dev);
1895 struct nouveau_connector *nv_connector;
1896 struct nvbios *bios = &drm->vbios;
1898 u8 owner = 1 << nv_crtc->index;
1902 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1903 nv_encoder->crtc = encoder->crtc;
1905 switch (nv_encoder->dcb->type) {
1906 case DCB_OUTPUT_TMDS:
1907 if (nv_encoder->dcb->sorconf.link & 1) {
1908 if (mode->clock < 165000)
1916 nv50_hdmi_mode_set(&nv_encoder->base.base, mode);
1918 case DCB_OUTPUT_LVDS:
1921 if (bios->fp_no_ddc) {
1922 if (bios->fp.dual_link)
1923 lvds.lvds.script |= 0x0100;
1924 if (bios->fp.if_is_24bit)
1925 lvds.lvds.script |= 0x0200;
1927 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1928 if (((u8 *)nv_connector->edid)[121] == 2)
1929 lvds.lvds.script |= 0x0100;
1931 if (mode->clock >= bios->fp.duallink_transition_clk) {
1932 lvds.lvds.script |= 0x0100;
1935 if (lvds.lvds.script & 0x0100) {
1936 if (bios->fp.strapless_is_24bit & 2)
1937 lvds.lvds.script |= 0x0200;
1939 if (bios->fp.strapless_is_24bit & 1)
1940 lvds.lvds.script |= 0x0200;
1943 if (nv_connector->base.display_info.bpc == 8)
1944 lvds.lvds.script |= 0x0200;
1947 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
1950 if (nv_connector->base.display_info.bpc == 6) {
1951 nv_encoder->dp.datarate = mode->clock * 18 / 8;
1954 if (nv_connector->base.display_info.bpc == 8) {
1955 nv_encoder->dp.datarate = mode->clock * 24 / 8;
1958 nv_encoder->dp.datarate = mode->clock * 30 / 8;
1962 if (nv_encoder->dcb->sorconf.link & 1)
1966 nv50_audio_mode_set(encoder, mode);
1973 nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON);
1975 if (nv50_vers(mast) >= GF110_DISP) {
1976 u32 *push = evo_wait(mast, 3);
1978 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1979 u32 syncs = 0x00000001;
1981 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1982 syncs |= 0x00000008;
1983 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1984 syncs |= 0x00000010;
1986 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1987 magic |= 0x00000001;
1989 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1990 evo_data(push, syncs | (depth << 6));
1991 evo_data(push, magic);
1992 evo_kick(push, mast);
1998 ctrl = (depth << 16) | (proto << 8);
1999 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2001 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2006 nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner);
2010 nv50_sor_destroy(struct drm_encoder *encoder)
2012 drm_encoder_cleanup(encoder);
2016 static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
2017 .dpms = nv50_sor_dpms,
2018 .mode_fixup = nv50_encoder_mode_fixup,
2019 .prepare = nv50_sor_disconnect,
2020 .commit = nv50_sor_commit,
2021 .mode_set = nv50_sor_mode_set,
2022 .disable = nv50_sor_disconnect,
2023 .get_crtc = nv50_display_crtc_get,
2026 static const struct drm_encoder_funcs nv50_sor_func = {
2027 .destroy = nv50_sor_destroy,
2031 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
2033 struct nouveau_drm *drm = nouveau_drm(connector->dev);
2034 struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
2035 struct nouveau_encoder *nv_encoder;
2036 struct drm_encoder *encoder;
2039 switch (dcbe->type) {
2040 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
2041 case DCB_OUTPUT_TMDS:
2044 type = DRM_MODE_ENCODER_TMDS;
2048 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2051 nv_encoder->dcb = dcbe;
2052 nv_encoder->or = ffs(dcbe->or) - 1;
2053 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
2054 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
2056 encoder = to_drm_encoder(nv_encoder);
2057 encoder->possible_crtcs = dcbe->heads;
2058 encoder->possible_clones = 0;
2059 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type);
2060 drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
2062 drm_mode_connector_attach_encoder(connector, encoder);
2066 /******************************************************************************
2068 *****************************************************************************/
2071 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
2073 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2074 struct nv50_disp *disp = nv50_disp(encoder->dev);
2076 struct nv50_disp_mthd_v1 base;
2077 struct nv50_disp_pior_pwr_v0 pwr;
2080 .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
2081 .base.hasht = nv_encoder->dcb->hasht,
2082 .base.hashm = nv_encoder->dcb->hashm,
2083 .pwr.state = mode == DRM_MODE_DPMS_ON,
2084 .pwr.type = nv_encoder->dcb->type,
2087 nvif_mthd(disp->disp, 0, &args, sizeof(args));
2091 nv50_pior_mode_fixup(struct drm_encoder *encoder,
2092 const struct drm_display_mode *mode,
2093 struct drm_display_mode *adjusted_mode)
2095 if (!nv50_encoder_mode_fixup(encoder, mode, adjusted_mode))
2097 adjusted_mode->clock *= 2;
2102 nv50_pior_commit(struct drm_encoder *encoder)
2107 nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2108 struct drm_display_mode *adjusted_mode)
2110 struct nv50_mast *mast = nv50_mast(encoder->dev);
2111 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2112 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2113 struct nouveau_connector *nv_connector;
2114 u8 owner = 1 << nv_crtc->index;
2118 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2119 switch (nv_connector->base.display_info.bpc) {
2120 case 10: depth = 0x6; break;
2121 case 8: depth = 0x5; break;
2122 case 6: depth = 0x2; break;
2123 default: depth = 0x0; break;
2126 switch (nv_encoder->dcb->type) {
2127 case DCB_OUTPUT_TMDS:
2136 nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2138 push = evo_wait(mast, 8);
2140 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2141 u32 ctrl = (depth << 16) | (proto << 8) | owner;
2142 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2144 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2146 evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2147 evo_data(push, ctrl);
2150 evo_kick(push, mast);
2153 nv_encoder->crtc = encoder->crtc;
2157 nv50_pior_disconnect(struct drm_encoder *encoder)
2159 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2160 struct nv50_mast *mast = nv50_mast(encoder->dev);
2161 const int or = nv_encoder->or;
2164 if (nv_encoder->crtc) {
2165 nv50_crtc_prepare(nv_encoder->crtc);
2167 push = evo_wait(mast, 4);
2169 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2170 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2171 evo_data(push, 0x00000000);
2173 evo_kick(push, mast);
2177 nv_encoder->crtc = NULL;
2181 nv50_pior_destroy(struct drm_encoder *encoder)
2183 drm_encoder_cleanup(encoder);
2187 static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2188 .dpms = nv50_pior_dpms,
2189 .mode_fixup = nv50_pior_mode_fixup,
2190 .prepare = nv50_pior_disconnect,
2191 .commit = nv50_pior_commit,
2192 .mode_set = nv50_pior_mode_set,
2193 .disable = nv50_pior_disconnect,
2194 .get_crtc = nv50_display_crtc_get,
2197 static const struct drm_encoder_funcs nv50_pior_func = {
2198 .destroy = nv50_pior_destroy,
2202 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2204 struct nouveau_drm *drm = nouveau_drm(connector->dev);
2205 struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
2206 struct nouveau_i2c_port *ddc = NULL;
2207 struct nouveau_encoder *nv_encoder;
2208 struct drm_encoder *encoder;
2211 switch (dcbe->type) {
2212 case DCB_OUTPUT_TMDS:
2213 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev));
2214 type = DRM_MODE_ENCODER_TMDS;
2217 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev));
2218 type = DRM_MODE_ENCODER_TMDS;
2224 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2227 nv_encoder->dcb = dcbe;
2228 nv_encoder->or = ffs(dcbe->or) - 1;
2229 nv_encoder->i2c = ddc;
2231 encoder = to_drm_encoder(nv_encoder);
2232 encoder->possible_crtcs = dcbe->heads;
2233 encoder->possible_clones = 0;
2234 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type);
2235 drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2237 drm_mode_connector_attach_encoder(connector, encoder);
2241 /******************************************************************************
2243 *****************************************************************************/
2246 nv50_fbdma_fini(struct nv50_fbdma *fbdma)
2249 for (i = 0; i < ARRAY_SIZE(fbdma->base); i++)
2250 nvif_object_fini(&fbdma->base[i]);
2251 nvif_object_fini(&fbdma->core);
2252 list_del(&fbdma->head);
2257 nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kind)
2259 struct nouveau_drm *drm = nouveau_drm(dev);
2260 struct nv50_disp *disp = nv50_disp(dev);
2261 struct nv50_mast *mast = nv50_mast(dev);
2262 struct __attribute__ ((packed)) {
2263 struct nv_dma_v0 base;
2265 struct nv50_dma_v0 nv50;
2266 struct gf100_dma_v0 gf100;
2267 struct gf110_dma_v0 gf110;
2270 struct nv50_fbdma *fbdma;
2271 struct drm_crtc *crtc;
2272 u32 size = sizeof(args.base);
2275 list_for_each_entry(fbdma, &disp->fbdma, head) {
2276 if (fbdma->core.handle == name)
2280 fbdma = kzalloc(sizeof(*fbdma), GFP_KERNEL);
2283 list_add(&fbdma->head, &disp->fbdma);
2285 args.base.target = NV_DMA_V0_TARGET_VRAM;
2286 args.base.access = NV_DMA_V0_ACCESS_RDWR;
2287 args.base.start = offset;
2288 args.base.limit = offset + length - 1;
2290 if (drm->device.info.chipset < 0x80) {
2291 args.nv50.part = NV50_DMA_V0_PART_256;
2292 size += sizeof(args.nv50);
2294 if (drm->device.info.chipset < 0xc0) {
2295 args.nv50.part = NV50_DMA_V0_PART_256;
2296 args.nv50.kind = kind;
2297 size += sizeof(args.nv50);
2299 if (drm->device.info.chipset < 0xd0) {
2300 args.gf100.kind = kind;
2301 size += sizeof(args.gf100);
2303 args.gf110.page = GF110_DMA_V0_PAGE_LP;
2304 args.gf110.kind = kind;
2305 size += sizeof(args.gf110);
2308 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2309 struct nv50_head *head = nv50_head(crtc);
2310 int ret = nvif_object_init(&head->sync.base.base.user, NULL,
2311 name, NV_DMA_IN_MEMORY, &args, size,
2312 &fbdma->base[head->base.index]);
2314 nv50_fbdma_fini(fbdma);
2319 ret = nvif_object_init(&mast->base.base.user, NULL, name,
2320 NV_DMA_IN_MEMORY, &args, size,
2323 nv50_fbdma_fini(fbdma);
2331 nv50_fb_dtor(struct drm_framebuffer *fb)
2336 nv50_fb_ctor(struct drm_framebuffer *fb)
2338 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
2339 struct nouveau_drm *drm = nouveau_drm(fb->dev);
2340 struct nouveau_bo *nvbo = nv_fb->nvbo;
2341 struct nv50_disp *disp = nv50_disp(fb->dev);
2342 u8 kind = nouveau_bo_tile_layout(nvbo) >> 8;
2343 u8 tile = nvbo->tile_mode;
2345 if (drm->device.info.chipset >= 0xc0)
2346 tile >>= 4; /* yep.. */
2348 switch (fb->depth) {
2349 case 8: nv_fb->r_format = 0x1e00; break;
2350 case 15: nv_fb->r_format = 0xe900; break;
2351 case 16: nv_fb->r_format = 0xe800; break;
2353 case 32: nv_fb->r_format = 0xcf00; break;
2354 case 30: nv_fb->r_format = 0xd100; break;
2356 NV_ERROR(drm, "unknown depth %d\n", fb->depth);
2360 if (disp->disp->oclass < G82_DISP) {
2361 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2362 (fb->pitches[0] | 0x00100000);
2363 nv_fb->r_format |= kind << 16;
2365 if (disp->disp->oclass < GF110_DISP) {
2366 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2367 (fb->pitches[0] | 0x00100000);
2369 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2370 (fb->pitches[0] | 0x01000000);
2372 nv_fb->r_handle = 0xffff0000 | kind;
2374 return nv50_fbdma_init(fb->dev, nv_fb->r_handle, 0,
2375 drm->device.info.ram_user, kind);
2378 /******************************************************************************
2380 *****************************************************************************/
2383 nv50_display_fini(struct drm_device *dev)
2388 nv50_display_init(struct drm_device *dev)
2390 struct nv50_disp *disp = nv50_disp(dev);
2391 struct drm_crtc *crtc;
2394 push = evo_wait(nv50_mast(dev), 32);
2398 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2399 struct nv50_sync *sync = nv50_sync(crtc);
2400 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
2403 evo_mthd(push, 0x0088, 1);
2404 evo_data(push, nv50_mast(dev)->base.sync.handle);
2405 evo_kick(push, nv50_mast(dev));
2410 nv50_display_destroy(struct drm_device *dev)
2412 struct nv50_disp *disp = nv50_disp(dev);
2413 struct nv50_fbdma *fbdma, *fbtmp;
2415 list_for_each_entry_safe(fbdma, fbtmp, &disp->fbdma, head) {
2416 nv50_fbdma_fini(fbdma);
2419 nv50_dmac_destroy(&disp->mast.base, disp->disp);
2421 nouveau_bo_unmap(disp->sync);
2423 nouveau_bo_unpin(disp->sync);
2424 nouveau_bo_ref(NULL, &disp->sync);
2426 nouveau_display(dev)->priv = NULL;
2431 nv50_display_create(struct drm_device *dev)
2433 struct nvif_device *device = &nouveau_drm(dev)->device;
2434 struct nouveau_drm *drm = nouveau_drm(dev);
2435 struct dcb_table *dcb = &drm->vbios.dcb;
2436 struct drm_connector *connector, *tmp;
2437 struct nv50_disp *disp;
2438 struct dcb_output *dcbe;
2441 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2444 INIT_LIST_HEAD(&disp->fbdma);
2446 nouveau_display(dev)->priv = disp;
2447 nouveau_display(dev)->dtor = nv50_display_destroy;
2448 nouveau_display(dev)->init = nv50_display_init;
2449 nouveau_display(dev)->fini = nv50_display_fini;
2450 nouveau_display(dev)->fb_ctor = nv50_fb_ctor;
2451 nouveau_display(dev)->fb_dtor = nv50_fb_dtor;
2452 disp->disp = &nouveau_display(dev)->disp;
2454 /* small shared memory area we use for notifiers and semaphores */
2455 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2456 0, 0x0000, NULL, NULL, &disp->sync);
2458 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2460 ret = nouveau_bo_map(disp->sync);
2462 nouveau_bo_unpin(disp->sync);
2465 nouveau_bo_ref(NULL, &disp->sync);
2471 /* allocate master evo channel */
2472 ret = nv50_core_create(disp->disp, disp->sync->bo.offset,
2477 /* create crtc objects to represent the hw heads */
2478 if (disp->disp->oclass >= GF110_DISP)
2479 crtcs = nvif_rd32(device, 0x022448);
2483 for (i = 0; i < crtcs; i++) {
2484 ret = nv50_crtc_create(dev, i);
2489 /* create encoder/connector objects based on VBIOS DCB table */
2490 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2491 connector = nouveau_connector_create(dev, dcbe->connector);
2492 if (IS_ERR(connector))
2495 if (dcbe->location == DCB_LOC_ON_CHIP) {
2496 switch (dcbe->type) {
2497 case DCB_OUTPUT_TMDS:
2498 case DCB_OUTPUT_LVDS:
2500 ret = nv50_sor_create(connector, dcbe);
2502 case DCB_OUTPUT_ANALOG:
2503 ret = nv50_dac_create(connector, dcbe);
2510 ret = nv50_pior_create(connector, dcbe);
2514 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2515 dcbe->location, dcbe->type,
2516 ffs(dcbe->or) - 1, ret);
2521 /* cull any connectors we created that don't have an encoder */
2522 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2523 if (connector->encoder_ids[0])
2526 NV_WARN(drm, "%s has no encoders, removing\n",
2528 connector->funcs->destroy(connector);
2533 nv50_display_destroy(dev);