drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26 #include <linux/hdmi.h>
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_atomic.h>
  30 #include <drm/drm_atomic_helper.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/drm_dp_helper.h>
  33 #include <drm/drm_fb_helper.h>
  34 #include <drm/drm_plane_helper.h>
  35 #include <drm/drm_edid.h>
  36
  37 #include <nvif/class.h>
  38 #include <nvif/cl0002.h>
  39 #include <nvif/cl5070.h>
  40 #include <nvif/cl507a.h>
  41 #include <nvif/cl507b.h>
  42 #include <nvif/cl507c.h>
  43 #include <nvif/cl507d.h>
  44 #include <nvif/cl507e.h>
  45 #include <nvif/event.h>
  46
  47 #include "nouveau_drv.h"
  48 #include "nouveau_dma.h"
  49 #include "nouveau_gem.h"
  50 #include "nouveau_connector.h"
  51 #include "nouveau_encoder.h"
  52 #include "nouveau_crtc.h"
  53 #include "nouveau_fence.h"
  54 #include "nouveau_fbcon.h"
  55 #include "nv50_display.h"
  56
  57 #define EVO_DMA_NR 9
  58
  59 #define EVO_MASTER  (0x00)
  60 #define EVO_FLIP(c) (0x01 + (c))
  61 #define EVO_OVLY(c) (0x05 + (c))
  62 #define EVO_OIMM(c) (0x09 + (c))
  63 #define EVO_CURS(c) (0x0d + (c))
  64
  65 /* offsets in shared sync bo of various structures */
  66 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
  67 #define EVO_MAST_NTFY     EVO_SYNC(      0, 0x00)
  68 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c) + 1, 0x00)
  69 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c) + 1, 0x10)
  70 #define EVO_FLIP_NTFY0(c) EVO_SYNC((c) + 1, 0x20)
  71 #define EVO_FLIP_NTFY1(c) EVO_SYNC((c) + 1, 0x30)
  72
  73 /******************************************************************************
  74  * Atomic state
  75  *****************************************************************************/
  76 #define nv50_atom(p) container_of((p), struct nv50_atom, state)
  77
  78 struct nv50_atom {
  79         struct drm_atomic_state state;
  80
  81         struct list_head outp;
  82         bool lock_core;
  83         bool flush_disable;
  84 };
  85
  86 struct nv50_outp_atom {
  87         struct list_head head;
  88
  89         struct drm_encoder *encoder;
  90         bool flush_disable;
  91
  92         union {
  93                 struct {
  94                         bool ctrl:1;
  95                 };
  96                 u8 mask;
  97         } clr;
  98
  99         union {
 100                 struct {
 101                         bool ctrl:1;
 102                 };
 103                 u8 mask;
 104         } set;
 105 };
 106
 107 #define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)
 108
 109 struct nv50_head_atom {
 110         struct drm_crtc_state state;
 111
 112         struct {
 113                 u16 iW;
 114                 u16 iH;
 115                 u16 oW;
 116                 u16 oH;
 117         } view;
 118
 119         struct nv50_head_mode {
 120                 bool interlace;
 121                 u32 clock;
 122                 struct {
 123                         u16 active;
 124                         u16 synce;
 125                         u16 blanke;
 126                         u16 blanks;
 127                 } h;
 128                 struct {
 129                         u32 active;
 130                         u16 synce;
 131                         u16 blanke;
 132                         u16 blanks;
 133                         u16 blank2s;
 134                         u16 blank2e;
 135                         u16 blankus;
 136                 } v;
 137         } mode;
 138
 139         struct {
 140                 bool visible;
 141                 u32 handle;
 142                 u64 offset:40;
 143                 u8  mode:4;
 144         } lut;
 145
 146         struct {
 147                 bool visible;
 148                 u32 handle;
 149                 u64 offset:40;
 150                 u8  format;
 151                 u8  kind:7;
 152                 u8  layout:1;
 153                 u8  block:4;
 154                 u32 pitch:20;
 155                 u16 x;
 156                 u16 y;
 157                 u16 w;
 158                 u16 h;
 159         } core;
 160
 161         struct {
 162                 bool visible;
 163                 u32 handle;
 164                 u64 offset:40;
 165                 u8  layout:1;
 166                 u8  format:1;
 167         } curs;
 168
 169         struct {
 170                 u8  depth;
 171                 u8  cpp;
 172                 u16 x;
 173                 u16 y;
 174                 u16 w;
 175                 u16 h;
 176         } base;
 177
 178         struct {
 179                 u8 cpp;
 180         } ovly;
 181
 182         struct {
 183                 bool enable:1;
 184                 u8 bits:2;
 185                 u8 mode:4;
 186         } dither;
 187
 188         struct {
 189                 struct {
 190                         u16 cos:12;
 191                         u16 sin:12;
 192                 } sat;
 193         } procamp;
 194
 195         union {
 196                 struct {
 197                         bool ilut:1;
 198                         bool core:1;
 199                         bool curs:1;
 200                 };
 201                 u8 mask;
 202         } clr;
 203
 204         union {
 205                 struct {
 206                         bool ilut:1;
 207                         bool core:1;
 208                         bool curs:1;
 209                         bool view:1;
 210                         bool mode:1;
 211                         bool base:1;
 212                         bool ovly:1;
 213                         bool dither:1;
 214                         bool procamp:1;
 215                 };
 216                 u16 mask;
 217         } set;
 218 };
 219
 220 static inline struct nv50_head_atom *
 221 nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc)
 222 {
 223         struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc);
 224         if (IS_ERR(statec))
 225                 return (void *)statec;
 226         return nv50_head_atom(statec);
 227 }
 228
 229 #define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state)
 230
 231 struct nv50_wndw_atom {
 232         struct drm_plane_state state;
 233         u8 interval;
 234
 235         struct {
 236                 u32  handle;
 237                 u16  offset:12;
 238                 bool awaken:1;
 239         } ntfy;
 240
 241         struct {
 242                 u32 handle;
 243                 u16 offset:12;
 244                 u32 acquire;
 245                 u32 release;
 246         } sema;
 247
 248         struct {
 249                 u8 enable:2;
 250         } lut;
 251
 252         struct {
 253                 u8  mode:2;
 254                 u8  interval:4;
 255
 256                 u8  format;
 257                 u8  kind:7;
 258                 u8  layout:1;
 259                 u8  block:4;
 260                 u32 pitch:20;
 261                 u16 w;
 262                 u16 h;
 263
 264                 u32 handle;
 265                 u64 offset;
 266         } image;
 267
 268         struct {
 269                 u16 x;
 270                 u16 y;
 271         } point;
 272
 273         union {
 274                 struct {
 275                         bool ntfy:1;
 276                         bool sema:1;
 277                         bool image:1;
 278                 };
 279                 u8 mask;
 280         } clr;
 281
 282         union {
 283                 struct {
 284                         bool ntfy:1;
 285                         bool sema:1;
 286                         bool image:1;
 287                         bool lut:1;
 288                         bool point:1;
 289                 };
 290                 u8 mask;
 291         } set;
 292 };
 293
 294 /******************************************************************************
 295  * EVO channel
 296  *****************************************************************************/
 297
 298 struct nv50_chan {
 299         struct nvif_object user;
 300         struct nvif_device *device;
 301 };
 302
 303 static int
 304 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
 305                  const s32 *oclass, u8 head, void *data, u32 size,
 306                  struct nv50_chan *chan)
 307 {
 308         struct nvif_sclass *sclass;
 309         int ret, i, n;
 310
 311         chan->device = device;
 312
 313         ret = n = nvif_object_sclass_get(disp, &sclass);
 314         if (ret < 0)
 315                 return ret;
 316
 317         while (oclass[0]) {
 318                 for (i = 0; i < n; i++) {
 319                         if (sclass[i].oclass == oclass[0]) {
 320                                 ret = nvif_object_init(disp, 0, oclass[0],
 321                                                        data, size, &chan->user);
 322                                 if (ret == 0)
 323                                         nvif_object_map(&chan->user, NULL, 0);
 324                                 nvif_object_sclass_put(&sclass);
 325                                 return ret;
 326                         }
 327                 }
 328                 oclass++;
 329         }
 330
 331         nvif_object_sclass_put(&sclass);
 332         return -ENOSYS;
 333 }
 334
 335 static void
 336 nv50_chan_destroy(struct nv50_chan *chan)
 337 {
 338         nvif_object_fini(&chan->user);
 339 }
 340
 341 /******************************************************************************
 342  * PIO EVO channel
 343  *****************************************************************************/
 344
 345 struct nv50_pioc {
 346         struct nv50_chan base;
 347 };
 348
 349 static void
 350 nv50_pioc_destroy(struct nv50_pioc *pioc)
 351 {
 352         nv50_chan_destroy(&pioc->base);
 353 }
 354
 355 static int
 356 nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp,
 357                  const s32 *oclass, u8 head, void *data, u32 size,
 358                  struct nv50_pioc *pioc)
 359 {
 360         return nv50_chan_create(device, disp, oclass, head, data, size,
 361                                 &pioc->base);
 362 }
 363
 364 /******************************************************************************
 365  * Overlay Immediate
 366  *****************************************************************************/
 367
 368 struct nv50_oimm {
 369         struct nv50_pioc base;
 370 };
 371
 372 static int
 373 nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp,
 374                  int head, struct nv50_oimm *oimm)
 375 {
 376         struct nv50_disp_cursor_v0 args = {
 377                 .head = head,
 378         };
 379         static const s32 oclass[] = {
 380                 GK104_DISP_OVERLAY,
 381                 GF110_DISP_OVERLAY,
 382                 GT214_DISP_OVERLAY,
 383                 G82_DISP_OVERLAY,
 384                 NV50_DISP_OVERLAY,
 385                 0
 386         };
 387
 388         return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
 389                                 &oimm->base);
 390 }
 391
 392 /******************************************************************************
 393  * DMA EVO channel
 394  *****************************************************************************/
 395
 396 struct nv50_dmac_ctxdma {
 397         struct list_head head;
 398         struct nvif_object object;
 399 };
 400
 401 struct nv50_dmac {
 402         struct nv50_chan base;
 403         dma_addr_t handle;
 404         u32 *ptr;
 405
 406         struct nvif_object sync;
 407         struct nvif_object vram;
 408         struct list_head ctxdma;
 409
 410         /* Protects against concurrent pushbuf access to this channel, lock is
 411          * grabbed by evo_wait (if the pushbuf reservation is successful) and
 412          * dropped again by evo_kick. */
 413         struct mutex lock;
 414 };
 415
 416 static void
 417 nv50_dmac_ctxdma_del(struct nv50_dmac_ctxdma *ctxdma)
 418 {
 419         nvif_object_fini(&ctxdma->object);
 420         list_del(&ctxdma->head);
 421         kfree(ctxdma);
 422 }
 423
 424 static struct nv50_dmac_ctxdma *
 425 nv50_dmac_ctxdma_new(struct nv50_dmac *dmac, struct nouveau_framebuffer *fb)
 426 {
 427         struct nouveau_drm *drm = nouveau_drm(fb->base.dev);
 428         struct nv50_dmac_ctxdma *ctxdma;
 429         const u8    kind = fb->nvbo->kind;
 430         const u32 handle = 0xfb000000 | kind;
 431         struct {
 432                 struct nv_dma_v0 base;
 433                 union {
 434                         struct nv50_dma_v0 nv50;
 435                         struct gf100_dma_v0 gf100;
 436                         struct gf119_dma_v0 gf119;
 437                 };
 438         } args = {};
 439         u32 argc = sizeof(args.base);
 440         int ret;
 441
 442         list_for_each_entry(ctxdma, &dmac->ctxdma, head) {
 443                 if (ctxdma->object.handle == handle)
 444                         return ctxdma;
 445         }
 446
 447         if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL)))
 448                 return ERR_PTR(-ENOMEM);
 449         list_add(&ctxdma->head, &dmac->ctxdma);
 450
 451         args.base.target = NV_DMA_V0_TARGET_VRAM;
 452         args.base.access = NV_DMA_V0_ACCESS_RDWR;
 453         args.base.start  = 0;
 454         args.base.limit  = drm->client.device.info.ram_user - 1;
 455
 456         if (drm->client.device.info.chipset < 0x80) {
 457                 args.nv50.part = NV50_DMA_V0_PART_256;
 458                 argc += sizeof(args.nv50);
 459         } else
 460         if (drm->client.device.info.chipset < 0xc0) {
 461                 args.nv50.part = NV50_DMA_V0_PART_256;
 462                 args.nv50.kind = kind;
 463                 argc += sizeof(args.nv50);
 464         } else
 465         if (drm->client.device.info.chipset < 0xd0) {
 466                 args.gf100.kind = kind;
 467                 argc += sizeof(args.gf100);
 468         } else {
 469                 args.gf119.page = GF119_DMA_V0_PAGE_LP;
 470                 args.gf119.kind = kind;
 471                 argc += sizeof(args.gf119);
 472         }
 473
 474         ret = nvif_object_init(&dmac->base.user, handle, NV_DMA_IN_MEMORY,
 475                                &args, argc, &ctxdma->object);
 476         if (ret) {
 477                 nv50_dmac_ctxdma_del(ctxdma);
 478                 return ERR_PTR(ret);
 479         }
 480
 481         return ctxdma;
 482 }
 483
 484 static void
 485 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
 486 {
 487         struct nvif_device *device = dmac->base.device;
 488         struct nv50_dmac_ctxdma *ctxdma, *ctxtmp;
 489
 490         list_for_each_entry_safe(ctxdma, ctxtmp, &dmac->ctxdma, head) {
 491                 nv50_dmac_ctxdma_del(ctxdma);
 492         }
 493
 494         nvif_object_fini(&dmac->vram);
 495         nvif_object_fini(&dmac->sync);
 496
 497         nv50_chan_destroy(&dmac->base);
 498
 499         if (dmac->ptr) {
 500                 struct device *dev = nvxx_device(device)->dev;
 501                 dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle);
 502         }
 503 }
 504
 505 static int
 506 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 507                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 508                  struct nv50_dmac *dmac)
 509 {
 510         struct nv50_disp_core_channel_dma_v0 *args = data;
 511         struct nvif_object pushbuf;
 512         int ret;
 513
 514         mutex_init(&dmac->lock);
 515         INIT_LIST_HEAD(&dmac->ctxdma);
 516
 517         dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE,
 518                                        &dmac->handle, GFP_KERNEL);
 519         if (!dmac->ptr)
 520                 return -ENOMEM;
 521
 522         ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
 523                                &(struct nv_dma_v0) {
 524                                         .target = NV_DMA_V0_TARGET_PCI_US,
 525                                         .access = NV_DMA_V0_ACCESS_RD,
 526                                         .start = dmac->handle + 0x0000,
 527                                         .limit = dmac->handle + 0x0fff,
 528                                }, sizeof(struct nv_dma_v0), &pushbuf);
 529         if (ret)
 530                 return ret;
 531
 532         args->pushbuf = nvif_handle(&pushbuf);
 533
 534         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 535                                &dmac->base);
 536         nvif_object_fini(&pushbuf);
 537         if (ret)
 538                 return ret;
 539
 540         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 541                                &(struct nv_dma_v0) {
 542                                         .target = NV_DMA_V0_TARGET_VRAM,
 543                                         .access = NV_DMA_V0_ACCESS_RDWR,
 544                                         .start = syncbuf + 0x0000,
 545                                         .limit = syncbuf + 0x0fff,
 546                                }, sizeof(struct nv_dma_v0),
 547                                &dmac->sync);
 548         if (ret)
 549                 return ret;
 550
 551         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 552                                &(struct nv_dma_v0) {
 553                                         .target = NV_DMA_V0_TARGET_VRAM,
 554                                         .access = NV_DMA_V0_ACCESS_RDWR,
 555                                         .start = 0,
 556                                         .limit = device->info.ram_user - 1,
 557                                }, sizeof(struct nv_dma_v0),
 558                                &dmac->vram);
 559         if (ret)
 560                 return ret;
 561
 562         return ret;
 563 }
 564
 565 /******************************************************************************
 566  * Core
 567  *****************************************************************************/
 568
 569 struct nv50_mast {
 570         struct nv50_dmac base;
 571 };
 572
 573 static int
 574 nv50_core_create(struct nvif_device *device, struct nvif_object *disp,
 575                  u64 syncbuf, struct nv50_mast *core)
 576 {
 577         struct nv50_disp_core_channel_dma_v0 args = {
 578                 .pushbuf = 0xb0007d00,
 579         };
 580         static const s32 oclass[] = {
 581                 GP102_DISP_CORE_CHANNEL_DMA,
 582                 GP100_DISP_CORE_CHANNEL_DMA,
 583                 GM200_DISP_CORE_CHANNEL_DMA,
 584                 GM107_DISP_CORE_CHANNEL_DMA,
 585                 GK110_DISP_CORE_CHANNEL_DMA,
 586                 GK104_DISP_CORE_CHANNEL_DMA,
 587                 GF110_DISP_CORE_CHANNEL_DMA,
 588                 GT214_DISP_CORE_CHANNEL_DMA,
 589                 GT206_DISP_CORE_CHANNEL_DMA,
 590                 GT200_DISP_CORE_CHANNEL_DMA,
 591                 G82_DISP_CORE_CHANNEL_DMA,
 592                 NV50_DISP_CORE_CHANNEL_DMA,
 593                 0
 594         };
 595
 596         return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args),
 597                                 syncbuf, &core->base);
 598 }
 599
 600 /******************************************************************************
 601  * Base
 602  *****************************************************************************/
 603
 604 struct nv50_sync {
 605         struct nv50_dmac base;
 606         u32 addr;
 607         u32 data;
 608 };
 609
 610 static int
 611 nv50_base_create(struct nvif_device *device, struct nvif_object *disp,
 612                  int head, u64 syncbuf, struct nv50_sync *base)
 613 {
 614         struct nv50_disp_base_channel_dma_v0 args = {
 615                 .pushbuf = 0xb0007c00 | head,
 616                 .head = head,
 617         };
 618         static const s32 oclass[] = {
 619                 GK110_DISP_BASE_CHANNEL_DMA,
 620                 GK104_DISP_BASE_CHANNEL_DMA,
 621                 GF110_DISP_BASE_CHANNEL_DMA,
 622                 GT214_DISP_BASE_CHANNEL_DMA,
 623                 GT200_DISP_BASE_CHANNEL_DMA,
 624                 G82_DISP_BASE_CHANNEL_DMA,
 625                 NV50_DISP_BASE_CHANNEL_DMA,
 626                 0
 627         };
 628
 629         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 630                                 syncbuf, &base->base);
 631 }
 632
 633 /******************************************************************************
 634  * Overlay
 635  *****************************************************************************/
 636
 637 struct nv50_ovly {
 638         struct nv50_dmac base;
 639 };
 640
 641 static int
 642 nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp,
 643                  int head, u64 syncbuf, struct nv50_ovly *ovly)
 644 {
 645         struct nv50_disp_overlay_channel_dma_v0 args = {
 646                 .pushbuf = 0xb0007e00 | head,
 647                 .head = head,
 648         };
 649         static const s32 oclass[] = {
 650                 GK104_DISP_OVERLAY_CONTROL_DMA,
 651                 GF110_DISP_OVERLAY_CONTROL_DMA,
 652                 GT214_DISP_OVERLAY_CHANNEL_DMA,
 653                 GT200_DISP_OVERLAY_CHANNEL_DMA,
 654                 G82_DISP_OVERLAY_CHANNEL_DMA,
 655                 NV50_DISP_OVERLAY_CHANNEL_DMA,
 656                 0
 657         };
 658
 659         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 660                                 syncbuf, &ovly->base);
 661 }
 662
 663 struct nv50_head {
 664         struct nouveau_crtc base;
 665         struct {
 666                 struct nouveau_bo *nvbo[2];
 667                 int next;
 668         } lut;
 669         struct nv50_ovly ovly;
 670         struct nv50_oimm oimm;
 671 };
 672
 673 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
 674 #define nv50_ovly(c) (&nv50_head(c)->ovly)
 675 #define nv50_oimm(c) (&nv50_head(c)->oimm)
 676 #define nv50_chan(c) (&(c)->base.base)
 677 #define nv50_vers(c) nv50_chan(c)->user.oclass
 678
 679 struct nv50_disp {
 680         struct nvif_object *disp;
 681         struct nv50_mast mast;
 682
 683         struct nouveau_bo *sync;
 684
 685         struct mutex mutex;
 686 };
 687
 688 static struct nv50_disp *
 689 nv50_disp(struct drm_device *dev)
 690 {
 691         return nouveau_display(dev)->priv;
 692 }
 693
 694 #define nv50_mast(d) (&nv50_disp(d)->mast)
 695
 696 /******************************************************************************
 697  * EVO channel helpers
 698  *****************************************************************************/
 699 static u32 *
 700 evo_wait(void *evoc, int nr)
 701 {
 702         struct nv50_dmac *dmac = evoc;
 703         struct nvif_device *device = dmac->base.device;
 704         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 705
 706         mutex_lock(&dmac->lock);
 707         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 708                 dmac->ptr[put] = 0x20000000;
 709
 710                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 711                 if (nvif_msec(device, 2000,
 712                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 713                                 break;
 714                 ) < 0) {
 715                         mutex_unlock(&dmac->lock);
 716                         pr_err("nouveau: evo channel stalled\n");
 717                         return NULL;
 718                 }
 719
 720                 put = 0;
 721         }
 722
 723         return dmac->ptr + put;
 724 }
 725
 726 static void
 727 evo_kick(u32 *push, void *evoc)
 728 {
 729         struct nv50_dmac *dmac = evoc;
 730         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 731         mutex_unlock(&dmac->lock);
 732 }
 733
 734 #define evo_mthd(p, m, s) do {                                          \
 735         const u32 _m = (m), _s = (s);                                   \
 736         if (drm_debug & DRM_UT_KMS)                                     \
 737                 pr_err("%04x %d %s\n", _m, _s, __func__);               \
 738         *((p)++) = ((_s << 18) | _m);                                   \
 739 } while(0)
 740
 741 #define evo_data(p, d) do {                                             \
 742         const u32 _d = (d);                                             \
 743         if (drm_debug & DRM_UT_KMS)                                     \
 744                 pr_err("\t%08x\n", _d);                                 \
 745         *((p)++) = _d;                                                  \
 746 } while(0)
 747
 748 /******************************************************************************
 749  * Plane
 750  *****************************************************************************/
 751 #define nv50_wndw(p) container_of((p), struct nv50_wndw, plane)
 752
 753 struct nv50_wndw {
 754         const struct nv50_wndw_func *func;
 755         struct nv50_dmac *dmac;
 756
 757         struct drm_plane plane;
 758
 759         struct nvif_notify notify;
 760         u16 ntfy;
 761         u16 sema;
 762         u32 data;
 763 };
 764
 765 struct nv50_wndw_func {
 766         void *(*dtor)(struct nv50_wndw *);
 767         int (*acquire)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
 768                        struct nv50_head_atom *asyh);
 769         void (*release)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
 770                         struct nv50_head_atom *asyh);
 771         void (*prepare)(struct nv50_wndw *, struct nv50_head_atom *asyh,
 772                         struct nv50_wndw_atom *asyw);
 773
 774         void (*sema_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 775         void (*sema_clr)(struct nv50_wndw *);
 776         void (*ntfy_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 777         void (*ntfy_clr)(struct nv50_wndw *);
 778         int (*ntfy_wait_begun)(struct nv50_wndw *, struct nv50_wndw_atom *);
 779         void (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 780         void (*image_clr)(struct nv50_wndw *);
 781         void (*lut)(struct nv50_wndw *, struct nv50_wndw_atom *);
 782         void (*point)(struct nv50_wndw *, struct nv50_wndw_atom *);
 783
 784         u32 (*update)(struct nv50_wndw *, u32 interlock);
 785 };
 786
 787 static int
 788 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
 789 {
 790         if (asyw->set.ntfy)
 791                 return wndw->func->ntfy_wait_begun(wndw, asyw);
 792         return 0;
 793 }
 794
 795 static u32
 796 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 interlock, bool flush,
 797                     struct nv50_wndw_atom *asyw)
 798 {
 799         if (asyw->clr.sema && (!asyw->set.sema || flush))
 800                 wndw->func->sema_clr(wndw);
 801         if (asyw->clr.ntfy && (!asyw->set.ntfy || flush))
 802                 wndw->func->ntfy_clr(wndw);
 803         if (asyw->clr.image && (!asyw->set.image || flush))
 804                 wndw->func->image_clr(wndw);
 805
 806         return flush ? wndw->func->update(wndw, interlock) : 0;
 807 }
 808
 809 static u32
 810 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 interlock,
 811                     struct nv50_wndw_atom *asyw)
 812 {
 813         if (interlock) {
 814                 asyw->image.mode = 0;
 815                 asyw->image.interval = 1;
 816         }
 817
 818         if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw);
 819         if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw);
 820         if (asyw->set.image) wndw->func->image_set(wndw, asyw);
 821         if (asyw->set.lut  ) wndw->func->lut      (wndw, asyw);
 822         if (asyw->set.point) wndw->func->point    (wndw, asyw);
 823
 824         return wndw->func->update(wndw, interlock);
 825 }
 826
 827 static void
 828 nv50_wndw_atomic_check_release(struct nv50_wndw *wndw,
 829                                struct nv50_wndw_atom *asyw,
 830                                struct nv50_head_atom *asyh)
 831 {
 832         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
 833         NV_ATOMIC(drm, "%s release\n", wndw->plane.name);
 834         wndw->func->release(wndw, asyw, asyh);
 835         asyw->ntfy.handle = 0;
 836         asyw->sema.handle = 0;
 837 }
 838
 839 static int
 840 nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw,
 841                                struct nv50_wndw_atom *asyw,
 842                                struct nv50_head_atom *asyh)
 843 {
 844         struct nouveau_framebuffer *fb = nouveau_framebuffer(asyw->state.fb);
 845         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
 846         int ret;
 847
 848         NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name);
 849
 850         asyw->image.w = fb->base.width;
 851         asyw->image.h = fb->base.height;
 852         asyw->image.kind = fb->nvbo->kind;
 853
 854         if (asyh->state.pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
 855                 asyw->interval = 0;
 856         else
 857                 asyw->interval = 1;
 858
 859         if (asyw->image.kind) {
 860                 asyw->image.layout = 0;
 861                 if (drm->client.device.info.chipset >= 0xc0)
 862                         asyw->image.block = fb->nvbo->mode >> 4;
 863                 else
 864                         asyw->image.block = fb->nvbo->mode;
 865                 asyw->image.pitch = (fb->base.pitches[0] / 4) << 4;
 866         } else {
 867                 asyw->image.layout = 1;
 868                 asyw->image.block  = 0;
 869                 asyw->image.pitch  = fb->base.pitches[0];
 870         }
 871
 872         ret = wndw->func->acquire(wndw, asyw, asyh);
 873         if (ret)
 874                 return ret;
 875
 876         if (asyw->set.image) {
 877                 if (!(asyw->image.mode = asyw->interval ? 0 : 1))
 878                         asyw->image.interval = asyw->interval;
 879                 else
 880                         asyw->image.interval = 0;
 881         }
 882
 883         return 0;
 884 }
 885
 886 static int
 887 nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state)
 888 {
 889         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 890         struct nv50_wndw *wndw = nv50_wndw(plane);
 891         struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state);
 892         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
 893         struct nv50_head_atom *harm = NULL, *asyh = NULL;
 894         bool varm = false, asyv = false, asym = false;
 895         int ret;
 896
 897         NV_ATOMIC(drm, "%s atomic_check\n", plane->name);
 898         if (asyw->state.crtc) {
 899                 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
 900                 if (IS_ERR(asyh))
 901                         return PTR_ERR(asyh);
 902                 asym = drm_atomic_crtc_needs_modeset(&asyh->state);
 903                 asyv = asyh->state.active;
 904         }
 905
 906         if (armw->state.crtc) {
 907                 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc);
 908                 if (IS_ERR(harm))
 909                         return PTR_ERR(harm);
 910                 varm = harm->state.crtc->state->active;
 911         }
 912
 913         if (asyv) {
 914                 asyw->point.x = asyw->state.crtc_x;
 915                 asyw->point.y = asyw->state.crtc_y;
 916                 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point)))
 917                         asyw->set.point = true;
 918
 919                 ret = nv50_wndw_atomic_check_acquire(wndw, asyw, asyh);
 920                 if (ret)
 921                         return ret;
 922         } else
 923         if (varm) {
 924                 nv50_wndw_atomic_check_release(wndw, asyw, harm);
 925         } else {
 926                 return 0;
 927         }
 928
 929         if (!asyv || asym) {
 930                 asyw->clr.ntfy = armw->ntfy.handle != 0;
 931                 asyw->clr.sema = armw->sema.handle != 0;
 932                 if (wndw->func->image_clr)
 933                         asyw->clr.image = armw->image.handle != 0;
 934                 asyw->set.lut = wndw->func->lut && asyv;
 935         }
 936
 937         return 0;
 938 }
 939
 940 static void
 941 nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state)
 942 {
 943         struct nouveau_framebuffer *fb = nouveau_framebuffer(old_state->fb);
 944         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 945
 946         NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb);
 947         if (!old_state->fb)
 948                 return;
 949
 950         nouveau_bo_unpin(fb->nvbo);
 951 }
 952
 953 static int
 954 nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state)
 955 {
 956         struct nouveau_framebuffer *fb = nouveau_framebuffer(state->fb);
 957         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 958         struct nv50_wndw *wndw = nv50_wndw(plane);
 959         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
 960         struct nv50_head_atom *asyh;
 961         struct nv50_dmac_ctxdma *ctxdma;
 962         int ret;
 963
 964         NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, state->fb);
 965         if (!asyw->state.fb)
 966                 return 0;
 967
 968         ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM, true);
 969         if (ret)
 970                 return ret;
 971
 972         ctxdma = nv50_dmac_ctxdma_new(wndw->dmac, fb);
 973         if (IS_ERR(ctxdma)) {
 974                 nouveau_bo_unpin(fb->nvbo);
 975                 return PTR_ERR(ctxdma);
 976         }
 977
 978         asyw->state.fence = reservation_object_get_excl_rcu(fb->nvbo->bo.resv);
 979         asyw->image.handle = ctxdma->object.handle;
 980         asyw->image.offset = fb->nvbo->bo.offset;
 981
 982         if (wndw->func->prepare) {
 983                 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
 984                 if (IS_ERR(asyh))
 985                         return PTR_ERR(asyh);
 986
 987                 wndw->func->prepare(wndw, asyh, asyw);
 988         }
 989
 990         return 0;
 991 }
 992
 993 static const struct drm_plane_helper_funcs
 994 nv50_wndw_helper = {
 995         .prepare_fb = nv50_wndw_prepare_fb,
 996         .cleanup_fb = nv50_wndw_cleanup_fb,
 997         .atomic_check = nv50_wndw_atomic_check,
 998 };
 999
1000 static void
1001 nv50_wndw_atomic_destroy_state(struct drm_plane *plane,
1002                                struct drm_plane_state *state)
1003 {
1004         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
1005         __drm_atomic_helper_plane_destroy_state(&asyw->state);
1006         kfree(asyw);
1007 }
1008
1009 static struct drm_plane_state *
1010 nv50_wndw_atomic_duplicate_state(struct drm_plane *plane)
1011 {
1012         struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state);
1013         struct nv50_wndw_atom *asyw;
1014         if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL)))
1015                 return NULL;
1016         __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state);
1017         asyw->interval = 1;
1018         asyw->sema = armw->sema;
1019         asyw->ntfy = armw->ntfy;
1020         asyw->image = armw->image;
1021         asyw->point = armw->point;
1022         asyw->lut = armw->lut;
1023         asyw->clr.mask = 0;
1024         asyw->set.mask = 0;
1025         return &asyw->state;
1026 }
1027
1028 static void
1029 nv50_wndw_reset(struct drm_plane *plane)
1030 {
1031         struct nv50_wndw_atom *asyw;
1032
1033         if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL))))
1034                 return;
1035
1036         if (plane->state)
1037                 plane->funcs->atomic_destroy_state(plane, plane->state);
1038         plane->state = &asyw->state;
1039         plane->state->plane = plane;
1040         plane->state->rotation = DRM_MODE_ROTATE_0;
1041 }
1042
1043 static void
1044 nv50_wndw_destroy(struct drm_plane *plane)
1045 {
1046         struct nv50_wndw *wndw = nv50_wndw(plane);
1047         void *data;
1048         nvif_notify_fini(&wndw->notify);
1049         data = wndw->func->dtor(wndw);
1050         drm_plane_cleanup(&wndw->plane);
1051         kfree(data);
1052 }
1053
1054 static const struct drm_plane_funcs
1055 nv50_wndw = {
1056         .update_plane = drm_atomic_helper_update_plane,
1057         .disable_plane = drm_atomic_helper_disable_plane,
1058         .destroy = nv50_wndw_destroy,
1059         .reset = nv50_wndw_reset,
1060         .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state,
1061         .atomic_destroy_state = nv50_wndw_atomic_destroy_state,
1062 };
1063
1064 static void
1065 nv50_wndw_fini(struct nv50_wndw *wndw)
1066 {
1067         nvif_notify_put(&wndw->notify);
1068 }
1069
1070 static void
1071 nv50_wndw_init(struct nv50_wndw *wndw)
1072 {
1073         nvif_notify_get(&wndw->notify);
1074 }
1075
1076 static int
1077 nv50_wndw_ctor(const struct nv50_wndw_func *func, struct drm_device *dev,
1078                enum drm_plane_type type, const char *name, int index,
1079                struct nv50_dmac *dmac, const u32 *format, int nformat,
1080                struct nv50_wndw *wndw)
1081 {
1082         int ret;
1083
1084         wndw->func = func;
1085         wndw->dmac = dmac;
1086
1087         ret = drm_universal_plane_init(dev, &wndw->plane, 0, &nv50_wndw,
1088                                        format, nformat, NULL,
1089                                        type, "%s-%d", name, index);
1090         if (ret)
1091                 return ret;
1092
1093         drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);
1094         return 0;
1095 }
1096
1097 /******************************************************************************
1098  * Cursor plane
1099  *****************************************************************************/
1100 #define nv50_curs(p) container_of((p), struct nv50_curs, wndw)
1101
1102 struct nv50_curs {
1103         struct nv50_wndw wndw;
1104         struct nvif_object chan;
1105 };
1106
1107 static u32
1108 nv50_curs_update(struct nv50_wndw *wndw, u32 interlock)
1109 {
1110         struct nv50_curs *curs = nv50_curs(wndw);
1111         nvif_wr32(&curs->chan, 0x0080, 0x00000000);
1112         return 0;
1113 }
1114
1115 static void
1116 nv50_curs_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1117 {
1118         struct nv50_curs *curs = nv50_curs(wndw);
1119         nvif_wr32(&curs->chan, 0x0084, (asyw->point.y << 16) | asyw->point.x);
1120 }
1121
1122 static void
1123 nv50_curs_prepare(struct nv50_wndw *wndw, struct nv50_head_atom *asyh,
1124                   struct nv50_wndw_atom *asyw)
1125 {
1126         u32 handle = nv50_disp(wndw->plane.dev)->mast.base.vram.handle;
1127         u32 offset = asyw->image.offset;
1128         if (asyh->curs.handle != handle || asyh->curs.offset != offset) {
1129                 asyh->curs.handle = handle;
1130                 asyh->curs.offset = offset;
1131                 asyh->set.curs = asyh->curs.visible;
1132         }
1133 }
1134
1135 static void
1136 nv50_curs_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1137                   struct nv50_head_atom *asyh)
1138 {
1139         asyh->curs.visible = false;
1140 }
1141
1142 static int
1143 nv50_curs_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1144                   struct nv50_head_atom *asyh)
1145 {
1146         struct drm_rect clip = {};
1147         int ret;
1148
1149         if (asyh->state.enable)
1150                 drm_mode_get_hv_timing(&asyh->state.mode,
1151                                        &clip.x2, &clip.y2);
1152
1153         ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state,
1154                                                   &clip,
1155                                                   DRM_PLANE_HELPER_NO_SCALING,
1156                                                   DRM_PLANE_HELPER_NO_SCALING,
1157                                                   true, true);
1158         asyh->curs.visible = asyw->state.visible;
1159         if (ret || !asyh->curs.visible)
1160                 return ret;
1161
1162         switch (asyw->state.fb->width) {
1163         case 32: asyh->curs.layout = 0; break;
1164         case 64: asyh->curs.layout = 1; break;
1165         default:
1166                 return -EINVAL;
1167         }
1168
1169         if (asyw->state.fb->width != asyw->state.fb->height)
1170                 return -EINVAL;
1171
1172         switch (asyw->state.fb->format->format) {
1173         case DRM_FORMAT_ARGB8888: asyh->curs.format = 1; break;
1174         default:
1175                 WARN_ON(1);
1176                 return -EINVAL;
1177         }
1178
1179         return 0;
1180 }
1181
1182 static void *
1183 nv50_curs_dtor(struct nv50_wndw *wndw)
1184 {
1185         struct nv50_curs *curs = nv50_curs(wndw);
1186         nvif_object_fini(&curs->chan);
1187         return curs;
1188 }
1189
1190 static const u32
1191 nv50_curs_format[] = {
1192         DRM_FORMAT_ARGB8888,
1193 };
1194
1195 static const struct nv50_wndw_func
1196 nv50_curs = {
1197         .dtor = nv50_curs_dtor,
1198         .acquire = nv50_curs_acquire,
1199         .release = nv50_curs_release,
1200         .prepare = nv50_curs_prepare,
1201         .point = nv50_curs_point,
1202         .update = nv50_curs_update,
1203 };
1204
1205 static int
1206 nv50_curs_new(struct nouveau_drm *drm, struct nv50_head *head,
1207               struct nv50_curs **pcurs)
1208 {
1209         static const struct nvif_mclass curses[] = {
1210                 { GK104_DISP_CURSOR, 0 },
1211                 { GF110_DISP_CURSOR, 0 },
1212                 { GT214_DISP_CURSOR, 0 },
1213                 {   G82_DISP_CURSOR, 0 },
1214                 {  NV50_DISP_CURSOR, 0 },
1215                 {}
1216         };
1217         struct nv50_disp_cursor_v0 args = {
1218                 .head = head->base.index,
1219         };
1220         struct nv50_disp *disp = nv50_disp(drm->dev);
1221         struct nv50_curs *curs;
1222         int cid, ret;
1223
1224         cid = nvif_mclass(disp->disp, curses);
1225         if (cid < 0) {
1226                 NV_ERROR(drm, "No supported cursor immediate class\n");
1227                 return cid;
1228         }
1229
1230         if (!(curs = *pcurs = kzalloc(sizeof(*curs), GFP_KERNEL)))
1231                 return -ENOMEM;
1232
1233         ret = nv50_wndw_ctor(&nv50_curs, drm->dev, DRM_PLANE_TYPE_CURSOR,
1234                              "curs", head->base.index, &disp->mast.base,
1235                              nv50_curs_format, ARRAY_SIZE(nv50_curs_format),
1236                              &curs->wndw);
1237         if (ret) {
1238                 kfree(curs);
1239                 return ret;
1240         }
1241
1242         ret = nvif_object_init(disp->disp, 0, curses[cid].oclass, &args,
1243                                sizeof(args), &curs->chan);
1244         if (ret) {
1245                 NV_ERROR(drm, "curs%04x allocation failed: %d\n",
1246                          curses[cid].oclass, ret);
1247                 return ret;
1248         }
1249
1250         return 0;
1251 }
1252
1253 /******************************************************************************
1254  * Primary plane
1255  *****************************************************************************/
1256 #define nv50_base(p) container_of((p), struct nv50_base, wndw)
1257
1258 struct nv50_base {
1259         struct nv50_wndw wndw;
1260         struct nv50_sync chan;
1261         int id;
1262 };
1263
1264 static int
1265 nv50_base_notify(struct nvif_notify *notify)
1266 {
1267         return NVIF_NOTIFY_KEEP;
1268 }
1269
1270 static void
1271 nv50_base_lut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1272 {
1273         struct nv50_base *base = nv50_base(wndw);
1274         u32 *push;
1275         if ((push = evo_wait(&base->chan, 2))) {
1276                 evo_mthd(push, 0x00e0, 1);
1277                 evo_data(push, asyw->lut.enable << 30);
1278                 evo_kick(push, &base->chan);
1279         }
1280 }
1281
1282 static void
1283 nv50_base_image_clr(struct nv50_wndw *wndw)
1284 {
1285         struct nv50_base *base = nv50_base(wndw);
1286         u32 *push;
1287         if ((push = evo_wait(&base->chan, 4))) {
1288                 evo_mthd(push, 0x0084, 1);
1289                 evo_data(push, 0x00000000);
1290                 evo_mthd(push, 0x00c0, 1);
1291                 evo_data(push, 0x00000000);
1292                 evo_kick(push, &base->chan);
1293         }
1294 }
1295
1296 static void
1297 nv50_base_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1298 {
1299         struct nv50_base *base = nv50_base(wndw);
1300         const s32 oclass = base->chan.base.base.user.oclass;
1301         u32 *push;
1302         if ((push = evo_wait(&base->chan, 10))) {
1303                 evo_mthd(push, 0x0084, 1);
1304                 evo_data(push, (asyw->image.mode << 8) |
1305                                (asyw->image.interval << 4));
1306                 evo_mthd(push, 0x00c0, 1);
1307                 evo_data(push, asyw->image.handle);
1308                 if (oclass < G82_DISP_BASE_CHANNEL_DMA) {
1309                         evo_mthd(push, 0x0800, 5);
1310                         evo_data(push, asyw->image.offset >> 8);
1311                         evo_data(push, 0x00000000);
1312                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1313                         evo_data(push, (asyw->image.layout << 20) |
1314                                         asyw->image.pitch |
1315                                         asyw->image.block);
1316                         evo_data(push, (asyw->image.kind << 16) |
1317                                        (asyw->image.format << 8));
1318                 } else
1319                 if (oclass < GF110_DISP_BASE_CHANNEL_DMA) {
1320                         evo_mthd(push, 0x0800, 5);
1321                         evo_data(push, asyw->image.offset >> 8);
1322                         evo_data(push, 0x00000000);
1323                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1324                         evo_data(push, (asyw->image.layout << 20) |
1325                                         asyw->image.pitch |
1326                                         asyw->image.block);
1327                         evo_data(push, asyw->image.format << 8);
1328                 } else {
1329                         evo_mthd(push, 0x0400, 5);
1330                         evo_data(push, asyw->image.offset >> 8);
1331                         evo_data(push, 0x00000000);
1332                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1333                         evo_data(push, (asyw->image.layout << 24) |
1334                                         asyw->image.pitch |
1335                                         asyw->image.block);
1336                         evo_data(push, asyw->image.format << 8);
1337                 }
1338                 evo_kick(push, &base->chan);
1339         }
1340 }
1341
1342 static void
1343 nv50_base_ntfy_clr(struct nv50_wndw *wndw)
1344 {
1345         struct nv50_base *base = nv50_base(wndw);
1346         u32 *push;
1347         if ((push = evo_wait(&base->chan, 2))) {
1348                 evo_mthd(push, 0x00a4, 1);
1349                 evo_data(push, 0x00000000);
1350                 evo_kick(push, &base->chan);
1351         }
1352 }
1353
1354 static void
1355 nv50_base_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1356 {
1357         struct nv50_base *base = nv50_base(wndw);
1358         u32 *push;
1359         if ((push = evo_wait(&base->chan, 3))) {
1360                 evo_mthd(push, 0x00a0, 2);
1361                 evo_data(push, (asyw->ntfy.awaken << 30) | asyw->ntfy.offset);
1362                 evo_data(push, asyw->ntfy.handle);
1363                 evo_kick(push, &base->chan);
1364         }
1365 }
1366
1367 static void
1368 nv50_base_sema_clr(struct nv50_wndw *wndw)
1369 {
1370         struct nv50_base *base = nv50_base(wndw);
1371         u32 *push;
1372         if ((push = evo_wait(&base->chan, 2))) {
1373                 evo_mthd(push, 0x0094, 1);
1374                 evo_data(push, 0x00000000);
1375                 evo_kick(push, &base->chan);
1376         }
1377 }
1378
1379 static void
1380 nv50_base_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1381 {
1382         struct nv50_base *base = nv50_base(wndw);
1383         u32 *push;
1384         if ((push = evo_wait(&base->chan, 5))) {
1385                 evo_mthd(push, 0x0088, 4);
1386                 evo_data(push, asyw->sema.offset);
1387                 evo_data(push, asyw->sema.acquire);
1388                 evo_data(push, asyw->sema.release);
1389                 evo_data(push, asyw->sema.handle);
1390                 evo_kick(push, &base->chan);
1391         }
1392 }
1393
1394 static u32
1395 nv50_base_update(struct nv50_wndw *wndw, u32 interlock)
1396 {
1397         struct nv50_base *base = nv50_base(wndw);
1398         u32 *push;
1399
1400         if (!(push = evo_wait(&base->chan, 2)))
1401                 return 0;
1402         evo_mthd(push, 0x0080, 1);
1403         evo_data(push, interlock);
1404         evo_kick(push, &base->chan);
1405
1406         if (base->chan.base.base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA)
1407                 return interlock ? 2 << (base->id * 8) : 0;
1408         return interlock ? 2 << (base->id * 4) : 0;
1409 }
1410
1411 static int
1412 nv50_base_ntfy_wait_begun(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1413 {
1414         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
1415         struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
1416         if (nvif_msec(&drm->client.device, 2000ULL,
1417                 u32 data = nouveau_bo_rd32(disp->sync, asyw->ntfy.offset / 4);
1418                 if ((data & 0xc0000000) == 0x40000000)
1419                         break;
1420                 usleep_range(1, 2);
1421         ) < 0)
1422                 return -ETIMEDOUT;
1423         return 0;
1424 }
1425
1426 static void
1427 nv50_base_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1428                   struct nv50_head_atom *asyh)
1429 {
1430         asyh->base.cpp = 0;
1431 }
1432
1433 static int
1434 nv50_base_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1435                   struct nv50_head_atom *asyh)
1436 {
1437         const struct drm_framebuffer *fb = asyw->state.fb;
1438         struct drm_rect clip = {};
1439         int ret;
1440
1441         if (!fb->format->depth)
1442                 return -EINVAL;
1443
1444         if (asyh->state.enable)
1445                 drm_mode_get_hv_timing(&asyh->state.mode,
1446                                        &clip.x2, &clip.y2);
1447
1448         ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state,
1449                                                   &clip,
1450                                                   DRM_PLANE_HELPER_NO_SCALING,
1451                                                   DRM_PLANE_HELPER_NO_SCALING,
1452                                                   false, true);
1453         if (ret)
1454                 return ret;
1455
1456         asyh->base.depth = fb->format->depth;
1457         asyh->base.cpp = fb->format->cpp[0];
1458         asyh->base.x = asyw->state.src.x1 >> 16;
1459         asyh->base.y = asyw->state.src.y1 >> 16;
1460         asyh->base.w = asyw->state.fb->width;
1461         asyh->base.h = asyw->state.fb->height;
1462
1463         switch (fb->format->format) {
1464         case DRM_FORMAT_C8         : asyw->image.format = 0x1e; break;
1465         case DRM_FORMAT_RGB565     : asyw->image.format = 0xe8; break;
1466         case DRM_FORMAT_XRGB1555   :
1467         case DRM_FORMAT_ARGB1555   : asyw->image.format = 0xe9; break;
1468         case DRM_FORMAT_XRGB8888   :
1469         case DRM_FORMAT_ARGB8888   : asyw->image.format = 0xcf; break;
1470         case DRM_FORMAT_XBGR2101010:
1471         case DRM_FORMAT_ABGR2101010: asyw->image.format = 0xd1; break;
1472         case DRM_FORMAT_XBGR8888   :
1473         case DRM_FORMAT_ABGR8888   : asyw->image.format = 0xd5; break;
1474         default:
1475                 WARN_ON(1);
1476                 return -EINVAL;
1477         }
1478
1479         asyw->lut.enable = 1;
1480         asyw->set.image = true;
1481         return 0;
1482 }
1483
1484 static void *
1485 nv50_base_dtor(struct nv50_wndw *wndw)
1486 {
1487         struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
1488         struct nv50_base *base = nv50_base(wndw);
1489         nv50_dmac_destroy(&base->chan.base, disp->disp);
1490         return base;
1491 }
1492
1493 static const u32
1494 nv50_base_format[] = {
1495         DRM_FORMAT_C8,
1496         DRM_FORMAT_RGB565,
1497         DRM_FORMAT_XRGB1555,
1498         DRM_FORMAT_ARGB1555,
1499         DRM_FORMAT_XRGB8888,
1500         DRM_FORMAT_ARGB8888,
1501         DRM_FORMAT_XBGR2101010,
1502         DRM_FORMAT_ABGR2101010,
1503         DRM_FORMAT_XBGR8888,
1504         DRM_FORMAT_ABGR8888,
1505 };
1506
1507 static const struct nv50_wndw_func
1508 nv50_base = {
1509         .dtor = nv50_base_dtor,
1510         .acquire = nv50_base_acquire,
1511         .release = nv50_base_release,
1512         .sema_set = nv50_base_sema_set,
1513         .sema_clr = nv50_base_sema_clr,
1514         .ntfy_set = nv50_base_ntfy_set,
1515         .ntfy_clr = nv50_base_ntfy_clr,
1516         .ntfy_wait_begun = nv50_base_ntfy_wait_begun,
1517         .image_set = nv50_base_image_set,
1518         .image_clr = nv50_base_image_clr,
1519         .lut = nv50_base_lut,
1520         .update = nv50_base_update,
1521 };
1522
1523 static int
1524 nv50_base_new(struct nouveau_drm *drm, struct nv50_head *head,
1525               struct nv50_base **pbase)
1526 {
1527         struct nv50_disp *disp = nv50_disp(drm->dev);
1528         struct nv50_base *base;
1529         int ret;
1530
1531         if (!(base = *pbase = kzalloc(sizeof(*base), GFP_KERNEL)))
1532                 return -ENOMEM;
1533         base->id = head->base.index;
1534         base->wndw.ntfy = EVO_FLIP_NTFY0(base->id);
1535         base->wndw.sema = EVO_FLIP_SEM0(base->id);
1536         base->wndw.data = 0x00000000;
1537
1538         ret = nv50_wndw_ctor(&nv50_base, drm->dev, DRM_PLANE_TYPE_PRIMARY,
1539                              "base", base->id, &base->chan.base,
1540                              nv50_base_format, ARRAY_SIZE(nv50_base_format),
1541                              &base->wndw);
1542         if (ret) {
1543                 kfree(base);
1544                 return ret;
1545         }
1546
1547         ret = nv50_base_create(&drm->client.device, disp->disp, base->id,
1548                                disp->sync->bo.offset, &base->chan);
1549         if (ret)
1550                 return ret;
1551
1552         return nvif_notify_init(&base->chan.base.base.user, nv50_base_notify,
1553                                 false,
1554                                 NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT,
1555                                 &(struct nvif_notify_uevent_req) {},
1556                                 sizeof(struct nvif_notify_uevent_req),
1557                                 sizeof(struct nvif_notify_uevent_rep),
1558                                 &base->wndw.notify);
1559 }
1560
1561 /******************************************************************************
1562  * Head
1563  *****************************************************************************/
1564 static void
1565 nv50_head_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
1566 {
1567         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1568         u32 *push;
1569         if ((push = evo_wait(core, 2))) {
1570                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1571                         evo_mthd(push, 0x08a8 + (head->base.index * 0x400), 1);
1572                 else
1573                         evo_mthd(push, 0x0498 + (head->base.index * 0x300), 1);
1574                 evo_data(push, (asyh->procamp.sat.sin << 20) |
1575                                (asyh->procamp.sat.cos << 8));
1576                 evo_kick(push, core);
1577         }
1578 }
1579
1580 static void
1581 nv50_head_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
1582 {
1583         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1584         u32 *push;
1585         if ((push = evo_wait(core, 2))) {
1586                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1587                         evo_mthd(push, 0x08a0 + (head->base.index * 0x0400), 1);
1588                 else
1589                 if (core->base.user.oclass < GK104_DISP_CORE_CHANNEL_DMA)
1590                         evo_mthd(push, 0x0490 + (head->base.index * 0x0300), 1);
1591                 else
1592                         evo_mthd(push, 0x04a0 + (head->base.index * 0x0300), 1);
1593                 evo_data(push, (asyh->dither.mode << 3) |
1594                                (asyh->dither.bits << 1) |
1595                                 asyh->dither.enable);
1596                 evo_kick(push, core);
1597         }
1598 }
1599
1600 static void
1601 nv50_head_ovly(struct nv50_head *head, struct nv50_head_atom *asyh)
1602 {
1603         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1604         u32 bounds = 0;
1605         u32 *push;
1606
1607         if (asyh->base.cpp) {
1608                 switch (asyh->base.cpp) {
1609                 case 8: bounds |= 0x00000500; break;
1610                 case 4: bounds |= 0x00000300; break;
1611                 case 2: bounds |= 0x00000100; break;
1612                 default:
1613                         WARN_ON(1);
1614                         break;
1615                 }
1616                 bounds |= 0x00000001;
1617         }
1618
1619         if ((push = evo_wait(core, 2))) {
1620                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1621                         evo_mthd(push, 0x0904 + head->base.index * 0x400, 1);
1622                 else
1623                         evo_mthd(push, 0x04d4 + head->base.index * 0x300, 1);
1624                 evo_data(push, bounds);
1625                 evo_kick(push, core);
1626         }
1627 }
1628
1629 static void
1630 nv50_head_base(struct nv50_head *head, struct nv50_head_atom *asyh)
1631 {
1632         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1633         u32 bounds = 0;
1634         u32 *push;
1635
1636         if (asyh->base.cpp) {
1637                 switch (asyh->base.cpp) {
1638                 case 8: bounds |= 0x00000500; break;
1639                 case 4: bounds |= 0x00000300; break;
1640                 case 2: bounds |= 0x00000100; break;
1641                 case 1: bounds |= 0x00000000; break;
1642                 default:
1643                         WARN_ON(1);
1644                         break;
1645                 }
1646                 bounds |= 0x00000001;
1647         }
1648
1649         if ((push = evo_wait(core, 2))) {
1650                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1651                         evo_mthd(push, 0x0900 + head->base.index * 0x400, 1);
1652                 else
1653                         evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1);
1654                 evo_data(push, bounds);
1655                 evo_kick(push, core);
1656         }
1657 }
1658
1659 static void
1660 nv50_head_curs_clr(struct nv50_head *head)
1661 {
1662         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1663         u32 *push;
1664         if ((push = evo_wait(core, 4))) {
1665                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1666                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
1667                         evo_data(push, 0x05000000);
1668                 } else
1669                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1670                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
1671                         evo_data(push, 0x05000000);
1672                         evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
1673                         evo_data(push, 0x00000000);
1674                 } else {
1675                         evo_mthd(push, 0x0480 + head->base.index * 0x300, 1);
1676                         evo_data(push, 0x05000000);
1677                         evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
1678                         evo_data(push, 0x00000000);
1679                 }
1680                 evo_kick(push, core);
1681         }
1682 }
1683
1684 static void
1685 nv50_head_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1686 {
1687         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1688         u32 *push;
1689         if ((push = evo_wait(core, 5))) {
1690                 if (core->base.user.oclass < G82_DISP_BASE_CHANNEL_DMA) {
1691                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
1692                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1693                                                     (asyh->curs.format << 24));
1694                         evo_data(push, asyh->curs.offset >> 8);
1695                 } else
1696                 if (core->base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA) {
1697                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
1698                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1699                                                     (asyh->curs.format << 24));
1700                         evo_data(push, asyh->curs.offset >> 8);
1701                         evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
1702                         evo_data(push, asyh->curs.handle);
1703                 } else {
1704                         evo_mthd(push, 0x0480 + head->base.index * 0x300, 2);
1705                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1706                                                     (asyh->curs.format << 24));
1707                         evo_data(push, asyh->curs.offset >> 8);
1708                         evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
1709                         evo_data(push, asyh->curs.handle);
1710                 }
1711                 evo_kick(push, core);
1712         }
1713 }
1714
1715 static void
1716 nv50_head_core_clr(struct nv50_head *head)
1717 {
1718         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1719         u32 *push;
1720         if ((push = evo_wait(core, 2))) {
1721                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1722                         evo_mthd(push, 0x0874 + head->base.index * 0x400, 1);
1723                 else
1724                         evo_mthd(push, 0x0474 + head->base.index * 0x300, 1);
1725                 evo_data(push, 0x00000000);
1726                 evo_kick(push, core);
1727         }
1728 }
1729
1730 static void
1731 nv50_head_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1732 {
1733         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1734         u32 *push;
1735         if ((push = evo_wait(core, 9))) {
1736                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1737                         evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
1738                         evo_data(push, asyh->core.offset >> 8);
1739                         evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
1740                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1741                         evo_data(push, asyh->core.layout << 20 |
1742                                        (asyh->core.pitch >> 8) << 8 |
1743                                        asyh->core.block);
1744                         evo_data(push, asyh->core.kind << 16 |
1745                                        asyh->core.format << 8);
1746                         evo_data(push, asyh->core.handle);
1747                         evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
1748                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1749                         /* EVO will complain with INVALID_STATE if we have an
1750                          * active cursor and (re)specify HeadSetContextDmaIso
1751                          * without also updating HeadSetOffsetCursor.
1752                          */
1753                         asyh->set.curs = asyh->curs.visible;
1754                 } else
1755                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1756                         evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
1757                         evo_data(push, asyh->core.offset >> 8);
1758                         evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
1759                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1760                         evo_data(push, asyh->core.layout << 20 |
1761                                        (asyh->core.pitch >> 8) << 8 |
1762                                        asyh->core.block);
1763                         evo_data(push, asyh->core.format << 8);
1764                         evo_data(push, asyh->core.handle);
1765                         evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
1766                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1767                 } else {
1768                         evo_mthd(push, 0x0460 + head->base.index * 0x300, 1);
1769                         evo_data(push, asyh->core.offset >> 8);
1770                         evo_mthd(push, 0x0468 + head->base.index * 0x300, 4);
1771                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1772                         evo_data(push, asyh->core.layout << 24 |
1773                                        (asyh->core.pitch >> 8) << 8 |
1774                                        asyh->core.block);
1775                         evo_data(push, asyh->core.format << 8);
1776                         evo_data(push, asyh->core.handle);
1777                         evo_mthd(push, 0x04b0 + head->base.index * 0x300, 1);
1778                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1779                 }
1780                 evo_kick(push, core);
1781         }
1782 }
1783
1784 static void
1785 nv50_head_lut_clr(struct nv50_head *head)
1786 {
1787         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1788         u32 *push;
1789         if ((push = evo_wait(core, 4))) {
1790                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1791                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
1792                         evo_data(push, 0x40000000);
1793                 } else
1794                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1795                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
1796                         evo_data(push, 0x40000000);
1797                         evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
1798                         evo_data(push, 0x00000000);
1799                 } else {
1800                         evo_mthd(push, 0x0440 + (head->base.index * 0x300), 1);
1801                         evo_data(push, 0x03000000);
1802                         evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
1803                         evo_data(push, 0x00000000);
1804                 }
1805                 evo_kick(push, core);
1806         }
1807 }
1808
1809 static void
1810 nv50_head_lut_load(struct drm_property_blob *blob, int mode,
1811                    struct nouveau_bo *nvbo)
1812 {
1813         struct drm_color_lut *in = (struct drm_color_lut *)blob->data;
1814         void __iomem *lut = (u8 *)nvbo_kmap_obj_iovirtual(nvbo);
1815         const int size = blob->length / sizeof(*in);
1816         int bits, shift, i;
1817         u16 zero, r, g, b;
1818
1819         /* This can't happen.. But it shuts the compiler up. */
1820         if (WARN_ON(size != 256))
1821                 return;
1822
1823         switch (mode) {
1824         case 0: /* LORES. */
1825         case 1: /* HIRES. */
1826                 bits = 11;
1827                 shift = 3;
1828                 zero = 0x0000;
1829                 break;
1830         case 7: /* INTERPOLATE_257_UNITY_RANGE. */
1831                 bits = 14;
1832                 shift = 0;
1833                 zero = 0x6000;
1834                 break;
1835         default:
1836                 WARN_ON(1);
1837                 return;
1838         }
1839
1840         for (i = 0; i < size; i++) {
1841                 r = (drm_color_lut_extract(in[i].  red, bits) + zero) << shift;
1842                 g = (drm_color_lut_extract(in[i].green, bits) + zero) << shift;
1843                 b = (drm_color_lut_extract(in[i]. blue, bits) + zero) << shift;
1844                 writew(r, lut + (i * 0x08) + 0);
1845                 writew(g, lut + (i * 0x08) + 2);
1846                 writew(b, lut + (i * 0x08) + 4);
1847         }
1848
1849         /* INTERPOLATE modes require a "next" entry to interpolate with,
1850          * so we replicate the last entry to deal with this for now.
1851          */
1852         writew(r, lut + (i * 0x08) + 0);
1853         writew(g, lut + (i * 0x08) + 2);
1854         writew(b, lut + (i * 0x08) + 4);
1855 }
1856
1857 static void
1858 nv50_head_lut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1859 {
1860         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1861         u32 *push;
1862         if ((push = evo_wait(core, 7))) {
1863                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1864                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1865                         evo_data(push, 0x80000000 | asyh->lut.mode << 30);
1866                         evo_data(push, asyh->lut.offset >> 8);
1867                 } else
1868                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1869                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1870                         evo_data(push, 0x80000000 | asyh->lut.mode << 30);
1871                         evo_data(push, asyh->lut.offset >> 8);
1872                         evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
1873                         evo_data(push, asyh->lut.handle);
1874                 } else {
1875                         evo_mthd(push, 0x0440 + (head->base.index * 0x300), 4);
1876                         evo_data(push, 0x80000000 | asyh->lut.mode << 24);
1877                         evo_data(push, asyh->lut.offset >> 8);
1878                         evo_data(push, 0x00000000);
1879                         evo_data(push, 0x00000000);
1880                         evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
1881                         evo_data(push, asyh->lut.handle);
1882                 }
1883                 evo_kick(push, core);
1884         }
1885 }
1886
1887 static void
1888 nv50_head_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
1889 {
1890         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1891         struct nv50_head_mode *m = &asyh->mode;
1892         u32 *push;
1893         if ((push = evo_wait(core, 14))) {
1894                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1895                         evo_mthd(push, 0x0804 + (head->base.index * 0x400), 2);
1896                         evo_data(push, 0x00800000 | m->clock);
1897                         evo_data(push, m->interlace ? 0x00000002 : 0x00000000);
1898                         evo_mthd(push, 0x0810 + (head->base.index * 0x400), 7);
1899                         evo_data(push, 0x00000000);
1900                         evo_data(push, (m->v.active  << 16) | m->h.active );
1901                         evo_data(push, (m->v.synce   << 16) | m->h.synce  );
1902                         evo_data(push, (m->v.blanke  << 16) | m->h.blanke );
1903                         evo_data(push, (m->v.blanks  << 16) | m->h.blanks );
1904                         evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1905                         evo_data(push, asyh->mode.v.blankus);
1906                         evo_mthd(push, 0x082c + (head->base.index * 0x400), 1);
1907                         evo_data(push, 0x00000000);
1908                 } else {
1909                         evo_mthd(push, 0x0410 + (head->base.index * 0x300), 6);
1910                         evo_data(push, 0x00000000);
1911                         evo_data(push, (m->v.active  << 16) | m->h.active );
1912                         evo_data(push, (m->v.synce   << 16) | m->h.synce  );
1913                         evo_data(push, (m->v.blanke  << 16) | m->h.blanke );
1914                         evo_data(push, (m->v.blanks  << 16) | m->h.blanks );
1915                         evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1916                         evo_mthd(push, 0x042c + (head->base.index * 0x300), 2);
1917                         evo_data(push, 0x00000000); /* ??? */
1918                         evo_data(push, 0xffffff00);
1919                         evo_mthd(push, 0x0450 + (head->base.index * 0x300), 3);
1920                         evo_data(push, m->clock * 1000);
1921                         evo_data(push, 0x00200000); /* ??? */
1922                         evo_data(push, m->clock * 1000);
1923                 }
1924                 evo_kick(push, core);
1925         }
1926 }
1927
1928 static void
1929 nv50_head_view(struct nv50_head *head, struct nv50_head_atom *asyh)
1930 {
1931         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1932         u32 *push;
1933         if ((push = evo_wait(core, 10))) {
1934                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1935                         evo_mthd(push, 0x08a4 + (head->base.index * 0x400), 1);
1936                         evo_data(push, 0x00000000);
1937                         evo_mthd(push, 0x08c8 + (head->base.index * 0x400), 1);
1938                         evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1939                         evo_mthd(push, 0x08d8 + (head->base.index * 0x400), 2);
1940                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1941                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1942                 } else {
1943                         evo_mthd(push, 0x0494 + (head->base.index * 0x300), 1);
1944                         evo_data(push, 0x00000000);
1945                         evo_mthd(push, 0x04b8 + (head->base.index * 0x300), 1);
1946                         evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1947                         evo_mthd(push, 0x04c0 + (head->base.index * 0x300), 3);
1948                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1949                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1950                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1951                 }
1952                 evo_kick(push, core);
1953         }
1954 }
1955
1956 static void
1957 nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool y)
1958 {
1959         if (asyh->clr.ilut && (!asyh->set.ilut || y))
1960                 nv50_head_lut_clr(head);
1961         if (asyh->clr.core && (!asyh->set.core || y))
1962                 nv50_head_core_clr(head);
1963         if (asyh->clr.curs && (!asyh->set.curs || y))
1964                 nv50_head_curs_clr(head);
1965 }
1966
1967 static void
1968 nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1969 {
1970         if (asyh->set.view   ) nv50_head_view    (head, asyh);
1971         if (asyh->set.mode   ) nv50_head_mode    (head, asyh);
1972         if (asyh->set.ilut   ) {
1973                 struct nouveau_bo *nvbo = head->lut.nvbo[head->lut.next];
1974                 struct drm_property_blob *blob = asyh->state.gamma_lut;
1975                 if (blob)
1976                         nv50_head_lut_load(blob, asyh->lut.mode, nvbo);
1977                 asyh->lut.offset = nvbo->bo.offset;
1978                 head->lut.next ^= 1;
1979                 nv50_head_lut_set(head, asyh);
1980         }
1981         if (asyh->set.core   ) nv50_head_core_set(head, asyh);
1982         if (asyh->set.curs   ) nv50_head_curs_set(head, asyh);
1983         if (asyh->set.base   ) nv50_head_base    (head, asyh);
1984         if (asyh->set.ovly   ) nv50_head_ovly    (head, asyh);
1985         if (asyh->set.dither ) nv50_head_dither  (head, asyh);
1986         if (asyh->set.procamp) nv50_head_procamp (head, asyh);
1987 }
1988
1989 static void
1990 nv50_head_atomic_check_procamp(struct nv50_head_atom *armh,
1991                                struct nv50_head_atom *asyh,
1992                                struct nouveau_conn_atom *asyc)
1993 {
1994         const int vib = asyc->procamp.color_vibrance - 100;
1995         const int hue = asyc->procamp.vibrant_hue - 90;
1996         const int adj = (vib > 0) ? 50 : 0;
1997         asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff;
1998         asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff;
1999         asyh->set.procamp = true;
2000 }
2001
2002 static void
2003 nv50_head_atomic_check_dither(struct nv50_head_atom *armh,
2004                               struct nv50_head_atom *asyh,
2005                               struct nouveau_conn_atom *asyc)
2006 {
2007         struct drm_connector *connector = asyc->state.connector;
2008         u32 mode = 0x00;
2009
2010         if (asyc->dither.mode == DITHERING_MODE_AUTO) {
2011                 if (asyh->base.depth > connector->display_info.bpc * 3)
2012                         mode = DITHERING_MODE_DYNAMIC2X2;
2013         } else {
2014                 mode = asyc->dither.mode;
2015         }
2016
2017         if (asyc->dither.depth == DITHERING_DEPTH_AUTO) {
2018                 if (connector->display_info.bpc >= 8)
2019                         mode |= DITHERING_DEPTH_8BPC;
2020         } else {
2021                 mode |= asyc->dither.depth;
2022         }
2023
2024         asyh->dither.enable = mode;
2025         asyh->dither.bits = mode >> 1;
2026         asyh->dither.mode = mode >> 3;
2027         asyh->set.dither = true;
2028 }
2029
2030 static void
2031 nv50_head_atomic_check_view(struct nv50_head_atom *armh,
2032                             struct nv50_head_atom *asyh,
2033                             struct nouveau_conn_atom *asyc)
2034 {
2035         struct drm_connector *connector = asyc->state.connector;
2036         struct drm_display_mode *omode = &asyh->state.adjusted_mode;
2037         struct drm_display_mode *umode = &asyh->state.mode;
2038         int mode = asyc->scaler.mode;
2039         struct edid *edid;
2040         int umode_vdisplay, omode_hdisplay, omode_vdisplay;
2041
2042         if (connector->edid_blob_ptr)
2043                 edid = (struct edid *)connector->edid_blob_ptr->data;
2044         else
2045                 edid = NULL;
2046
2047         if (!asyc->scaler.full) {
2048                 if (mode == DRM_MODE_SCALE_NONE)
2049                         omode = umode;
2050         } else {
2051                 /* Non-EDID LVDS/eDP mode. */
2052                 mode = DRM_MODE_SCALE_FULLSCREEN;
2053         }
2054
2055         /* For the user-specified mode, we must ignore doublescan and
2056          * the like, but honor frame packing.
2057          */
2058         umode_vdisplay = umode->vdisplay;
2059         if ((umode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2060                 umode_vdisplay += umode->vtotal;
2061         asyh->view.iW = umode->hdisplay;
2062         asyh->view.iH = umode_vdisplay;
2063         /* For the output mode, we can just use the stock helper. */
2064         drm_mode_get_hv_timing(omode, &omode_hdisplay, &omode_vdisplay);
2065         asyh->view.oW = omode_hdisplay;
2066         asyh->view.oH = omode_vdisplay;
2067
2068         /* Add overscan compensation if necessary, will keep the aspect
2069          * ratio the same as the backend mode unless overridden by the
2070          * user setting both hborder and vborder properties.
2071          */
2072         if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
2073             (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
2074              drm_detect_hdmi_monitor(edid)))) {
2075                 u32 bX = asyc->scaler.underscan.hborder;
2076                 u32 bY = asyc->scaler.underscan.vborder;
2077                 u32 r = (asyh->view.oH << 19) / asyh->view.oW;
2078
2079                 if (bX) {
2080                         asyh->view.oW -= (bX * 2);
2081                         if (bY) asyh->view.oH -= (bY * 2);
2082                         else    asyh->view.oH  = ((asyh->view.oW * r) + (r / 2)) >> 19;
2083                 } else {
2084                         asyh->view.oW -= (asyh->view.oW >> 4) + 32;
2085                         if (bY) asyh->view.oH -= (bY * 2);
2086                         else    asyh->view.oH  = ((asyh->view.oW * r) + (r / 2)) >> 19;
2087                 }
2088         }
2089
2090         /* Handle CENTER/ASPECT scaling, taking into account the areas
2091          * removed already for overscan compensation.
2092          */
2093         switch (mode) {
2094         case DRM_MODE_SCALE_CENTER:
2095                 asyh->view.oW = min((u16)umode->hdisplay, asyh->view.oW);
2096                 asyh->view.oH = min((u16)umode_vdisplay, asyh->view.oH);
2097                 /* fall-through */
2098         case DRM_MODE_SCALE_ASPECT:
2099                 if (asyh->view.oH < asyh->view.oW) {
2100                         u32 r = (asyh->view.iW << 19) / asyh->view.iH;
2101                         asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
2102                 } else {
2103                         u32 r = (asyh->view.iH << 19) / asyh->view.iW;
2104                         asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
2105                 }
2106                 break;
2107         default:
2108                 break;
2109         }
2110
2111         asyh->set.view = true;
2112 }
2113
2114 static void
2115 nv50_head_atomic_check_lut(struct nv50_head *head,
2116                            struct nv50_head_atom *armh,
2117                            struct nv50_head_atom *asyh)
2118 {
2119         struct nv50_disp *disp = nv50_disp(head->base.base.dev);
2120
2121         /* An I8 surface without an input LUT makes no sense, and
2122          * EVO will throw an error if you try.
2123          *
2124          * Legacy clients actually cause this due to the order in
2125          * which they call ioctls, so we will enable the LUT with
2126          * whatever contents the buffer already contains to avoid
2127          * triggering the error check.
2128          */
2129         if (!asyh->state.gamma_lut && asyh->base.cpp != 1) {
2130                 asyh->lut.handle = 0;
2131                 asyh->clr.ilut = armh->lut.visible;
2132                 return;
2133         }
2134
2135         if (disp->disp->oclass < GF110_DISP) {
2136                 asyh->lut.mode = (asyh->base.cpp == 1) ? 0 : 1;
2137                 asyh->set.ilut = true;
2138         } else {
2139                 asyh->lut.mode = 7;
2140                 asyh->set.ilut = asyh->state.color_mgmt_changed;
2141         }
2142         asyh->lut.handle = disp->mast.base.vram.handle;
2143 }
2144
2145 static void
2146 nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
2147 {
2148         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
2149         struct nv50_head_mode *m = &asyh->mode;
2150         u32 blankus;
2151
2152         drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
2153
2154         /*
2155          * DRM modes are defined in terms of a repeating interval
2156          * starting with the active display area.  The hardware modes
2157          * are defined in terms of a repeating interval starting one
2158          * unit (pixel or line) into the sync pulse.  So, add bias.
2159          */
2160
2161         m->h.active = mode->crtc_htotal;
2162         m->h.synce  = mode->crtc_hsync_end - mode->crtc_hsync_start - 1;
2163         m->h.blanke = mode->crtc_hblank_end - mode->crtc_hsync_start - 1;
2164         m->h.blanks = m->h.blanke + mode->crtc_hdisplay;
2165
2166         m->v.active = mode->crtc_vtotal;
2167         m->v.synce  = mode->crtc_vsync_end - mode->crtc_vsync_start - 1;
2168         m->v.blanke = mode->crtc_vblank_end - mode->crtc_vsync_start - 1;
2169         m->v.blanks = m->v.blanke + mode->crtc_vdisplay;
2170
2171         /*XXX: Safe underestimate, even "0" works */
2172         blankus = (m->v.active - mode->crtc_vdisplay - 2) * m->h.active;
2173         blankus *= 1000;
2174         blankus /= mode->crtc_clock;
2175         m->v.blankus = blankus;
2176
2177         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2178                 m->v.blank2e =  m->v.active + m->v.blanke;
2179                 m->v.blank2s =  m->v.blank2e + mode->crtc_vdisplay;
2180                 m->v.active  = (m->v.active * 2) + 1;
2181                 m->interlace = true;
2182         } else {
2183                 m->v.blank2e = 0;
2184                 m->v.blank2s = 1;
2185                 m->interlace = false;
2186         }
2187         m->clock = mode->crtc_clock;
2188
2189         asyh->set.mode = true;
2190 }
2191
2192 static int
2193 nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
2194 {
2195         struct nouveau_drm *drm = nouveau_drm(crtc->dev);
2196         struct nv50_disp *disp = nv50_disp(crtc->dev);
2197         struct nv50_head *head = nv50_head(crtc);
2198         struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
2199         struct nv50_head_atom *asyh = nv50_head_atom(state);
2200         struct nouveau_conn_atom *asyc = NULL;
2201         struct drm_connector_state *conns;
2202         struct drm_connector *conn;
2203         int i;
2204
2205         NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
2206         if (asyh->state.active) {
2207                 for_each_new_connector_in_state(asyh->state.state, conn, conns, i) {
2208                         if (conns->crtc == crtc) {
2209                                 asyc = nouveau_conn_atom(conns);
2210                                 break;
2211                         }
2212                 }
2213
2214                 if (armh->state.active) {
2215                         if (asyc) {
2216                                 if (asyh->state.mode_changed)
2217                                         asyc->set.scaler = true;
2218                                 if (armh->base.depth != asyh->base.depth)
2219                                         asyc->set.dither = true;
2220                         }
2221                 } else {
2222                         if (asyc)
2223                                 asyc->set.mask = ~0;
2224                         asyh->set.mask = ~0;
2225                 }
2226
2227                 if (asyh->state.mode_changed)
2228                         nv50_head_atomic_check_mode(head, asyh);
2229
2230                 if (asyh->state.color_mgmt_changed ||
2231                     asyh->base.cpp != armh->base.cpp)
2232                         nv50_head_atomic_check_lut(head, armh, asyh);
2233                 asyh->lut.visible = asyh->lut.handle != 0;
2234
2235                 if (asyc) {
2236                         if (asyc->set.scaler)
2237                                 nv50_head_atomic_check_view(armh, asyh, asyc);
2238                         if (asyc->set.dither)
2239                                 nv50_head_atomic_check_dither(armh, asyh, asyc);
2240                         if (asyc->set.procamp)
2241                                 nv50_head_atomic_check_procamp(armh, asyh, asyc);
2242                 }
2243
2244                 if ((asyh->core.visible = (asyh->base.cpp != 0))) {
2245                         asyh->core.x = asyh->base.x;
2246                         asyh->core.y = asyh->base.y;
2247                         asyh->core.w = asyh->base.w;
2248                         asyh->core.h = asyh->base.h;
2249                 } else
2250                 if ((asyh->core.visible = asyh->curs.visible) ||
2251                     (asyh->core.visible = asyh->lut.visible)) {
2252                         /*XXX: We need to either find some way of having the
2253                          *     primary base layer appear black, while still
2254                          *     being able to display the other layers, or we
2255                          *     need to allocate a dummy black surface here.
2256                          */
2257                         asyh->core.x = 0;
2258                         asyh->core.y = 0;
2259                         asyh->core.w = asyh->state.mode.hdisplay;
2260                         asyh->core.h = asyh->state.mode.vdisplay;
2261                 }
2262                 asyh->core.handle = disp->mast.base.vram.handle;
2263                 asyh->core.offset = 0;
2264                 asyh->core.format = 0xcf;
2265                 asyh->core.kind = 0;
2266                 asyh->core.layout = 1;
2267                 asyh->core.block = 0;
2268                 asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4;
2269                 asyh->set.base = armh->base.cpp != asyh->base.cpp;
2270                 asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
2271         } else {
2272                 asyh->lut.visible = false;
2273                 asyh->core.visible = false;
2274                 asyh->curs.visible = false;
2275                 asyh->base.cpp = 0;
2276                 asyh->ovly.cpp = 0;
2277         }
2278
2279         if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
2280                 if (asyh->core.visible) {
2281                         if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
2282                                 asyh->set.core = true;
2283                 } else
2284                 if (armh->core.visible) {
2285                         asyh->clr.core = true;
2286                 }
2287
2288                 if (asyh->curs.visible) {
2289                         if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))
2290                                 asyh->set.curs = true;
2291                 } else
2292                 if (armh->curs.visible) {
2293                         asyh->clr.curs = true;
2294                 }
2295         } else {
2296                 asyh->clr.ilut = armh->lut.visible;
2297                 asyh->clr.core = armh->core.visible;
2298                 asyh->clr.curs = armh->curs.visible;
2299                 asyh->set.ilut = asyh->lut.visible;
2300                 asyh->set.core = asyh->core.visible;
2301                 asyh->set.curs = asyh->curs.visible;
2302         }
2303
2304         if (asyh->clr.mask || asyh->set.mask)
2305                 nv50_atom(asyh->state.state)->lock_core = true;
2306         return 0;
2307 }
2308
2309 static const struct drm_crtc_helper_funcs
2310 nv50_head_help = {
2311         .atomic_check = nv50_head_atomic_check,
2312 };
2313
2314 static void
2315 nv50_head_atomic_destroy_state(struct drm_crtc *crtc,
2316                                struct drm_crtc_state *state)
2317 {
2318         struct nv50_head_atom *asyh = nv50_head_atom(state);
2319         __drm_atomic_helper_crtc_destroy_state(&asyh->state);
2320         kfree(asyh);
2321 }
2322
2323 static struct drm_crtc_state *
2324 nv50_head_atomic_duplicate_state(struct drm_crtc *crtc)
2325 {
2326         struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
2327         struct nv50_head_atom *asyh;
2328         if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL)))
2329                 return NULL;
2330         __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state);
2331         asyh->view = armh->view;
2332         asyh->mode = armh->mode;
2333         asyh->lut  = armh->lut;
2334         asyh->core = armh->core;
2335         asyh->curs = armh->curs;
2336         asyh->base = armh->base;
2337         asyh->ovly = armh->ovly;
2338         asyh->dither = armh->dither;
2339         asyh->procamp = armh->procamp;
2340         asyh->clr.mask = 0;
2341         asyh->set.mask = 0;
2342         return &asyh->state;
2343 }
2344
2345 static void
2346 __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc,
2347                                struct drm_crtc_state *state)
2348 {
2349         if (crtc->state)
2350                 crtc->funcs->atomic_destroy_state(crtc, crtc->state);
2351         crtc->state = state;
2352         crtc->state->crtc = crtc;
2353 }
2354
2355 static void
2356 nv50_head_reset(struct drm_crtc *crtc)
2357 {
2358         struct nv50_head_atom *asyh;
2359
2360         if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL))))
2361                 return;
2362
2363         __drm_atomic_helper_crtc_reset(crtc, &asyh->state);
2364 }
2365
2366 static void
2367 nv50_head_destroy(struct drm_crtc *crtc)
2368 {
2369         struct nv50_disp *disp = nv50_disp(crtc->dev);
2370         struct nv50_head *head = nv50_head(crtc);
2371         int i;
2372
2373         nv50_dmac_destroy(&head->ovly.base, disp->disp);
2374         nv50_pioc_destroy(&head->oimm.base);
2375
2376         for (i = 0; i < ARRAY_SIZE(head->lut.nvbo); i++)
2377                 nouveau_bo_unmap_unpin_unref(&head->lut.nvbo[i]);
2378
2379         drm_crtc_cleanup(crtc);
2380         kfree(crtc);
2381 }
2382
2383 static const struct drm_crtc_funcs
2384 nv50_head_func = {
2385         .reset = nv50_head_reset,
2386         .gamma_set = drm_atomic_helper_legacy_gamma_set,
2387         .destroy = nv50_head_destroy,
2388         .set_config = drm_atomic_helper_set_config,
2389         .page_flip = drm_atomic_helper_page_flip,
2390         .atomic_duplicate_state = nv50_head_atomic_duplicate_state,
2391         .atomic_destroy_state = nv50_head_atomic_destroy_state,
2392 };
2393
2394 static int
2395 nv50_head_create(struct drm_device *dev, int index)
2396 {
2397         struct nouveau_drm *drm = nouveau_drm(dev);
2398         struct nvif_device *device = &drm->client.device;
2399         struct nv50_disp *disp = nv50_disp(dev);
2400         struct nv50_head *head;
2401         struct nv50_base *base;
2402         struct nv50_curs *curs;
2403         struct drm_crtc *crtc;
2404         int ret, i;
2405
2406         head = kzalloc(sizeof(*head), GFP_KERNEL);
2407         if (!head)
2408                 return -ENOMEM;
2409
2410         head->base.index = index;
2411         ret = nv50_base_new(drm, head, &base);
2412         if (ret == 0)
2413                 ret = nv50_curs_new(drm, head, &curs);
2414         if (ret) {
2415                 kfree(head);
2416                 return ret;
2417         }
2418
2419         crtc = &head->base.base;
2420         drm_crtc_init_with_planes(dev, crtc, &base->wndw.plane,
2421                                   &curs->wndw.plane, &nv50_head_func,
2422                                   "head-%d", head->base.index);
2423         drm_crtc_helper_add(crtc, &nv50_head_help);
2424         drm_mode_crtc_set_gamma_size(crtc, 256);
2425
2426         for (i = 0; i < ARRAY_SIZE(head->lut.nvbo); i++) {
2427                 ret = nouveau_bo_new_pin_map(&drm->client, 1025 * 8, 0x100,
2428                                              TTM_PL_FLAG_VRAM,
2429                                              &head->lut.nvbo[i]);
2430                 if (ret)
2431                         goto out;
2432         }
2433
2434         /* allocate overlay resources */
2435         ret = nv50_oimm_create(device, disp->disp, index, &head->oimm);
2436         if (ret)
2437                 goto out;
2438
2439         ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset,
2440                                &head->ovly);
2441         if (ret)
2442                 goto out;
2443
2444 out:
2445         if (ret)
2446                 nv50_head_destroy(crtc);
2447         return ret;
2448 }
2449
2450 /******************************************************************************
2451  * Output path helpers
2452  *****************************************************************************/
2453 static void
2454 nv50_outp_release(struct nouveau_encoder *nv_encoder)
2455 {
2456         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
2457         struct {
2458                 struct nv50_disp_mthd_v1 base;
2459         } args = {
2460                 .base.version = 1,
2461                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
2462                 .base.hasht  = nv_encoder->dcb->hasht,
2463                 .base.hashm  = nv_encoder->dcb->hashm,
2464         };
2465
2466         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2467         nv_encoder->or = -1;
2468         nv_encoder->link = 0;
2469 }
2470
2471 static int
2472 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
2473 {
2474         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
2475         struct nv50_disp *disp = nv50_disp(drm->dev);
2476         struct {
2477                 struct nv50_disp_mthd_v1 base;
2478                 struct nv50_disp_acquire_v0 info;
2479         } args = {
2480                 .base.version = 1,
2481                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
2482                 .base.hasht  = nv_encoder->dcb->hasht,
2483                 .base.hashm  = nv_encoder->dcb->hashm,
2484         };
2485         int ret;
2486
2487         ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
2488         if (ret) {
2489                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
2490                 return ret;
2491         }
2492
2493         nv_encoder->or = args.info.or;
2494         nv_encoder->link = args.info.link;
2495         return 0;
2496 }
2497
2498 static int
2499 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
2500                             struct drm_crtc_state *crtc_state,
2501                             struct drm_connector_state *conn_state,
2502                             struct drm_display_mode *native_mode)
2503 {
2504         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
2505         struct drm_display_mode *mode = &crtc_state->mode;
2506         struct drm_connector *connector = conn_state->connector;
2507         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
2508         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
2509
2510         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
2511         asyc->scaler.full = false;
2512         if (!native_mode)
2513                 return 0;
2514
2515         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
2516                 switch (connector->connector_type) {
2517                 case DRM_MODE_CONNECTOR_LVDS:
2518                 case DRM_MODE_CONNECTOR_eDP:
2519                         /* Force use of scaler for non-EDID modes. */
2520                         if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
2521                                 break;
2522                         mode = native_mode;
2523                         asyc->scaler.full = true;
2524                         break;
2525                 default:
2526                         break;
2527                 }
2528         } else {
2529                 mode = native_mode;
2530         }
2531
2532         if (!drm_mode_equal(adjusted_mode, mode)) {
2533                 drm_mode_copy(adjusted_mode, mode);
2534                 crtc_state->mode_changed = true;
2535         }
2536
2537         return 0;
2538 }
2539
2540 static int
2541 nv50_outp_atomic_check(struct drm_encoder *encoder,
2542                        struct drm_crtc_state *crtc_state,
2543                        struct drm_connector_state *conn_state)
2544 {
2545         struct nouveau_connector *nv_connector =
2546                 nouveau_connector(conn_state->connector);
2547         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
2548                                            nv_connector->native_mode);
2549 }
2550
2551 /******************************************************************************
2552  * DAC
2553  *****************************************************************************/
2554 static void
2555 nv50_dac_disable(struct drm_encoder *encoder)
2556 {
2557         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2558         struct nv50_mast *mast = nv50_mast(encoder->dev);
2559         const int or = nv_encoder->or;
2560         u32 *push;
2561
2562         if (nv_encoder->crtc) {
2563                 push = evo_wait(mast, 4);
2564                 if (push) {
2565                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2566                                 evo_mthd(push, 0x0400 + (or * 0x080), 1);
2567                                 evo_data(push, 0x00000000);
2568                         } else {
2569                                 evo_mthd(push, 0x0180 + (or * 0x020), 1);
2570                                 evo_data(push, 0x00000000);
2571                         }
2572                         evo_kick(push, mast);
2573                 }
2574         }
2575
2576         nv_encoder->crtc = NULL;
2577         nv50_outp_release(nv_encoder);
2578 }
2579
2580 static void
2581 nv50_dac_enable(struct drm_encoder *encoder)
2582 {
2583         struct nv50_mast *mast = nv50_mast(encoder->dev);
2584         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2585         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2586         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
2587         u32 *push;
2588
2589         nv50_outp_acquire(nv_encoder);
2590
2591         push = evo_wait(mast, 8);
2592         if (push) {
2593                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2594                         u32 syncs = 0x00000000;
2595
2596                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2597                                 syncs |= 0x00000001;
2598                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2599                                 syncs |= 0x00000002;
2600
2601                         evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
2602                         evo_data(push, 1 << nv_crtc->index);
2603                         evo_data(push, syncs);
2604                 } else {
2605                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
2606                         u32 syncs = 0x00000001;
2607
2608                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2609                                 syncs |= 0x00000008;
2610                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2611                                 syncs |= 0x00000010;
2612
2613                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2614                                 magic |= 0x00000001;
2615
2616                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
2617                         evo_data(push, syncs);
2618                         evo_data(push, magic);
2619                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
2620                         evo_data(push, 1 << nv_crtc->index);
2621                 }
2622
2623                 evo_kick(push, mast);
2624         }
2625
2626         nv_encoder->crtc = encoder->crtc;
2627 }
2628
2629 static enum drm_connector_status
2630 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2631 {
2632         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2633         struct nv50_disp *disp = nv50_disp(encoder->dev);
2634         struct {
2635                 struct nv50_disp_mthd_v1 base;
2636                 struct nv50_disp_dac_load_v0 load;
2637         } args = {
2638                 .base.version = 1,
2639                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
2640                 .base.hasht  = nv_encoder->dcb->hasht,
2641                 .base.hashm  = nv_encoder->dcb->hashm,
2642         };
2643         int ret;
2644
2645         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
2646         if (args.load.data == 0)
2647                 args.load.data = 340;
2648
2649         ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
2650         if (ret || !args.load.load)
2651                 return connector_status_disconnected;
2652
2653         return connector_status_connected;
2654 }
2655
2656 static const struct drm_encoder_helper_funcs
2657 nv50_dac_help = {
2658         .atomic_check = nv50_outp_atomic_check,
2659         .enable = nv50_dac_enable,
2660         .disable = nv50_dac_disable,
2661         .detect = nv50_dac_detect
2662 };
2663
2664 static void
2665 nv50_dac_destroy(struct drm_encoder *encoder)
2666 {
2667         drm_encoder_cleanup(encoder);
2668         kfree(encoder);
2669 }
2670
2671 static const struct drm_encoder_funcs
2672 nv50_dac_func = {
2673         .destroy = nv50_dac_destroy,
2674 };
2675
2676 static int
2677 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
2678 {
2679         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2680         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
2681         struct nvkm_i2c_bus *bus;
2682         struct nouveau_encoder *nv_encoder;
2683         struct drm_encoder *encoder;
2684         int type = DRM_MODE_ENCODER_DAC;
2685
2686         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2687         if (!nv_encoder)
2688                 return -ENOMEM;
2689         nv_encoder->dcb = dcbe;
2690
2691         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
2692         if (bus)
2693                 nv_encoder->i2c = &bus->i2c;
2694
2695         encoder = to_drm_encoder(nv_encoder);
2696         encoder->possible_crtcs = dcbe->heads;
2697         encoder->possible_clones = 0;
2698         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
2699                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
2700         drm_encoder_helper_add(encoder, &nv50_dac_help);
2701
2702         drm_mode_connector_attach_encoder(connector, encoder);
2703         return 0;
2704 }
2705
2706 /******************************************************************************
2707  * Audio
2708  *****************************************************************************/
2709 static void
2710 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2711 {
2712         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2713         struct nv50_disp *disp = nv50_disp(encoder->dev);
2714         struct {
2715                 struct nv50_disp_mthd_v1 base;
2716                 struct nv50_disp_sor_hda_eld_v0 eld;
2717         } args = {
2718                 .base.version = 1,
2719                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2720                 .base.hasht   = nv_encoder->dcb->hasht,
2721                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
2722                                 (0x0100 << nv_crtc->index),
2723         };
2724
2725         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2726 }
2727
2728 static void
2729 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
2730 {
2731         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2732         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2733         struct nouveau_connector *nv_connector;
2734         struct nv50_disp *disp = nv50_disp(encoder->dev);
2735         struct __packed {
2736                 struct {
2737                         struct nv50_disp_mthd_v1 mthd;
2738                         struct nv50_disp_sor_hda_eld_v0 eld;
2739                 } base;
2740                 u8 data[sizeof(nv_connector->base.eld)];
2741         } args = {
2742                 .base.mthd.version = 1,
2743                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2744                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
2745                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
2746                                      (0x0100 << nv_crtc->index),
2747         };
2748
2749         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2750         if (!drm_detect_monitor_audio(nv_connector->edid))
2751                 return;
2752
2753         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
2754
2755         nvif_mthd(disp->disp, 0, &args,
2756                   sizeof(args.base) + drm_eld_size(args.data));
2757 }
2758
2759 /******************************************************************************
2760  * HDMI
2761  *****************************************************************************/
2762 static void
2763 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2764 {
2765         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2766         struct nv50_disp *disp = nv50_disp(encoder->dev);
2767         struct {
2768                 struct nv50_disp_mthd_v1 base;
2769                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2770         } args = {
2771                 .base.version = 1,
2772                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2773                 .base.hasht  = nv_encoder->dcb->hasht,
2774                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
2775                                (0x0100 << nv_crtc->index),
2776         };
2777
2778         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2779 }
2780
2781 static void
2782 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
2783 {
2784         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2785         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2786         struct nv50_disp *disp = nv50_disp(encoder->dev);
2787         struct {
2788                 struct nv50_disp_mthd_v1 base;
2789                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2790                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
2791         } args = {
2792                 .base.version = 1,
2793                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2794                 .base.hasht  = nv_encoder->dcb->hasht,
2795                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
2796                                (0x0100 << nv_crtc->index),
2797                 .pwr.state = 1,
2798                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
2799         };
2800         struct nouveau_connector *nv_connector;
2801         u32 max_ac_packet;
2802         union hdmi_infoframe avi_frame;
2803         union hdmi_infoframe vendor_frame;
2804         int ret;
2805         int size;
2806
2807         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2808         if (!drm_detect_hdmi_monitor(nv_connector->edid))
2809                 return;
2810
2811         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode,
2812                                                        false);
2813         if (!ret) {
2814                 /* We have an AVI InfoFrame, populate it to the display */
2815                 args.pwr.avi_infoframe_length
2816                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
2817         }
2818
2819         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
2820                                                           &nv_connector->base, mode);
2821         if (!ret) {
2822                 /* We have a Vendor InfoFrame, populate it to the display */
2823                 args.pwr.vendor_infoframe_length
2824                         = hdmi_infoframe_pack(&vendor_frame,
2825                                               args.infoframes
2826                                               + args.pwr.avi_infoframe_length,
2827                                               17);
2828         }
2829
2830         max_ac_packet  = mode->htotal - mode->hdisplay;
2831         max_ac_packet -= args.pwr.rekey;
2832         max_ac_packet -= 18; /* constant from tegra */
2833         args.pwr.max_ac_packet = max_ac_packet / 32;
2834
2835         size = sizeof(args.base)
2836                 + sizeof(args.pwr)
2837                 + args.pwr.avi_infoframe_length
2838                 + args.pwr.vendor_infoframe_length;
2839         nvif_mthd(disp->disp, 0, &args, size);
2840         nv50_audio_enable(encoder, mode);
2841 }
2842
2843 /******************************************************************************
2844  * MST
2845  *****************************************************************************/
2846 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
2847 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
2848 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
2849
2850 struct nv50_mstm {
2851         struct nouveau_encoder *outp;
2852
2853         struct drm_dp_mst_topology_mgr mgr;
2854         struct nv50_msto *msto[4];
2855
2856         bool modified;
2857         bool disabled;
2858         int links;
2859 };
2860
2861 struct nv50_mstc {
2862         struct nv50_mstm *mstm;
2863         struct drm_dp_mst_port *port;
2864         struct drm_connector connector;
2865
2866         struct drm_display_mode *native;
2867         struct edid *edid;
2868
2869         int pbn;
2870 };
2871
2872 struct nv50_msto {
2873         struct drm_encoder encoder;
2874
2875         struct nv50_head *head;
2876         struct nv50_mstc *mstc;
2877         bool disabled;
2878 };
2879
2880 static struct drm_dp_payload *
2881 nv50_msto_payload(struct nv50_msto *msto)
2882 {
2883         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2884         struct nv50_mstc *mstc = msto->mstc;
2885         struct nv50_mstm *mstm = mstc->mstm;
2886         int vcpi = mstc->port->vcpi.vcpi, i;
2887
2888         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
2889         for (i = 0; i < mstm->mgr.max_payloads; i++) {
2890                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
2891                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
2892                           mstm->outp->base.base.name, i, payload->vcpi,
2893                           payload->start_slot, payload->num_slots);
2894         }
2895
2896         for (i = 0; i < mstm->mgr.max_payloads; i++) {
2897                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
2898                 if (payload->vcpi == vcpi)
2899                         return payload;
2900         }
2901
2902         return NULL;
2903 }
2904
2905 static void
2906 nv50_msto_cleanup(struct nv50_msto *msto)
2907 {
2908         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2909         struct nv50_mstc *mstc = msto->mstc;
2910         struct nv50_mstm *mstm = mstc->mstm;
2911
2912         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
2913         if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
2914                 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
2915         if (msto->disabled) {
2916                 msto->mstc = NULL;
2917                 msto->head = NULL;
2918                 msto->disabled = false;
2919         }
2920 }
2921
2922 static void
2923 nv50_msto_prepare(struct nv50_msto *msto)
2924 {
2925         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2926         struct nv50_mstc *mstc = msto->mstc;
2927         struct nv50_mstm *mstm = mstc->mstm;
2928         struct {
2929                 struct nv50_disp_mthd_v1 base;
2930                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
2931         } args = {
2932                 .base.version = 1,
2933                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
2934                 .base.hasht  = mstm->outp->dcb->hasht,
2935                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
2936                                (0x0100 << msto->head->base.index),
2937         };
2938
2939         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
2940         if (mstc->port && mstc->port->vcpi.vcpi > 0) {
2941                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
2942                 if (payload) {
2943                         args.vcpi.start_slot = payload->start_slot;
2944                         args.vcpi.num_slots = payload->num_slots;
2945                         args.vcpi.pbn = mstc->port->vcpi.pbn;
2946                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
2947                 }
2948         }
2949
2950         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
2951                   msto->encoder.name, msto->head->base.base.name,
2952                   args.vcpi.start_slot, args.vcpi.num_slots,
2953                   args.vcpi.pbn, args.vcpi.aligned_pbn);
2954         nvif_mthd(&drm->display->disp, 0, &args, sizeof(args));
2955 }
2956
2957 static int
2958 nv50_msto_atomic_check(struct drm_encoder *encoder,
2959                        struct drm_crtc_state *crtc_state,
2960                        struct drm_connector_state *conn_state)
2961 {
2962         struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
2963         struct nv50_mstm *mstm = mstc->mstm;
2964         int bpp = conn_state->connector->display_info.bpc * 3;
2965         int slots;
2966
2967         mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
2968
2969         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
2970         if (slots < 0)
2971                 return slots;
2972
2973         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
2974                                            mstc->native);
2975 }
2976
2977 static void
2978 nv50_msto_enable(struct drm_encoder *encoder)
2979 {
2980         struct nv50_head *head = nv50_head(encoder->crtc);
2981         struct nv50_msto *msto = nv50_msto(encoder);
2982         struct nv50_mstc *mstc = NULL;
2983         struct nv50_mstm *mstm = NULL;
2984         struct drm_connector *connector;
2985         struct drm_connector_list_iter conn_iter;
2986         u8 proto, depth;
2987         int slots;
2988         bool r;
2989
2990         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
2991         drm_for_each_connector_iter(connector, &conn_iter) {
2992                 if (connector->state->best_encoder == &msto->encoder) {
2993                         mstc = nv50_mstc(connector);
2994                         mstm = mstc->mstm;
2995                         break;
2996                 }
2997         }
2998         drm_connector_list_iter_end(&conn_iter);
2999
3000         if (WARN_ON(!mstc))
3001                 return;
3002
3003         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
3004         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
3005         WARN_ON(!r);
3006
3007         if (!mstm->links++)
3008                 nv50_outp_acquire(mstm->outp);
3009
3010         if (mstm->outp->link & 1)
3011                 proto = 0x8;
3012         else
3013                 proto = 0x9;
3014
3015         switch (mstc->connector.display_info.bpc) {
3016         case  6: depth = 0x2; break;
3017         case  8: depth = 0x5; break;
3018         case 10:
3019         default: depth = 0x6; break;
3020         }
3021
3022         mstm->outp->update(mstm->outp, head->base.index,
3023                            &head->base.base.state->adjusted_mode, proto, depth);
3024
3025         msto->head = head;
3026         msto->mstc = mstc;
3027         mstm->modified = true;
3028 }
3029
3030 static void
3031 nv50_msto_disable(struct drm_encoder *encoder)
3032 {
3033         struct nv50_msto *msto = nv50_msto(encoder);
3034         struct nv50_mstc *mstc = msto->mstc;
3035         struct nv50_mstm *mstm = mstc->mstm;
3036
3037         if (mstc->port)
3038                 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
3039
3040         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
3041         mstm->modified = true;
3042         if (!--mstm->links)
3043                 mstm->disabled = true;
3044         msto->disabled = true;
3045 }
3046
3047 static const struct drm_encoder_helper_funcs
3048 nv50_msto_help = {
3049         .disable = nv50_msto_disable,
3050         .enable = nv50_msto_enable,
3051         .atomic_check = nv50_msto_atomic_check,
3052 };
3053
3054 static void
3055 nv50_msto_destroy(struct drm_encoder *encoder)
3056 {
3057         struct nv50_msto *msto = nv50_msto(encoder);
3058         drm_encoder_cleanup(&msto->encoder);
3059         kfree(msto);
3060 }
3061
3062 static const struct drm_encoder_funcs
3063 nv50_msto = {
3064         .destroy = nv50_msto_destroy,
3065 };
3066
3067 static int
3068 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
3069               struct nv50_msto **pmsto)
3070 {
3071         struct nv50_msto *msto;
3072         int ret;
3073
3074         if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
3075                 return -ENOMEM;
3076
3077         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
3078                                DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
3079         if (ret) {
3080                 kfree(*pmsto);
3081                 *pmsto = NULL;
3082                 return ret;
3083         }
3084
3085         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
3086         msto->encoder.possible_crtcs = heads;
3087         return 0;
3088 }
3089
3090 static struct drm_encoder *
3091 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
3092                               struct drm_connector_state *connector_state)
3093 {
3094         struct nv50_head *head = nv50_head(connector_state->crtc);
3095         struct nv50_mstc *mstc = nv50_mstc(connector);
3096         if (mstc->port) {
3097                 struct nv50_mstm *mstm = mstc->mstm;
3098                 return &mstm->msto[head->base.index]->encoder;
3099         }
3100         return NULL;
3101 }
3102
3103 static struct drm_encoder *
3104 nv50_mstc_best_encoder(struct drm_connector *connector)
3105 {
3106         struct nv50_mstc *mstc = nv50_mstc(connector);
3107         if (mstc->port) {
3108                 struct nv50_mstm *mstm = mstc->mstm;
3109                 return &mstm->msto[0]->encoder;
3110         }
3111         return NULL;
3112 }
3113
3114 static enum drm_mode_status
3115 nv50_mstc_mode_valid(struct drm_connector *connector,
3116                      struct drm_display_mode *mode)
3117 {
3118         return MODE_OK;
3119 }
3120
3121 static int
3122 nv50_mstc_get_modes(struct drm_connector *connector)
3123 {
3124         struct nv50_mstc *mstc = nv50_mstc(connector);
3125         int ret = 0;
3126
3127         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
3128         drm_mode_connector_update_edid_property(&mstc->connector, mstc->edid);
3129         if (mstc->edid)
3130                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
3131
3132         if (!mstc->connector.display_info.bpc)
3133                 mstc->connector.display_info.bpc = 8;
3134
3135         if (mstc->native)
3136                 drm_mode_destroy(mstc->connector.dev, mstc->native);
3137         mstc->native = nouveau_conn_native_mode(&mstc->connector);
3138         return ret;
3139 }
3140
3141 static const struct drm_connector_helper_funcs
3142 nv50_mstc_help = {
3143         .get_modes = nv50_mstc_get_modes,
3144         .mode_valid = nv50_mstc_mode_valid,
3145         .best_encoder = nv50_mstc_best_encoder,
3146         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
3147 };
3148
3149 static enum drm_connector_status
3150 nv50_mstc_detect(struct drm_connector *connector, bool force)
3151 {
3152         struct nv50_mstc *mstc = nv50_mstc(connector);
3153         if (!mstc->port)
3154                 return connector_status_disconnected;
3155         return drm_dp_mst_detect_port(connector, mstc->port->mgr, mstc->port);
3156 }
3157
3158 static void
3159 nv50_mstc_destroy(struct drm_connector *connector)
3160 {
3161         struct nv50_mstc *mstc = nv50_mstc(connector);
3162         drm_connector_cleanup(&mstc->connector);
3163         kfree(mstc);
3164 }
3165
3166 static const struct drm_connector_funcs
3167 nv50_mstc = {
3168         .reset = nouveau_conn_reset,
3169         .detect = nv50_mstc_detect,
3170         .fill_modes = drm_helper_probe_single_connector_modes,
3171         .destroy = nv50_mstc_destroy,
3172         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
3173         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
3174         .atomic_set_property = nouveau_conn_atomic_set_property,
3175         .atomic_get_property = nouveau_conn_atomic_get_property,
3176 };
3177
3178 static int
3179 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
3180               const char *path, struct nv50_mstc **pmstc)
3181 {
3182         struct drm_device *dev = mstm->outp->base.base.dev;
3183         struct nv50_mstc *mstc;
3184         int ret, i;
3185
3186         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
3187                 return -ENOMEM;
3188         mstc->mstm = mstm;
3189         mstc->port = port;
3190
3191         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
3192                                  DRM_MODE_CONNECTOR_DisplayPort);
3193         if (ret) {
3194                 kfree(*pmstc);
3195                 *pmstc = NULL;
3196                 return ret;
3197         }
3198
3199         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
3200
3201         mstc->connector.funcs->reset(&mstc->connector);
3202         nouveau_conn_attach_properties(&mstc->connector);
3203
3204         for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
3205                 drm_mode_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
3206
3207         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
3208         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
3209         drm_mode_connector_set_path_property(&mstc->connector, path);
3210         return 0;
3211 }
3212
3213 static void
3214 nv50_mstm_cleanup(struct nv50_mstm *mstm)
3215 {
3216         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
3217         struct drm_encoder *encoder;
3218         int ret;
3219
3220         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
3221         ret = drm_dp_check_act_status(&mstm->mgr);
3222
3223         ret = drm_dp_update_payload_part2(&mstm->mgr);
3224
3225         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
3226                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
3227                         struct nv50_msto *msto = nv50_msto(encoder);
3228                         struct nv50_mstc *mstc = msto->mstc;
3229                         if (mstc && mstc->mstm == mstm)
3230                                 nv50_msto_cleanup(msto);
3231                 }
3232         }
3233
3234         mstm->modified = false;
3235 }
3236
3237 static void
3238 nv50_mstm_prepare(struct nv50_mstm *mstm)
3239 {
3240         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
3241         struct drm_encoder *encoder;
3242         int ret;
3243
3244         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
3245         ret = drm_dp_update_payload_part1(&mstm->mgr);
3246
3247         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
3248                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
3249                         struct nv50_msto *msto = nv50_msto(encoder);
3250                         struct nv50_mstc *mstc = msto->mstc;
3251                         if (mstc && mstc->mstm == mstm)
3252                                 nv50_msto_prepare(msto);
3253                 }
3254         }
3255
3256         if (mstm->disabled) {
3257                 if (!mstm->links)
3258                         nv50_outp_release(mstm->outp);
3259                 mstm->disabled = false;
3260         }
3261 }
3262
3263 static void
3264 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr)
3265 {
3266         struct nv50_mstm *mstm = nv50_mstm(mgr);
3267         drm_kms_helper_hotplug_event(mstm->outp->base.base.dev);
3268 }
3269
3270 static void
3271 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
3272                             struct drm_connector *connector)
3273 {
3274         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3275         struct nv50_mstc *mstc = nv50_mstc(connector);
3276
3277         drm_connector_unregister(&mstc->connector);
3278
3279         drm_modeset_lock_all(drm->dev);
3280         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
3281         mstc->port = NULL;
3282         drm_modeset_unlock_all(drm->dev);
3283
3284         drm_connector_unreference(&mstc->connector);
3285 }
3286
3287 static void
3288 nv50_mstm_register_connector(struct drm_connector *connector)
3289 {
3290         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3291
3292         drm_modeset_lock_all(drm->dev);
3293         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
3294         drm_modeset_unlock_all(drm->dev);
3295
3296         drm_connector_register(connector);
3297 }
3298
3299 static struct drm_connector *
3300 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
3301                         struct drm_dp_mst_port *port, const char *path)
3302 {
3303         struct nv50_mstm *mstm = nv50_mstm(mgr);
3304         struct nv50_mstc *mstc;
3305         int ret;
3306
3307         ret = nv50_mstc_new(mstm, port, path, &mstc);
3308         if (ret) {
3309                 if (mstc)
3310                         mstc->connector.funcs->destroy(&mstc->connector);
3311                 return NULL;
3312         }
3313
3314         return &mstc->connector;
3315 }
3316
3317 static const struct drm_dp_mst_topology_cbs
3318 nv50_mstm = {
3319         .add_connector = nv50_mstm_add_connector,
3320         .register_connector = nv50_mstm_register_connector,
3321         .destroy_connector = nv50_mstm_destroy_connector,
3322         .hotplug = nv50_mstm_hotplug,
3323 };
3324
3325 void
3326 nv50_mstm_service(struct nv50_mstm *mstm)
3327 {
3328         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
3329         bool handled = true;
3330         int ret;
3331         u8 esi[8] = {};
3332
3333         if (!aux)
3334                 return;
3335
3336         while (handled) {
3337                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
3338                 if (ret != 8) {
3339                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
3340                         return;
3341                 }
3342
3343                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
3344                 if (!handled)
3345                         break;
3346
3347                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
3348         }
3349 }
3350
3351 void
3352 nv50_mstm_remove(struct nv50_mstm *mstm)
3353 {
3354         if (mstm)
3355                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
3356 }
3357
3358 static int
3359 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
3360 {
3361         struct nouveau_encoder *outp = mstm->outp;
3362         struct {
3363                 struct nv50_disp_mthd_v1 base;
3364                 struct nv50_disp_sor_dp_mst_link_v0 mst;
3365         } args = {
3366                 .base.version = 1,
3367                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
3368                 .base.hasht = outp->dcb->hasht,
3369                 .base.hashm = outp->dcb->hashm,
3370                 .mst.state = state,
3371         };
3372         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
3373         struct nvif_object *disp = &drm->display->disp;
3374         int ret;
3375
3376         if (dpcd >= 0x12) {
3377                 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CTRL, &dpcd);
3378                 if (ret < 0)
3379                         return ret;
3380
3381                 dpcd &= ~DP_MST_EN;
3382                 if (state)
3383                         dpcd |= DP_MST_EN;
3384
3385                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, dpcd);
3386                 if (ret < 0)
3387                         return ret;
3388         }
3389
3390         return nvif_mthd(disp, 0, &args, sizeof(args));
3391 }
3392
3393 int
3394 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
3395 {
3396         int ret, state = 0;
3397
3398         if (!mstm)
3399                 return 0;
3400
3401         if (dpcd[0] >= 0x12) {
3402                 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CAP, &dpcd[1]);
3403                 if (ret < 0)
3404                         return ret;
3405
3406                 if (!(dpcd[1] & DP_MST_CAP))
3407                         dpcd[0] = 0x11;
3408                 else
3409                         state = allow;
3410         }
3411
3412         ret = nv50_mstm_enable(mstm, dpcd[0], state);
3413         if (ret)
3414                 return ret;
3415
3416         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, state);
3417         if (ret)
3418                 return nv50_mstm_enable(mstm, dpcd[0], 0);
3419
3420         return mstm->mgr.mst_state;
3421 }
3422
3423 static void
3424 nv50_mstm_fini(struct nv50_mstm *mstm)
3425 {
3426         if (mstm && mstm->mgr.mst_state)
3427                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
3428 }
3429
3430 static void
3431 nv50_mstm_init(struct nv50_mstm *mstm)
3432 {
3433         if (mstm && mstm->mgr.mst_state)
3434                 drm_dp_mst_topology_mgr_resume(&mstm->mgr);
3435 }
3436
3437 static void
3438 nv50_mstm_del(struct nv50_mstm **pmstm)
3439 {
3440         struct nv50_mstm *mstm = *pmstm;
3441         if (mstm) {
3442                 kfree(*pmstm);
3443                 *pmstm = NULL;
3444         }
3445 }
3446
3447 static int
3448 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
3449               int conn_base_id, struct nv50_mstm **pmstm)
3450 {
3451         const int max_payloads = hweight8(outp->dcb->heads);
3452         struct drm_device *dev = outp->base.base.dev;
3453         struct nv50_mstm *mstm;
3454         int ret, i;
3455         u8 dpcd;
3456
3457         /* This is a workaround for some monitors not functioning
3458          * correctly in MST mode on initial module load.  I think
3459          * some bad interaction with the VBIOS may be responsible.
3460          *
3461          * A good ol' off and on again seems to work here ;)
3462          */
3463         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
3464         if (ret >= 0 && dpcd >= 0x12)
3465                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
3466
3467         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
3468                 return -ENOMEM;
3469         mstm->outp = outp;
3470         mstm->mgr.cbs = &nv50_mstm;
3471
3472         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
3473                                            max_payloads, conn_base_id);
3474         if (ret)
3475                 return ret;
3476
3477         for (i = 0; i < max_payloads; i++) {
3478                 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
3479                                     i, &mstm->msto[i]);
3480                 if (ret)
3481                         return ret;
3482         }
3483
3484         return 0;
3485 }
3486
3487 /******************************************************************************
3488  * SOR
3489  *****************************************************************************/
3490 static void
3491 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
3492                 struct drm_display_mode *mode, u8 proto, u8 depth)
3493 {
3494         struct nv50_dmac *core = &nv50_mast(nv_encoder->base.base.dev)->base;
3495         u32 *push;
3496
3497         if (!mode) {
3498                 nv_encoder->ctrl &= ~BIT(head);
3499                 if (!(nv_encoder->ctrl & 0x0000000f))
3500                         nv_encoder->ctrl = 0;
3501         } else {
3502                 nv_encoder->ctrl |= proto << 8;
3503                 nv_encoder->ctrl |= BIT(head);
3504         }
3505
3506         if ((push = evo_wait(core, 6))) {
3507                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
3508                         if (mode) {
3509                                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3510                                         nv_encoder->ctrl |= 0x00001000;
3511                                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3512                                         nv_encoder->ctrl |= 0x00002000;
3513                                 nv_encoder->ctrl |= depth << 16;
3514                         }
3515                         evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
3516                 } else {
3517                         if (mode) {
3518                                 u32 magic = 0x31ec6000 | (head << 25);
3519                                 u32 syncs = 0x00000001;
3520                                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3521                                         syncs |= 0x00000008;
3522                                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3523                                         syncs |= 0x00000010;
3524                                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
3525                                         magic |= 0x00000001;
3526
3527                                 evo_mthd(push, 0x0404 + (head * 0x300), 2);
3528                                 evo_data(push, syncs | (depth << 6));
3529                                 evo_data(push, magic);
3530                         }
3531                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
3532                 }
3533                 evo_data(push, nv_encoder->ctrl);
3534                 evo_kick(push, core);
3535         }
3536 }
3537
3538 static void
3539 nv50_sor_disable(struct drm_encoder *encoder)
3540 {
3541         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3542         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
3543
3544         nv_encoder->crtc = NULL;
3545
3546         if (nv_crtc) {
3547                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
3548                 u8 pwr;
3549
3550                 if (aux) {
3551                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
3552                         if (ret == 0) {
3553                                 pwr &= ~DP_SET_POWER_MASK;
3554                                 pwr |=  DP_SET_POWER_D3;
3555                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
3556                         }
3557                 }
3558
3559                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
3560                 nv50_audio_disable(encoder, nv_crtc);
3561                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
3562                 nv50_outp_release(nv_encoder);
3563         }
3564 }
3565
3566 static void
3567 nv50_sor_enable(struct drm_encoder *encoder)
3568 {
3569         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3570         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3571         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
3572         struct {
3573                 struct nv50_disp_mthd_v1 base;
3574                 struct nv50_disp_sor_lvds_script_v0 lvds;
3575         } lvds = {
3576                 .base.version = 1,
3577                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
3578                 .base.hasht   = nv_encoder->dcb->hasht,
3579                 .base.hashm   = nv_encoder->dcb->hashm,
3580         };
3581         struct nv50_disp *disp = nv50_disp(encoder->dev);
3582         struct drm_device *dev = encoder->dev;
3583         struct nouveau_drm *drm = nouveau_drm(dev);
3584         struct nouveau_connector *nv_connector;
3585         struct nvbios *bios = &drm->vbios;
3586         u8 proto = 0xf;
3587         u8 depth = 0x0;
3588
3589         nv_connector = nouveau_encoder_connector_get(nv_encoder);
3590         nv_encoder->crtc = encoder->crtc;
3591         nv50_outp_acquire(nv_encoder);
3592
3593         switch (nv_encoder->dcb->type) {
3594         case DCB_OUTPUT_TMDS:
3595                 if (nv_encoder->link & 1) {
3596                         proto = 0x1;
3597                         /* Only enable dual-link if:
3598                          *  - Need to (i.e. rate > 165MHz)
3599                          *  - DCB says we can
3600                          *  - Not an HDMI monitor, since there's no dual-link
3601                          *    on HDMI.
3602                          */
3603                         if (mode->clock >= 165000 &&
3604                             nv_encoder->dcb->duallink_possible &&
3605                             !drm_detect_hdmi_monitor(nv_connector->edid))
3606                                 proto |= 0x4;
3607                 } else {
3608                         proto = 0x2;
3609                 }
3610
3611                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
3612                 break;
3613         case DCB_OUTPUT_LVDS:
3614                 proto = 0x0;
3615
3616                 if (bios->fp_no_ddc) {
3617                         if (bios->fp.dual_link)
3618                                 lvds.lvds.script |= 0x0100;
3619                         if (bios->fp.if_is_24bit)
3620                                 lvds.lvds.script |= 0x0200;
3621                 } else {
3622                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
3623                                 if (((u8 *)nv_connector->edid)[121] == 2)
3624                                         lvds.lvds.script |= 0x0100;
3625                         } else
3626                         if (mode->clock >= bios->fp.duallink_transition_clk) {
3627                                 lvds.lvds.script |= 0x0100;
3628                         }
3629
3630                         if (lvds.lvds.script & 0x0100) {
3631                                 if (bios->fp.strapless_is_24bit & 2)
3632                                         lvds.lvds.script |= 0x0200;
3633                         } else {
3634                                 if (bios->fp.strapless_is_24bit & 1)
3635                                         lvds.lvds.script |= 0x0200;
3636                         }
3637
3638                         if (nv_connector->base.display_info.bpc == 8)
3639                                 lvds.lvds.script |= 0x0200;
3640                 }
3641
3642                 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
3643                 break;
3644         case DCB_OUTPUT_DP:
3645                 if (nv_connector->base.display_info.bpc == 6)
3646                         depth = 0x2;
3647                 else
3648                 if (nv_connector->base.display_info.bpc == 8)
3649                         depth = 0x5;
3650                 else
3651                         depth = 0x6;
3652
3653                 if (nv_encoder->link & 1)
3654                         proto = 0x8;
3655                 else
3656                         proto = 0x9;
3657
3658                 nv50_audio_enable(encoder, mode);
3659                 break;
3660         default:
3661                 BUG();
3662                 break;
3663         }
3664
3665         nv_encoder->update(nv_encoder, nv_crtc->index, mode, proto, depth);
3666 }
3667
3668 static const struct drm_encoder_helper_funcs
3669 nv50_sor_help = {
3670         .atomic_check = nv50_outp_atomic_check,
3671         .enable = nv50_sor_enable,
3672         .disable = nv50_sor_disable,
3673 };
3674
3675 static void
3676 nv50_sor_destroy(struct drm_encoder *encoder)
3677 {
3678         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3679         nv50_mstm_del(&nv_encoder->dp.mstm);
3680         drm_encoder_cleanup(encoder);
3681         kfree(encoder);
3682 }
3683
3684 static const struct drm_encoder_funcs
3685 nv50_sor_func = {
3686         .destroy = nv50_sor_destroy,
3687 };
3688
3689 static int
3690 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
3691 {
3692         struct nouveau_connector *nv_connector = nouveau_connector(connector);
3693         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3694         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
3695         struct nouveau_encoder *nv_encoder;
3696         struct drm_encoder *encoder;
3697         int type, ret;
3698
3699         switch (dcbe->type) {
3700         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
3701         case DCB_OUTPUT_TMDS:
3702         case DCB_OUTPUT_DP:
3703         default:
3704                 type = DRM_MODE_ENCODER_TMDS;
3705                 break;
3706         }
3707
3708         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
3709         if (!nv_encoder)
3710                 return -ENOMEM;
3711         nv_encoder->dcb = dcbe;
3712         nv_encoder->update = nv50_sor_update;
3713
3714         encoder = to_drm_encoder(nv_encoder);
3715         encoder->possible_crtcs = dcbe->heads;
3716         encoder->possible_clones = 0;
3717         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
3718                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
3719         drm_encoder_helper_add(encoder, &nv50_sor_help);
3720
3721         drm_mode_connector_attach_encoder(connector, encoder);
3722
3723         if (dcbe->type == DCB_OUTPUT_DP) {
3724                 struct nv50_disp *disp = nv50_disp(encoder->dev);
3725                 struct nvkm_i2c_aux *aux =
3726                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
3727                 if (aux) {
3728                         if (disp->disp->oclass < GF110_DISP) {
3729                                 /* HW has no support for address-only
3730                                  * transactions, so we're required to
3731                                  * use custom I2C-over-AUX code.
3732                                  */
3733                                 nv_encoder->i2c = &aux->i2c;
3734                         } else {
3735                                 nv_encoder->i2c = &nv_connector->aux.ddc;
3736                         }
3737                         nv_encoder->aux = aux;
3738                 }
3739
3740                 /*TODO: Use DP Info Table to check for support. */
3741                 if (disp->disp->oclass >= GF110_DISP) {
3742                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
3743                                             nv_connector->base.base.id,
3744                                             &nv_encoder->dp.mstm);
3745                         if (ret)
3746                                 return ret;
3747                 }
3748         } else {
3749                 struct nvkm_i2c_bus *bus =
3750                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
3751                 if (bus)
3752                         nv_encoder->i2c = &bus->i2c;
3753         }
3754
3755         return 0;
3756 }
3757
3758 /******************************************************************************
3759  * PIOR
3760  *****************************************************************************/
3761 static int
3762 nv50_pior_atomic_check(struct drm_encoder *encoder,
3763                        struct drm_crtc_state *crtc_state,
3764                        struct drm_connector_state *conn_state)
3765 {
3766         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
3767         if (ret)
3768                 return ret;
3769         crtc_state->adjusted_mode.clock *= 2;
3770         return 0;
3771 }
3772
3773 static void
3774 nv50_pior_disable(struct drm_encoder *encoder)
3775 {
3776         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3777         struct nv50_mast *mast = nv50_mast(encoder->dev);
3778         const int or = nv_encoder->or;
3779         u32 *push;
3780
3781         if (nv_encoder->crtc) {
3782                 push = evo_wait(mast, 4);
3783                 if (push) {
3784                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
3785                                 evo_mthd(push, 0x0700 + (or * 0x040), 1);
3786                                 evo_data(push, 0x00000000);
3787                         }
3788                         evo_kick(push, mast);
3789                 }
3790         }
3791
3792         nv_encoder->crtc = NULL;
3793         nv50_outp_release(nv_encoder);
3794 }
3795
3796 static void
3797 nv50_pior_enable(struct drm_encoder *encoder)
3798 {
3799         struct nv50_mast *mast = nv50_mast(encoder->dev);
3800         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3801         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3802         struct nouveau_connector *nv_connector;
3803         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
3804         u8 owner = 1 << nv_crtc->index;
3805         u8 proto, depth;
3806         u32 *push;
3807
3808         nv50_outp_acquire(nv_encoder);
3809
3810         nv_connector = nouveau_encoder_connector_get(nv_encoder);
3811         switch (nv_connector->base.display_info.bpc) {
3812         case 10: depth = 0x6; break;
3813         case  8: depth = 0x5; break;
3814         case  6: depth = 0x2; break;
3815         default: depth = 0x0; break;
3816         }
3817
3818         switch (nv_encoder->dcb->type) {
3819         case DCB_OUTPUT_TMDS:
3820         case DCB_OUTPUT_DP:
3821                 proto = 0x0;
3822                 break;
3823         default:
3824                 BUG();
3825                 break;
3826         }
3827
3828         push = evo_wait(mast, 8);
3829         if (push) {
3830                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
3831                         u32 ctrl = (depth << 16) | (proto << 8) | owner;
3832                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3833                                 ctrl |= 0x00001000;
3834                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3835                                 ctrl |= 0x00002000;
3836                         evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
3837                         evo_data(push, ctrl);
3838                 }
3839
3840                 evo_kick(push, mast);
3841         }
3842
3843         nv_encoder->crtc = encoder->crtc;
3844 }
3845
3846 static const struct drm_encoder_helper_funcs
3847 nv50_pior_help = {
3848         .atomic_check = nv50_pior_atomic_check,
3849         .enable = nv50_pior_enable,
3850         .disable = nv50_pior_disable,
3851 };
3852
3853 static void
3854 nv50_pior_destroy(struct drm_encoder *encoder)
3855 {
3856         drm_encoder_cleanup(encoder);
3857         kfree(encoder);
3858 }
3859
3860 static const struct drm_encoder_funcs
3861 nv50_pior_func = {
3862         .destroy = nv50_pior_destroy,
3863 };
3864
3865 static int
3866 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
3867 {
3868         struct nouveau_connector *nv_connector = nouveau_connector(connector);
3869         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3870         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
3871         struct nvkm_i2c_bus *bus = NULL;
3872         struct nvkm_i2c_aux *aux = NULL;
3873         struct i2c_adapter *ddc;
3874         struct nouveau_encoder *nv_encoder;
3875         struct drm_encoder *encoder;
3876         int type;
3877
3878         switch (dcbe->type) {
3879         case DCB_OUTPUT_TMDS:
3880                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
3881                 ddc  = bus ? &bus->i2c : NULL;
3882                 type = DRM_MODE_ENCODER_TMDS;
3883                 break;
3884         case DCB_OUTPUT_DP:
3885                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
3886                 ddc  = aux ? &nv_connector->aux.ddc : NULL;
3887                 type = DRM_MODE_ENCODER_TMDS;
3888                 break;
3889         default:
3890                 return -ENODEV;
3891         }
3892
3893         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
3894         if (!nv_encoder)
3895                 return -ENOMEM;
3896         nv_encoder->dcb = dcbe;
3897         nv_encoder->i2c = ddc;
3898         nv_encoder->aux = aux;
3899
3900         encoder = to_drm_encoder(nv_encoder);
3901         encoder->possible_crtcs = dcbe->heads;
3902         encoder->possible_clones = 0;
3903         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
3904                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
3905         drm_encoder_helper_add(encoder, &nv50_pior_help);
3906
3907         drm_mode_connector_attach_encoder(connector, encoder);
3908         return 0;
3909 }
3910
3911 /******************************************************************************
3912  * Atomic
3913  *****************************************************************************/
3914
3915 static void
3916 nv50_disp_atomic_commit_core(struct nouveau_drm *drm, u32 interlock)
3917 {
3918         struct nv50_disp *disp = nv50_disp(drm->dev);
3919         struct nv50_dmac *core = &disp->mast.base;
3920         struct nv50_mstm *mstm;
3921         struct drm_encoder *encoder;
3922         u32 *push;
3923
3924         NV_ATOMIC(drm, "commit core %08x\n", interlock);
3925
3926         drm_for_each_encoder(encoder, drm->dev) {
3927                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
3928                         mstm = nouveau_encoder(encoder)->dp.mstm;
3929                         if (mstm && mstm->modified)
3930                                 nv50_mstm_prepare(mstm);
3931                 }
3932         }
3933
3934         if ((push = evo_wait(core, 5))) {
3935                 evo_mthd(push, 0x0084, 1);
3936                 evo_data(push, 0x80000000);
3937                 evo_mthd(push, 0x0080, 2);
3938                 evo_data(push, interlock);
3939                 evo_data(push, 0x00000000);
3940                 nouveau_bo_wr32(disp->sync, 0, 0x00000000);
3941                 evo_kick(push, core);
3942                 if (nvif_msec(&drm->client.device, 2000ULL,
3943                         if (nouveau_bo_rd32(disp->sync, 0))
3944                                 break;
3945                         usleep_range(1, 2);
3946                 ) < 0)
3947                         NV_ERROR(drm, "EVO timeout\n");
3948         }
3949
3950         drm_for_each_encoder(encoder, drm->dev) {
3951                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
3952                         mstm = nouveau_encoder(encoder)->dp.mstm;
3953                         if (mstm && mstm->modified)
3954                                 nv50_mstm_cleanup(mstm);
3955                 }
3956         }
3957 }
3958
3959 static void
3960 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
3961 {
3962         struct drm_device *dev = state->dev;
3963         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
3964         struct drm_crtc *crtc;
3965         struct drm_plane_state *new_plane_state;
3966         struct drm_plane *plane;
3967         struct nouveau_drm *drm = nouveau_drm(dev);
3968         struct nv50_disp *disp = nv50_disp(dev);
3969         struct nv50_atom *atom = nv50_atom(state);
3970         struct nv50_outp_atom *outp, *outt;
3971         u32 interlock_core = 0;
3972         u32 interlock_chan = 0;
3973         int i;
3974
3975         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
3976         drm_atomic_helper_wait_for_fences(dev, state, false);
3977         drm_atomic_helper_wait_for_dependencies(state);
3978         drm_atomic_helper_update_legacy_modeset_state(dev, state);
3979
3980         if (atom->lock_core)
3981                 mutex_lock(&disp->mutex);
3982
3983         /* Disable head(s). */
3984         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
3985                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
3986                 struct nv50_head *head = nv50_head(crtc);
3987
3988                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
3989                           asyh->clr.mask, asyh->set.mask);
3990                 if (old_crtc_state->active && !new_crtc_state->active)
3991                         drm_crtc_vblank_off(crtc);
3992
3993                 if (asyh->clr.mask) {
3994                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
3995                         interlock_core |= 1;
3996                 }
3997         }
3998
3999         /* Disable plane(s). */
4000         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
4001                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
4002                 struct nv50_wndw *wndw = nv50_wndw(plane);
4003
4004                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
4005                           asyw->clr.mask, asyw->set.mask);
4006                 if (!asyw->clr.mask)
4007                         continue;
4008
4009                 interlock_chan |= nv50_wndw_flush_clr(wndw, interlock_core,
4010                                                       atom->flush_disable,
4011                                                       asyw);
4012         }
4013
4014         /* Disable output path(s). */
4015         list_for_each_entry(outp, &atom->outp, head) {
4016                 const struct drm_encoder_helper_funcs *help;
4017                 struct drm_encoder *encoder;
4018
4019                 encoder = outp->encoder;
4020                 help = encoder->helper_private;
4021
4022                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
4023                           outp->clr.mask, outp->set.mask);
4024
4025                 if (outp->clr.mask) {
4026                         help->disable(encoder);
4027                         interlock_core |= 1;
4028                         if (outp->flush_disable) {
4029                                 nv50_disp_atomic_commit_core(drm, interlock_chan);
4030                                 interlock_core = 0;
4031                                 interlock_chan = 0;
4032                         }
4033                 }
4034         }
4035
4036         /* Flush disable. */
4037         if (interlock_core) {
4038                 if (atom->flush_disable) {
4039                         nv50_disp_atomic_commit_core(drm, interlock_chan);
4040                         interlock_core = 0;
4041                         interlock_chan = 0;
4042                 }
4043         }
4044
4045         /* Update output path(s). */
4046         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
4047                 const struct drm_encoder_helper_funcs *help;
4048                 struct drm_encoder *encoder;
4049
4050                 encoder = outp->encoder;
4051                 help = encoder->helper_private;
4052
4053                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
4054                           outp->set.mask, outp->clr.mask);
4055
4056                 if (outp->set.mask) {
4057                         help->enable(encoder);
4058                         interlock_core = 1;
4059                 }
4060
4061                 list_del(&outp->head);
4062                 kfree(outp);
4063         }
4064
4065         /* Update head(s). */
4066         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4067                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
4068                 struct nv50_head *head = nv50_head(crtc);
4069
4070                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
4071                           asyh->set.mask, asyh->clr.mask);
4072
4073                 if (asyh->set.mask) {
4074                         nv50_head_flush_set(head, asyh);
4075                         interlock_core = 1;
4076                 }
4077
4078                 if (new_crtc_state->active) {
4079                         if (!old_crtc_state->active)
4080                                 drm_crtc_vblank_on(crtc);
4081                         if (new_crtc_state->event)
4082                                 drm_crtc_vblank_get(crtc);
4083                 }
4084         }
4085
4086         /* Update plane(s). */
4087         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
4088                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
4089                 struct nv50_wndw *wndw = nv50_wndw(plane);
4090
4091                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
4092                           asyw->set.mask, asyw->clr.mask);
4093                 if ( !asyw->set.mask &&
4094                     (!asyw->clr.mask || atom->flush_disable))
4095                         continue;
4096
4097                 interlock_chan |= nv50_wndw_flush_set(wndw, interlock_core, asyw);
4098         }
4099
4100         /* Flush update. */
4101         if (interlock_core) {
4102                 if (!interlock_chan && atom->state.legacy_cursor_update) {
4103                         u32 *push = evo_wait(&disp->mast, 2);
4104                         if (push) {
4105                                 evo_mthd(push, 0x0080, 1);
4106                                 evo_data(push, 0x00000000);
4107                                 evo_kick(push, &disp->mast);
4108                         }
4109                 } else {
4110                         nv50_disp_atomic_commit_core(drm, interlock_chan);
4111                 }
4112         }
4113
4114         if (atom->lock_core)
4115                 mutex_unlock(&disp->mutex);
4116
4117         /* Wait for HW to signal completion. */
4118         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
4119                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
4120                 struct nv50_wndw *wndw = nv50_wndw(plane);
4121                 int ret = nv50_wndw_wait_armed(wndw, asyw);
4122                 if (ret)
4123                         NV_ERROR(drm, "%s: timeout\n", plane->name);
4124         }
4125
4126         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4127                 if (new_crtc_state->event) {
4128                         unsigned long flags;
4129                         /* Get correct count/ts if racing with vblank irq */
4130                         if (new_crtc_state->active)
4131                                 drm_crtc_accurate_vblank_count(crtc);
4132                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
4133                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
4134                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4135
4136                         new_crtc_state->event = NULL;
4137                         if (new_crtc_state->active)
4138                                 drm_crtc_vblank_put(crtc);
4139                 }
4140         }
4141
4142         drm_atomic_helper_commit_hw_done(state);
4143         drm_atomic_helper_cleanup_planes(dev, state);
4144         drm_atomic_helper_commit_cleanup_done(state);
4145         drm_atomic_state_put(state);
4146 }
4147
4148 static void
4149 nv50_disp_atomic_commit_work(struct work_struct *work)
4150 {
4151         struct drm_atomic_state *state =
4152                 container_of(work, typeof(*state), commit_work);
4153         nv50_disp_atomic_commit_tail(state);
4154 }
4155
4156 static int
4157 nv50_disp_atomic_commit(struct drm_device *dev,
4158                         struct drm_atomic_state *state, bool nonblock)
4159 {
4160         struct nouveau_drm *drm = nouveau_drm(dev);
4161         struct nv50_disp *disp = nv50_disp(dev);
4162         struct drm_plane_state *new_plane_state;
4163         struct drm_plane *plane;
4164         struct drm_crtc *crtc;
4165         bool active = false;
4166         int ret, i;
4167
4168         ret = pm_runtime_get_sync(dev->dev);
4169         if (ret < 0 && ret != -EACCES)
4170                 return ret;
4171
4172         ret = drm_atomic_helper_setup_commit(state, nonblock);
4173         if (ret)
4174                 goto done;
4175
4176         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
4177
4178         ret = drm_atomic_helper_prepare_planes(dev, state);
4179         if (ret)
4180                 goto done;
4181
4182         if (!nonblock) {
4183                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
4184                 if (ret)
4185                         goto err_cleanup;
4186         }
4187
4188         ret = drm_atomic_helper_swap_state(state, true);
4189         if (ret)
4190                 goto err_cleanup;
4191
4192         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
4193                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
4194                 struct nv50_wndw *wndw = nv50_wndw(plane);
4195
4196                 if (asyw->set.image) {
4197                         asyw->ntfy.handle = wndw->dmac->sync.handle;
4198                         asyw->ntfy.offset = wndw->ntfy;
4199                         asyw->ntfy.awaken = false;
4200                         asyw->set.ntfy = true;
4201                         nouveau_bo_wr32(disp->sync, wndw->ntfy / 4, 0x00000000);
4202                         wndw->ntfy ^= 0x10;
4203                 }
4204         }
4205
4206         drm_atomic_state_get(state);
4207
4208         if (nonblock)
4209                 queue_work(system_unbound_wq, &state->commit_work);
4210         else
4211                 nv50_disp_atomic_commit_tail(state);
4212
4213         drm_for_each_crtc(crtc, dev) {
4214                 if (crtc->state->enable) {
4215                         if (!drm->have_disp_power_ref) {
4216                                 drm->have_disp_power_ref = true;
4217                                 return 0;
4218                         }
4219                         active = true;
4220                         break;
4221                 }
4222         }
4223
4224         if (!active && drm->have_disp_power_ref) {
4225                 pm_runtime_put_autosuspend(dev->dev);
4226                 drm->have_disp_power_ref = false;
4227         }
4228
4229 err_cleanup:
4230         if (ret)
4231                 drm_atomic_helper_cleanup_planes(dev, state);
4232 done:
4233         pm_runtime_put_autosuspend(dev->dev);
4234         return ret;
4235 }
4236
4237 static struct nv50_outp_atom *
4238 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
4239 {
4240         struct nv50_outp_atom *outp;
4241
4242         list_for_each_entry(outp, &atom->outp, head) {
4243                 if (outp->encoder == encoder)
4244                         return outp;
4245         }
4246
4247         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
4248         if (!outp)
4249                 return ERR_PTR(-ENOMEM);
4250
4251         list_add(&outp->head, &atom->outp);
4252         outp->encoder = encoder;
4253         return outp;
4254 }
4255
4256 static int
4257 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
4258                                 struct drm_connector_state *old_connector_state)
4259 {
4260         struct drm_encoder *encoder = old_connector_state->best_encoder;
4261         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4262         struct drm_crtc *crtc;
4263         struct nv50_outp_atom *outp;
4264
4265         if (!(crtc = old_connector_state->crtc))
4266                 return 0;
4267
4268         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
4269         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
4270         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
4271                 outp = nv50_disp_outp_atomic_add(atom, encoder);
4272                 if (IS_ERR(outp))
4273                         return PTR_ERR(outp);
4274
4275                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
4276                         outp->flush_disable = true;
4277                         atom->flush_disable = true;
4278                 }
4279                 outp->clr.ctrl = true;
4280                 atom->lock_core = true;
4281         }
4282
4283         return 0;
4284 }
4285
4286 static int
4287 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
4288                                 struct drm_connector_state *connector_state)
4289 {
4290         struct drm_encoder *encoder = connector_state->best_encoder;
4291         struct drm_crtc_state *new_crtc_state;
4292         struct drm_crtc *crtc;
4293         struct nv50_outp_atom *outp;
4294
4295         if (!(crtc = connector_state->crtc))
4296                 return 0;
4297
4298         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
4299         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
4300                 outp = nv50_disp_outp_atomic_add(atom, encoder);
4301                 if (IS_ERR(outp))
4302                         return PTR_ERR(outp);
4303
4304                 outp->set.ctrl = true;
4305                 atom->lock_core = true;
4306         }
4307
4308         return 0;
4309 }
4310
4311 static int
4312 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
4313 {
4314         struct nv50_atom *atom = nv50_atom(state);
4315         struct drm_connector_state *old_connector_state, *new_connector_state;
4316         struct drm_connector *connector;
4317         int ret, i;
4318
4319         ret = drm_atomic_helper_check(dev, state);
4320         if (ret)
4321                 return ret;
4322
4323         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
4324                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
4325                 if (ret)
4326                         return ret;
4327
4328                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
4329                 if (ret)
4330                         return ret;
4331         }
4332
4333         return 0;
4334 }
4335
4336 static void
4337 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
4338 {
4339         struct nv50_atom *atom = nv50_atom(state);
4340         struct nv50_outp_atom *outp, *outt;
4341
4342         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
4343                 list_del(&outp->head);
4344                 kfree(outp);
4345         }
4346
4347         drm_atomic_state_default_clear(state);
4348 }
4349
4350 static void
4351 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
4352 {
4353         struct nv50_atom *atom = nv50_atom(state);
4354         drm_atomic_state_default_release(&atom->state);
4355         kfree(atom);
4356 }
4357
4358 static struct drm_atomic_state *
4359 nv50_disp_atomic_state_alloc(struct drm_device *dev)
4360 {
4361         struct nv50_atom *atom;
4362         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
4363             drm_atomic_state_init(dev, &atom->state) < 0) {
4364                 kfree(atom);
4365                 return NULL;
4366         }
4367         INIT_LIST_HEAD(&atom->outp);
4368         return &atom->state;
4369 }
4370
4371 static const struct drm_mode_config_funcs
4372 nv50_disp_func = {
4373         .fb_create = nouveau_user_framebuffer_create,
4374         .output_poll_changed = drm_fb_helper_output_poll_changed,
4375         .atomic_check = nv50_disp_atomic_check,
4376         .atomic_commit = nv50_disp_atomic_commit,
4377         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
4378         .atomic_state_clear = nv50_disp_atomic_state_clear,
4379         .atomic_state_free = nv50_disp_atomic_state_free,
4380 };
4381
4382 /******************************************************************************
4383  * Init
4384  *****************************************************************************/
4385
4386 void
4387 nv50_display_fini(struct drm_device *dev)
4388 {
4389         struct nouveau_encoder *nv_encoder;
4390         struct drm_encoder *encoder;
4391         struct drm_plane *plane;
4392
4393         drm_for_each_plane(plane, dev) {
4394                 struct nv50_wndw *wndw = nv50_wndw(plane);
4395                 if (plane->funcs != &nv50_wndw)
4396                         continue;
4397                 nv50_wndw_fini(wndw);
4398         }
4399
4400         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4401                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
4402                         nv_encoder = nouveau_encoder(encoder);
4403                         nv50_mstm_fini(nv_encoder->dp.mstm);
4404                 }
4405         }
4406 }
4407
4408 int
4409 nv50_display_init(struct drm_device *dev)
4410 {
4411         struct drm_encoder *encoder;
4412         struct drm_plane *plane;
4413         u32 *push;
4414
4415         push = evo_wait(nv50_mast(dev), 32);
4416         if (!push)
4417                 return -EBUSY;
4418
4419         evo_mthd(push, 0x0088, 1);
4420         evo_data(push, nv50_mast(dev)->base.sync.handle);
4421         evo_kick(push, nv50_mast(dev));
4422
4423         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4424                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
4425                         struct nouveau_encoder *nv_encoder =
4426                                 nouveau_encoder(encoder);
4427                         nv50_mstm_init(nv_encoder->dp.mstm);
4428                 }
4429         }
4430
4431         drm_for_each_plane(plane, dev) {
4432                 struct nv50_wndw *wndw = nv50_wndw(plane);
4433                 if (plane->funcs != &nv50_wndw)
4434                         continue;
4435                 nv50_wndw_init(wndw);
4436         }
4437
4438         return 0;
4439 }
4440
4441 void
4442 nv50_display_destroy(struct drm_device *dev)
4443 {
4444         struct nv50_disp *disp = nv50_disp(dev);
4445
4446         nv50_dmac_destroy(&disp->mast.base, disp->disp);
4447
4448         nouveau_bo_unmap(disp->sync);
4449         if (disp->sync)
4450                 nouveau_bo_unpin(disp->sync);
4451         nouveau_bo_ref(NULL, &disp->sync);
4452
4453         nouveau_display(dev)->priv = NULL;
4454         kfree(disp);
4455 }
4456
4457 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
4458 static int nouveau_atomic = 0;
4459 module_param_named(atomic, nouveau_atomic, int, 0400);
4460
4461 int
4462 nv50_display_create(struct drm_device *dev)
4463 {
4464         struct nvif_device *device = &nouveau_drm(dev)->client.device;
4465         struct nouveau_drm *drm = nouveau_drm(dev);
4466         struct dcb_table *dcb = &drm->vbios.dcb;
4467         struct drm_connector *connector, *tmp;
4468         struct nv50_disp *disp;
4469         struct dcb_output *dcbe;
4470         int crtcs, ret, i;
4471
4472         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
4473         if (!disp)
4474                 return -ENOMEM;
4475
4476         mutex_init(&disp->mutex);
4477
4478         nouveau_display(dev)->priv = disp;
4479         nouveau_display(dev)->dtor = nv50_display_destroy;
4480         nouveau_display(dev)->init = nv50_display_init;
4481         nouveau_display(dev)->fini = nv50_display_fini;
4482         disp->disp = &nouveau_display(dev)->disp;
4483         dev->mode_config.funcs = &nv50_disp_func;
4484         if (nouveau_atomic)
4485                 dev->driver->driver_features |= DRIVER_ATOMIC;
4486
4487         /* small shared memory area we use for notifiers and semaphores */
4488         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
4489                              0, 0x0000, NULL, NULL, &disp->sync);
4490         if (!ret) {
4491                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
4492                 if (!ret) {
4493                         ret = nouveau_bo_map(disp->sync);
4494                         if (ret)
4495                                 nouveau_bo_unpin(disp->sync);
4496                 }
4497                 if (ret)
4498                         nouveau_bo_ref(NULL, &disp->sync);
4499         }
4500
4501         if (ret)
4502                 goto out;
4503
4504         /* allocate master evo channel */
4505         ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset,
4506                               &disp->mast);
4507         if (ret)
4508                 goto out;
4509
4510         /* create crtc objects to represent the hw heads */
4511         if (disp->disp->oclass >= GF110_DISP)
4512                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
4513         else
4514                 crtcs = 0x3;
4515
4516         for (i = 0; i < fls(crtcs); i++) {
4517                 if (!(crtcs & (1 << i)))
4518                         continue;
4519                 ret = nv50_head_create(dev, i);
4520                 if (ret)
4521                         goto out;
4522         }
4523
4524         /* create encoder/connector objects based on VBIOS DCB table */
4525         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
4526                 connector = nouveau_connector_create(dev, dcbe->connector);
4527                 if (IS_ERR(connector))
4528                         continue;
4529
4530                 if (dcbe->location == DCB_LOC_ON_CHIP) {
4531                         switch (dcbe->type) {
4532                         case DCB_OUTPUT_TMDS:
4533                         case DCB_OUTPUT_LVDS:
4534                         case DCB_OUTPUT_DP:
4535                                 ret = nv50_sor_create(connector, dcbe);
4536                                 break;
4537                         case DCB_OUTPUT_ANALOG:
4538                                 ret = nv50_dac_create(connector, dcbe);
4539                                 break;
4540                         default:
4541                                 ret = -ENODEV;
4542                                 break;
4543                         }
4544                 } else {
4545                         ret = nv50_pior_create(connector, dcbe);
4546                 }
4547
4548                 if (ret) {
4549                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
4550                                      dcbe->location, dcbe->type,
4551                                      ffs(dcbe->or) - 1, ret);
4552                         ret = 0;
4553                 }
4554         }
4555
4556         /* cull any connectors we created that don't have an encoder */
4557         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
4558                 if (connector->encoder_ids[0])
4559                         continue;
4560
4561                 NV_WARN(drm, "%s has no encoders, removing\n",
4562                         connector->name);
4563                 connector->funcs->destroy(connector);
4564         }
4565
4566 out:
4567         if (ret)
4568                 nv50_display_destroy(dev);
4569         return ret;
4570 }