2 #include "nouveau_drv.h"
3 #include <drm/nouveau_drm.h>
5 static struct drm_mm_node *
6 nv20_fb_alloc_tag(struct drm_device *dev, uint32_t size)
8 struct drm_nouveau_private *dev_priv = dev->dev_private;
9 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
10 struct drm_mm_node *mem;
13 ret = drm_mm_pre_get(&pfb->tag_heap);
17 spin_lock(&dev_priv->tile.lock);
18 mem = drm_mm_search_free(&pfb->tag_heap, size, 0, 0);
20 mem = drm_mm_get_block_atomic(mem, size, 0);
21 spin_unlock(&dev_priv->tile.lock);
27 nv20_fb_free_tag(struct drm_device *dev, struct drm_mm_node **pmem)
29 struct drm_nouveau_private *dev_priv = dev->dev_private;
30 struct drm_mm_node *mem = *pmem;
32 spin_lock(&dev_priv->tile.lock);
33 drm_mm_put_block(mem);
34 spin_unlock(&dev_priv->tile.lock);
40 nv20_fb_init_tile_region(struct drm_device *dev, int i, uint32_t addr,
41 uint32_t size, uint32_t pitch, uint32_t flags)
43 struct drm_nouveau_private *dev_priv = dev->dev_private;
44 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
45 int bpp = (flags & NOUVEAU_GEM_TILE_32BPP ? 32 : 16);
47 tile->addr = 0x00000001 | addr;
48 tile->limit = max(1u, addr + size) - 1;
51 /* Allocate some of the on-die tag memory, used to store Z
52 * compression meta-data (most likely just a bitmap determining
53 * if a given tile is compressed or not).
55 if (flags & NOUVEAU_GEM_TILE_ZETA) {
56 tile->tag_mem = nv20_fb_alloc_tag(dev, size / 256);
58 /* Enable Z compression */
59 tile->zcomp = tile->tag_mem->start;
60 if (dev_priv->chipset >= 0x25) {
62 tile->zcomp |= NV25_PFB_ZCOMP_MODE_16;
64 tile->zcomp |= NV25_PFB_ZCOMP_MODE_32;
66 tile->zcomp |= NV20_PFB_ZCOMP_EN;
68 tile->zcomp |= NV20_PFB_ZCOMP_MODE_32;
77 nv20_fb_free_tile_region(struct drm_device *dev, int i)
79 struct drm_nouveau_private *dev_priv = dev->dev_private;
80 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
82 tile->addr = tile->limit = tile->pitch = tile->zcomp = 0;
83 nv20_fb_free_tag(dev, &tile->tag_mem);
87 nv20_fb_set_tile_region(struct drm_device *dev, int i)
89 struct drm_nouveau_private *dev_priv = dev->dev_private;
90 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
92 nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit);
93 nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch);
94 nv_wr32(dev, NV10_PFB_TILE(i), tile->addr);
95 nv_wr32(dev, NV20_PFB_ZCOMP(i), tile->zcomp);
99 nv20_fb_vram_init(struct drm_device *dev)
101 struct drm_nouveau_private *dev_priv = dev->dev_private;
102 u32 mem_size = nv_rd32(dev, 0x10020c);
103 u32 pbus1218 = nv_rd32(dev, 0x001218);
105 dev_priv->vram_size = mem_size & 0xff000000;
106 switch (pbus1218 & 0x00000300) {
107 case 0x00000000: dev_priv->vram_type = NV_MEM_TYPE_SDRAM; break;
108 case 0x00000100: dev_priv->vram_type = NV_MEM_TYPE_DDR1; break;
109 case 0x00000200: dev_priv->vram_type = NV_MEM_TYPE_GDDR3; break;
110 case 0x00000300: dev_priv->vram_type = NV_MEM_TYPE_GDDR2; break;
117 nv20_fb_init(struct drm_device *dev)
119 struct drm_nouveau_private *dev_priv = dev->dev_private;
120 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
123 if (dev_priv->chipset >= 0x25)
124 drm_mm_init(&pfb->tag_heap, 0, 64 * 1024);
126 drm_mm_init(&pfb->tag_heap, 0, 32 * 1024);
128 /* Turn all the tiling regions off. */
129 pfb->num_tiles = NV10_PFB_TILE__SIZE;
130 for (i = 0; i < pfb->num_tiles; i++)
131 pfb->set_tile_region(dev, i);
137 nv20_fb_takedown(struct drm_device *dev)
139 struct drm_nouveau_private *dev_priv = dev->dev_private;
140 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
143 for (i = 0; i < pfb->num_tiles; i++)
144 pfb->free_tile_region(dev, i);
146 drm_mm_takedown(&pfb->tag_heap);