2 * Copyright 2007 Matthieu CASTET <castet.matthieu@free.fr>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drm.h"
28 #include "nouveau_drv.h"
30 #define NV10_FIFO_NUMBER 32
33 uint32_t pipe_0x0000[0x040/4];
34 uint32_t pipe_0x0040[0x010/4];
35 uint32_t pipe_0x0200[0x0c0/4];
36 uint32_t pipe_0x4400[0x080/4];
37 uint32_t pipe_0x6400[0x3b0/4];
38 uint32_t pipe_0x6800[0x2f0/4];
39 uint32_t pipe_0x6c00[0x030/4];
40 uint32_t pipe_0x7000[0x130/4];
41 uint32_t pipe_0x7400[0x0c0/4];
42 uint32_t pipe_0x7800[0x0c0/4];
45 static int nv10_graph_ctx_regs[] = {
46 NV10_PGRAPH_CTX_SWITCH1,
47 NV10_PGRAPH_CTX_SWITCH2,
48 NV10_PGRAPH_CTX_SWITCH3,
49 NV10_PGRAPH_CTX_SWITCH4,
50 NV10_PGRAPH_CTX_SWITCH5,
51 NV10_PGRAPH_CTX_CACHE1, /* 8 values from 0x400160 to 0x40017c */
52 NV10_PGRAPH_CTX_CACHE2, /* 8 values from 0x400180 to 0x40019c */
53 NV10_PGRAPH_CTX_CACHE3, /* 8 values from 0x4001a0 to 0x4001bc */
54 NV10_PGRAPH_CTX_CACHE4, /* 8 values from 0x4001c0 to 0x4001dc */
55 NV10_PGRAPH_CTX_CACHE5, /* 8 values from 0x4001e0 to 0x4001fc */
92 NV04_PGRAPH_DMA_START_0,
93 NV04_PGRAPH_DMA_START_1,
94 NV04_PGRAPH_DMA_LENGTH,
96 NV10_PGRAPH_DMA_PITCH,
100 NV04_PGRAPH_BOFFSET1,
103 NV04_PGRAPH_BOFFSET2,
106 NV04_PGRAPH_BOFFSET3,
109 NV04_PGRAPH_BOFFSET4,
112 NV04_PGRAPH_BOFFSET5,
122 NV04_PGRAPH_BSWIZZLE2,
123 NV04_PGRAPH_BSWIZZLE5,
126 NV04_PGRAPH_PATT_COLOR0,
127 NV04_PGRAPH_PATT_COLOR1,
128 NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */
192 NV04_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */
194 NV04_PGRAPH_PATTERN_SHAPE,
195 NV03_PGRAPH_MONO_COLOR0,
198 NV04_PGRAPH_BETA_AND,
199 NV04_PGRAPH_BETA_PREMULT,
215 NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00-0x400f1c */
216 NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20-0x400f3c */
233 NV10_PGRAPH_GLOBALSTATE0,
234 NV10_PGRAPH_GLOBALSTATE1,
235 NV04_PGRAPH_STORED_FMT,
236 NV04_PGRAPH_SOURCE_COLOR,
237 NV03_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */
238 NV03_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */
301 NV03_PGRAPH_ABS_UCLIP_XMIN,
302 NV03_PGRAPH_ABS_UCLIP_XMAX,
303 NV03_PGRAPH_ABS_UCLIP_YMIN,
304 NV03_PGRAPH_ABS_UCLIP_YMAX,
309 NV03_PGRAPH_ABS_UCLIPA_XMIN,
310 NV03_PGRAPH_ABS_UCLIPA_XMAX,
311 NV03_PGRAPH_ABS_UCLIPA_YMIN,
312 NV03_PGRAPH_ABS_UCLIPA_YMAX,
313 NV03_PGRAPH_ABS_ICLIP_XMAX,
314 NV03_PGRAPH_ABS_ICLIP_YMAX,
315 NV03_PGRAPH_XY_LOGIC_MISC0,
316 NV03_PGRAPH_XY_LOGIC_MISC1,
317 NV03_PGRAPH_XY_LOGIC_MISC2,
318 NV03_PGRAPH_XY_LOGIC_MISC3,
323 NV10_PGRAPH_COMBINER0_IN_ALPHA,
324 NV10_PGRAPH_COMBINER1_IN_ALPHA,
325 NV10_PGRAPH_COMBINER0_IN_RGB,
326 NV10_PGRAPH_COMBINER1_IN_RGB,
327 NV10_PGRAPH_COMBINER_COLOR0,
328 NV10_PGRAPH_COMBINER_COLOR1,
329 NV10_PGRAPH_COMBINER0_OUT_ALPHA,
330 NV10_PGRAPH_COMBINER1_OUT_ALPHA,
331 NV10_PGRAPH_COMBINER0_OUT_RGB,
332 NV10_PGRAPH_COMBINER1_OUT_RGB,
333 NV10_PGRAPH_COMBINER_FINAL0,
334 NV10_PGRAPH_COMBINER_FINAL1,
351 NV04_PGRAPH_PASSTHRU_0,
352 NV04_PGRAPH_PASSTHRU_1,
353 NV04_PGRAPH_PASSTHRU_2,
354 NV10_PGRAPH_DIMX_TEXTURE,
355 NV10_PGRAPH_WDIMX_TEXTURE,
356 NV10_PGRAPH_DVD_COLORFMT,
357 NV10_PGRAPH_SCALED_FORMAT,
358 NV04_PGRAPH_MISC24_0,
359 NV04_PGRAPH_MISC24_1,
360 NV04_PGRAPH_MISC24_2,
367 static int nv17_graph_ctx_regs[] = {
389 int nv10[ARRAY_SIZE(nv10_graph_ctx_regs)];
390 int nv17[ARRAY_SIZE(nv17_graph_ctx_regs)];
391 struct pipe_state pipe_state;
394 static void nv10_graph_save_pipe(struct nouveau_channel *chan)
396 struct drm_device *dev = chan->dev;
397 struct graph_state *pgraph_ctx = chan->pgraph_ctx;
398 struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state;
400 #define PIPE_SAVE(addr) \
402 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \
403 for (i = 0; i < ARRAY_SIZE(fifo_pipe_state->pipe_##addr); i++) \
404 fifo_pipe_state->pipe_##addr[i] = nv_rd32(dev, NV10_PGRAPH_PIPE_DATA); \
421 static void nv10_graph_load_pipe(struct nouveau_channel *chan)
423 struct drm_device *dev = chan->dev;
424 struct graph_state *pgraph_ctx = chan->pgraph_ctx;
425 struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state;
427 uint32_t xfmode0, xfmode1;
428 #define PIPE_RESTORE(addr) \
430 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \
431 for (i = 0; i < ARRAY_SIZE(fifo_pipe_state->pipe_##addr); i++) \
432 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, fifo_pipe_state->pipe_##addr[i]); \
436 nouveau_wait_for_idle(dev);
437 /* XXX check haiku comments */
438 xfmode0 = nv_rd32(dev, NV10_PGRAPH_XFMODE0);
439 xfmode1 = nv_rd32(dev, NV10_PGRAPH_XFMODE1);
440 nv_wr32(dev, NV10_PGRAPH_XFMODE0, 0x10000000);
441 nv_wr32(dev, NV10_PGRAPH_XFMODE1, 0x00000000);
442 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
443 for (i = 0; i < 4; i++)
444 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
445 for (i = 0; i < 4; i++)
446 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000);
448 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
449 for (i = 0; i < 3; i++)
450 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
452 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
453 for (i = 0; i < 3; i++)
454 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000);
456 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
457 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000008);
460 PIPE_RESTORE(0x0200);
461 nouveau_wait_for_idle(dev);
464 nv_wr32(dev, NV10_PGRAPH_XFMODE0, xfmode0);
465 nv_wr32(dev, NV10_PGRAPH_XFMODE1, xfmode1);
466 PIPE_RESTORE(0x6400);
467 PIPE_RESTORE(0x6800);
468 PIPE_RESTORE(0x6c00);
469 PIPE_RESTORE(0x7000);
470 PIPE_RESTORE(0x7400);
471 PIPE_RESTORE(0x7800);
472 PIPE_RESTORE(0x4400);
473 PIPE_RESTORE(0x0000);
474 PIPE_RESTORE(0x0040);
475 nouveau_wait_for_idle(dev);
480 static void nv10_graph_create_pipe(struct nouveau_channel *chan)
482 struct drm_device *dev = chan->dev;
483 struct graph_state *pgraph_ctx = chan->pgraph_ctx;
484 struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state;
485 uint32_t *fifo_pipe_state_addr;
487 #define PIPE_INIT(addr) \
489 fifo_pipe_state_addr = fifo_pipe_state->pipe_##addr; \
491 #define PIPE_INIT_END(addr) \
493 uint32_t *__end_addr = fifo_pipe_state->pipe_##addr + \
494 ARRAY_SIZE(fifo_pipe_state->pipe_##addr); \
495 if (fifo_pipe_state_addr != __end_addr) \
496 NV_ERROR(dev, "incomplete pipe init for 0x%x : %p/%p\n", \
497 addr, fifo_pipe_state_addr, __end_addr); \
499 #define NV_WRITE_PIPE_INIT(value) *(fifo_pipe_state_addr++) = value
502 for (i = 0; i < 48; i++)
503 NV_WRITE_PIPE_INIT(0x00000000);
504 PIPE_INIT_END(0x0200);
507 for (i = 0; i < 211; i++)
508 NV_WRITE_PIPE_INIT(0x00000000);
509 NV_WRITE_PIPE_INIT(0x3f800000);
510 NV_WRITE_PIPE_INIT(0x40000000);
511 NV_WRITE_PIPE_INIT(0x40000000);
512 NV_WRITE_PIPE_INIT(0x40000000);
513 NV_WRITE_PIPE_INIT(0x40000000);
514 NV_WRITE_PIPE_INIT(0x00000000);
515 NV_WRITE_PIPE_INIT(0x00000000);
516 NV_WRITE_PIPE_INIT(0x3f800000);
517 NV_WRITE_PIPE_INIT(0x00000000);
518 NV_WRITE_PIPE_INIT(0x3f000000);
519 NV_WRITE_PIPE_INIT(0x3f000000);
520 NV_WRITE_PIPE_INIT(0x00000000);
521 NV_WRITE_PIPE_INIT(0x00000000);
522 NV_WRITE_PIPE_INIT(0x00000000);
523 NV_WRITE_PIPE_INIT(0x00000000);
524 NV_WRITE_PIPE_INIT(0x3f800000);
525 NV_WRITE_PIPE_INIT(0x00000000);
526 NV_WRITE_PIPE_INIT(0x00000000);
527 NV_WRITE_PIPE_INIT(0x00000000);
528 NV_WRITE_PIPE_INIT(0x00000000);
529 NV_WRITE_PIPE_INIT(0x00000000);
530 NV_WRITE_PIPE_INIT(0x3f800000);
531 NV_WRITE_PIPE_INIT(0x3f800000);
532 NV_WRITE_PIPE_INIT(0x3f800000);
533 NV_WRITE_PIPE_INIT(0x3f800000);
534 PIPE_INIT_END(0x6400);
537 for (i = 0; i < 162; i++)
538 NV_WRITE_PIPE_INIT(0x00000000);
539 NV_WRITE_PIPE_INIT(0x3f800000);
540 for (i = 0; i < 25; i++)
541 NV_WRITE_PIPE_INIT(0x00000000);
542 PIPE_INIT_END(0x6800);
545 NV_WRITE_PIPE_INIT(0x00000000);
546 NV_WRITE_PIPE_INIT(0x00000000);
547 NV_WRITE_PIPE_INIT(0x00000000);
548 NV_WRITE_PIPE_INIT(0x00000000);
549 NV_WRITE_PIPE_INIT(0xbf800000);
550 NV_WRITE_PIPE_INIT(0x00000000);
551 NV_WRITE_PIPE_INIT(0x00000000);
552 NV_WRITE_PIPE_INIT(0x00000000);
553 NV_WRITE_PIPE_INIT(0x00000000);
554 NV_WRITE_PIPE_INIT(0x00000000);
555 NV_WRITE_PIPE_INIT(0x00000000);
556 NV_WRITE_PIPE_INIT(0x00000000);
557 PIPE_INIT_END(0x6c00);
560 NV_WRITE_PIPE_INIT(0x00000000);
561 NV_WRITE_PIPE_INIT(0x00000000);
562 NV_WRITE_PIPE_INIT(0x00000000);
563 NV_WRITE_PIPE_INIT(0x00000000);
564 NV_WRITE_PIPE_INIT(0x00000000);
565 NV_WRITE_PIPE_INIT(0x00000000);
566 NV_WRITE_PIPE_INIT(0x00000000);
567 NV_WRITE_PIPE_INIT(0x00000000);
568 NV_WRITE_PIPE_INIT(0x00000000);
569 NV_WRITE_PIPE_INIT(0x00000000);
570 NV_WRITE_PIPE_INIT(0x00000000);
571 NV_WRITE_PIPE_INIT(0x00000000);
572 NV_WRITE_PIPE_INIT(0x7149f2ca);
573 NV_WRITE_PIPE_INIT(0x00000000);
574 NV_WRITE_PIPE_INIT(0x00000000);
575 NV_WRITE_PIPE_INIT(0x00000000);
576 NV_WRITE_PIPE_INIT(0x7149f2ca);
577 NV_WRITE_PIPE_INIT(0x00000000);
578 NV_WRITE_PIPE_INIT(0x00000000);
579 NV_WRITE_PIPE_INIT(0x00000000);
580 NV_WRITE_PIPE_INIT(0x7149f2ca);
581 NV_WRITE_PIPE_INIT(0x00000000);
582 NV_WRITE_PIPE_INIT(0x00000000);
583 NV_WRITE_PIPE_INIT(0x00000000);
584 NV_WRITE_PIPE_INIT(0x7149f2ca);
585 NV_WRITE_PIPE_INIT(0x00000000);
586 NV_WRITE_PIPE_INIT(0x00000000);
587 NV_WRITE_PIPE_INIT(0x00000000);
588 NV_WRITE_PIPE_INIT(0x7149f2ca);
589 NV_WRITE_PIPE_INIT(0x00000000);
590 NV_WRITE_PIPE_INIT(0x00000000);
591 NV_WRITE_PIPE_INIT(0x00000000);
592 NV_WRITE_PIPE_INIT(0x7149f2ca);
593 NV_WRITE_PIPE_INIT(0x00000000);
594 NV_WRITE_PIPE_INIT(0x00000000);
595 NV_WRITE_PIPE_INIT(0x00000000);
596 NV_WRITE_PIPE_INIT(0x7149f2ca);
597 NV_WRITE_PIPE_INIT(0x00000000);
598 NV_WRITE_PIPE_INIT(0x00000000);
599 NV_WRITE_PIPE_INIT(0x00000000);
600 NV_WRITE_PIPE_INIT(0x7149f2ca);
601 for (i = 0; i < 35; i++)
602 NV_WRITE_PIPE_INIT(0x00000000);
603 PIPE_INIT_END(0x7000);
606 for (i = 0; i < 48; i++)
607 NV_WRITE_PIPE_INIT(0x00000000);
608 PIPE_INIT_END(0x7400);
611 for (i = 0; i < 48; i++)
612 NV_WRITE_PIPE_INIT(0x00000000);
613 PIPE_INIT_END(0x7800);
616 for (i = 0; i < 32; i++)
617 NV_WRITE_PIPE_INIT(0x00000000);
618 PIPE_INIT_END(0x4400);
621 for (i = 0; i < 16; i++)
622 NV_WRITE_PIPE_INIT(0x00000000);
623 PIPE_INIT_END(0x0000);
626 for (i = 0; i < 4; i++)
627 NV_WRITE_PIPE_INIT(0x00000000);
628 PIPE_INIT_END(0x0040);
632 #undef NV_WRITE_PIPE_INIT
635 static int nv10_graph_ctx_regs_find_offset(struct drm_device *dev, int reg)
638 for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++) {
639 if (nv10_graph_ctx_regs[i] == reg)
642 NV_ERROR(dev, "unknow offset nv10_ctx_regs %d\n", reg);
646 static int nv17_graph_ctx_regs_find_offset(struct drm_device *dev, int reg)
649 for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++) {
650 if (nv17_graph_ctx_regs[i] == reg)
653 NV_ERROR(dev, "unknow offset nv17_ctx_regs %d\n", reg);
657 int nv10_graph_load_context(struct nouveau_channel *chan)
659 struct drm_device *dev = chan->dev;
660 struct drm_nouveau_private *dev_priv = dev->dev_private;
661 struct graph_state *pgraph_ctx = chan->pgraph_ctx;
665 for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++)
666 nv_wr32(dev, nv10_graph_ctx_regs[i], pgraph_ctx->nv10[i]);
667 if (dev_priv->chipset >= 0x17) {
668 for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++)
669 nv_wr32(dev, nv17_graph_ctx_regs[i],
670 pgraph_ctx->nv17[i]);
673 nv10_graph_load_pipe(chan);
675 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
676 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER);
677 nv_wr32(dev, NV10_PGRAPH_CTX_USER, (tmp & 0xffffff) | chan->id << 24);
678 tmp = nv_rd32(dev, NV10_PGRAPH_FFINTFC_ST2);
679 nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2, tmp & 0xcfffffff);
684 nv10_graph_unload_context(struct drm_device *dev)
686 struct drm_nouveau_private *dev_priv = dev->dev_private;
687 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
688 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
689 struct nouveau_channel *chan;
690 struct graph_state *ctx;
694 chan = pgraph->channel(dev);
697 ctx = chan->pgraph_ctx;
699 for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++)
700 ctx->nv10[i] = nv_rd32(dev, nv10_graph_ctx_regs[i]);
702 if (dev_priv->chipset >= 0x17) {
703 for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++)
704 ctx->nv17[i] = nv_rd32(dev, nv17_graph_ctx_regs[i]);
707 nv10_graph_save_pipe(chan);
709 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000000);
710 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff;
711 tmp |= (pfifo->channels - 1) << 24;
712 nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp);
717 nv10_graph_context_switch(struct drm_device *dev)
719 struct drm_nouveau_private *dev_priv = dev->dev_private;
720 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
721 struct nouveau_channel *chan = NULL;
724 pgraph->fifo_access(dev, false);
725 nouveau_wait_for_idle(dev);
727 /* If previous context is valid, we need to save it */
728 nv10_graph_unload_context(dev);
730 /* Load context for next channel */
731 chid = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
732 chan = dev_priv->fifos[chid];
734 nv10_graph_load_context(chan);
736 pgraph->fifo_access(dev, true);
739 #define NV_WRITE_CTX(reg, val) do { \
740 int offset = nv10_graph_ctx_regs_find_offset(dev, reg); \
742 pgraph_ctx->nv10[offset] = val; \
745 #define NV17_WRITE_CTX(reg, val) do { \
746 int offset = nv17_graph_ctx_regs_find_offset(dev, reg); \
748 pgraph_ctx->nv17[offset] = val; \
751 struct nouveau_channel *
752 nv10_graph_channel(struct drm_device *dev)
754 struct drm_nouveau_private *dev_priv = dev->dev_private;
755 int chid = dev_priv->engine.fifo.channels;
757 if (nv_rd32(dev, NV10_PGRAPH_CTX_CONTROL) & 0x00010000)
758 chid = nv_rd32(dev, NV10_PGRAPH_CTX_USER) >> 24;
760 if (chid >= dev_priv->engine.fifo.channels)
763 return dev_priv->fifos[chid];
766 int nv10_graph_create_context(struct nouveau_channel *chan)
768 struct drm_device *dev = chan->dev;
769 struct drm_nouveau_private *dev_priv = dev->dev_private;
770 struct graph_state *pgraph_ctx;
772 NV_DEBUG(dev, "nv10_graph_context_create %d\n", chan->id);
774 chan->pgraph_ctx = pgraph_ctx = kzalloc(sizeof(*pgraph_ctx),
776 if (pgraph_ctx == NULL)
780 NV_WRITE_CTX(0x00400e88, 0x08000000);
781 NV_WRITE_CTX(0x00400e9c, 0x4b7fffff);
782 NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff);
783 NV_WRITE_CTX(0x00400e10, 0x00001000);
784 NV_WRITE_CTX(0x00400e14, 0x00001000);
785 NV_WRITE_CTX(0x00400e30, 0x00080008);
786 NV_WRITE_CTX(0x00400e34, 0x00080008);
787 if (dev_priv->chipset >= 0x17) {
788 /* is it really needed ??? */
789 NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4,
790 nv_rd32(dev, NV10_PGRAPH_DEBUG_4));
791 NV17_WRITE_CTX(0x004006b0, nv_rd32(dev, 0x004006b0));
792 NV17_WRITE_CTX(0x00400eac, 0x0fff0000);
793 NV17_WRITE_CTX(0x00400eb0, 0x0fff0000);
794 NV17_WRITE_CTX(0x00400ec0, 0x00000080);
795 NV17_WRITE_CTX(0x00400ed0, 0x00000080);
797 NV_WRITE_CTX(NV10_PGRAPH_CTX_USER, chan->id << 24);
799 nv10_graph_create_pipe(chan);
803 void nv10_graph_destroy_context(struct nouveau_channel *chan)
805 struct graph_state *pgraph_ctx = chan->pgraph_ctx;
808 chan->pgraph_ctx = NULL;
811 int nv10_graph_init(struct drm_device *dev)
813 struct drm_nouveau_private *dev_priv = dev->dev_private;
817 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
818 ~NV_PMC_ENABLE_PGRAPH);
819 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
820 NV_PMC_ENABLE_PGRAPH);
822 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
823 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
825 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
826 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
827 nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x00118700);
828 /* nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x24E00810); */ /* 0x25f92ad9 */
829 nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x25f92ad9);
830 nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0x55DE0830 |
833 if (dev_priv->chipset >= 0x17) {
834 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x1f000000);
835 nv_wr32(dev, 0x004006b0, 0x40000020);
837 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000);
839 /* copy tile info from PFB */
840 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) {
841 nv_wr32(dev, NV10_PGRAPH_TILE(i),
842 nv_rd32(dev, NV10_PFB_TILE(i)));
843 nv_wr32(dev, NV10_PGRAPH_TLIMIT(i),
844 nv_rd32(dev, NV10_PFB_TLIMIT(i)));
845 nv_wr32(dev, NV10_PGRAPH_TSIZE(i),
846 nv_rd32(dev, NV10_PFB_TSIZE(i)));
847 nv_wr32(dev, NV10_PGRAPH_TSTATUS(i),
848 nv_rd32(dev, NV10_PFB_TSTATUS(i)));
851 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH1, 0x00000000);
852 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH2, 0x00000000);
853 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH3, 0x00000000);
854 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH4, 0x00000000);
855 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
857 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff;
858 tmp |= (dev_priv->engine.fifo.channels - 1) << 24;
859 nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp);
860 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
861 nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2, 0x08000000);
866 void nv10_graph_takedown(struct drm_device *dev)
870 struct nouveau_pgraph_object_class nv10_graph_grclass[] = {
871 { 0x0030, false, NULL }, /* null */
872 { 0x0039, false, NULL }, /* m2mf */
873 { 0x004a, false, NULL }, /* gdirect */
874 { 0x005f, false, NULL }, /* imageblit */
875 { 0x009f, false, NULL }, /* imageblit (nv12) */
876 { 0x008a, false, NULL }, /* ifc */
877 { 0x0089, false, NULL }, /* sifm */
878 { 0x0062, false, NULL }, /* surf2d */
879 { 0x0043, false, NULL }, /* rop */
880 { 0x0012, false, NULL }, /* beta1 */
881 { 0x0072, false, NULL }, /* beta4 */
882 { 0x0019, false, NULL }, /* cliprect */
883 { 0x0044, false, NULL }, /* pattern */
884 { 0x0052, false, NULL }, /* swzsurf */
885 { 0x0093, false, NULL }, /* surf3d */
886 { 0x0094, false, NULL }, /* tex_tri */
887 { 0x0095, false, NULL }, /* multitex_tri */
888 { 0x0056, false, NULL }, /* celcius (nv10) */
889 { 0x0096, false, NULL }, /* celcius (nv11) */
890 { 0x0099, false, NULL }, /* celcius (nv17) */