2 * Copyright 2007 Matthieu CASTET <castet.matthieu@free.fr>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drm.h"
28 #include "nouveau_drv.h"
30 #define NV10_FIFO_NUMBER 32
33 uint32_t pipe_0x0000[0x040/4];
34 uint32_t pipe_0x0040[0x010/4];
35 uint32_t pipe_0x0200[0x0c0/4];
36 uint32_t pipe_0x4400[0x080/4];
37 uint32_t pipe_0x6400[0x3b0/4];
38 uint32_t pipe_0x6800[0x2f0/4];
39 uint32_t pipe_0x6c00[0x030/4];
40 uint32_t pipe_0x7000[0x130/4];
41 uint32_t pipe_0x7400[0x0c0/4];
42 uint32_t pipe_0x7800[0x0c0/4];
45 static int nv10_graph_ctx_regs[] = {
46 NV10_PGRAPH_CTX_SWITCH1,
47 NV10_PGRAPH_CTX_SWITCH2,
48 NV10_PGRAPH_CTX_SWITCH3,
49 NV10_PGRAPH_CTX_SWITCH4,
50 NV10_PGRAPH_CTX_SWITCH5,
51 NV10_PGRAPH_CTX_CACHE1, /* 8 values from 0x400160 to 0x40017c */
52 NV10_PGRAPH_CTX_CACHE2, /* 8 values from 0x400180 to 0x40019c */
53 NV10_PGRAPH_CTX_CACHE3, /* 8 values from 0x4001a0 to 0x4001bc */
54 NV10_PGRAPH_CTX_CACHE4, /* 8 values from 0x4001c0 to 0x4001dc */
55 NV10_PGRAPH_CTX_CACHE5, /* 8 values from 0x4001e0 to 0x4001fc */
92 NV04_PGRAPH_DMA_START_0,
93 NV04_PGRAPH_DMA_START_1,
94 NV04_PGRAPH_DMA_LENGTH,
96 NV10_PGRAPH_DMA_PITCH,
100 NV04_PGRAPH_BOFFSET1,
103 NV04_PGRAPH_BOFFSET2,
106 NV04_PGRAPH_BOFFSET3,
109 NV04_PGRAPH_BOFFSET4,
112 NV04_PGRAPH_BOFFSET5,
122 NV04_PGRAPH_BSWIZZLE2,
123 NV04_PGRAPH_BSWIZZLE5,
126 NV04_PGRAPH_PATT_COLOR0,
127 NV04_PGRAPH_PATT_COLOR1,
128 NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */
192 NV04_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */
194 NV04_PGRAPH_PATTERN_SHAPE,
195 NV03_PGRAPH_MONO_COLOR0,
198 NV04_PGRAPH_BETA_AND,
199 NV04_PGRAPH_BETA_PREMULT,
215 NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00-0x400f1c */
216 NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20-0x400f3c */
233 NV10_PGRAPH_GLOBALSTATE0,
234 NV10_PGRAPH_GLOBALSTATE1,
235 NV04_PGRAPH_STORED_FMT,
236 NV04_PGRAPH_SOURCE_COLOR,
237 NV03_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */
238 NV03_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */
301 NV03_PGRAPH_ABS_UCLIP_XMIN,
302 NV03_PGRAPH_ABS_UCLIP_XMAX,
303 NV03_PGRAPH_ABS_UCLIP_YMIN,
304 NV03_PGRAPH_ABS_UCLIP_YMAX,
309 NV03_PGRAPH_ABS_UCLIPA_XMIN,
310 NV03_PGRAPH_ABS_UCLIPA_XMAX,
311 NV03_PGRAPH_ABS_UCLIPA_YMIN,
312 NV03_PGRAPH_ABS_UCLIPA_YMAX,
313 NV03_PGRAPH_ABS_ICLIP_XMAX,
314 NV03_PGRAPH_ABS_ICLIP_YMAX,
315 NV03_PGRAPH_XY_LOGIC_MISC0,
316 NV03_PGRAPH_XY_LOGIC_MISC1,
317 NV03_PGRAPH_XY_LOGIC_MISC2,
318 NV03_PGRAPH_XY_LOGIC_MISC3,
323 NV10_PGRAPH_COMBINER0_IN_ALPHA,
324 NV10_PGRAPH_COMBINER1_IN_ALPHA,
325 NV10_PGRAPH_COMBINER0_IN_RGB,
326 NV10_PGRAPH_COMBINER1_IN_RGB,
327 NV10_PGRAPH_COMBINER_COLOR0,
328 NV10_PGRAPH_COMBINER_COLOR1,
329 NV10_PGRAPH_COMBINER0_OUT_ALPHA,
330 NV10_PGRAPH_COMBINER1_OUT_ALPHA,
331 NV10_PGRAPH_COMBINER0_OUT_RGB,
332 NV10_PGRAPH_COMBINER1_OUT_RGB,
333 NV10_PGRAPH_COMBINER_FINAL0,
334 NV10_PGRAPH_COMBINER_FINAL1,
351 NV04_PGRAPH_PASSTHRU_0,
352 NV04_PGRAPH_PASSTHRU_1,
353 NV04_PGRAPH_PASSTHRU_2,
354 NV10_PGRAPH_DIMX_TEXTURE,
355 NV10_PGRAPH_WDIMX_TEXTURE,
356 NV10_PGRAPH_DVD_COLORFMT,
357 NV10_PGRAPH_SCALED_FORMAT,
358 NV04_PGRAPH_MISC24_0,
359 NV04_PGRAPH_MISC24_1,
360 NV04_PGRAPH_MISC24_2,
367 static int nv17_graph_ctx_regs[] = {
389 int nv10[ARRAY_SIZE(nv10_graph_ctx_regs)];
390 int nv17[ARRAY_SIZE(nv17_graph_ctx_regs)];
391 struct pipe_state pipe_state;
392 uint32_t lma_window[4];
395 #define PIPE_SAVE(dev, state, addr) \
398 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \
399 for (__i = 0; __i < ARRAY_SIZE(state); __i++) \
400 state[__i] = nv_rd32(dev, NV10_PGRAPH_PIPE_DATA); \
403 #define PIPE_RESTORE(dev, state, addr) \
406 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, addr); \
407 for (__i = 0; __i < ARRAY_SIZE(state); __i++) \
408 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, state[__i]); \
411 static void nv10_graph_save_pipe(struct nouveau_channel *chan)
413 struct drm_device *dev = chan->dev;
414 struct graph_state *pgraph_ctx = chan->pgraph_ctx;
415 struct pipe_state *pipe = &pgraph_ctx->pipe_state;
417 PIPE_SAVE(dev, pipe->pipe_0x4400, 0x4400);
418 PIPE_SAVE(dev, pipe->pipe_0x0200, 0x0200);
419 PIPE_SAVE(dev, pipe->pipe_0x6400, 0x6400);
420 PIPE_SAVE(dev, pipe->pipe_0x6800, 0x6800);
421 PIPE_SAVE(dev, pipe->pipe_0x6c00, 0x6c00);
422 PIPE_SAVE(dev, pipe->pipe_0x7000, 0x7000);
423 PIPE_SAVE(dev, pipe->pipe_0x7400, 0x7400);
424 PIPE_SAVE(dev, pipe->pipe_0x7800, 0x7800);
425 PIPE_SAVE(dev, pipe->pipe_0x0040, 0x0040);
426 PIPE_SAVE(dev, pipe->pipe_0x0000, 0x0000);
429 static void nv10_graph_load_pipe(struct nouveau_channel *chan)
431 struct drm_device *dev = chan->dev;
432 struct graph_state *pgraph_ctx = chan->pgraph_ctx;
433 struct pipe_state *pipe = &pgraph_ctx->pipe_state;
434 uint32_t xfmode0, xfmode1;
437 nouveau_wait_for_idle(dev);
438 /* XXX check haiku comments */
439 xfmode0 = nv_rd32(dev, NV10_PGRAPH_XFMODE0);
440 xfmode1 = nv_rd32(dev, NV10_PGRAPH_XFMODE1);
441 nv_wr32(dev, NV10_PGRAPH_XFMODE0, 0x10000000);
442 nv_wr32(dev, NV10_PGRAPH_XFMODE1, 0x00000000);
443 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
444 for (i = 0; i < 4; i++)
445 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
446 for (i = 0; i < 4; i++)
447 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000);
449 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
450 for (i = 0; i < 3; i++)
451 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
453 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
454 for (i = 0; i < 3; i++)
455 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000);
457 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
458 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000008);
461 PIPE_RESTORE(dev, pipe->pipe_0x0200, 0x0200);
462 nouveau_wait_for_idle(dev);
465 nv_wr32(dev, NV10_PGRAPH_XFMODE0, xfmode0);
466 nv_wr32(dev, NV10_PGRAPH_XFMODE1, xfmode1);
467 PIPE_RESTORE(dev, pipe->pipe_0x6400, 0x6400);
468 PIPE_RESTORE(dev, pipe->pipe_0x6800, 0x6800);
469 PIPE_RESTORE(dev, pipe->pipe_0x6c00, 0x6c00);
470 PIPE_RESTORE(dev, pipe->pipe_0x7000, 0x7000);
471 PIPE_RESTORE(dev, pipe->pipe_0x7400, 0x7400);
472 PIPE_RESTORE(dev, pipe->pipe_0x7800, 0x7800);
473 PIPE_RESTORE(dev, pipe->pipe_0x4400, 0x4400);
474 PIPE_RESTORE(dev, pipe->pipe_0x0000, 0x0000);
475 PIPE_RESTORE(dev, pipe->pipe_0x0040, 0x0040);
476 nouveau_wait_for_idle(dev);
479 static void nv10_graph_create_pipe(struct nouveau_channel *chan)
481 struct drm_device *dev = chan->dev;
482 struct graph_state *pgraph_ctx = chan->pgraph_ctx;
483 struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state;
484 uint32_t *fifo_pipe_state_addr;
486 #define PIPE_INIT(addr) \
488 fifo_pipe_state_addr = fifo_pipe_state->pipe_##addr; \
490 #define PIPE_INIT_END(addr) \
492 uint32_t *__end_addr = fifo_pipe_state->pipe_##addr + \
493 ARRAY_SIZE(fifo_pipe_state->pipe_##addr); \
494 if (fifo_pipe_state_addr != __end_addr) \
495 NV_ERROR(dev, "incomplete pipe init for 0x%x : %p/%p\n", \
496 addr, fifo_pipe_state_addr, __end_addr); \
498 #define NV_WRITE_PIPE_INIT(value) *(fifo_pipe_state_addr++) = value
501 for (i = 0; i < 48; i++)
502 NV_WRITE_PIPE_INIT(0x00000000);
503 PIPE_INIT_END(0x0200);
506 for (i = 0; i < 211; i++)
507 NV_WRITE_PIPE_INIT(0x00000000);
508 NV_WRITE_PIPE_INIT(0x3f800000);
509 NV_WRITE_PIPE_INIT(0x40000000);
510 NV_WRITE_PIPE_INIT(0x40000000);
511 NV_WRITE_PIPE_INIT(0x40000000);
512 NV_WRITE_PIPE_INIT(0x40000000);
513 NV_WRITE_PIPE_INIT(0x00000000);
514 NV_WRITE_PIPE_INIT(0x00000000);
515 NV_WRITE_PIPE_INIT(0x3f800000);
516 NV_WRITE_PIPE_INIT(0x00000000);
517 NV_WRITE_PIPE_INIT(0x3f000000);
518 NV_WRITE_PIPE_INIT(0x3f000000);
519 NV_WRITE_PIPE_INIT(0x00000000);
520 NV_WRITE_PIPE_INIT(0x00000000);
521 NV_WRITE_PIPE_INIT(0x00000000);
522 NV_WRITE_PIPE_INIT(0x00000000);
523 NV_WRITE_PIPE_INIT(0x3f800000);
524 NV_WRITE_PIPE_INIT(0x00000000);
525 NV_WRITE_PIPE_INIT(0x00000000);
526 NV_WRITE_PIPE_INIT(0x00000000);
527 NV_WRITE_PIPE_INIT(0x00000000);
528 NV_WRITE_PIPE_INIT(0x00000000);
529 NV_WRITE_PIPE_INIT(0x3f800000);
530 NV_WRITE_PIPE_INIT(0x3f800000);
531 NV_WRITE_PIPE_INIT(0x3f800000);
532 NV_WRITE_PIPE_INIT(0x3f800000);
533 PIPE_INIT_END(0x6400);
536 for (i = 0; i < 162; i++)
537 NV_WRITE_PIPE_INIT(0x00000000);
538 NV_WRITE_PIPE_INIT(0x3f800000);
539 for (i = 0; i < 25; i++)
540 NV_WRITE_PIPE_INIT(0x00000000);
541 PIPE_INIT_END(0x6800);
544 NV_WRITE_PIPE_INIT(0x00000000);
545 NV_WRITE_PIPE_INIT(0x00000000);
546 NV_WRITE_PIPE_INIT(0x00000000);
547 NV_WRITE_PIPE_INIT(0x00000000);
548 NV_WRITE_PIPE_INIT(0xbf800000);
549 NV_WRITE_PIPE_INIT(0x00000000);
550 NV_WRITE_PIPE_INIT(0x00000000);
551 NV_WRITE_PIPE_INIT(0x00000000);
552 NV_WRITE_PIPE_INIT(0x00000000);
553 NV_WRITE_PIPE_INIT(0x00000000);
554 NV_WRITE_PIPE_INIT(0x00000000);
555 NV_WRITE_PIPE_INIT(0x00000000);
556 PIPE_INIT_END(0x6c00);
559 NV_WRITE_PIPE_INIT(0x00000000);
560 NV_WRITE_PIPE_INIT(0x00000000);
561 NV_WRITE_PIPE_INIT(0x00000000);
562 NV_WRITE_PIPE_INIT(0x00000000);
563 NV_WRITE_PIPE_INIT(0x00000000);
564 NV_WRITE_PIPE_INIT(0x00000000);
565 NV_WRITE_PIPE_INIT(0x00000000);
566 NV_WRITE_PIPE_INIT(0x00000000);
567 NV_WRITE_PIPE_INIT(0x00000000);
568 NV_WRITE_PIPE_INIT(0x00000000);
569 NV_WRITE_PIPE_INIT(0x00000000);
570 NV_WRITE_PIPE_INIT(0x00000000);
571 NV_WRITE_PIPE_INIT(0x7149f2ca);
572 NV_WRITE_PIPE_INIT(0x00000000);
573 NV_WRITE_PIPE_INIT(0x00000000);
574 NV_WRITE_PIPE_INIT(0x00000000);
575 NV_WRITE_PIPE_INIT(0x7149f2ca);
576 NV_WRITE_PIPE_INIT(0x00000000);
577 NV_WRITE_PIPE_INIT(0x00000000);
578 NV_WRITE_PIPE_INIT(0x00000000);
579 NV_WRITE_PIPE_INIT(0x7149f2ca);
580 NV_WRITE_PIPE_INIT(0x00000000);
581 NV_WRITE_PIPE_INIT(0x00000000);
582 NV_WRITE_PIPE_INIT(0x00000000);
583 NV_WRITE_PIPE_INIT(0x7149f2ca);
584 NV_WRITE_PIPE_INIT(0x00000000);
585 NV_WRITE_PIPE_INIT(0x00000000);
586 NV_WRITE_PIPE_INIT(0x00000000);
587 NV_WRITE_PIPE_INIT(0x7149f2ca);
588 NV_WRITE_PIPE_INIT(0x00000000);
589 NV_WRITE_PIPE_INIT(0x00000000);
590 NV_WRITE_PIPE_INIT(0x00000000);
591 NV_WRITE_PIPE_INIT(0x7149f2ca);
592 NV_WRITE_PIPE_INIT(0x00000000);
593 NV_WRITE_PIPE_INIT(0x00000000);
594 NV_WRITE_PIPE_INIT(0x00000000);
595 NV_WRITE_PIPE_INIT(0x7149f2ca);
596 NV_WRITE_PIPE_INIT(0x00000000);
597 NV_WRITE_PIPE_INIT(0x00000000);
598 NV_WRITE_PIPE_INIT(0x00000000);
599 NV_WRITE_PIPE_INIT(0x7149f2ca);
600 for (i = 0; i < 35; i++)
601 NV_WRITE_PIPE_INIT(0x00000000);
602 PIPE_INIT_END(0x7000);
605 for (i = 0; i < 48; i++)
606 NV_WRITE_PIPE_INIT(0x00000000);
607 PIPE_INIT_END(0x7400);
610 for (i = 0; i < 48; i++)
611 NV_WRITE_PIPE_INIT(0x00000000);
612 PIPE_INIT_END(0x7800);
615 for (i = 0; i < 32; i++)
616 NV_WRITE_PIPE_INIT(0x00000000);
617 PIPE_INIT_END(0x4400);
620 for (i = 0; i < 16; i++)
621 NV_WRITE_PIPE_INIT(0x00000000);
622 PIPE_INIT_END(0x0000);
625 for (i = 0; i < 4; i++)
626 NV_WRITE_PIPE_INIT(0x00000000);
627 PIPE_INIT_END(0x0040);
631 #undef NV_WRITE_PIPE_INIT
634 static int nv10_graph_ctx_regs_find_offset(struct drm_device *dev, int reg)
637 for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++) {
638 if (nv10_graph_ctx_regs[i] == reg)
641 NV_ERROR(dev, "unknow offset nv10_ctx_regs %d\n", reg);
645 static int nv17_graph_ctx_regs_find_offset(struct drm_device *dev, int reg)
648 for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++) {
649 if (nv17_graph_ctx_regs[i] == reg)
652 NV_ERROR(dev, "unknow offset nv17_ctx_regs %d\n", reg);
656 int nv10_graph_load_context(struct nouveau_channel *chan)
658 struct drm_device *dev = chan->dev;
659 struct drm_nouveau_private *dev_priv = dev->dev_private;
660 struct graph_state *pgraph_ctx = chan->pgraph_ctx;
664 for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++)
665 nv_wr32(dev, nv10_graph_ctx_regs[i], pgraph_ctx->nv10[i]);
666 if (dev_priv->chipset >= 0x17) {
667 for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++)
668 nv_wr32(dev, nv17_graph_ctx_regs[i],
669 pgraph_ctx->nv17[i]);
672 nv10_graph_load_pipe(chan);
674 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
675 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER);
676 nv_wr32(dev, NV10_PGRAPH_CTX_USER, (tmp & 0xffffff) | chan->id << 24);
677 tmp = nv_rd32(dev, NV10_PGRAPH_FFINTFC_ST2);
678 nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2, tmp & 0xcfffffff);
683 nv10_graph_unload_context(struct drm_device *dev)
685 struct drm_nouveau_private *dev_priv = dev->dev_private;
686 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
687 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
688 struct nouveau_channel *chan;
689 struct graph_state *ctx;
693 chan = pgraph->channel(dev);
696 ctx = chan->pgraph_ctx;
698 for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++)
699 ctx->nv10[i] = nv_rd32(dev, nv10_graph_ctx_regs[i]);
701 if (dev_priv->chipset >= 0x17) {
702 for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++)
703 ctx->nv17[i] = nv_rd32(dev, nv17_graph_ctx_regs[i]);
706 nv10_graph_save_pipe(chan);
708 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000000);
709 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff;
710 tmp |= (pfifo->channels - 1) << 24;
711 nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp);
716 nv10_graph_context_switch(struct drm_device *dev)
718 struct drm_nouveau_private *dev_priv = dev->dev_private;
719 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
720 struct nouveau_channel *chan = NULL;
723 pgraph->fifo_access(dev, false);
724 nouveau_wait_for_idle(dev);
726 /* If previous context is valid, we need to save it */
727 nv10_graph_unload_context(dev);
729 /* Load context for next channel */
730 chid = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
731 chan = dev_priv->fifos[chid];
733 nv10_graph_load_context(chan);
735 pgraph->fifo_access(dev, true);
738 #define NV_WRITE_CTX(reg, val) do { \
739 int offset = nv10_graph_ctx_regs_find_offset(dev, reg); \
741 pgraph_ctx->nv10[offset] = val; \
744 #define NV17_WRITE_CTX(reg, val) do { \
745 int offset = nv17_graph_ctx_regs_find_offset(dev, reg); \
747 pgraph_ctx->nv17[offset] = val; \
750 struct nouveau_channel *
751 nv10_graph_channel(struct drm_device *dev)
753 struct drm_nouveau_private *dev_priv = dev->dev_private;
754 int chid = dev_priv->engine.fifo.channels;
756 if (nv_rd32(dev, NV10_PGRAPH_CTX_CONTROL) & 0x00010000)
757 chid = nv_rd32(dev, NV10_PGRAPH_CTX_USER) >> 24;
759 if (chid >= dev_priv->engine.fifo.channels)
762 return dev_priv->fifos[chid];
765 int nv10_graph_create_context(struct nouveau_channel *chan)
767 struct drm_device *dev = chan->dev;
768 struct drm_nouveau_private *dev_priv = dev->dev_private;
769 struct graph_state *pgraph_ctx;
771 NV_DEBUG(dev, "nv10_graph_context_create %d\n", chan->id);
773 chan->pgraph_ctx = pgraph_ctx = kzalloc(sizeof(*pgraph_ctx),
775 if (pgraph_ctx == NULL)
779 NV_WRITE_CTX(0x00400e88, 0x08000000);
780 NV_WRITE_CTX(0x00400e9c, 0x4b7fffff);
781 NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff);
782 NV_WRITE_CTX(0x00400e10, 0x00001000);
783 NV_WRITE_CTX(0x00400e14, 0x00001000);
784 NV_WRITE_CTX(0x00400e30, 0x00080008);
785 NV_WRITE_CTX(0x00400e34, 0x00080008);
786 if (dev_priv->chipset >= 0x17) {
787 /* is it really needed ??? */
788 NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4,
789 nv_rd32(dev, NV10_PGRAPH_DEBUG_4));
790 NV17_WRITE_CTX(0x004006b0, nv_rd32(dev, 0x004006b0));
791 NV17_WRITE_CTX(0x00400eac, 0x0fff0000);
792 NV17_WRITE_CTX(0x00400eb0, 0x0fff0000);
793 NV17_WRITE_CTX(0x00400ec0, 0x00000080);
794 NV17_WRITE_CTX(0x00400ed0, 0x00000080);
796 NV_WRITE_CTX(NV10_PGRAPH_CTX_USER, chan->id << 24);
798 nv10_graph_create_pipe(chan);
802 void nv10_graph_destroy_context(struct nouveau_channel *chan)
804 struct graph_state *pgraph_ctx = chan->pgraph_ctx;
807 chan->pgraph_ctx = NULL;
811 nv10_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
812 uint32_t size, uint32_t pitch)
814 uint32_t limit = max(1u, addr + size) - 1;
819 nv_wr32(dev, NV10_PGRAPH_TLIMIT(i), limit);
820 nv_wr32(dev, NV10_PGRAPH_TSIZE(i), pitch);
821 nv_wr32(dev, NV10_PGRAPH_TILE(i), addr);
824 int nv10_graph_init(struct drm_device *dev)
826 struct drm_nouveau_private *dev_priv = dev->dev_private;
830 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
831 ~NV_PMC_ENABLE_PGRAPH);
832 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
833 NV_PMC_ENABLE_PGRAPH);
835 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
836 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
838 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
839 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
840 nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x00118700);
841 /* nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x24E00810); */ /* 0x25f92ad9 */
842 nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x25f92ad9);
843 nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0x55DE0830 |
846 if (dev_priv->chipset >= 0x17) {
847 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x1f000000);
848 nv_wr32(dev, 0x400a10, 0x3ff3fb6);
849 nv_wr32(dev, 0x400838, 0x2f8684);
850 nv_wr32(dev, 0x40083c, 0x115f3f);
851 nv_wr32(dev, 0x004006b0, 0x40000020);
853 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000);
855 /* Turn all the tiling regions off. */
856 for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
857 nv10_graph_set_region_tiling(dev, i, 0, 0, 0);
859 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH1, 0x00000000);
860 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH2, 0x00000000);
861 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH3, 0x00000000);
862 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH4, 0x00000000);
863 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
865 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff;
866 tmp |= (dev_priv->engine.fifo.channels - 1) << 24;
867 nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp);
868 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
869 nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2, 0x08000000);
874 void nv10_graph_takedown(struct drm_device *dev)
879 nv17_graph_mthd_lma_window(struct nouveau_channel *chan, int grclass,
880 int mthd, uint32_t data)
882 struct drm_device *dev = chan->dev;
883 struct graph_state *ctx = chan->pgraph_ctx;
884 struct pipe_state *pipe = &ctx->pipe_state;
885 struct drm_nouveau_private *dev_priv = dev->dev_private;
886 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
887 uint32_t pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3];
888 uint32_t xfmode0, xfmode1;
891 ctx->lma_window[(mthd - 0x1638) / 4] = data;
896 nouveau_wait_for_idle(dev);
898 PIPE_SAVE(dev, pipe_0x0040, 0x0040);
899 PIPE_SAVE(dev, pipe->pipe_0x0200, 0x0200);
901 PIPE_RESTORE(dev, ctx->lma_window, 0x6790);
903 nouveau_wait_for_idle(dev);
905 xfmode0 = nv_rd32(dev, NV10_PGRAPH_XFMODE0);
906 xfmode1 = nv_rd32(dev, NV10_PGRAPH_XFMODE1);
908 PIPE_SAVE(dev, pipe->pipe_0x4400, 0x4400);
909 PIPE_SAVE(dev, pipe_0x64c0, 0x64c0);
910 PIPE_SAVE(dev, pipe_0x6ab0, 0x6ab0);
911 PIPE_SAVE(dev, pipe_0x6a80, 0x6a80);
913 nouveau_wait_for_idle(dev);
915 nv_wr32(dev, NV10_PGRAPH_XFMODE0, 0x10000000);
916 nv_wr32(dev, NV10_PGRAPH_XFMODE1, 0x00000000);
917 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
918 for (i = 0; i < 4; i++)
919 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
920 for (i = 0; i < 4; i++)
921 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000);
923 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
924 for (i = 0; i < 3; i++)
925 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
927 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
928 for (i = 0; i < 3; i++)
929 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000);
931 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
932 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000008);
934 PIPE_RESTORE(dev, pipe->pipe_0x0200, 0x0200);
936 nouveau_wait_for_idle(dev);
938 PIPE_RESTORE(dev, pipe_0x0040, 0x0040);
940 nv_wr32(dev, NV10_PGRAPH_XFMODE0, xfmode0);
941 nv_wr32(dev, NV10_PGRAPH_XFMODE1, xfmode1);
943 PIPE_RESTORE(dev, pipe_0x64c0, 0x64c0);
944 PIPE_RESTORE(dev, pipe_0x6ab0, 0x6ab0);
945 PIPE_RESTORE(dev, pipe_0x6a80, 0x6a80);
946 PIPE_RESTORE(dev, pipe->pipe_0x4400, 0x4400);
948 nv_wr32(dev, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0);
949 nv_wr32(dev, NV10_PGRAPH_PIPE_DATA, 0x00000000);
951 nouveau_wait_for_idle(dev);
953 pgraph->fifo_access(dev, true);
959 nv17_graph_mthd_lma_enable(struct nouveau_channel *chan, int grclass,
960 int mthd, uint32_t data)
962 struct drm_device *dev = chan->dev;
963 struct drm_nouveau_private *dev_priv = dev->dev_private;
964 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
966 nouveau_wait_for_idle(dev);
968 nv_wr32(dev, NV10_PGRAPH_DEBUG_4,
969 nv_rd32(dev, NV10_PGRAPH_DEBUG_4) | 0x1 << 8);
970 nv_wr32(dev, 0x004006b0,
971 nv_rd32(dev, 0x004006b0) | 0x8 << 24);
973 pgraph->fifo_access(dev, true);
978 static struct nouveau_pgraph_object_method nv17_graph_celsius_mthds[] = {
979 { 0x1638, nv17_graph_mthd_lma_window },
980 { 0x163c, nv17_graph_mthd_lma_window },
981 { 0x1640, nv17_graph_mthd_lma_window },
982 { 0x1644, nv17_graph_mthd_lma_window },
983 { 0x1658, nv17_graph_mthd_lma_enable },
987 struct nouveau_pgraph_object_class nv10_graph_grclass[] = {
988 { 0x0030, false, NULL }, /* null */
989 { 0x0039, false, NULL }, /* m2mf */
990 { 0x004a, false, NULL }, /* gdirect */
991 { 0x005f, false, NULL }, /* imageblit */
992 { 0x009f, false, NULL }, /* imageblit (nv12) */
993 { 0x008a, false, NULL }, /* ifc */
994 { 0x0089, false, NULL }, /* sifm */
995 { 0x0062, false, NULL }, /* surf2d */
996 { 0x0043, false, NULL }, /* rop */
997 { 0x0012, false, NULL }, /* beta1 */
998 { 0x0072, false, NULL }, /* beta4 */
999 { 0x0019, false, NULL }, /* cliprect */
1000 { 0x0044, false, NULL }, /* pattern */
1001 { 0x0052, false, NULL }, /* swzsurf */
1002 { 0x0093, false, NULL }, /* surf3d */
1003 { 0x0094, false, NULL }, /* tex_tri */
1004 { 0x0095, false, NULL }, /* multitex_tri */
1005 { 0x0056, false, NULL }, /* celcius (nv10) */
1006 { 0x0096, false, NULL }, /* celcius (nv11) */
1007 { 0x0099, false, nv17_graph_celsius_mthds }, /* celcius (nv17) */