2 #include "nouveau_drv.h"
3 #include <drm/nouveau_drm.h>
4 #include "nouveau_hw.h"
7 nv04_timer_init(struct drm_device *dev)
9 struct drm_nouveau_private *dev_priv = dev->dev_private;
12 nv_wr32(dev, NV04_PTIMER_INTR_EN_0, 0x00000000);
13 nv_wr32(dev, NV04_PTIMER_INTR_0, 0xFFFFFFFF);
15 /* aim for 31.25MHz, which gives us nanosecond timestamps */
18 /* determine base clock for timer source */
19 if (dev_priv->chipset < 0x40) {
20 n = nouveau_hw_get_clock(dev, PLL_CORE);
22 if (dev_priv->chipset == 0x40) {
23 /*XXX: figure this out */
26 n = dev_priv->crystal;
33 nv_wr32(dev, 0x009220, m - 1);
37 NV_WARN(dev, "PTIMER: unknown input clock freq\n");
38 if (!nv_rd32(dev, NV04_PTIMER_NUMERATOR) ||
39 !nv_rd32(dev, NV04_PTIMER_DENOMINATOR)) {
40 nv_wr32(dev, NV04_PTIMER_NUMERATOR, 1);
41 nv_wr32(dev, NV04_PTIMER_DENOMINATOR, 1);
46 /* reduce ratio to acceptable values */
47 while (((n % 5) == 0) && ((d % 5) == 0)) {
52 while (((n % 2) == 0) && ((d % 2) == 0)) {
57 while (n > 0xffff || d > 0xffff) {
62 nv_wr32(dev, NV04_PTIMER_NUMERATOR, n);
63 nv_wr32(dev, NV04_PTIMER_DENOMINATOR, d);
68 nv04_timer_read(struct drm_device *dev)
73 hi = nv_rd32(dev, NV04_PTIMER_TIME_1);
74 lo = nv_rd32(dev, NV04_PTIMER_TIME_0);
75 } while (hi != nv_rd32(dev, NV04_PTIMER_TIME_1));
77 return ((u64)hi << 32 | lo);
81 nv04_timer_takedown(struct drm_device *dev)