3 #include "nouveau_drv.h"
4 #include "nouveau_ramht.h"
6 /* returns the size of fifo context */
8 nouveau_fifo_ctx_size(struct drm_device *dev)
10 struct drm_nouveau_private *dev_priv = dev->dev_private;
12 if (dev_priv->chipset >= 0x40)
15 if (dev_priv->chipset >= 0x17)
21 int nv04_instmem_init(struct drm_device *dev)
23 struct drm_nouveau_private *dev_priv = dev->dev_private;
24 struct nouveau_gpuobj *ramht = NULL;
28 /* Setup shared RAMHT */
29 ret = nouveau_gpuobj_new_fake(dev, 0x10000, ~0, 4096,
30 NVOBJ_FLAG_ZERO_ALLOC, &ramht);
34 ret = nouveau_ramht_new(dev, ramht, &dev_priv->ramht);
35 nouveau_gpuobj_ref(NULL, &ramht);
40 ret = nouveau_gpuobj_new_fake(dev, 0x11200, ~0, 512,
41 NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ramro);
46 length = dev_priv->engine.fifo.channels * nouveau_fifo_ctx_size(dev);
47 switch (dev_priv->card_type) {
56 ret = nouveau_gpuobj_new_fake(dev, offset, ~0, length,
57 NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ramfc);
61 /* Only allow space after RAMFC to be used for object allocation */
64 /* It appears RAMRO (or something?) is controlled by 0x2220/0x2230
65 * on certain NV4x chipsets as well as RAMFC. When 0x2230 == 0
66 * ("new style" control) the upper 16-bits of 0x2220 points at this
67 * other mysterious table that's clobbering important things.
69 * We're now pointing this at RAMIN+0x30000 to avoid RAMFC getting
70 * smashed to pieces on us, so reserve 0x30000-0x40000 too..
72 if (dev_priv->card_type >= NV_40) {
77 ret = drm_mm_init(&dev_priv->ramin_heap, offset,
78 dev_priv->ramin_rsvd_vram - offset);
80 NV_ERROR(dev, "Failed to init RAMIN heap: %d\n", ret);
84 dev_priv->ramin_available = true;
89 nv04_instmem_takedown(struct drm_device *dev)
91 struct drm_nouveau_private *dev_priv = dev->dev_private;
93 nouveau_ramht_ref(NULL, &dev_priv->ramht, NULL);
94 nouveau_gpuobj_ref(NULL, &dev_priv->ramro);
95 nouveau_gpuobj_ref(NULL, &dev_priv->ramfc);
99 nv04_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj,
106 nv04_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
111 nv04_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
117 nv04_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
123 nv04_instmem_flush(struct drm_device *dev)
128 nv04_instmem_suspend(struct drm_device *dev)
134 nv04_instmem_resume(struct drm_device *dev)