2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 #include <linux/swab.h>
29 #include "drm_sarea.h"
30 #include "drm_crtc_helper.h"
31 #include <linux/vgaarb.h>
33 #include "nouveau_drv.h"
34 #include "nouveau_drm.h"
35 #include "nv50_display.h"
37 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
38 static void nouveau_stub_takedown(struct drm_device *dev) {}
40 static int nouveau_init_engine_ptrs(struct drm_device *dev)
42 struct drm_nouveau_private *dev_priv = dev->dev_private;
43 struct nouveau_engine *engine = &dev_priv->engine;
45 switch (dev_priv->chipset & 0xf0) {
47 engine->instmem.init = nv04_instmem_init;
48 engine->instmem.takedown = nv04_instmem_takedown;
49 engine->instmem.suspend = nv04_instmem_suspend;
50 engine->instmem.resume = nv04_instmem_resume;
51 engine->instmem.populate = nv04_instmem_populate;
52 engine->instmem.clear = nv04_instmem_clear;
53 engine->instmem.bind = nv04_instmem_bind;
54 engine->instmem.unbind = nv04_instmem_unbind;
55 engine->instmem.prepare_access = nv04_instmem_prepare_access;
56 engine->instmem.finish_access = nv04_instmem_finish_access;
57 engine->mc.init = nv04_mc_init;
58 engine->mc.takedown = nv04_mc_takedown;
59 engine->timer.init = nv04_timer_init;
60 engine->timer.read = nv04_timer_read;
61 engine->timer.takedown = nv04_timer_takedown;
62 engine->fb.init = nv04_fb_init;
63 engine->fb.takedown = nv04_fb_takedown;
64 engine->graph.grclass = nv04_graph_grclass;
65 engine->graph.init = nv04_graph_init;
66 engine->graph.takedown = nv04_graph_takedown;
67 engine->graph.fifo_access = nv04_graph_fifo_access;
68 engine->graph.channel = nv04_graph_channel;
69 engine->graph.create_context = nv04_graph_create_context;
70 engine->graph.destroy_context = nv04_graph_destroy_context;
71 engine->graph.load_context = nv04_graph_load_context;
72 engine->graph.unload_context = nv04_graph_unload_context;
73 engine->fifo.channels = 16;
74 engine->fifo.init = nv04_fifo_init;
75 engine->fifo.takedown = nouveau_stub_takedown;
76 engine->fifo.disable = nv04_fifo_disable;
77 engine->fifo.enable = nv04_fifo_enable;
78 engine->fifo.reassign = nv04_fifo_reassign;
79 engine->fifo.channel_id = nv04_fifo_channel_id;
80 engine->fifo.create_context = nv04_fifo_create_context;
81 engine->fifo.destroy_context = nv04_fifo_destroy_context;
82 engine->fifo.load_context = nv04_fifo_load_context;
83 engine->fifo.unload_context = nv04_fifo_unload_context;
86 engine->instmem.init = nv04_instmem_init;
87 engine->instmem.takedown = nv04_instmem_takedown;
88 engine->instmem.suspend = nv04_instmem_suspend;
89 engine->instmem.resume = nv04_instmem_resume;
90 engine->instmem.populate = nv04_instmem_populate;
91 engine->instmem.clear = nv04_instmem_clear;
92 engine->instmem.bind = nv04_instmem_bind;
93 engine->instmem.unbind = nv04_instmem_unbind;
94 engine->instmem.prepare_access = nv04_instmem_prepare_access;
95 engine->instmem.finish_access = nv04_instmem_finish_access;
96 engine->mc.init = nv04_mc_init;
97 engine->mc.takedown = nv04_mc_takedown;
98 engine->timer.init = nv04_timer_init;
99 engine->timer.read = nv04_timer_read;
100 engine->timer.takedown = nv04_timer_takedown;
101 engine->fb.init = nv10_fb_init;
102 engine->fb.takedown = nv10_fb_takedown;
103 engine->graph.grclass = nv10_graph_grclass;
104 engine->graph.init = nv10_graph_init;
105 engine->graph.takedown = nv10_graph_takedown;
106 engine->graph.channel = nv10_graph_channel;
107 engine->graph.create_context = nv10_graph_create_context;
108 engine->graph.destroy_context = nv10_graph_destroy_context;
109 engine->graph.fifo_access = nv04_graph_fifo_access;
110 engine->graph.load_context = nv10_graph_load_context;
111 engine->graph.unload_context = nv10_graph_unload_context;
112 engine->fifo.channels = 32;
113 engine->fifo.init = nv10_fifo_init;
114 engine->fifo.takedown = nouveau_stub_takedown;
115 engine->fifo.disable = nv04_fifo_disable;
116 engine->fifo.enable = nv04_fifo_enable;
117 engine->fifo.reassign = nv04_fifo_reassign;
118 engine->fifo.channel_id = nv10_fifo_channel_id;
119 engine->fifo.create_context = nv10_fifo_create_context;
120 engine->fifo.destroy_context = nv10_fifo_destroy_context;
121 engine->fifo.load_context = nv10_fifo_load_context;
122 engine->fifo.unload_context = nv10_fifo_unload_context;
125 engine->instmem.init = nv04_instmem_init;
126 engine->instmem.takedown = nv04_instmem_takedown;
127 engine->instmem.suspend = nv04_instmem_suspend;
128 engine->instmem.resume = nv04_instmem_resume;
129 engine->instmem.populate = nv04_instmem_populate;
130 engine->instmem.clear = nv04_instmem_clear;
131 engine->instmem.bind = nv04_instmem_bind;
132 engine->instmem.unbind = nv04_instmem_unbind;
133 engine->instmem.prepare_access = nv04_instmem_prepare_access;
134 engine->instmem.finish_access = nv04_instmem_finish_access;
135 engine->mc.init = nv04_mc_init;
136 engine->mc.takedown = nv04_mc_takedown;
137 engine->timer.init = nv04_timer_init;
138 engine->timer.read = nv04_timer_read;
139 engine->timer.takedown = nv04_timer_takedown;
140 engine->fb.init = nv10_fb_init;
141 engine->fb.takedown = nv10_fb_takedown;
142 engine->graph.grclass = nv20_graph_grclass;
143 engine->graph.init = nv20_graph_init;
144 engine->graph.takedown = nv20_graph_takedown;
145 engine->graph.channel = nv10_graph_channel;
146 engine->graph.create_context = nv20_graph_create_context;
147 engine->graph.destroy_context = nv20_graph_destroy_context;
148 engine->graph.fifo_access = nv04_graph_fifo_access;
149 engine->graph.load_context = nv20_graph_load_context;
150 engine->graph.unload_context = nv20_graph_unload_context;
151 engine->fifo.channels = 32;
152 engine->fifo.init = nv10_fifo_init;
153 engine->fifo.takedown = nouveau_stub_takedown;
154 engine->fifo.disable = nv04_fifo_disable;
155 engine->fifo.enable = nv04_fifo_enable;
156 engine->fifo.reassign = nv04_fifo_reassign;
157 engine->fifo.channel_id = nv10_fifo_channel_id;
158 engine->fifo.create_context = nv10_fifo_create_context;
159 engine->fifo.destroy_context = nv10_fifo_destroy_context;
160 engine->fifo.load_context = nv10_fifo_load_context;
161 engine->fifo.unload_context = nv10_fifo_unload_context;
164 engine->instmem.init = nv04_instmem_init;
165 engine->instmem.takedown = nv04_instmem_takedown;
166 engine->instmem.suspend = nv04_instmem_suspend;
167 engine->instmem.resume = nv04_instmem_resume;
168 engine->instmem.populate = nv04_instmem_populate;
169 engine->instmem.clear = nv04_instmem_clear;
170 engine->instmem.bind = nv04_instmem_bind;
171 engine->instmem.unbind = nv04_instmem_unbind;
172 engine->instmem.prepare_access = nv04_instmem_prepare_access;
173 engine->instmem.finish_access = nv04_instmem_finish_access;
174 engine->mc.init = nv04_mc_init;
175 engine->mc.takedown = nv04_mc_takedown;
176 engine->timer.init = nv04_timer_init;
177 engine->timer.read = nv04_timer_read;
178 engine->timer.takedown = nv04_timer_takedown;
179 engine->fb.init = nv10_fb_init;
180 engine->fb.takedown = nv10_fb_takedown;
181 engine->graph.grclass = nv30_graph_grclass;
182 engine->graph.init = nv30_graph_init;
183 engine->graph.takedown = nv20_graph_takedown;
184 engine->graph.fifo_access = nv04_graph_fifo_access;
185 engine->graph.channel = nv10_graph_channel;
186 engine->graph.create_context = nv20_graph_create_context;
187 engine->graph.destroy_context = nv20_graph_destroy_context;
188 engine->graph.load_context = nv20_graph_load_context;
189 engine->graph.unload_context = nv20_graph_unload_context;
190 engine->fifo.channels = 32;
191 engine->fifo.init = nv10_fifo_init;
192 engine->fifo.takedown = nouveau_stub_takedown;
193 engine->fifo.disable = nv04_fifo_disable;
194 engine->fifo.enable = nv04_fifo_enable;
195 engine->fifo.reassign = nv04_fifo_reassign;
196 engine->fifo.channel_id = nv10_fifo_channel_id;
197 engine->fifo.create_context = nv10_fifo_create_context;
198 engine->fifo.destroy_context = nv10_fifo_destroy_context;
199 engine->fifo.load_context = nv10_fifo_load_context;
200 engine->fifo.unload_context = nv10_fifo_unload_context;
204 engine->instmem.init = nv04_instmem_init;
205 engine->instmem.takedown = nv04_instmem_takedown;
206 engine->instmem.suspend = nv04_instmem_suspend;
207 engine->instmem.resume = nv04_instmem_resume;
208 engine->instmem.populate = nv04_instmem_populate;
209 engine->instmem.clear = nv04_instmem_clear;
210 engine->instmem.bind = nv04_instmem_bind;
211 engine->instmem.unbind = nv04_instmem_unbind;
212 engine->instmem.prepare_access = nv04_instmem_prepare_access;
213 engine->instmem.finish_access = nv04_instmem_finish_access;
214 engine->mc.init = nv40_mc_init;
215 engine->mc.takedown = nv40_mc_takedown;
216 engine->timer.init = nv04_timer_init;
217 engine->timer.read = nv04_timer_read;
218 engine->timer.takedown = nv04_timer_takedown;
219 engine->fb.init = nv40_fb_init;
220 engine->fb.takedown = nv40_fb_takedown;
221 engine->graph.grclass = nv40_graph_grclass;
222 engine->graph.init = nv40_graph_init;
223 engine->graph.takedown = nv40_graph_takedown;
224 engine->graph.fifo_access = nv04_graph_fifo_access;
225 engine->graph.channel = nv40_graph_channel;
226 engine->graph.create_context = nv40_graph_create_context;
227 engine->graph.destroy_context = nv40_graph_destroy_context;
228 engine->graph.load_context = nv40_graph_load_context;
229 engine->graph.unload_context = nv40_graph_unload_context;
230 engine->fifo.channels = 32;
231 engine->fifo.init = nv40_fifo_init;
232 engine->fifo.takedown = nouveau_stub_takedown;
233 engine->fifo.disable = nv04_fifo_disable;
234 engine->fifo.enable = nv04_fifo_enable;
235 engine->fifo.reassign = nv04_fifo_reassign;
236 engine->fifo.channel_id = nv10_fifo_channel_id;
237 engine->fifo.create_context = nv40_fifo_create_context;
238 engine->fifo.destroy_context = nv40_fifo_destroy_context;
239 engine->fifo.load_context = nv40_fifo_load_context;
240 engine->fifo.unload_context = nv40_fifo_unload_context;
243 case 0x80: /* gotta love NVIDIA's consistency.. */
246 engine->instmem.init = nv50_instmem_init;
247 engine->instmem.takedown = nv50_instmem_takedown;
248 engine->instmem.suspend = nv50_instmem_suspend;
249 engine->instmem.resume = nv50_instmem_resume;
250 engine->instmem.populate = nv50_instmem_populate;
251 engine->instmem.clear = nv50_instmem_clear;
252 engine->instmem.bind = nv50_instmem_bind;
253 engine->instmem.unbind = nv50_instmem_unbind;
254 engine->instmem.prepare_access = nv50_instmem_prepare_access;
255 engine->instmem.finish_access = nv50_instmem_finish_access;
256 engine->mc.init = nv50_mc_init;
257 engine->mc.takedown = nv50_mc_takedown;
258 engine->timer.init = nv04_timer_init;
259 engine->timer.read = nv04_timer_read;
260 engine->timer.takedown = nv04_timer_takedown;
261 engine->fb.init = nouveau_stub_init;
262 engine->fb.takedown = nouveau_stub_takedown;
263 engine->graph.grclass = nv50_graph_grclass;
264 engine->graph.init = nv50_graph_init;
265 engine->graph.takedown = nv50_graph_takedown;
266 engine->graph.fifo_access = nv50_graph_fifo_access;
267 engine->graph.channel = nv50_graph_channel;
268 engine->graph.create_context = nv50_graph_create_context;
269 engine->graph.destroy_context = nv50_graph_destroy_context;
270 engine->graph.load_context = nv50_graph_load_context;
271 engine->graph.unload_context = nv50_graph_unload_context;
272 engine->fifo.channels = 128;
273 engine->fifo.init = nv50_fifo_init;
274 engine->fifo.takedown = nv50_fifo_takedown;
275 engine->fifo.disable = nv04_fifo_disable;
276 engine->fifo.enable = nv04_fifo_enable;
277 engine->fifo.reassign = nv04_fifo_reassign;
278 engine->fifo.channel_id = nv50_fifo_channel_id;
279 engine->fifo.create_context = nv50_fifo_create_context;
280 engine->fifo.destroy_context = nv50_fifo_destroy_context;
281 engine->fifo.load_context = nv50_fifo_load_context;
282 engine->fifo.unload_context = nv50_fifo_unload_context;
285 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
293 nouveau_vga_set_decode(void *priv, bool state)
296 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
297 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
299 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
303 nouveau_card_init_channel(struct drm_device *dev)
305 struct drm_nouveau_private *dev_priv = dev->dev_private;
306 struct nouveau_gpuobj *gpuobj;
309 ret = nouveau_channel_alloc(dev, &dev_priv->channel,
310 (struct drm_file *)-2,
316 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
317 0, nouveau_mem_fb_amount(dev),
318 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
323 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
329 ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
330 dev_priv->gart_info.aper_size,
331 NV_DMA_ACCESS_RW, &gpuobj, NULL);
335 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
342 nouveau_gpuobj_del(dev, &gpuobj);
343 nouveau_channel_free(dev_priv->channel);
344 dev_priv->channel = NULL;
349 nouveau_card_init(struct drm_device *dev)
351 struct drm_nouveau_private *dev_priv = dev->dev_private;
352 struct nouveau_engine *engine;
355 NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
357 if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
360 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
362 /* Initialise internal driver API hooks */
363 ret = nouveau_init_engine_ptrs(dev);
366 engine = &dev_priv->engine;
367 dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
369 /* Parse BIOS tables / Run init tables if card not POSTed */
370 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
371 ret = nouveau_bios_init(dev);
376 ret = nouveau_gpuobj_early_init(dev);
380 /* Initialise instance memory, must happen before mem_init so we
381 * know exactly how much VRAM we're able to use for "normal"
384 ret = engine->instmem.init(dev);
386 goto out_gpuobj_early;
388 /* Setup the memory manager */
389 ret = nouveau_mem_init(dev);
393 ret = nouveau_gpuobj_init(dev);
398 ret = engine->mc.init(dev);
403 ret = engine->timer.init(dev);
408 ret = engine->fb.init(dev);
413 ret = engine->graph.init(dev);
418 ret = engine->fifo.init(dev);
422 /* this call irq_preinstall, register irq handler and
423 * call irq_postinstall
425 ret = drm_irq_install(dev);
429 ret = drm_vblank_init(dev, 0);
433 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
435 if (!engine->graph.accel_blocked) {
436 ret = nouveau_card_init_channel(dev);
441 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
442 if (dev_priv->card_type >= NV_50)
443 ret = nv50_display_create(dev);
445 ret = nv04_display_create(dev);
450 ret = nouveau_backlight_init(dev);
452 NV_ERROR(dev, "Error %d registering backlight\n", ret);
454 dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
456 if (drm_core_check_feature(dev, DRIVER_MODESET))
457 drm_helper_initial_config(dev);
462 drm_irq_uninstall(dev);
464 engine->fifo.takedown(dev);
466 engine->graph.takedown(dev);
468 engine->fb.takedown(dev);
470 engine->timer.takedown(dev);
472 engine->mc.takedown(dev);
474 nouveau_gpuobj_takedown(dev);
476 nouveau_mem_close(dev);
478 engine->instmem.takedown(dev);
480 nouveau_gpuobj_late_takedown(dev);
482 nouveau_bios_takedown(dev);
484 vga_client_register(dev->pdev, NULL, NULL, NULL);
488 static void nouveau_card_takedown(struct drm_device *dev)
490 struct drm_nouveau_private *dev_priv = dev->dev_private;
491 struct nouveau_engine *engine = &dev_priv->engine;
493 NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
495 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
496 nouveau_backlight_exit(dev);
498 if (dev_priv->channel) {
499 nouveau_channel_free(dev_priv->channel);
500 dev_priv->channel = NULL;
503 engine->fifo.takedown(dev);
504 engine->graph.takedown(dev);
505 engine->fb.takedown(dev);
506 engine->timer.takedown(dev);
507 engine->mc.takedown(dev);
509 mutex_lock(&dev->struct_mutex);
510 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
511 mutex_unlock(&dev->struct_mutex);
512 nouveau_sgdma_takedown(dev);
514 nouveau_gpuobj_takedown(dev);
515 nouveau_mem_close(dev);
516 engine->instmem.takedown(dev);
518 if (drm_core_check_feature(dev, DRIVER_MODESET))
519 drm_irq_uninstall(dev);
521 nouveau_gpuobj_late_takedown(dev);
522 nouveau_bios_takedown(dev);
524 vga_client_register(dev->pdev, NULL, NULL, NULL);
526 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
530 /* here a client dies, release the stuff that was allocated for its
532 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
534 nouveau_channel_cleanup(dev, file_priv);
537 /* first module load, setup the mmio/fb mapping */
538 /* KMS: we need mmio at load time, not when the first drm client opens. */
539 int nouveau_firstopen(struct drm_device *dev)
544 /* if we have an OF card, copy vbios to RAMIN */
545 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
547 #if defined(__powerpc__)
549 const uint32_t *bios;
550 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
552 NV_INFO(dev, "Unable to get the OF node\n");
556 bios = of_get_property(dn, "NVDA,BMP", &size);
558 for (i = 0; i < size; i += 4)
559 nv_wi32(dev, i, bios[i/4]);
560 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
562 NV_INFO(dev, "Unable to get the OF bios\n");
567 int nouveau_load(struct drm_device *dev, unsigned long flags)
569 struct drm_nouveau_private *dev_priv;
571 resource_size_t mmio_start_offs;
573 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
576 dev->dev_private = dev_priv;
579 dev_priv->flags = flags & NOUVEAU_FLAGS;
580 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
582 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
583 dev->pci_vendor, dev->pci_device, dev->pdev->class);
585 dev_priv->acpi_dsm = nouveau_dsm_probe(dev);
587 if (dev_priv->acpi_dsm)
588 nouveau_hybrid_setup(dev);
590 dev_priv->wq = create_workqueue("nouveau");
594 /* resource 0 is mmio regs */
595 /* resource 1 is linear FB */
596 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
597 /* resource 6 is bios */
599 /* map the mmio regs */
600 mmio_start_offs = pci_resource_start(dev->pdev, 0);
601 dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
602 if (!dev_priv->mmio) {
603 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
604 "Please report your setup to " DRIVER_EMAIL "\n");
607 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
608 (unsigned long long)mmio_start_offs);
611 /* Put the card in BE mode if it's not */
612 if (nv_rd32(dev, NV03_PMC_BOOT_1))
613 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
618 /* Time to determine the card architecture */
619 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
621 /* We're dealing with >=NV10 */
622 if ((reg0 & 0x0f000000) > 0) {
623 /* Bit 27-20 contain the architecture in hex */
624 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
626 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
627 dev_priv->chipset = 0x04;
629 dev_priv->chipset = 0xff;
631 switch (dev_priv->chipset & 0xf0) {
636 dev_priv->card_type = dev_priv->chipset & 0xf0;
640 dev_priv->card_type = NV_40;
646 dev_priv->card_type = NV_50;
649 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
653 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
654 dev_priv->card_type, reg0);
656 /* map larger RAMIN aperture on NV40 cards */
657 dev_priv->ramin = NULL;
658 if (dev_priv->card_type >= NV_40) {
660 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
663 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
664 dev_priv->ramin = ioremap(
665 pci_resource_start(dev->pdev, ramin_bar),
666 dev_priv->ramin_size);
667 if (!dev_priv->ramin) {
668 NV_ERROR(dev, "Failed to init RAMIN mapping, "
669 "limited instance memory available\n");
673 /* On older cards (or if the above failed), create a map covering
674 * the BAR0 PRAMIN aperture */
675 if (!dev_priv->ramin) {
676 dev_priv->ramin_size = 1 * 1024 * 1024;
677 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
678 dev_priv->ramin_size);
679 if (!dev_priv->ramin) {
680 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
685 nouveau_OF_copy_vbios_to_ramin(dev);
688 if (dev->pci_device == 0x01a0)
689 dev_priv->flags |= NV_NFORCE;
690 else if (dev->pci_device == 0x01f0)
691 dev_priv->flags |= NV_NFORCE2;
693 /* For kernel modesetting, init card now and bring up fbcon */
694 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
695 int ret = nouveau_card_init(dev);
703 static void nouveau_close(struct drm_device *dev)
705 struct drm_nouveau_private *dev_priv = dev->dev_private;
707 /* In the case of an error dev_priv may not be be allocated yet */
708 if (dev_priv && dev_priv->card_type)
709 nouveau_card_takedown(dev);
712 /* KMS: we need mmio at load time, not when the first drm client opens. */
713 void nouveau_lastclose(struct drm_device *dev)
715 if (drm_core_check_feature(dev, DRIVER_MODESET))
721 int nouveau_unload(struct drm_device *dev)
723 struct drm_nouveau_private *dev_priv = dev->dev_private;
725 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
726 if (dev_priv->card_type >= NV_50)
727 nv50_display_destroy(dev);
729 nv04_display_destroy(dev);
733 iounmap(dev_priv->mmio);
734 iounmap(dev_priv->ramin);
737 dev->dev_private = NULL;
742 nouveau_ioctl_card_init(struct drm_device *dev, void *data,
743 struct drm_file *file_priv)
745 return nouveau_card_init(dev);
748 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
749 struct drm_file *file_priv)
751 struct drm_nouveau_private *dev_priv = dev->dev_private;
752 struct drm_nouveau_getparam *getparam = data;
754 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
756 switch (getparam->param) {
757 case NOUVEAU_GETPARAM_CHIPSET_ID:
758 getparam->value = dev_priv->chipset;
760 case NOUVEAU_GETPARAM_PCI_VENDOR:
761 getparam->value = dev->pci_vendor;
763 case NOUVEAU_GETPARAM_PCI_DEVICE:
764 getparam->value = dev->pci_device;
766 case NOUVEAU_GETPARAM_BUS_TYPE:
767 if (drm_device_is_agp(dev))
768 getparam->value = NV_AGP;
769 else if (drm_device_is_pcie(dev))
770 getparam->value = NV_PCIE;
772 getparam->value = NV_PCI;
774 case NOUVEAU_GETPARAM_FB_PHYSICAL:
775 getparam->value = dev_priv->fb_phys;
777 case NOUVEAU_GETPARAM_AGP_PHYSICAL:
778 getparam->value = dev_priv->gart_info.aper_base;
780 case NOUVEAU_GETPARAM_PCI_PHYSICAL:
782 getparam->value = (unsigned long)dev->sg->virtual;
784 NV_ERROR(dev, "Requested PCIGART address, "
785 "while no PCIGART was created\n");
789 case NOUVEAU_GETPARAM_FB_SIZE:
790 getparam->value = dev_priv->fb_available_size;
792 case NOUVEAU_GETPARAM_AGP_SIZE:
793 getparam->value = dev_priv->gart_info.aper_size;
795 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
796 getparam->value = dev_priv->vm_vram_base;
799 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
807 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
808 struct drm_file *file_priv)
810 struct drm_nouveau_setparam *setparam = data;
812 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
814 switch (setparam->param) {
816 NV_ERROR(dev, "unknown parameter %lld\n", setparam->param);
823 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
824 bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
825 uint32_t reg, uint32_t mask, uint32_t val)
827 struct drm_nouveau_private *dev_priv = dev->dev_private;
828 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
829 uint64_t start = ptimer->read(dev);
832 if ((nv_rd32(dev, reg) & mask) == val)
834 } while (ptimer->read(dev) - start < timeout);
839 /* Waits for PGRAPH to go completely idle */
840 bool nouveau_wait_for_idle(struct drm_device *dev)
842 if (!nv_wait(NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
843 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
844 nv_rd32(dev, NV04_PGRAPH_STATUS));