2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
59 #define MAX_NUM_DCB_ENTRIES 16
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
68 struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
79 u32 busy_placements[3];
80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
89 struct nouveau_channel *channel;
96 struct nouveau_tile_reg *tile;
98 struct drm_gem_object *gem;
99 struct drm_file *cpu_filp;
103 static inline struct nouveau_bo *
104 nouveau_bo(struct ttm_buffer_object *bo)
106 return container_of(bo, struct nouveau_bo, bo);
109 static inline struct nouveau_bo *
110 nouveau_gem_object(struct drm_gem_object *gem)
112 return gem ? gem->driver_private : NULL;
115 /* TODO: submit equivalent to TTM generic API upstream? */
116 static inline void __iomem *
117 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
121 &nvbo->kmap, &is_iomem);
122 WARN_ON_ONCE(ioptr && !is_iomem);
127 NV_NFORCE = 0x10000000,
128 NV_NFORCE2 = 0x20000000
131 #define NVOBJ_ENGINE_SW 0
132 #define NVOBJ_ENGINE_GR 1
133 #define NVOBJ_ENGINE_DISPLAY 2
134 #define NVOBJ_ENGINE_INT 0xdeadbeef
136 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
137 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
138 #define NVOBJ_FLAG_FAKE (1 << 3)
139 struct nouveau_gpuobj {
140 struct drm_device *dev;
141 struct list_head list;
143 struct drm_mm_node *im_pramin;
144 struct nouveau_bo *im_backing;
145 uint32_t im_backing_start;
146 uint32_t *im_backing_suspend;
159 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
163 struct nouveau_channel {
164 struct drm_device *dev;
167 /* owner of this fifo */
168 struct drm_file *file_priv;
169 /* mapping of the fifo itself */
170 struct drm_local_map *map;
172 /* mapping of the regs controling the fifo */
179 /* lock protects the pending list only */
181 struct list_head pending;
183 uint32_t sequence_ack;
184 atomic_t last_sequence_irq;
187 /* DMA push buffer */
188 struct nouveau_gpuobj *pushbuf;
189 struct nouveau_bo *pushbuf_bo;
190 uint32_t pushbuf_base;
192 /* Notifier memory */
193 struct nouveau_bo *notifier_bo;
194 struct drm_mm notifier_heap;
197 struct nouveau_gpuobj *ramfc;
198 struct nouveau_gpuobj *cache;
201 /* XXX may be merge 2 pointers as private data ??? */
202 struct nouveau_gpuobj *ramin_grctx;
206 struct nouveau_gpuobj *vm_pd;
207 struct nouveau_gpuobj *vm_gart_pt;
208 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
211 struct nouveau_gpuobj *ramin; /* Private instmem */
212 struct drm_mm ramin_heap; /* Private PRAMIN heap */
213 struct nouveau_ramht *ramht; /* Hash table */
215 /* GPU object info for stuff used in-kernel (mm_enabled) */
217 uint32_t vram_handle;
218 uint32_t gart_handle;
221 /* Push buffer state (only for drm's channel on !mm_enabled) */
227 /* access via pushbuf_bo */
235 uint32_t sw_subchannel[8];
238 struct nouveau_gpuobj *vblsem;
239 uint32_t vblsem_offset;
240 uint32_t vblsem_rval;
241 struct list_head vbl_wait;
247 struct drm_info_list info;
251 struct nouveau_instmem_engine {
254 int (*init)(struct drm_device *dev);
255 void (*takedown)(struct drm_device *dev);
256 int (*suspend)(struct drm_device *dev);
257 void (*resume)(struct drm_device *dev);
259 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
261 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
262 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
263 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
264 void (*flush)(struct drm_device *);
267 struct nouveau_mc_engine {
268 int (*init)(struct drm_device *dev);
269 void (*takedown)(struct drm_device *dev);
272 struct nouveau_timer_engine {
273 int (*init)(struct drm_device *dev);
274 void (*takedown)(struct drm_device *dev);
275 uint64_t (*read)(struct drm_device *dev);
278 struct nouveau_fb_engine {
281 int (*init)(struct drm_device *dev);
282 void (*takedown)(struct drm_device *dev);
284 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
285 uint32_t size, uint32_t pitch);
288 struct nouveau_fifo_engine {
291 struct nouveau_gpuobj *playlist[2];
294 int (*init)(struct drm_device *);
295 void (*takedown)(struct drm_device *);
297 void (*disable)(struct drm_device *);
298 void (*enable)(struct drm_device *);
299 bool (*reassign)(struct drm_device *, bool enable);
300 bool (*cache_flush)(struct drm_device *dev);
301 bool (*cache_pull)(struct drm_device *dev, bool enable);
303 int (*channel_id)(struct drm_device *);
305 int (*create_context)(struct nouveau_channel *);
306 void (*destroy_context)(struct nouveau_channel *);
307 int (*load_context)(struct nouveau_channel *);
308 int (*unload_context)(struct drm_device *);
311 struct nouveau_pgraph_object_method {
313 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
317 struct nouveau_pgraph_object_class {
320 struct nouveau_pgraph_object_method *methods;
323 struct nouveau_pgraph_engine {
324 struct nouveau_pgraph_object_class *grclass;
328 /* NV2x/NV3x context table (0x400780) */
329 struct nouveau_gpuobj *ctx_table;
331 int (*init)(struct drm_device *);
332 void (*takedown)(struct drm_device *);
334 void (*fifo_access)(struct drm_device *, bool);
336 struct nouveau_channel *(*channel)(struct drm_device *);
337 int (*create_context)(struct nouveau_channel *);
338 void (*destroy_context)(struct nouveau_channel *);
339 int (*load_context)(struct nouveau_channel *);
340 int (*unload_context)(struct drm_device *);
342 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
343 uint32_t size, uint32_t pitch);
346 struct nouveau_display_engine {
347 int (*early_init)(struct drm_device *);
348 void (*late_takedown)(struct drm_device *);
349 int (*create)(struct drm_device *);
350 int (*init)(struct drm_device *);
351 void (*destroy)(struct drm_device *);
354 struct nouveau_gpio_engine {
355 int (*init)(struct drm_device *);
356 void (*takedown)(struct drm_device *);
358 int (*get)(struct drm_device *, enum dcb_gpio_tag);
359 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
361 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
364 struct nouveau_engine {
365 struct nouveau_instmem_engine instmem;
366 struct nouveau_mc_engine mc;
367 struct nouveau_timer_engine timer;
368 struct nouveau_fb_engine fb;
369 struct nouveau_pgraph_engine graph;
370 struct nouveau_fifo_engine fifo;
371 struct nouveau_display_engine display;
372 struct nouveau_gpio_engine gpio;
375 struct nouveau_pll_vals {
379 uint8_t N1, M1, N2, M2;
381 uint8_t M1, N1, M2, N2;
386 } __attribute__((packed));
393 enum nv04_fp_display_regs {
403 struct nv04_crtc_reg {
404 unsigned char MiscOutReg; /* */
407 uint8_t Sequencer[5];
409 uint8_t Attribute[21];
410 unsigned char DAC[768]; /* Internal Colorlookuptable */
420 uint32_t crtc_eng_ctrl;
423 uint32_t nv10_cursync;
424 struct nouveau_pll_vals pllvals;
425 uint32_t ramdac_gen_ctrl;
431 uint32_t tv_vsync_delay;
434 uint32_t tv_hsync_delay;
435 uint32_t tv_hsync_delay2;
436 uint32_t fp_horiz_regs[7];
437 uint32_t fp_vert_regs[7];
440 uint32_t dither_regs[6];
444 uint32_t fp_margin_color;
449 uint32_t ctv_regs[38];
452 struct nv04_output_reg {
457 struct nv04_mode_state {
485 uint32_t cursorConfig;
494 struct nv04_crtc_reg crtc_reg[2];
497 enum nouveau_card_type {
507 struct drm_nouveau_private {
508 struct drm_device *dev;
510 /* the card type, takes NV_* as values */
511 enum nouveau_card_type card_type;
512 /* exact chipset, derived from NV_PMC_BOOT_0 */
520 struct nouveau_bo *vga_ram;
522 struct workqueue_struct *wq;
523 struct work_struct irq_work;
524 struct work_struct hpd_work;
526 struct list_head vbl_waiting;
529 struct drm_global_reference mem_global_ref;
530 struct ttm_bo_global_ref bo_global_ref;
531 struct ttm_bo_device bdev;
532 atomic_t validate_sequence;
535 int fifo_alloc_count;
536 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
538 struct nouveau_engine engine;
539 struct nouveau_channel *channel;
541 /* For PFIFO and PGRAPH. */
542 spinlock_t context_switch_lock;
544 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
545 struct nouveau_ramht *ramht;
546 uint32_t ramin_rsvd_vram;
547 uint32_t ramht_offset;
550 uint32_t ramfc_offset;
552 uint32_t ramro_offset;
557 NOUVEAU_GART_NONE = 0,
565 struct nouveau_gpuobj *sg_ctxdma;
566 struct page *sg_dummy_page;
567 dma_addr_t sg_dummy_bus;
570 /* nv10-nv40 tiling regions */
572 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
576 /* VRAM/fb configuration */
578 uint64_t vram_sys_base;
581 uint64_t fb_available_size;
582 uint64_t fb_mappable_pages;
583 uint64_t fb_aper_free;
586 /* G8x/G9x virtual address space */
587 uint64_t vm_gart_base;
588 uint64_t vm_gart_size;
589 uint64_t vm_vram_base;
590 uint64_t vm_vram_size;
592 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
595 struct drm_mm ramin_heap;
597 struct list_head gpuobj_list;
601 struct nv04_mode_state mode_reg;
602 struct nv04_mode_state saved_reg;
603 uint32_t saved_vga_font[4][16384];
605 uint32_t dac_users[4];
607 struct nouveau_suspend_resume {
608 uint32_t *ramin_copy;
611 struct backlight_device *backlight;
613 struct nouveau_channel *evo;
615 struct dcb_entry *dcb;
621 struct dentry *channel_root;
624 struct nouveau_fbdev *nfbdev;
625 struct apertures_struct *apertures;
628 static inline struct drm_nouveau_private *
629 nouveau_bdev(struct ttm_bo_device *bd)
631 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
635 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
637 struct nouveau_bo *prev;
643 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
645 struct ttm_buffer_object *bo = &prev->bo;
653 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
654 struct drm_nouveau_private *nv = dev->dev_private; \
655 if (!nouveau_channel_owner(dev, (cl), (id))) { \
656 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
657 DRM_CURRENTPID, (id)); \
660 (ch) = nv->fifos[(id)]; \
664 extern int nouveau_noagp;
665 extern int nouveau_duallink;
666 extern int nouveau_uscript_lvds;
667 extern int nouveau_uscript_tmds;
668 extern int nouveau_vram_pushbuf;
669 extern int nouveau_vram_notify;
670 extern int nouveau_fbpercrtc;
671 extern int nouveau_tv_disable;
672 extern char *nouveau_tv_norm;
673 extern int nouveau_reg_debug;
674 extern char *nouveau_vbios;
675 extern int nouveau_ignorelid;
676 extern int nouveau_nofbaccel;
677 extern int nouveau_noaccel;
678 extern int nouveau_override_conntype;
680 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
681 extern int nouveau_pci_resume(struct pci_dev *pdev);
683 /* nouveau_state.c */
684 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
685 extern int nouveau_load(struct drm_device *, unsigned long flags);
686 extern int nouveau_firstopen(struct drm_device *);
687 extern void nouveau_lastclose(struct drm_device *);
688 extern int nouveau_unload(struct drm_device *);
689 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
691 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
693 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
694 uint32_t reg, uint32_t mask, uint32_t val);
695 extern bool nouveau_wait_for_idle(struct drm_device *);
696 extern int nouveau_card_init(struct drm_device *);
699 extern int nouveau_mem_detect(struct drm_device *dev);
700 extern int nouveau_mem_init(struct drm_device *);
701 extern int nouveau_mem_init_agp(struct drm_device *);
702 extern int nouveau_mem_reset_agp(struct drm_device *);
703 extern void nouveau_mem_close(struct drm_device *);
704 extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
708 extern void nv10_mem_expire_tiling(struct drm_device *dev,
709 struct nouveau_tile_reg *tile,
710 struct nouveau_fence *fence);
711 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
712 uint32_t size, uint32_t flags,
714 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
717 /* nouveau_notifier.c */
718 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
719 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
720 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
721 int cout, uint32_t *offset);
722 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
723 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
725 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
728 /* nouveau_channel.c */
729 extern struct drm_ioctl_desc nouveau_ioctls[];
730 extern int nouveau_max_ioctl;
731 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
732 extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
734 extern int nouveau_channel_alloc(struct drm_device *dev,
735 struct nouveau_channel **chan,
736 struct drm_file *file_priv,
737 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
738 extern void nouveau_channel_free(struct nouveau_channel *);
740 /* nouveau_object.c */
741 extern int nouveau_gpuobj_early_init(struct drm_device *);
742 extern int nouveau_gpuobj_init(struct drm_device *);
743 extern void nouveau_gpuobj_takedown(struct drm_device *);
744 extern void nouveau_gpuobj_late_takedown(struct drm_device *);
745 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
746 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
747 extern void nouveau_gpuobj_resume(struct drm_device *dev);
748 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
749 uint32_t vram_h, uint32_t tt_h);
750 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
751 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
752 uint32_t size, int align, uint32_t flags,
753 struct nouveau_gpuobj **);
754 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
755 struct nouveau_gpuobj **);
756 extern int nouveau_gpuobj_new_fake(struct drm_device *,
757 uint32_t p_offset, uint32_t b_offset,
758 uint32_t size, uint32_t flags,
759 struct nouveau_gpuobj **);
760 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
761 uint64_t offset, uint64_t size, int access,
762 int target, struct nouveau_gpuobj **);
763 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
764 uint64_t offset, uint64_t size,
765 int access, struct nouveau_gpuobj **,
767 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
768 struct nouveau_gpuobj **);
769 extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
770 struct nouveau_gpuobj **);
771 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
773 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
777 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
778 extern void nouveau_irq_preinstall(struct drm_device *);
779 extern int nouveau_irq_postinstall(struct drm_device *);
780 extern void nouveau_irq_uninstall(struct drm_device *);
782 /* nouveau_sgdma.c */
783 extern int nouveau_sgdma_init(struct drm_device *);
784 extern void nouveau_sgdma_takedown(struct drm_device *);
785 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
787 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
789 /* nouveau_debugfs.c */
790 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
791 extern int nouveau_debugfs_init(struct drm_minor *);
792 extern void nouveau_debugfs_takedown(struct drm_minor *);
793 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
794 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
797 nouveau_debugfs_init(struct drm_minor *minor)
802 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
807 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
813 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
819 extern void nouveau_dma_pre_init(struct nouveau_channel *);
820 extern int nouveau_dma_init(struct nouveau_channel *);
821 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
824 #define ROM_BIOS_PAGE 4096
825 #if defined(CONFIG_ACPI)
826 void nouveau_register_dsm_handler(void);
827 void nouveau_unregister_dsm_handler(void);
828 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
829 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
830 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
832 static inline void nouveau_register_dsm_handler(void) {}
833 static inline void nouveau_unregister_dsm_handler(void) {}
834 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
835 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
836 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
839 /* nouveau_backlight.c */
840 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
841 extern int nouveau_backlight_init(struct drm_device *);
842 extern void nouveau_backlight_exit(struct drm_device *);
844 static inline int nouveau_backlight_init(struct drm_device *dev)
849 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
853 extern int nouveau_bios_init(struct drm_device *);
854 extern void nouveau_bios_takedown(struct drm_device *dev);
855 extern int nouveau_run_vbios_init(struct drm_device *);
856 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
858 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
860 extern struct dcb_connector_table_entry *
861 nouveau_bios_connector_entry(struct drm_device *, int index);
862 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
864 extern int nouveau_bios_run_display_table(struct drm_device *,
866 uint32_t script, int pxclk);
867 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
869 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
870 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
871 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
872 bool *dl, bool *if_is_24bit);
873 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
874 int head, int pxclk);
875 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
876 enum LVDS_script, int pxclk);
879 int nouveau_ttm_global_init(struct drm_nouveau_private *);
880 void nouveau_ttm_global_release(struct drm_nouveau_private *);
881 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
884 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
885 uint8_t *data, int data_nr);
886 bool nouveau_dp_detect(struct drm_encoder *);
887 bool nouveau_dp_link_train(struct drm_encoder *);
890 extern int nv04_fb_init(struct drm_device *);
891 extern void nv04_fb_takedown(struct drm_device *);
894 extern int nv10_fb_init(struct drm_device *);
895 extern void nv10_fb_takedown(struct drm_device *);
896 extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
900 extern int nv30_fb_init(struct drm_device *);
901 extern void nv30_fb_takedown(struct drm_device *);
904 extern int nv40_fb_init(struct drm_device *);
905 extern void nv40_fb_takedown(struct drm_device *);
906 extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
910 extern int nv50_fb_init(struct drm_device *);
911 extern void nv50_fb_takedown(struct drm_device *);
914 extern int nvc0_fb_init(struct drm_device *);
915 extern void nvc0_fb_takedown(struct drm_device *);
918 extern int nv04_fifo_init(struct drm_device *);
919 extern void nv04_fifo_disable(struct drm_device *);
920 extern void nv04_fifo_enable(struct drm_device *);
921 extern bool nv04_fifo_reassign(struct drm_device *, bool);
922 extern bool nv04_fifo_cache_flush(struct drm_device *);
923 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
924 extern int nv04_fifo_channel_id(struct drm_device *);
925 extern int nv04_fifo_create_context(struct nouveau_channel *);
926 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
927 extern int nv04_fifo_load_context(struct nouveau_channel *);
928 extern int nv04_fifo_unload_context(struct drm_device *);
931 extern int nv10_fifo_init(struct drm_device *);
932 extern int nv10_fifo_channel_id(struct drm_device *);
933 extern int nv10_fifo_create_context(struct nouveau_channel *);
934 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
935 extern int nv10_fifo_load_context(struct nouveau_channel *);
936 extern int nv10_fifo_unload_context(struct drm_device *);
939 extern int nv40_fifo_init(struct drm_device *);
940 extern int nv40_fifo_create_context(struct nouveau_channel *);
941 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
942 extern int nv40_fifo_load_context(struct nouveau_channel *);
943 extern int nv40_fifo_unload_context(struct drm_device *);
946 extern int nv50_fifo_init(struct drm_device *);
947 extern void nv50_fifo_takedown(struct drm_device *);
948 extern int nv50_fifo_channel_id(struct drm_device *);
949 extern int nv50_fifo_create_context(struct nouveau_channel *);
950 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
951 extern int nv50_fifo_load_context(struct nouveau_channel *);
952 extern int nv50_fifo_unload_context(struct drm_device *);
955 extern int nvc0_fifo_init(struct drm_device *);
956 extern void nvc0_fifo_takedown(struct drm_device *);
957 extern void nvc0_fifo_disable(struct drm_device *);
958 extern void nvc0_fifo_enable(struct drm_device *);
959 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
960 extern bool nvc0_fifo_cache_flush(struct drm_device *);
961 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
962 extern int nvc0_fifo_channel_id(struct drm_device *);
963 extern int nvc0_fifo_create_context(struct nouveau_channel *);
964 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
965 extern int nvc0_fifo_load_context(struct nouveau_channel *);
966 extern int nvc0_fifo_unload_context(struct drm_device *);
969 extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
970 extern int nv04_graph_init(struct drm_device *);
971 extern void nv04_graph_takedown(struct drm_device *);
972 extern void nv04_graph_fifo_access(struct drm_device *, bool);
973 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
974 extern int nv04_graph_create_context(struct nouveau_channel *);
975 extern void nv04_graph_destroy_context(struct nouveau_channel *);
976 extern int nv04_graph_load_context(struct nouveau_channel *);
977 extern int nv04_graph_unload_context(struct drm_device *);
978 extern void nv04_graph_context_switch(struct drm_device *);
981 extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
982 extern int nv10_graph_init(struct drm_device *);
983 extern void nv10_graph_takedown(struct drm_device *);
984 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
985 extern int nv10_graph_create_context(struct nouveau_channel *);
986 extern void nv10_graph_destroy_context(struct nouveau_channel *);
987 extern int nv10_graph_load_context(struct nouveau_channel *);
988 extern int nv10_graph_unload_context(struct drm_device *);
989 extern void nv10_graph_context_switch(struct drm_device *);
990 extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
994 extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
995 extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
996 extern int nv20_graph_create_context(struct nouveau_channel *);
997 extern void nv20_graph_destroy_context(struct nouveau_channel *);
998 extern int nv20_graph_load_context(struct nouveau_channel *);
999 extern int nv20_graph_unload_context(struct drm_device *);
1000 extern int nv20_graph_init(struct drm_device *);
1001 extern void nv20_graph_takedown(struct drm_device *);
1002 extern int nv30_graph_init(struct drm_device *);
1003 extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1004 uint32_t, uint32_t);
1007 extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1008 extern int nv40_graph_init(struct drm_device *);
1009 extern void nv40_graph_takedown(struct drm_device *);
1010 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1011 extern int nv40_graph_create_context(struct nouveau_channel *);
1012 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1013 extern int nv40_graph_load_context(struct nouveau_channel *);
1014 extern int nv40_graph_unload_context(struct drm_device *);
1015 extern void nv40_grctx_init(struct nouveau_grctx *);
1016 extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1017 uint32_t, uint32_t);
1020 extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1021 extern int nv50_graph_init(struct drm_device *);
1022 extern void nv50_graph_takedown(struct drm_device *);
1023 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1024 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1025 extern int nv50_graph_create_context(struct nouveau_channel *);
1026 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1027 extern int nv50_graph_load_context(struct nouveau_channel *);
1028 extern int nv50_graph_unload_context(struct drm_device *);
1029 extern void nv50_graph_context_switch(struct drm_device *);
1030 extern int nv50_grctx_init(struct nouveau_grctx *);
1033 extern int nvc0_graph_init(struct drm_device *);
1034 extern void nvc0_graph_takedown(struct drm_device *);
1035 extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1036 extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1037 extern int nvc0_graph_create_context(struct nouveau_channel *);
1038 extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1039 extern int nvc0_graph_load_context(struct nouveau_channel *);
1040 extern int nvc0_graph_unload_context(struct drm_device *);
1042 /* nv04_instmem.c */
1043 extern int nv04_instmem_init(struct drm_device *);
1044 extern void nv04_instmem_takedown(struct drm_device *);
1045 extern int nv04_instmem_suspend(struct drm_device *);
1046 extern void nv04_instmem_resume(struct drm_device *);
1047 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1049 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1050 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1051 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1052 extern void nv04_instmem_flush(struct drm_device *);
1054 /* nv50_instmem.c */
1055 extern int nv50_instmem_init(struct drm_device *);
1056 extern void nv50_instmem_takedown(struct drm_device *);
1057 extern int nv50_instmem_suspend(struct drm_device *);
1058 extern void nv50_instmem_resume(struct drm_device *);
1059 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1061 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1062 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1063 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1064 extern void nv50_instmem_flush(struct drm_device *);
1065 extern void nv84_instmem_flush(struct drm_device *);
1066 extern void nv50_vm_flush(struct drm_device *, int engine);
1068 /* nvc0_instmem.c */
1069 extern int nvc0_instmem_init(struct drm_device *);
1070 extern void nvc0_instmem_takedown(struct drm_device *);
1071 extern int nvc0_instmem_suspend(struct drm_device *);
1072 extern void nvc0_instmem_resume(struct drm_device *);
1073 extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1075 extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1076 extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1077 extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1078 extern void nvc0_instmem_flush(struct drm_device *);
1081 extern int nv04_mc_init(struct drm_device *);
1082 extern void nv04_mc_takedown(struct drm_device *);
1085 extern int nv40_mc_init(struct drm_device *);
1086 extern void nv40_mc_takedown(struct drm_device *);
1089 extern int nv50_mc_init(struct drm_device *);
1090 extern void nv50_mc_takedown(struct drm_device *);
1093 extern int nv04_timer_init(struct drm_device *);
1094 extern uint64_t nv04_timer_read(struct drm_device *);
1095 extern void nv04_timer_takedown(struct drm_device *);
1097 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1101 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1102 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1103 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1104 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1105 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1108 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1109 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1110 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1112 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1113 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1116 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1117 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1120 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1122 /* nv04_display.c */
1123 extern int nv04_display_early_init(struct drm_device *);
1124 extern void nv04_display_late_takedown(struct drm_device *);
1125 extern int nv04_display_create(struct drm_device *);
1126 extern int nv04_display_init(struct drm_device *);
1127 extern void nv04_display_destroy(struct drm_device *);
1130 extern int nv04_crtc_create(struct drm_device *, int index);
1133 extern struct ttm_bo_driver nouveau_bo_driver;
1134 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1135 int size, int align, uint32_t flags,
1136 uint32_t tile_mode, uint32_t tile_flags,
1137 bool no_vm, bool mappable, struct nouveau_bo **);
1138 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1139 extern int nouveau_bo_unpin(struct nouveau_bo *);
1140 extern int nouveau_bo_map(struct nouveau_bo *);
1141 extern void nouveau_bo_unmap(struct nouveau_bo *);
1142 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1144 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1145 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1146 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1147 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1148 extern int nouveau_bo_sync_gpu(struct nouveau_bo *, struct nouveau_channel *);
1150 /* nouveau_fence.c */
1151 struct nouveau_fence;
1152 extern int nouveau_fence_init(struct nouveau_channel *);
1153 extern void nouveau_fence_fini(struct nouveau_channel *);
1154 extern void nouveau_fence_update(struct nouveau_channel *);
1155 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1157 extern int nouveau_fence_emit(struct nouveau_fence *);
1158 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1159 extern bool nouveau_fence_signalled(void *obj, void *arg);
1160 extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1161 extern int nouveau_fence_flush(void *obj, void *arg);
1162 extern void nouveau_fence_unref(void **obj);
1163 extern void *nouveau_fence_ref(void *obj);
1166 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1167 int size, int align, uint32_t flags,
1168 uint32_t tile_mode, uint32_t tile_flags,
1169 bool no_vm, bool mappable, struct nouveau_bo **);
1170 extern int nouveau_gem_object_new(struct drm_gem_object *);
1171 extern void nouveau_gem_object_del(struct drm_gem_object *);
1172 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1174 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1176 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1178 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1180 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1184 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1185 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1188 int nv50_gpio_init(struct drm_device *dev);
1189 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1190 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1191 void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1194 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1195 int *N1, int *M1, int *N2, int *M2, int *P);
1196 int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1197 int clk, int *N, int *fN, int *M, int *P);
1199 #ifndef ioread32_native
1201 #define ioread16_native ioread16be
1202 #define iowrite16_native iowrite16be
1203 #define ioread32_native ioread32be
1204 #define iowrite32_native iowrite32be
1205 #else /* def __BIG_ENDIAN */
1206 #define ioread16_native ioread16
1207 #define iowrite16_native iowrite16
1208 #define ioread32_native ioread32
1209 #define iowrite32_native iowrite32
1210 #endif /* def __BIG_ENDIAN else */
1211 #endif /* !ioread32_native */
1213 /* channel control reg access */
1214 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1216 return ioread32_native(chan->user + reg);
1219 static inline void nvchan_wr32(struct nouveau_channel *chan,
1220 unsigned reg, u32 val)
1222 iowrite32_native(val, chan->user + reg);
1225 /* register access */
1226 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1228 struct drm_nouveau_private *dev_priv = dev->dev_private;
1229 return ioread32_native(dev_priv->mmio + reg);
1232 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1234 struct drm_nouveau_private *dev_priv = dev->dev_private;
1235 iowrite32_native(val, dev_priv->mmio + reg);
1238 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1240 u32 tmp = nv_rd32(dev, reg);
1241 nv_wr32(dev, reg, (tmp & ~mask) | val);
1245 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1247 struct drm_nouveau_private *dev_priv = dev->dev_private;
1248 return ioread8(dev_priv->mmio + reg);
1251 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1253 struct drm_nouveau_private *dev_priv = dev->dev_private;
1254 iowrite8(val, dev_priv->mmio + reg);
1257 #define nv_wait(reg, mask, val) \
1258 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1261 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1263 struct drm_nouveau_private *dev_priv = dev->dev_private;
1264 return ioread32_native(dev_priv->ramin + offset);
1267 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1269 struct drm_nouveau_private *dev_priv = dev->dev_private;
1270 iowrite32_native(val, dev_priv->ramin + offset);
1274 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1275 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1279 * Argument d is (struct drm_device *).
1281 #define NV_PRINTK(level, d, fmt, arg...) \
1282 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1283 pci_name(d->pdev), ##arg)
1284 #ifndef NV_DEBUG_NOTRACE
1285 #define NV_DEBUG(d, fmt, arg...) do { \
1286 if (drm_debug & DRM_UT_DRIVER) { \
1287 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1291 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1292 if (drm_debug & DRM_UT_KMS) { \
1293 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1298 #define NV_DEBUG(d, fmt, arg...) do { \
1299 if (drm_debug & DRM_UT_DRIVER) \
1300 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1302 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1303 if (drm_debug & DRM_UT_KMS) \
1304 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1307 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1308 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1309 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1310 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1311 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1313 /* nouveau_reg_debug bitmask */
1315 NOUVEAU_REG_DEBUG_MC = 0x1,
1316 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1317 NOUVEAU_REG_DEBUG_FB = 0x4,
1318 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1319 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1320 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1321 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1322 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1323 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1324 NOUVEAU_REG_DEBUG_EVO = 0x200,
1327 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1328 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1329 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1333 nv_two_heads(struct drm_device *dev)
1335 struct drm_nouveau_private *dev_priv = dev->dev_private;
1336 const int impl = dev->pci_device & 0x0ff0;
1338 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1339 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1346 nv_gf4_disp_arch(struct drm_device *dev)
1348 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1352 nv_two_reg_pll(struct drm_device *dev)
1354 struct drm_nouveau_private *dev_priv = dev->dev_private;
1355 const int impl = dev->pci_device & 0x0ff0;
1357 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1363 nv_match_device(struct drm_device *dev, unsigned device,
1364 unsigned sub_vendor, unsigned sub_device)
1366 return dev->pdev->device == device &&
1367 dev->pdev->subsystem_vendor == sub_vendor &&
1368 dev->pdev->subsystem_device == sub_device;
1371 #define NV_SW 0x0000506e
1372 #define NV_SW_DMA_SEMAPHORE 0x00000060
1373 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1374 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1375 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1376 #define NV_SW_DMA_VBLSEM 0x0000018c
1377 #define NV_SW_VBLSEM_OFFSET 0x00000400
1378 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1379 #define NV_SW_VBLSEM_RELEASE 0x00000408
1381 #endif /* __NOUVEAU_DRV_H__ */