2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "nouveau@lists.freedesktop.org"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20120316"
35 #define DRIVER_MAJOR 1
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 0
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 #define XXX_THIS_IS_A_HACK
49 #include <subdev/vm.h>
50 #include <subdev/fb.h>
51 #include <core/gpuobj.h>
54 NV_MEM_TYPE_UNKNOWN = 0,
67 struct nouveau_fpriv {
69 struct list_head channels;
70 struct nouveau_vm *vm;
73 static inline struct nouveau_fpriv *
74 nouveau_fpriv(struct drm_file *file_priv)
76 return file_priv ? file_priv->driver_priv : NULL;
79 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
81 #include <nouveau_drm.h>
82 #include "nouveau_reg.h"
83 #include <nouveau_bios.h>
84 #include "nouveau_util.h"
89 #include <subdev/bios/pll.h>
90 #include "nouveau_compat.h"
92 #define nouveau_gpuobj_new(d,c,s,a,f,o) \
93 _nouveau_gpuobj_new((d), (c) ? ((struct nouveau_channel *)(c))->ramin : NULL, \
96 #define nouveau_vm_new(d,o,l,m,v) \
97 _nouveau_vm_new((d), (o), (l), (m), (v))
99 #define nv50_vm_flush_engine(d,e) \
100 _nv50_vm_flush_engine((d), (e))
102 #define MAX_NUM_DCB_ENTRIES 16
104 #define NOUVEAU_MAX_CHANNEL_NR 4096
105 #define NOUVEAU_MAX_TILE_NR 15
107 #include "nouveau_bo.h"
109 #define nouveau_bo_tile_layout(nvbo) \
110 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
112 static inline struct nouveau_bo *
113 nouveau_gem_object(struct drm_gem_object *gem)
115 return gem ? gem->driver_private : NULL;
118 /* TODO: submit equivalent to TTM generic API upstream? */
119 static inline void __iomem *
120 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
123 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
124 &nvbo->kmap, &is_iomem);
125 WARN_ON_ONCE(ioptr && !is_iomem);
130 NV_NFORCE = 0x10000000,
131 NV_NFORCE2 = 0x20000000
134 #define NVOBJ_ENGINE_SW 0
135 #define NVOBJ_ENGINE_GR 1
136 #define NVOBJ_ENGINE_CRYPT 2
137 #define NVOBJ_ENGINE_COPY0 3
138 #define NVOBJ_ENGINE_COPY1 4
139 #define NVOBJ_ENGINE_MPEG 5
140 #define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG
141 #define NVOBJ_ENGINE_BSP 6
142 #define NVOBJ_ENGINE_VP 7
143 #define NVOBJ_ENGINE_FIFO 14
144 #define NVOBJ_ENGINE_FENCE 15
145 #define NVOBJ_ENGINE_NR 16
146 #define NVOBJ_ENGINE_DISPLAY (NVOBJ_ENGINE_NR + 0) /*XXX*/
148 struct nouveau_page_flip_state {
149 struct list_head head;
150 struct drm_pending_vblank_event *event;
151 int crtc, bpp, pitch, x, y;
155 enum nouveau_channel_mutex_class {
156 NOUVEAU_UCHANNEL_MUTEX,
157 NOUVEAU_KCHANNEL_MUTEX
160 struct nouveau_channel {
161 struct drm_device *dev;
162 struct list_head list;
165 /* references to the channel data structure */
167 /* users of the hardware channel resources, the hardware
168 * context will be kicked off when it reaches zero. */
172 /* owner of this fifo */
173 struct drm_file *file_priv;
174 /* mapping of the fifo itself */
175 struct drm_local_map *map;
177 /* mapping of the regs controlling the fifo */
180 uint32_t user_get_hi;
183 /* DMA push buffer */
184 struct nouveau_gpuobj *pushbuf;
185 struct nouveau_bo *pushbuf_bo;
186 struct nouveau_vma pushbuf_vma;
187 uint64_t pushbuf_base;
189 /* Notifier memory */
190 struct nouveau_bo *notifier_bo;
191 struct nouveau_vma notifier_vma;
192 struct drm_mm notifier_heap;
195 struct nouveau_gpuobj *engptr;
196 struct nouveau_gpuobj *ramfc;
198 /* Execution engine contexts */
199 void *engctx[NVOBJ_ENGINE_NR];
202 struct nouveau_vm *vm;
203 struct nouveau_gpuobj *vm_pd;
206 struct nouveau_gpuobj *ramin; /* Private instmem */
207 struct nouveau_ramht *ramht; /* Hash table */
209 /* GPU object info for stuff used in-kernel (mm_enabled) */
211 uint32_t vram_handle;
212 uint32_t gart_handle;
215 /* Push buffer state (only for drm's channel on !mm_enabled) */
221 /* access via pushbuf_bo */
232 struct drm_info_list info;
236 struct nouveau_exec_engine {
237 void (*destroy)(struct drm_device *, int engine);
238 int (*init)(struct drm_device *, int engine);
239 int (*fini)(struct drm_device *, int engine, bool suspend);
240 int (*context_new)(struct nouveau_channel *, int engine);
241 void (*context_del)(struct nouveau_channel *, int engine);
242 int (*object_new)(struct nouveau_channel *, int engine,
243 u32 handle, u16 class);
244 void (*set_tile_region)(struct drm_device *dev, int i);
245 void (*tlb_flush)(struct drm_device *, int engine);
248 struct nouveau_display_engine {
250 int (*early_init)(struct drm_device *);
251 void (*late_takedown)(struct drm_device *);
252 int (*create)(struct drm_device *);
253 void (*destroy)(struct drm_device *);
254 int (*init)(struct drm_device *);
255 void (*fini)(struct drm_device *);
257 struct drm_property *dithering_mode;
258 struct drm_property *dithering_depth;
259 struct drm_property *underscan_property;
260 struct drm_property *underscan_hborder_property;
261 struct drm_property *underscan_vborder_property;
262 /* not really hue and saturation: */
263 struct drm_property *vibrant_hue_property;
264 struct drm_property *color_vibrance_property;
267 struct nouveau_pm_voltage_level {
268 u32 voltage; /* microvolts */
272 struct nouveau_pm_voltage {
277 struct nouveau_pm_voltage_level *level;
281 /* Exclusive upper limits */
282 #define NV_MEM_CL_DDR2_MAX 8
283 #define NV_MEM_WR_DDR2_MAX 9
284 #define NV_MEM_CL_DDR3_MAX 17
285 #define NV_MEM_WR_DDR3_MAX 17
286 #define NV_MEM_CL_GDDR3_MAX 16
287 #define NV_MEM_WR_GDDR3_MAX 18
288 #define NV_MEM_CL_GDDR5_MAX 21
289 #define NV_MEM_WR_GDDR5_MAX 20
291 struct nouveau_pm_memtiming {
303 struct nouveau_pm_tbl_header {
310 struct nouveau_pm_tbl_entry {
316 u8 tRFC; /* Byte 5 */
318 u8 tRAS; /* Byte 7 */
325 u8 RAM_FT1; /* 14, a bitmask of random RAM features */
334 struct nouveau_pm_profile;
335 struct nouveau_pm_profile_func {
336 void (*destroy)(struct nouveau_pm_profile *);
337 void (*init)(struct nouveau_pm_profile *);
338 void (*fini)(struct nouveau_pm_profile *);
339 struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *);
342 struct nouveau_pm_profile {
343 const struct nouveau_pm_profile_func *func;
344 struct list_head head;
348 #define NOUVEAU_PM_MAX_LEVEL 8
349 struct nouveau_pm_level {
350 struct nouveau_pm_profile profile;
351 struct device_attribute dev_attr;
355 struct nouveau_pm_memtiming timing;
366 u32 unka0; /* nva3:nvc0 */
367 u32 hub01; /* nvc0- */
368 u32 hub06; /* nvc0- */
369 u32 hub07; /* nvc0- */
371 u32 volt_min; /* microvolts */
376 struct nouveau_pm_temp_sensor_constants {
384 struct nouveau_pm_threshold_temp {
390 struct nouveau_pm_fan {
398 struct nouveau_pm_engine {
399 struct nouveau_pm_voltage voltage;
400 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
402 struct nouveau_pm_temp_sensor_constants sensor_constants;
403 struct nouveau_pm_threshold_temp threshold_temp;
404 struct nouveau_pm_fan fan;
406 struct nouveau_pm_profile *profile_ac;
407 struct nouveau_pm_profile *profile_dc;
408 struct nouveau_pm_profile *profile;
409 struct list_head profiles;
411 struct nouveau_pm_level boot;
412 struct nouveau_pm_level *cur;
414 struct device *hwmon;
415 struct notifier_block acpi_nb;
417 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
418 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
419 int (*clocks_set)(struct drm_device *, void *);
421 int (*voltage_get)(struct drm_device *);
422 int (*voltage_set)(struct drm_device *, int voltage);
423 int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
424 int (*pwm_set)(struct drm_device *, int line, u32, u32);
425 int (*temp_get)(struct drm_device *);
428 struct nouveau_engine {
429 struct nouveau_display_engine display;
430 struct nouveau_pm_engine pm;
433 enum nouveau_card_type {
445 struct drm_nouveau_private {
446 struct drm_device *dev;
451 /* the card type, takes NV_* as values */
452 enum nouveau_card_type card_type;
453 /* exact chipset, derived from NV_PMC_BOOT_0 */
458 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR];
459 struct list_head classes;
461 struct nouveau_bo *vga_ram;
463 /* interrupt handling */
464 void (*irq_handler[32])(struct drm_device *);
468 struct drm_global_reference mem_global_ref;
469 struct ttm_bo_global_ref bo_global_ref;
470 struct ttm_bo_device bdev;
471 atomic_t validate_sequence;
472 int (*move)(struct nouveau_channel *,
473 struct ttm_buffer_object *,
474 struct ttm_mem_reg *, struct ttm_mem_reg *);
480 struct nouveau_bo *bo;
485 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
488 struct nouveau_engine engine;
489 struct nouveau_channel *channel;
491 /* For PFIFO and PGRAPH. */
492 spinlock_t context_switch_lock;
494 /* VM/PRAMIN flush, legacy PRAMIN aperture */
497 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
498 struct nouveau_ramht *ramht;
502 NOUVEAU_GART_NONE = 0,
503 NOUVEAU_GART_AGP, /* AGP */
504 NOUVEAU_GART_PDMA, /* paged dma object */
505 NOUVEAU_GART_HW /* on-chip gart/vm */
511 struct ttm_backend_func *func;
513 struct nouveau_gpuobj *sg_ctxdma;
516 /* nv10-nv40 tiling regions */
518 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
522 uint64_t fb_available_size;
523 uint64_t fb_mappable_pages;
524 uint64_t fb_aper_free;
527 /* G8x/G9x virtual address space */
528 struct nouveau_vm *chan_vm;
532 struct list_head i2c_ports;
534 struct backlight_device *backlight;
537 struct dentry *channel_root;
540 struct nouveau_fbdev *nfbdev;
541 struct apertures_struct *apertures;
544 static inline struct drm_nouveau_private *
545 nouveau_private(struct drm_device *dev)
547 return dev->dev_private;
550 static inline struct drm_nouveau_private *
551 nouveau_bdev(struct ttm_bo_device *bd)
553 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
557 extern int nouveau_modeset;
558 extern int nouveau_duallink;
559 extern int nouveau_uscript_lvds;
560 extern int nouveau_uscript_tmds;
561 extern int nouveau_vram_pushbuf;
562 extern int nouveau_vram_notify;
563 extern char *nouveau_vram_type;
564 extern int nouveau_fbpercrtc;
565 extern int nouveau_tv_disable;
566 extern char *nouveau_tv_norm;
567 extern int nouveau_reg_debug;
568 extern int nouveau_ignorelid;
569 extern int nouveau_nofbaccel;
570 extern int nouveau_noaccel;
571 extern int nouveau_force_post;
572 extern int nouveau_override_conntype;
573 extern char *nouveau_perflvl;
574 extern int nouveau_perflvl_wr;
575 extern int nouveau_msi;
576 extern int nouveau_ctxfw;
577 extern int nouveau_mxmdcb;
579 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
580 extern int nouveau_pci_resume(struct pci_dev *pdev);
582 /* nouveau_state.c */
583 extern int nouveau_open(struct drm_device *, struct drm_file *);
584 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
585 extern void nouveau_postclose(struct drm_device *, struct drm_file *);
586 extern int nouveau_load(struct drm_device *, unsigned long flags);
587 extern int nouveau_firstopen(struct drm_device *);
588 extern void nouveau_lastclose(struct drm_device *);
589 extern int nouveau_unload(struct drm_device *);
590 extern bool nouveau_wait_for_idle(struct drm_device *);
591 extern int nouveau_card_init(struct drm_device *);
594 extern int nouveau_mem_vram_init(struct drm_device *);
595 extern void nouveau_mem_vram_fini(struct drm_device *);
596 extern int nouveau_mem_gart_init(struct drm_device *);
597 extern void nouveau_mem_gart_fini(struct drm_device *);
598 extern void nouveau_mem_close(struct drm_device *);
599 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
600 extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq,
601 struct nouveau_pm_memtiming *);
602 extern void nouveau_mem_timing_read(struct drm_device *,
603 struct nouveau_pm_memtiming *);
604 extern int nouveau_mem_vbios_type(struct drm_device *);
605 extern struct nouveau_tile_reg *nv10_mem_set_tiling(
606 struct drm_device *dev, uint32_t addr, uint32_t size,
607 uint32_t pitch, uint32_t flags);
608 extern void nv10_mem_put_tile_region(struct drm_device *dev,
609 struct nouveau_tile_reg *tile,
610 struct nouveau_fence *fence);
611 extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
612 extern const struct ttm_mem_type_manager_func nouveau_gart_manager;
613 extern const struct ttm_mem_type_manager_func nv04_gart_manager;
615 /* nouveau_notifier.c */
616 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
617 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
618 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
619 int cout, uint32_t start, uint32_t end,
622 /* nouveau_channel.c */
623 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
624 extern int nouveau_channel_alloc(struct drm_device *dev,
625 struct nouveau_channel **chan,
626 struct drm_file *file_priv,
627 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
628 extern struct nouveau_channel *
629 nouveau_channel_get_unlocked(struct nouveau_channel *);
630 extern struct nouveau_channel *
631 nouveau_channel_get(struct drm_file *, int id);
632 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
633 extern void nouveau_channel_put(struct nouveau_channel **);
634 extern void nouveau_channel_ref(struct nouveau_channel *chan,
635 struct nouveau_channel **pchan);
636 extern int nouveau_channel_idle(struct nouveau_channel *chan);
638 /* nouveau_gpuobj.c */
639 #define NVOBJ_ENGINE_ADD(d, e, p) do { \
640 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
641 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \
644 #define NVOBJ_ENGINE_DEL(d, e) do { \
645 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
646 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \
649 #define NVOBJ_CLASS(d, c, e) do { \
650 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
655 #define NVOBJ_MTHD(d, c, m, e) do { \
656 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
661 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
662 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
663 int (*exec)(struct nouveau_channel *,
664 u32 class, u32 mthd, u32 data));
665 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
666 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
667 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
668 uint32_t vram_h, uint32_t tt_h);
669 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
670 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
671 uint64_t offset, uint64_t size, int access,
672 int target, struct nouveau_gpuobj **);
673 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
674 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
675 u64 size, int target, int access, u32 type,
676 u32 comp, struct nouveau_gpuobj **pobj);
677 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
678 int class, u64 base, u64 size, int target,
679 int access, u32 type, u32 comp);
681 int nouveau_gpuobj_map_vm(struct nouveau_gpuobj *gpuobj, struct nouveau_vm *vm,
682 u32 flags, struct nouveau_vma *vma);
683 void nouveau_gpuobj_unmap(struct nouveau_vma *vma);
686 extern int nouveau_irq_init(struct drm_device *);
687 extern void nouveau_irq_fini(struct drm_device *);
688 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
689 extern void nouveau_irq_register(struct drm_device *, int status_bit,
690 void (*)(struct drm_device *));
691 extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
692 extern void nouveau_irq_preinstall(struct drm_device *);
693 extern int nouveau_irq_postinstall(struct drm_device *);
694 extern void nouveau_irq_uninstall(struct drm_device *);
696 /* nouveau_sgdma.c */
697 extern int nouveau_sgdma_init(struct drm_device *);
698 extern void nouveau_sgdma_takedown(struct drm_device *);
699 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
701 extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev,
704 struct page *dummy_read_page);
706 /* nouveau_debugfs.c */
707 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
708 extern int nouveau_debugfs_init(struct drm_minor *);
709 extern void nouveau_debugfs_takedown(struct drm_minor *);
710 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
711 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
714 nouveau_debugfs_init(struct drm_minor *minor)
719 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
724 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
730 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
736 extern void nouveau_dma_init(struct nouveau_channel *);
737 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
740 #define ROM_BIOS_PAGE 4096
741 #if defined(CONFIG_ACPI)
742 void nouveau_register_dsm_handler(void);
743 void nouveau_unregister_dsm_handler(void);
744 void nouveau_switcheroo_optimus_dsm(void);
745 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
746 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
747 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
749 static inline void nouveau_register_dsm_handler(void) {}
750 static inline void nouveau_unregister_dsm_handler(void) {}
751 static inline void nouveau_switcheroo_optimus_dsm(void) {}
752 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
753 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
754 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
757 /* nouveau_backlight.c */
758 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
759 extern int nouveau_backlight_init(struct drm_device *);
760 extern void nouveau_backlight_exit(struct drm_device *);
762 static inline int nouveau_backlight_init(struct drm_device *dev)
767 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
771 extern int nouveau_bios_init(struct drm_device *);
772 extern void nouveau_bios_takedown(struct drm_device *dev);
773 extern int nouveau_run_vbios_init(struct drm_device *);
774 extern struct dcb_connector_table_entry *
775 nouveau_bios_connector_entry(struct drm_device *, int index);
776 extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
777 struct dcb_output *, int crtc);
778 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
779 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
780 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
781 bool *dl, bool *if_is_24bit);
782 extern int run_tmds_table(struct drm_device *, struct dcb_output *,
783 int head, int pxclk);
784 extern int call_lvds_script(struct drm_device *, struct dcb_output *, int head,
785 enum LVDS_script, int pxclk);
786 bool bios_encoder_match(struct dcb_output *, u32 hash);
789 int nouveau_mxm_init(struct drm_device *dev);
790 void nouveau_mxm_fini(struct drm_device *dev);
793 int nouveau_ttm_global_init(struct drm_nouveau_private *);
794 void nouveau_ttm_global_release(struct drm_nouveau_private *);
795 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
798 void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
801 extern int nv04_graph_create(struct drm_device *);
802 extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16);
803 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
804 u32 class, u32 mthd, u32 data);
805 extern struct nouveau_bitfield nv04_graph_nsource[];
808 extern int nv10_graph_create(struct drm_device *);
809 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
810 extern struct nouveau_bitfield nv10_graph_intr[];
811 extern struct nouveau_bitfield nv10_graph_nstatus[];
814 extern int nv20_graph_create(struct drm_device *);
817 extern int nv40_graph_create(struct drm_device *);
818 extern void nv40_grctx_init(struct drm_device *, u32 *size);
819 extern void nv40_grctx_fill(struct drm_device *, struct nouveau_gpuobj *);
822 extern int nv50_graph_create(struct drm_device *);
823 extern struct nouveau_enum nv50_data_error_names[];
824 extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst);
825 extern int nv50_grctx_init(struct drm_device *, u32 *, u32, u32 *, u32 *);
826 extern void nv50_grctx_fill(struct drm_device *, struct nouveau_gpuobj *);
829 extern int nvc0_graph_create(struct drm_device *);
830 extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst);
833 extern int nve0_graph_create(struct drm_device *);
836 extern int nv84_crypt_create(struct drm_device *);
839 extern int nv98_crypt_create(struct drm_device *dev);
842 extern int nva3_copy_create(struct drm_device *dev);
845 extern int nvc0_copy_create(struct drm_device *dev, int engine);
848 extern int nv31_mpeg_create(struct drm_device *dev);
851 extern int nv50_mpeg_create(struct drm_device *dev);
855 extern int nv84_bsp_create(struct drm_device *dev);
859 extern int nv84_vp_create(struct drm_device *dev);
862 extern int nv98_ppp_create(struct drm_device *dev);
864 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
868 extern int nvd0_display_create(struct drm_device *);
869 extern void nvd0_display_destroy(struct drm_device *);
870 extern int nvd0_display_init(struct drm_device *);
871 extern void nvd0_display_fini(struct drm_device *);
872 struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc);
873 void nvd0_display_flip_stop(struct drm_crtc *);
874 int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
875 struct nouveau_channel *, u32 swap_interval);
878 extern int nouveau_gem_new(struct drm_device *, int size, int align,
879 uint32_t domain, uint32_t tile_mode,
880 uint32_t tile_flags, struct nouveau_bo **);
881 extern int nouveau_gem_object_new(struct drm_gem_object *);
882 extern void nouveau_gem_object_del(struct drm_gem_object *);
883 extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *);
884 extern void nouveau_gem_object_close(struct drm_gem_object *,
886 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
888 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
890 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
892 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
894 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
897 extern struct dma_buf *nouveau_gem_prime_export(struct drm_device *dev,
898 struct drm_gem_object *obj, int flags);
899 extern struct drm_gem_object *nouveau_gem_prime_import(struct drm_device *dev,
900 struct dma_buf *dma_buf);
902 /* nouveau_display.c */
903 int nouveau_display_create(struct drm_device *dev);
904 void nouveau_display_destroy(struct drm_device *dev);
905 int nouveau_display_init(struct drm_device *dev);
906 void nouveau_display_fini(struct drm_device *dev);
907 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
908 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
909 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
910 struct drm_pending_vblank_event *event);
911 int nouveau_finish_page_flip(struct nouveau_channel *,
912 struct nouveau_page_flip_state *);
913 int nouveau_display_dumb_create(struct drm_file *, struct drm_device *,
914 struct drm_mode_create_dumb *args);
915 int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *,
916 uint32_t handle, uint64_t *offset);
917 int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *,
920 #ifndef ioread32_native
922 #define ioread16_native ioread16be
923 #define iowrite16_native iowrite16be
924 #define ioread32_native ioread32be
925 #define iowrite32_native iowrite32be
926 #else /* def __BIG_ENDIAN */
927 #define ioread16_native ioread16
928 #define iowrite16_native iowrite16
929 #define ioread32_native ioread32
930 #define iowrite32_native iowrite32
931 #endif /* def __BIG_ENDIAN else */
932 #endif /* !ioread32_native */
934 /* channel control reg access */
935 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
937 return ioread32_native(chan->user + reg);
940 static inline void nvchan_wr32(struct nouveau_channel *chan,
941 unsigned reg, u32 val)
943 iowrite32_native(val, chan->user + reg);
946 /* register access */
947 #define nv_rd08 _nv_rd08
948 #define nv_wr08 _nv_wr08
949 #define nv_rd32 _nv_rd32
950 #define nv_wr32 _nv_wr32
951 #define nv_mask _nv_mask
953 #define nv_wait(dev, reg, mask, val) \
954 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
955 #define nv_wait_ne(dev, reg, mask, val) \
956 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
957 #define nv_wait_cb(dev, func, data) \
958 nouveau_wait_cb(dev, 2000000000ULL, (func), (data))
962 * Argument d is (struct drm_device *).
964 #define NV_PRINTK(level, d, fmt, arg...) \
965 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
966 pci_name(d->pdev), ##arg)
967 #ifndef NV_DEBUG_NOTRACE
968 #define NV_DEBUG(d, fmt, arg...) do { \
969 if (drm_debug & DRM_UT_DRIVER) { \
970 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
974 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
975 if (drm_debug & DRM_UT_KMS) { \
976 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
981 #define NV_DEBUG(d, fmt, arg...) do { \
982 if (drm_debug & DRM_UT_DRIVER) \
983 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
985 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
986 if (drm_debug & DRM_UT_KMS) \
987 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
990 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
991 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
992 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
993 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
994 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
995 #define NV_WARNONCE(d, fmt, arg...) do { \
996 static int _warned = 0; \
998 NV_WARN(d, fmt, ##arg); \
1003 /* nouveau_reg_debug bitmask */
1005 NOUVEAU_REG_DEBUG_MC = 0x1,
1006 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1007 NOUVEAU_REG_DEBUG_FB = 0x4,
1008 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1009 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1010 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1011 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1012 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1013 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1014 NOUVEAU_REG_DEBUG_EVO = 0x200,
1015 NOUVEAU_REG_DEBUG_AUXCH = 0x400
1018 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1019 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1020 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1024 nv_two_heads(struct drm_device *dev)
1026 struct drm_nouveau_private *dev_priv = dev->dev_private;
1027 const int impl = dev->pci_device & 0x0ff0;
1029 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1030 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1037 nv_gf4_disp_arch(struct drm_device *dev)
1039 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1043 nv_two_reg_pll(struct drm_device *dev)
1045 struct drm_nouveau_private *dev_priv = dev->dev_private;
1046 const int impl = dev->pci_device & 0x0ff0;
1048 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1054 nv_match_device(struct drm_device *dev, unsigned device,
1055 unsigned sub_vendor, unsigned sub_device)
1057 return dev->pdev->device == device &&
1058 dev->pdev->subsystem_vendor == sub_vendor &&
1059 dev->pdev->subsystem_device == sub_device;
1062 static inline void *
1063 nv_engine(struct drm_device *dev, int engine)
1065 struct drm_nouveau_private *dev_priv = dev->dev_private;
1066 return (void *)dev_priv->eng[engine];
1069 /* returns 1 if device is one of the nv4x using the 0x4497 object class,
1070 * helpful to determine a number of other hardware features
1073 nv44_graph_class(struct drm_device *dev)
1075 struct drm_nouveau_private *dev_priv = dev->dev_private;
1077 if ((dev_priv->chipset & 0xf0) == 0x60)
1080 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
1083 /* memory type/access flags, do not match hardware values */
1084 #define NV_MEM_ACCESS_RO 1
1085 #define NV_MEM_ACCESS_WO 2
1086 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
1087 #define NV_MEM_ACCESS_SYS 4
1088 #define NV_MEM_ACCESS_VM 8
1089 #define NV_MEM_ACCESS_NOSNOOP 16
1091 #define NV_MEM_TARGET_VRAM 0
1092 #define NV_MEM_TARGET_PCI 1
1093 #define NV_MEM_TARGET_PCI_NOSNOOP 2
1094 #define NV_MEM_TARGET_VM 3
1095 #define NV_MEM_TARGET_GART 4
1097 #define NV_MEM_TYPE_VM 0x7f
1098 #define NV_MEM_COMP_VM 0x03
1101 #define NV01_SUBCHAN_OBJECT 0x00000000
1102 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010
1103 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014
1104 #define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018
1105 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c
1106 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001
1107 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002
1108 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004
1109 #define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000
1110 #define NV84_SUBCHAN_NOTIFY_INTR 0x00000020
1111 #define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024
1112 #define NV10_SUBCHAN_REF_CNT 0x00000050
1113 #define NVSW_SUBCHAN_PAGE_FLIP 0x00000054
1114 #define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
1115 #define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
1116 #define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
1117 #define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c
1118 #define NV40_SUBCHAN_YIELD 0x00000080
1120 /* NV_SW object class */
1121 #define NV_SW 0x0000506e
1122 #define NV_SW_DMA_VBLSEM 0x0000018c
1123 #define NV_SW_VBLSEM_OFFSET 0x00000400
1124 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1125 #define NV_SW_VBLSEM_RELEASE 0x00000408
1126 #define NV_SW_PAGE_FLIP 0x00000500
1128 #endif /* __NOUVEAU_DRV_H__ */