2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/delay.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/vga_switcheroo.h>
30 #include <linux/mmu_notifier.h>
31 #include <linux/dynamic_debug.h>
33 #include <drm/drm_aperture.h>
34 #include <drm/drm_drv.h>
35 #include <drm/drm_fbdev_generic.h>
36 #include <drm/drm_gem_ttm_helper.h>
37 #include <drm/drm_ioctl.h>
38 #include <drm/drm_vblank.h>
40 #include <core/gpuobj.h>
41 #include <core/option.h>
43 #include <core/tegra.h>
45 #include <nvif/driver.h>
46 #include <nvif/fifo.h>
47 #include <nvif/push006c.h>
48 #include <nvif/user.h>
50 #include <nvif/class.h>
51 #include <nvif/cl0002.h>
53 #include "nouveau_drv.h"
54 #include "nouveau_dma.h"
55 #include "nouveau_ttm.h"
56 #include "nouveau_gem.h"
57 #include "nouveau_vga.h"
58 #include "nouveau_led.h"
59 #include "nouveau_hwmon.h"
60 #include "nouveau_acpi.h"
61 #include "nouveau_bios.h"
62 #include "nouveau_ioctl.h"
63 #include "nouveau_abi16.h"
64 #include "nouveau_fence.h"
65 #include "nouveau_debugfs.h"
66 #include "nouveau_usif.h"
67 #include "nouveau_connector.h"
68 #include "nouveau_platform.h"
69 #include "nouveau_svm.h"
70 #include "nouveau_dmem.h"
72 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
84 MODULE_PARM_DESC(config, "option string to pass to driver core");
85 static char *nouveau_config;
86 module_param_named(config, nouveau_config, charp, 0400);
88 MODULE_PARM_DESC(debug, "debug string to pass to driver core");
89 static char *nouveau_debug;
90 module_param_named(debug, nouveau_debug, charp, 0400);
92 MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
93 static int nouveau_noaccel = 0;
94 module_param_named(noaccel, nouveau_noaccel, int, 0400);
96 MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
97 "0 = disabled, 1 = enabled, 2 = headless)");
98 int nouveau_modeset = -1;
99 module_param_named(modeset, nouveau_modeset, int, 0400);
101 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
102 static int nouveau_atomic = 0;
103 module_param_named(atomic, nouveau_atomic, int, 0400);
105 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
106 static int nouveau_runtime_pm = -1;
107 module_param_named(runpm, nouveau_runtime_pm, int, 0400);
109 static struct drm_driver driver_stub;
110 static struct drm_driver driver_pci;
111 static struct drm_driver driver_platform;
114 nouveau_pci_name(struct pci_dev *pdev)
116 u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
117 name |= pdev->bus->number << 16;
118 name |= PCI_SLOT(pdev->devfn) << 8;
119 return name | PCI_FUNC(pdev->devfn);
123 nouveau_platform_name(struct platform_device *platformdev)
125 return platformdev->id;
129 nouveau_name(struct drm_device *dev)
131 if (dev_is_pci(dev->dev))
132 return nouveau_pci_name(to_pci_dev(dev->dev));
134 return nouveau_platform_name(to_platform_device(dev->dev));
138 nouveau_cli_work_ready(struct dma_fence *fence)
142 spin_lock_irq(fence->lock);
143 if (!dma_fence_is_signaled_locked(fence))
145 spin_unlock_irq(fence->lock);
148 dma_fence_put(fence);
153 nouveau_cli_work(struct work_struct *w)
155 struct nouveau_cli *cli = container_of(w, typeof(*cli), work);
156 struct nouveau_cli_work *work, *wtmp;
157 mutex_lock(&cli->lock);
158 list_for_each_entry_safe(work, wtmp, &cli->worker, head) {
159 if (!work->fence || nouveau_cli_work_ready(work->fence)) {
160 list_del(&work->head);
164 mutex_unlock(&cli->lock);
168 nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb)
170 struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb);
171 schedule_work(&work->cli->work);
175 nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence,
176 struct nouveau_cli_work *work)
178 work->fence = dma_fence_get(fence);
180 mutex_lock(&cli->lock);
181 list_add_tail(&work->head, &cli->worker);
182 if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence))
183 nouveau_cli_work_fence(fence, &work->cb);
184 mutex_unlock(&cli->lock);
188 nouveau_cli_fini(struct nouveau_cli *cli)
190 /* All our channels are dead now, which means all the fences they
191 * own are signalled, and all callback functions have been called.
193 * So, after flushing the workqueue, there should be nothing left.
195 flush_work(&cli->work);
196 WARN_ON(!list_empty(&cli->worker));
198 usif_client_fini(cli);
199 nouveau_vmm_fini(&cli->svm);
200 nouveau_vmm_fini(&cli->vmm);
201 nvif_mmu_dtor(&cli->mmu);
202 nvif_device_dtor(&cli->device);
203 mutex_lock(&cli->drm->master.lock);
204 nvif_client_dtor(&cli->base);
205 mutex_unlock(&cli->drm->master.lock);
209 nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
210 struct nouveau_cli *cli)
212 static const struct nvif_mclass
214 { NVIF_CLASS_MEM_GF100, -1 },
215 { NVIF_CLASS_MEM_NV50 , -1 },
216 { NVIF_CLASS_MEM_NV04 , -1 },
219 static const struct nvif_mclass
221 { NVIF_CLASS_MMU_GF100, -1 },
222 { NVIF_CLASS_MMU_NV50 , -1 },
223 { NVIF_CLASS_MMU_NV04 , -1 },
226 static const struct nvif_mclass
228 { NVIF_CLASS_VMM_GP100, -1 },
229 { NVIF_CLASS_VMM_GM200, -1 },
230 { NVIF_CLASS_VMM_GF100, -1 },
231 { NVIF_CLASS_VMM_NV50 , -1 },
232 { NVIF_CLASS_VMM_NV04 , -1 },
235 u64 device = nouveau_name(drm->dev);
238 snprintf(cli->name, sizeof(cli->name), "%s", sname);
240 mutex_init(&cli->mutex);
241 usif_client_init(cli);
243 INIT_WORK(&cli->work, nouveau_cli_work);
244 INIT_LIST_HEAD(&cli->worker);
245 mutex_init(&cli->lock);
247 if (cli == &drm->master) {
248 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug,
249 cli->name, device, &cli->base);
251 mutex_lock(&drm->master.lock);
252 ret = nvif_client_ctor(&drm->master.base, cli->name, device,
254 mutex_unlock(&drm->master.lock);
257 NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret);
261 ret = nvif_device_ctor(&cli->base.object, "drmDevice", 0, NV_DEVICE,
262 &(struct nv_device_v0) {
265 }, sizeof(struct nv_device_v0),
268 NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret);
272 ret = nvif_mclass(&cli->device.object, mmus);
274 NV_PRINTK(err, cli, "No supported MMU class\n");
278 ret = nvif_mmu_ctor(&cli->device.object, "drmMmu", mmus[ret].oclass,
281 NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret);
285 ret = nvif_mclass(&cli->mmu.object, vmms);
287 NV_PRINTK(err, cli, "No supported VMM class\n");
291 ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm);
293 NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret);
297 ret = nvif_mclass(&cli->mmu.object, mems);
299 NV_PRINTK(err, cli, "No supported MEM class\n");
303 cli->mem = &mems[ret];
307 nouveau_cli_fini(cli);
312 nouveau_accel_ce_fini(struct nouveau_drm *drm)
314 nouveau_channel_idle(drm->cechan);
315 nvif_object_dtor(&drm->ttm.copy);
316 nouveau_channel_del(&drm->cechan);
320 nouveau_accel_ce_init(struct nouveau_drm *drm)
322 struct nvif_device *device = &drm->client.device;
326 /* Allocate channel that has access to a (preferably async) copy
327 * engine, to use for TTM buffer moves.
329 runm = nvif_fifo_runlist_ce(device);
331 NV_DEBUG(drm, "no ce runlist\n");
335 ret = nouveau_channel_new(drm, device, false, runm, NvDmaFB, NvDmaTT, &drm->cechan);
337 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
341 nouveau_accel_gr_fini(struct nouveau_drm *drm)
343 nouveau_channel_idle(drm->channel);
344 nvif_object_dtor(&drm->ntfy);
345 nvkm_gpuobj_del(&drm->notify);
346 nouveau_channel_del(&drm->channel);
350 nouveau_accel_gr_init(struct nouveau_drm *drm)
352 struct nvif_device *device = &drm->client.device;
356 /* Allocate channel that has access to the graphics engine. */
357 runm = nvif_fifo_runlist(device, NV_DEVICE_HOST_RUNLIST_ENGINES_GR);
359 NV_DEBUG(drm, "no gr runlist\n");
363 ret = nouveau_channel_new(drm, device, false, runm, NvDmaFB, NvDmaTT, &drm->channel);
365 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
366 nouveau_accel_gr_fini(drm);
370 /* A SW class is used on pre-NV50 HW to assist with handling the
371 * synchronisation of page flips, as well as to implement fences
372 * on TNT/TNT2 HW that lacks any kind of support in host.
374 if (!drm->channel->nvsw.client && device->info.family < NV_DEVICE_INFO_V0_TESLA) {
375 ret = nvif_object_ctor(&drm->channel->user, "drmNvsw",
376 NVDRM_NVSW, nouveau_abi16_swclass(drm),
377 NULL, 0, &drm->channel->nvsw);
379 if (ret == 0 && device->info.chipset >= 0x11) {
380 ret = nvif_object_ctor(&drm->channel->user, "drmBlit",
382 NULL, 0, &drm->channel->blit);
386 struct nvif_push *push = drm->channel->chan.push;
387 ret = PUSH_WAIT(push, 8);
389 if (device->info.chipset >= 0x11) {
390 PUSH_NVSQ(push, NV05F, 0x0000, drm->channel->blit.handle);
391 PUSH_NVSQ(push, NV09F, 0x0120, 0,
395 PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle);
400 NV_ERROR(drm, "failed to allocate sw or blit class, %d\n", ret);
401 nouveau_accel_gr_fini(drm);
406 /* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason,
407 * even if notification is never requested, so, allocate a ctxdma on
408 * any GPU where it's possible we'll end up using M2MF for BO moves.
410 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
411 ret = nvkm_gpuobj_new(nvxx_device(device), 32, 0, false, NULL,
414 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
415 nouveau_accel_gr_fini(drm);
419 ret = nvif_object_ctor(&drm->channel->user, "drmM2mfNtfy",
420 NvNotify0, NV_DMA_IN_MEMORY,
421 &(struct nv_dma_v0) {
422 .target = NV_DMA_V0_TARGET_VRAM,
423 .access = NV_DMA_V0_ACCESS_RDWR,
424 .start = drm->notify->addr,
425 .limit = drm->notify->addr + 31
426 }, sizeof(struct nv_dma_v0),
429 nouveau_accel_gr_fini(drm);
436 nouveau_accel_fini(struct nouveau_drm *drm)
438 nouveau_accel_ce_fini(drm);
439 nouveau_accel_gr_fini(drm);
441 nouveau_fence(drm)->dtor(drm);
442 nouveau_channels_fini(drm);
446 nouveau_accel_init(struct nouveau_drm *drm)
448 struct nvif_device *device = &drm->client.device;
449 struct nvif_sclass *sclass;
455 /* Initialise global support for channels, and synchronisation. */
456 ret = nouveau_channels_init(drm);
460 /*XXX: this is crap, but the fence/channel stuff is a little
461 * backwards in some places. this will be fixed.
463 ret = n = nvif_object_sclass_get(&device->object, &sclass);
467 for (ret = -ENOSYS, i = 0; i < n; i++) {
468 switch (sclass[i].oclass) {
469 case NV03_CHANNEL_DMA:
470 ret = nv04_fence_create(drm);
472 case NV10_CHANNEL_DMA:
473 ret = nv10_fence_create(drm);
475 case NV17_CHANNEL_DMA:
476 case NV40_CHANNEL_DMA:
477 ret = nv17_fence_create(drm);
479 case NV50_CHANNEL_GPFIFO:
480 ret = nv50_fence_create(drm);
482 case G82_CHANNEL_GPFIFO:
483 ret = nv84_fence_create(drm);
485 case FERMI_CHANNEL_GPFIFO:
486 case KEPLER_CHANNEL_GPFIFO_A:
487 case KEPLER_CHANNEL_GPFIFO_B:
488 case MAXWELL_CHANNEL_GPFIFO_A:
489 case PASCAL_CHANNEL_GPFIFO_A:
490 case VOLTA_CHANNEL_GPFIFO_A:
491 case TURING_CHANNEL_GPFIFO_A:
492 case AMPERE_CHANNEL_GPFIFO_A:
493 case AMPERE_CHANNEL_GPFIFO_B:
494 ret = nvc0_fence_create(drm);
501 nvif_object_sclass_put(&sclass);
503 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
504 nouveau_accel_fini(drm);
508 /* Volta requires access to a doorbell register for kickoff. */
509 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) {
510 ret = nvif_user_ctor(device, "drmUsermode");
515 /* Allocate channels we need to support various functions. */
516 nouveau_accel_gr_init(drm);
517 nouveau_accel_ce_init(drm);
519 /* Initialise accelerated TTM buffer moves. */
520 nouveau_bo_move_init(drm);
523 static void __printf(2, 3)
524 nouveau_drm_errorf(struct nvif_object *object, const char *fmt, ...)
526 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
527 struct va_format vaf;
533 NV_ERROR(drm, "%pV", &vaf);
537 static void __printf(2, 3)
538 nouveau_drm_debugf(struct nvif_object *object, const char *fmt, ...)
540 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
541 struct va_format vaf;
547 NV_DEBUG(drm, "%pV", &vaf);
551 static const struct nvif_parent_func
553 .debugf = nouveau_drm_debugf,
554 .errorf = nouveau_drm_errorf,
558 nouveau_drm_device_init(struct drm_device *dev)
560 struct nouveau_drm *drm;
563 if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL)))
565 dev->dev_private = drm;
568 nvif_parent_ctor(&nouveau_parent, &drm->parent);
569 drm->master.base.object.parent = &drm->parent;
571 ret = nouveau_cli_init(drm, "DRM-master", &drm->master);
575 ret = nouveau_cli_init(drm, "DRM", &drm->client);
579 nvxx_client(&drm->client.base)->debug =
580 nvkm_dbgopt(nouveau_debug, "DRM");
582 INIT_LIST_HEAD(&drm->clients);
583 mutex_init(&drm->clients_lock);
584 spin_lock_init(&drm->tile.lock);
586 /* workaround an odd issue on nvc1 by disabling the device's
587 * nosnoop capability. hopefully won't cause issues until a
588 * better fix is found - assuming there is one...
590 if (drm->client.device.info.chipset == 0xc1)
591 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);
593 nouveau_vga_init(drm);
595 ret = nouveau_ttm_init(drm);
599 ret = nouveau_bios_init(dev);
603 nouveau_accel_init(drm);
605 ret = nouveau_display_create(dev);
609 if (dev->mode_config.num_crtc) {
610 ret = nouveau_display_init(dev, false, false);
615 nouveau_debugfs_init(drm);
616 nouveau_hwmon_init(dev);
617 nouveau_svm_init(drm);
618 nouveau_dmem_init(drm);
619 nouveau_led_init(dev);
621 if (nouveau_pmops_runtime()) {
622 pm_runtime_use_autosuspend(dev->dev);
623 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
624 pm_runtime_set_active(dev->dev);
625 pm_runtime_allow(dev->dev);
626 pm_runtime_mark_last_busy(dev->dev);
627 pm_runtime_put(dev->dev);
633 nouveau_display_destroy(dev);
635 nouveau_accel_fini(drm);
636 nouveau_bios_takedown(dev);
638 nouveau_ttm_fini(drm);
640 nouveau_vga_fini(drm);
641 nouveau_cli_fini(&drm->client);
643 nouveau_cli_fini(&drm->master);
645 nvif_parent_dtor(&drm->parent);
651 nouveau_drm_device_fini(struct drm_device *dev)
653 struct nouveau_cli *cli, *temp_cli;
654 struct nouveau_drm *drm = nouveau_drm(dev);
656 if (nouveau_pmops_runtime()) {
657 pm_runtime_get_sync(dev->dev);
658 pm_runtime_forbid(dev->dev);
661 nouveau_led_fini(dev);
662 nouveau_dmem_fini(drm);
663 nouveau_svm_fini(drm);
664 nouveau_hwmon_fini(dev);
665 nouveau_debugfs_fini(drm);
667 if (dev->mode_config.num_crtc)
668 nouveau_display_fini(dev, false, false);
669 nouveau_display_destroy(dev);
671 nouveau_accel_fini(drm);
672 nouveau_bios_takedown(dev);
674 nouveau_ttm_fini(drm);
675 nouveau_vga_fini(drm);
678 * There may be existing clients from as-yet unclosed files. For now,
679 * clean them up here rather than deferring until the file is closed,
680 * but this likely not correct if we want to support hot-unplugging
683 mutex_lock(&drm->clients_lock);
684 list_for_each_entry_safe(cli, temp_cli, &drm->clients, head) {
685 list_del(&cli->head);
686 mutex_lock(&cli->mutex);
688 nouveau_abi16_fini(cli->abi16);
689 mutex_unlock(&cli->mutex);
690 nouveau_cli_fini(cli);
693 mutex_unlock(&drm->clients_lock);
695 nouveau_cli_fini(&drm->client);
696 nouveau_cli_fini(&drm->master);
697 nvif_parent_dtor(&drm->parent);
698 mutex_destroy(&drm->clients_lock);
703 * On some Intel PCIe bridge controllers doing a
704 * D0 -> D3hot -> D3cold -> D0 sequence causes Nvidia GPUs to not reappear.
705 * Skipping the intermediate D3hot step seems to make it work again. This is
706 * probably caused by not meeting the expectation the involved AML code has
707 * when the GPU is put into D3hot state before invoking it.
709 * This leads to various manifestations of this issue:
710 * - AML code execution to power on the GPU hits an infinite loop (as the
711 * code waits on device memory to change).
712 * - kernel crashes, as all PCI reads return -1, which most code isn't able
713 * to handle well enough.
715 * In all cases dmesg will contain at least one line like this:
716 * 'nouveau 0000:01:00.0: Refused to change power state, currently in D3'
717 * followed by a lot of nouveau timeouts.
719 * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not
720 * documented PCI config space register 0x248 of the Intel PCIe bridge
721 * controller (0x1901) in order to change the state of the PCIe link between
722 * the PCIe port and the GPU. There are alternative code paths using other
723 * registers, which seem to work fine (executed pre Windows 8):
724 * - 0xbc bit 0x20 (publicly available documentation claims 'reserved')
725 * - 0xb0 bit 0x10 (link disable)
726 * Changing the conditions inside the firmware by poking into the relevant
727 * addresses does resolve the issue, but it seemed to be ACPI private memory
728 * and not any device accessible memory at all, so there is no portable way of
729 * changing the conditions.
730 * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared.
732 * The only systems where this behavior can be seen are hybrid graphics laptops
733 * with a secondary Nvidia Maxwell, Pascal or Turing GPU. It's unclear whether
734 * this issue only occurs in combination with listed Intel PCIe bridge
735 * controllers and the mentioned GPUs or other devices as well.
737 * documentation on the PCIe bridge controller can be found in the
738 * "7th Generation Intel® Processor Families for H Platforms Datasheet Volume 2"
739 * Section "12 PCI Express* Controller (x16) Registers"
742 static void quirk_broken_nv_runpm(struct pci_dev *pdev)
744 struct drm_device *dev = pci_get_drvdata(pdev);
745 struct nouveau_drm *drm = nouveau_drm(dev);
746 struct pci_dev *bridge = pci_upstream_bridge(pdev);
748 if (!bridge || bridge->vendor != PCI_VENDOR_ID_INTEL)
751 switch (bridge->device) {
753 drm->old_pm_cap = pdev->pm_cap;
755 NV_INFO(drm, "Disabling PCI power management to avoid bug\n");
760 static int nouveau_drm_probe(struct pci_dev *pdev,
761 const struct pci_device_id *pent)
763 struct nvkm_device *device;
764 struct drm_device *drm_dev;
767 if (vga_switcheroo_client_probe_defer(pdev))
768 return -EPROBE_DEFER;
770 /* We need to check that the chipset is supported before booting
771 * fbdev off the hardware, as there's no way to put it back.
773 ret = nvkm_device_pci_new(pdev, nouveau_config, "error",
774 true, false, 0, &device);
778 nvkm_device_del(&device);
780 /* Remove conflicting drivers (vesafb, efifb etc). */
781 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver_pci);
785 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug,
786 true, true, ~0ULL, &device);
790 pci_set_master(pdev);
793 driver_pci.driver_features |= DRIVER_ATOMIC;
795 drm_dev = drm_dev_alloc(&driver_pci, &pdev->dev);
796 if (IS_ERR(drm_dev)) {
797 ret = PTR_ERR(drm_dev);
801 ret = pci_enable_device(pdev);
805 pci_set_drvdata(pdev, drm_dev);
807 ret = nouveau_drm_device_init(drm_dev);
811 ret = drm_dev_register(drm_dev, pent->driver_data);
813 goto fail_drm_dev_init;
815 if (nouveau_drm(drm_dev)->client.device.info.ram_size <= 32 * 1024 * 1024)
816 drm_fbdev_generic_setup(drm_dev, 8);
818 drm_fbdev_generic_setup(drm_dev, 32);
820 quirk_broken_nv_runpm(pdev);
824 nouveau_drm_device_fini(drm_dev);
826 pci_disable_device(pdev);
828 drm_dev_put(drm_dev);
830 nvkm_device_del(&device);
835 nouveau_drm_device_remove(struct drm_device *dev)
837 struct nouveau_drm *drm = nouveau_drm(dev);
838 struct nvkm_client *client;
839 struct nvkm_device *device;
843 client = nvxx_client(&drm->client.base);
844 device = nvkm_device_find(client->device);
846 nouveau_drm_device_fini(dev);
848 nvkm_device_del(&device);
852 nouveau_drm_remove(struct pci_dev *pdev)
854 struct drm_device *dev = pci_get_drvdata(pdev);
855 struct nouveau_drm *drm = nouveau_drm(dev);
857 /* revert our workaround */
859 pdev->pm_cap = drm->old_pm_cap;
860 nouveau_drm_device_remove(dev);
861 pci_disable_device(pdev);
865 nouveau_do_suspend(struct drm_device *dev, bool runtime)
867 struct nouveau_drm *drm = nouveau_drm(dev);
868 struct ttm_resource_manager *man;
871 nouveau_svm_suspend(drm);
872 nouveau_dmem_suspend(drm);
873 nouveau_led_suspend(dev);
875 if (dev->mode_config.num_crtc) {
876 NV_DEBUG(drm, "suspending display...\n");
877 ret = nouveau_display_suspend(dev, runtime);
882 NV_DEBUG(drm, "evicting buffers...\n");
884 man = ttm_manager_type(&drm->ttm.bdev, TTM_PL_VRAM);
885 ttm_resource_manager_evict_all(&drm->ttm.bdev, man);
887 NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
889 ret = nouveau_channel_idle(drm->cechan);
895 ret = nouveau_channel_idle(drm->channel);
900 NV_DEBUG(drm, "suspending fence...\n");
901 if (drm->fence && nouveau_fence(drm)->suspend) {
902 if (!nouveau_fence(drm)->suspend(drm)) {
908 NV_DEBUG(drm, "suspending object tree...\n");
909 ret = nvif_client_suspend(&drm->master.base);
916 if (drm->fence && nouveau_fence(drm)->resume)
917 nouveau_fence(drm)->resume(drm);
920 if (dev->mode_config.num_crtc) {
921 NV_DEBUG(drm, "resuming display...\n");
922 nouveau_display_resume(dev, runtime);
928 nouveau_do_resume(struct drm_device *dev, bool runtime)
931 struct nouveau_drm *drm = nouveau_drm(dev);
933 NV_DEBUG(drm, "resuming object tree...\n");
934 ret = nvif_client_resume(&drm->master.base);
936 NV_ERROR(drm, "Client resume failed with error: %d\n", ret);
940 NV_DEBUG(drm, "resuming fence...\n");
941 if (drm->fence && nouveau_fence(drm)->resume)
942 nouveau_fence(drm)->resume(drm);
944 nouveau_run_vbios_init(dev);
946 if (dev->mode_config.num_crtc) {
947 NV_DEBUG(drm, "resuming display...\n");
948 nouveau_display_resume(dev, runtime);
951 nouveau_led_resume(dev);
952 nouveau_dmem_resume(drm);
953 nouveau_svm_resume(drm);
958 nouveau_pmops_suspend(struct device *dev)
960 struct pci_dev *pdev = to_pci_dev(dev);
961 struct drm_device *drm_dev = pci_get_drvdata(pdev);
964 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
965 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
968 ret = nouveau_do_suspend(drm_dev, false);
972 pci_save_state(pdev);
973 pci_disable_device(pdev);
974 pci_set_power_state(pdev, PCI_D3hot);
980 nouveau_pmops_resume(struct device *dev)
982 struct pci_dev *pdev = to_pci_dev(dev);
983 struct drm_device *drm_dev = pci_get_drvdata(pdev);
986 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
987 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
990 pci_set_power_state(pdev, PCI_D0);
991 pci_restore_state(pdev);
992 ret = pci_enable_device(pdev);
995 pci_set_master(pdev);
997 ret = nouveau_do_resume(drm_dev, false);
999 /* Monitors may have been connected / disconnected during suspend */
1000 nouveau_display_hpd_resume(drm_dev);
1006 nouveau_pmops_freeze(struct device *dev)
1008 struct pci_dev *pdev = to_pci_dev(dev);
1009 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1010 return nouveau_do_suspend(drm_dev, false);
1014 nouveau_pmops_thaw(struct device *dev)
1016 struct pci_dev *pdev = to_pci_dev(dev);
1017 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1018 return nouveau_do_resume(drm_dev, false);
1022 nouveau_pmops_runtime(void)
1024 if (nouveau_runtime_pm == -1)
1025 return nouveau_is_optimus() || nouveau_is_v1_dsm();
1026 return nouveau_runtime_pm == 1;
1030 nouveau_pmops_runtime_suspend(struct device *dev)
1032 struct pci_dev *pdev = to_pci_dev(dev);
1033 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1036 if (!nouveau_pmops_runtime()) {
1037 pm_runtime_forbid(dev);
1041 nouveau_switcheroo_optimus_dsm();
1042 ret = nouveau_do_suspend(drm_dev, true);
1043 pci_save_state(pdev);
1044 pci_disable_device(pdev);
1045 pci_ignore_hotplug(pdev);
1046 pci_set_power_state(pdev, PCI_D3cold);
1047 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1052 nouveau_pmops_runtime_resume(struct device *dev)
1054 struct pci_dev *pdev = to_pci_dev(dev);
1055 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1056 struct nouveau_drm *drm = nouveau_drm(drm_dev);
1057 struct nvif_device *device = &nouveau_drm(drm_dev)->client.device;
1060 if (!nouveau_pmops_runtime()) {
1061 pm_runtime_forbid(dev);
1065 pci_set_power_state(pdev, PCI_D0);
1066 pci_restore_state(pdev);
1067 ret = pci_enable_device(pdev);
1070 pci_set_master(pdev);
1072 ret = nouveau_do_resume(drm_dev, true);
1074 NV_ERROR(drm, "resume failed with: %d\n", ret);
1079 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
1080 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1082 /* Monitors may have been connected / disconnected during suspend */
1083 nouveau_display_hpd_resume(drm_dev);
1089 nouveau_pmops_runtime_idle(struct device *dev)
1091 if (!nouveau_pmops_runtime()) {
1092 pm_runtime_forbid(dev);
1096 pm_runtime_mark_last_busy(dev);
1097 pm_runtime_autosuspend(dev);
1098 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1103 nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
1105 struct nouveau_drm *drm = nouveau_drm(dev);
1106 struct nouveau_cli *cli;
1107 char name[32], tmpname[TASK_COMM_LEN];
1110 /* need to bring up power immediately if opening device */
1111 ret = pm_runtime_get_sync(dev->dev);
1112 if (ret < 0 && ret != -EACCES) {
1113 pm_runtime_put_autosuspend(dev->dev);
1117 get_task_comm(tmpname, current);
1118 snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
1120 if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) {
1125 ret = nouveau_cli_init(drm, name, cli);
1129 fpriv->driver_priv = cli;
1131 mutex_lock(&drm->clients_lock);
1132 list_add(&cli->head, &drm->clients);
1133 mutex_unlock(&drm->clients_lock);
1137 nouveau_cli_fini(cli);
1141 pm_runtime_mark_last_busy(dev->dev);
1142 pm_runtime_put_autosuspend(dev->dev);
1147 nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
1149 struct nouveau_cli *cli = nouveau_cli(fpriv);
1150 struct nouveau_drm *drm = nouveau_drm(dev);
1154 * The device is gone, and as it currently stands all clients are
1155 * cleaned up in the removal codepath. In the future this may change
1156 * so that we can support hot-unplugging, but for now we immediately
1157 * return to avoid a double-free situation.
1159 if (!drm_dev_enter(dev, &dev_index))
1162 pm_runtime_get_sync(dev->dev);
1164 mutex_lock(&cli->mutex);
1166 nouveau_abi16_fini(cli->abi16);
1167 mutex_unlock(&cli->mutex);
1169 mutex_lock(&drm->clients_lock);
1170 list_del(&cli->head);
1171 mutex_unlock(&drm->clients_lock);
1173 nouveau_cli_fini(cli);
1175 pm_runtime_mark_last_busy(dev->dev);
1176 pm_runtime_put_autosuspend(dev->dev);
1177 drm_dev_exit(dev_index);
1180 static const struct drm_ioctl_desc
1181 nouveau_ioctls[] = {
1182 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_RENDER_ALLOW),
1183 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1184 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_RENDER_ALLOW),
1185 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_RENDER_ALLOW),
1186 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_RENDER_ALLOW),
1187 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_RENDER_ALLOW),
1188 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_RENDER_ALLOW),
1189 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW),
1190 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW),
1191 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLOW),
1192 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_RENDER_ALLOW),
1193 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_RENDER_ALLOW),
1194 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_RENDER_ALLOW),
1195 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_RENDER_ALLOW),
1199 nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1201 struct drm_file *filp = file->private_data;
1202 struct drm_device *dev = filp->minor->dev;
1205 ret = pm_runtime_get_sync(dev->dev);
1206 if (ret < 0 && ret != -EACCES) {
1207 pm_runtime_put_autosuspend(dev->dev);
1211 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
1212 case DRM_NOUVEAU_NVIF:
1213 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
1216 ret = drm_ioctl(file, cmd, arg);
1220 pm_runtime_mark_last_busy(dev->dev);
1221 pm_runtime_put_autosuspend(dev->dev);
1225 static const struct file_operations
1226 nouveau_driver_fops = {
1227 .owner = THIS_MODULE,
1229 .release = drm_release,
1230 .unlocked_ioctl = nouveau_drm_ioctl,
1231 .mmap = drm_gem_mmap,
1234 #if defined(CONFIG_COMPAT)
1235 .compat_ioctl = nouveau_compat_ioctl,
1237 .llseek = noop_llseek,
1240 static struct drm_driver
1242 .driver_features = DRIVER_GEM |
1245 .open = nouveau_drm_open,
1246 .postclose = nouveau_drm_postclose,
1247 .lastclose = nouveau_vga_lastclose,
1249 #if defined(CONFIG_DEBUG_FS)
1250 .debugfs_init = nouveau_drm_debugfs_init,
1253 .ioctls = nouveau_ioctls,
1254 .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
1255 .fops = &nouveau_driver_fops,
1257 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1258 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1259 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
1260 .gem_prime_mmap = drm_gem_prime_mmap,
1262 .dumb_create = nouveau_display_dumb_create,
1263 .dumb_map_offset = drm_gem_ttm_dumb_map_offset,
1265 .name = DRIVER_NAME,
1266 .desc = DRIVER_DESC,
1268 .date = GIT_REVISION,
1270 .date = DRIVER_DATE,
1272 .major = DRIVER_MAJOR,
1273 .minor = DRIVER_MINOR,
1274 .patchlevel = DRIVER_PATCHLEVEL,
1277 static struct pci_device_id
1278 nouveau_drm_pci_table[] = {
1280 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1281 .class = PCI_BASE_CLASS_DISPLAY << 16,
1282 .class_mask = 0xff << 16,
1285 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
1286 .class = PCI_BASE_CLASS_DISPLAY << 16,
1287 .class_mask = 0xff << 16,
1292 static void nouveau_display_options(void)
1294 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
1296 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
1297 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
1298 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
1299 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
1300 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
1301 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
1302 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
1303 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
1304 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
1305 DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz);
1308 static const struct dev_pm_ops nouveau_pm_ops = {
1309 .suspend = nouveau_pmops_suspend,
1310 .resume = nouveau_pmops_resume,
1311 .freeze = nouveau_pmops_freeze,
1312 .thaw = nouveau_pmops_thaw,
1313 .poweroff = nouveau_pmops_freeze,
1314 .restore = nouveau_pmops_resume,
1315 .runtime_suspend = nouveau_pmops_runtime_suspend,
1316 .runtime_resume = nouveau_pmops_runtime_resume,
1317 .runtime_idle = nouveau_pmops_runtime_idle,
1320 static struct pci_driver
1321 nouveau_drm_pci_driver = {
1323 .id_table = nouveau_drm_pci_table,
1324 .probe = nouveau_drm_probe,
1325 .remove = nouveau_drm_remove,
1326 .driver.pm = &nouveau_pm_ops,
1330 nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
1331 struct platform_device *pdev,
1332 struct nvkm_device **pdevice)
1334 struct drm_device *drm;
1337 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug,
1338 true, true, ~0ULL, pdevice);
1342 drm = drm_dev_alloc(&driver_platform, &pdev->dev);
1348 err = nouveau_drm_device_init(drm);
1352 platform_set_drvdata(pdev, drm);
1359 nvkm_device_del(pdevice);
1361 return ERR_PTR(err);
1365 nouveau_drm_init(void)
1367 driver_pci = driver_stub;
1368 driver_platform = driver_stub;
1370 nouveau_display_options();
1372 if (nouveau_modeset == -1) {
1373 if (drm_firmware_drivers_only())
1374 nouveau_modeset = 0;
1377 if (!nouveau_modeset)
1380 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1381 platform_driver_register(&nouveau_platform_driver);
1384 nouveau_register_dsm_handler();
1385 nouveau_backlight_ctor();
1388 return pci_register_driver(&nouveau_drm_pci_driver);
1395 nouveau_drm_exit(void)
1397 if (!nouveau_modeset)
1401 pci_unregister_driver(&nouveau_drm_pci_driver);
1403 nouveau_backlight_dtor();
1404 nouveau_unregister_dsm_handler();
1406 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1407 platform_driver_unregister(&nouveau_platform_driver);
1409 if (IS_ENABLED(CONFIG_DRM_NOUVEAU_SVM))
1410 mmu_notifier_synchronize();
1413 module_init(nouveau_drm_init);
1414 module_exit(nouveau_drm_exit);
1416 MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
1417 MODULE_AUTHOR(DRIVER_AUTHOR);
1418 MODULE_DESCRIPTION(DRIVER_DESC);
1419 MODULE_LICENSE("GPL and additional rights");